Datasheet AD632 Datasheet (ANALOG DEVICES)

Internally Trimmed

Data Sheet

FEATURES

Pretrimmed to ±0.5% maximum 4-quadrant error
All inputs (X, Y, and Z) differential, high impedance for

[(X

− X2)(Y1 − Y2)/10] + Z2 transfer function

1

Scale-factor adjustable to provide up to ×10 gain
Low noise design: 90 mV rms, 10 Hz to 10 kHz
Low cost, monolithic construction
Excellent long-term stability

APPLICATIONS

High quality analog signal processing
Differential ratio and percentage computations
Algebraic and trigonometric function synthesis
Accurate voltage controlled oscillators and filters

GENERAL DESCRIPTION

The AD632 is an internally trimmed monolithic four-quadrant
multiplier/divider. The AD632B has a maximum multiplying
error of ±0.5% without external trims.

Excellent supply rejection, low temperature coefficients, and
long-term stability of the on-chip thin film resistors and buried
zener reference preserve accuracy even under adverse conditions.
The simplicity and flexibility of use provide an attractive alternative
approach to the solution of complex control functions.

The AD632 is pin-for-pin compatible with the industry
standard AD532 but with improved specifications and a fully
differential high impedance Z input. The AD632 is capable of
providing gains of up to ×10, frequently eliminating the need
for separate instrumentation amplifiers to precondition the
inputs. The AD632 can be effectively employed as a variable
gain differential input amplifier with high common-mode

Precision IC Multiplier

AD632

FUNCTIONAL BLOCK DIAGRAM

STABLE

REFERENCE

AND BIAS

X

1

2

1

2

1

25kΩ

V-I

V-I

V-I

TRANSLINE AR

MULTIPLIER

ELEMENT

0.75 ATTEN

X

Y

Y

Z

Z

2

2.7kΩ

V

OS

TRANSFER FUNCT ION

V

Figure 1.

(X

– X2) (Y1 – Y2)

1

= A – (Z1 – Z2)

O

A

HIGH GAIN

OUTPUT

AMPLIFIER

rejection. The effectiveness of the variable gain capability is
enhanced by the inherent low noise of the AD632 at 90 μV rms.

PRODUCT HIGHLIGHTS

1. Guaranteed performance over temperature.

2. The AD632A and AD632B are specified for maximum

multiplying errors of ±1.0% and ±0.5% of full scale,
respectively, at +25°C and are rated for operation from

−25°C to +85°C.

3. Maximum multiplying errors of ±2.0% (AD632S) and

±1.0% (AD632T) are guaranteed over the extended
temperature range of −55°C to +125°C.

4. High reliability.

5. The AD632S and AD632T series are available with MIL-

STD-883 Level B screening.

6. All devices are available in either the hermetically sealed

TO-100 metal can or ceramic DIP package.

+V

S

–V

S

10

OUT

09040-007

Rev. C

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©1979–2011 Analog Devices, Inc. All rights reserved.

AD632 Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Absolute Maximum Ratings ............................................................ 5

REVISION HISTORY

12/11—Rev. B to Rev. C

Updated Format .................................................................. Universal

Added Figure 1, Renumbered Sequentially .................................. 1

Deleted Chip Dimensions and Pad Layout Section ..................... 5

Changes to Figure 3 and Figure 4 ................................................... 6

Added Table 3 and Table 4 .............................................................. 6

Changes to the Operations as a Divider Section .......................... 9

Updated Outline Dimensions ....................................................... 10

Thermal Resistance .......................................................................5

Pin Configurations and Function Descriptions ............................6

Typical Performance Characteristics ..............................................7

Operation As a Multiplier ................................................................8

Operation As a Divider .....................................................................9

Outline Dimensions ....................................................................... 10

Ordering Guide .......................................................................... 11

4/10—Rev. A to Rev. B

Changes to Pin Configurations and Product Highlights

Sections .............................................................................................. 1

Changes to Thermal Characteristics Section ................................ 3

Updated Outline Dimensions ......................................................... 6

Changes to Ordering Guide ............................................................ 6

Rev. C | Page 2 of 12

Data Sheet AD632

2

2121

Z

YYXX

+

−−

V10

)()(

2

2121

Z

YYXX

+

−−

V10

)()(

2

2121

Z

YYXX

+

−−

V10

)()(

2

2121

Z

YYXX

+

−−

V10

)()(

SPECIFICATIONS

@ +25°C, VS = ±15 V, R ≥ 2 kΩ, unless otherwise noted. Specifications shown in boldface are tested on all production units at final
electrical test. Results from those tests are used to calculate outgoing quality levels.

Table 1.

AD632A AD632B AD632S AD632T

Parameter Min Typ Max Min Typ Max Min Typ Max Min Typ Max Units

MULTIPLIER PERFORMANCE

Transfer Function

Total Error1 (−10 V ≤ X, Y ≤ +10 V)
TA = Min to Max

±1.5

Total Error vs. Temperature ±0.022 ±0.015

±1.0

±1.0

±0.5

±1.0

±2.0

±0.02

±0.5

±1.0

±0.01

Scale Factor Error

(SF = 10,000 V Nominal)2 ±0.25 ±0.1 ±0.25 ±0.1 %

Temperature Coefficient of

±0.02

±0.01

±0.2

±0.005

Scaling Voltage
Supply Rejection (±15 V ± 1 V) ±0.01 ±0.01 ±0.01 ±0.01 %
Nonlinearity

X (X = 20 V p-p, Y = 10 V) ±0.4 ±0.2 ±0.3 ±0.4 ±0.2 ±0.3 %

Y (Y = 20 V p-p, X = 10 V) ±0.2 ±0.1 ±0.1 ±0.2 ±0.1 ±0.1 %
Feedthrough3

X (Y Nulled, X = 20 V p-p 50 Hz) ±0.3 ±0.15 ±0.3 ±0.3 ±0.15 ±0.3 %

Y (X Nulled, Y = 20 V p-p 50 Hz) ±0.01 ±0.01 ±0.1 ±0.01 ±0.01 ±0.1 %
Output Offset Voltage ±5
Output Offset Voltage Drift 200 100

±2 ±15 ±5

±30

±30

500

±2 ±15 mV

300

DYNAMICS

Small Signal BW, (V
1% Amplitude Error

(C

= 1000 pF)

LOAD

Slew Rate (V

OUT

Settling Time (to 1%, ΔV

= 0.1 rms) 1 1 1 1 MHz

OUT

50 50 50 50 kHz

20 p-p) 20 20 20 20 V/µs

= 20 V) 2 2 2 2 µs

OUT

NOISE

Noise Spectral Density

SF = 10 V 0.8 0.8 0.8 0.8 µV/√Hz

SF = 3 V4 0.4 0.4 0.4 0.4 µV/√Hz
Wideband Noise

A = 10 Hz to 5 MHz 1.0 1.0 1.0 1.0 mV/rms

P = 10 Hz to 10 kHz 90 90 90 90 µV/rms

OUTPUT

Output Voltage Swing

±11

±11

±11

V

±11

Output Impedance (f ≤ 1 kHz) 0.1 0.1 0.1 0.1 Ω
Output Short-Circuit Current

(RL = 0, TA = Min to Max) 30 30 30 30 mA
Amplifier Open-Loop Gain

70 70 70 70 dB

(f = 50 Hz)

INPUT AMPLIFIERS (X, Y, and Z)5

Signal Voltage Range

±10 ±10 ±10 ±10 V
(Differential or Common­Mode Operating Diff.)

Offset Voltage X, Y ±12 ±12 ±12 ±12 V
Offset Voltage Drift X, Y ±5

±20

±2

±10

±5

±20

±2

±10

Offset Voltage Z 100 50 100 150 µV/°C
Offset Voltage Z ±5

±30

±2

±15

±5

±30

±2

±15

Offset Voltage Drift Z 200 100 500 300 µV/°C

%
%
%/°C

%/°C

µV/°C

mV

mV

Rev. C | Page 3 of 12

AD632 Data Sheet

1

21

12

Y

XX

ZZ

+

−−)(

)(

V10

1

21

12

Y

XX

ZZ

+

−−)(

)(

V10

1

21

12

Y

XX

ZZ

+

−−)(

)(

V10

1

21

12

Y

XX

ZZ

+

−−)(

)(

V10

2

21

ZXX+

−

V10

)(

2

2

21

ZXX+

−

V10

)(

2

2

21

ZXX+

−

V10

)(

2

2

21

ZXX+

−

V10

)(

2

SQUARE-ROOTER PERFORMANCE

212

XZZ +− )(V10

212

XZZ +− )(V10

212

XZZ +− )(V10

212

XZZ +− )(V10

AD632A AD632B AD632S AD632T

Parameter Min Typ Max Min Typ Max Min Typ Max Min Typ Max Units

CMRR
Bias Current 0.8
Offset Current 0.1 0.1 0.1 0.1 µA
Differential Resistance 10 10 10 10 MΩ

DIVIDER PERFORMANCE

Transfer Function(X1 > X2)

60

80

2.0

90

70

0.8

2.0

80

60

0.8

2.0

90 dM

70

0.8

2.0

µA

Total Error1

(X = 10 V, −10 V ≤ Z ≤ +10 V) ±0.75 ±0.35 ±0.75 ±0.35 %
(X = 1 V, −1 V ≤ Z ≤ +1 V) ±2.0 ±1.0 ±2.0 ±1.0 %
(0.1 V ≤ X ≤ 10 V, −10 V ≤ Z ≤

±2.5 ±1.0 ±2.5 ±1.0 %

10 V)

SQUARER PERFORMANCE

Transfer Function

Total Error (−10 V ≤ X ≤ 10 V) ±0.6 ±0.3 ±0.6 ±0.3 %

Transfer Function, (Z1 ≤ Z2)

Total Error1 (1 V ≤ Z ≤ 10 V)

±1.0 ±0.5 ±1.0 ±0.5 %

POWER SUPPLY SPECIFICATIONS

Supply Voltage

Rated Performance ±15 ±15 ±15 ±15 V

Operating ±8

±18

±8

±18

±8

±22

±8

±22

Supply Current

Quiescent 4

1

Figures given are percent of full-scale, ±10 V (that is, 0.01% = 1 mV).

2

Can be reduced to 3 V using an external resistor between –VS and SF.

3

Irreducible component due to nonlinearity: excludes effect of offsets.

4

Using an external resistor adjusted to give a value of SF = 3 V.

5

See the functional block diagram (Figure 1) for definition of sections.

4 6 4

6

6

4 6 mA

V

Rev. C | Page 4 of 12

Data Sheet AD632

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.

Table 2. Thermal Resistance

Package Type θJA θJC Unit

10-Lead TO-100 150 25 °C/W
14-Lead SBDIP 95 25 °C/W

Rev. C | Page 5 of 12

AD632 Data Sheet

4

OUT

Product.

10

Y2

Y Multiplicand Inverting Input.

4, 5, 6, 8

NC

No Connection. Do not connect to
12

Y2

Y Multiplicand Inverting Input.

V

OS

Z2 (GND)

Y2

–V

S

Z1

OUT

+V

S

Y1

X2

X1

6

7

8

9

10

3

4

2

1

5

(Not to S cale)

AD632

09040-001

1
2
3
4

+V

S

14

Y1

13

Y2

12

V

OS

11

5

Z2

10

6

X2

9

Z1

OUT

–V

S

NC
NC
NC

X1

7

NC

8

NC = NO CONNECT

AD632

TOP VIEW

(Not to S cale)

09040-002

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

Figure 2. Pin Configuration, H-Package, TO-100

Figure 3. Pin Configuration, D-Package, SBDIP

Table 3. Pin Function Descriptions, 10-Pin TO-100

Pin No. Mnemonic Description

1 Y1 Y Multiplicand Noninverting Input.
2 +VS Positive Supply Voltage.
3 Z1 Summing Node Noninverting Input.

5 −VS Negative Supply Voltage.
6 X1 X Multiplicand Noninverting Input.
7 X2 X Multiplicand Inverting Input.
8 Z2 Summing Node Inverting Input.
9 VOS Offset Voltage Adjustment.

Table 4. Pin Function Descriptions, 14-Lead SBDIP

Pin No. Mnemonic Description

1 Z1 Summing Node Noninverting Input.
2 OUT Product.
3 −VS Negative Supply Voltage.

this pin.
7 X1 X Multiplicand Noninverting Input.
9 X2 X Multiplicand Noninverting Input.
10 Z2 Summing Node Inverting Input.
11 VOS Offset Voltage Adjustment.

13 Y1 Y Multiplicand Noninverting Input.
14 +VS Positive Supply Voltage.

Rev. C | Page 6 of 12

Data Sheet AD632

1000

0.1
10 10M

09040-004

FEEDTHRO UGH (mV p-p)

FREQUENCY ( Hz )

100 1k 10k 100k 1M

100

10

1

Y FEEDTHROUGH

X FEEDTHROUGH

–30

10k 10M

09040-005

OUTPUT RESPONSE (dB)

FREQUENCY (Hz )

100k 1M

0

–10

–20

CL = 0pF

CL = 1000pF

NORMAL
CONNECTION

CL ≤ 1000pF
C

F

≤ 200pF

WITH ×10
FEEDBACK
ATTENUATOR

C

L

≤ 1000pF

C

F

= 0pF

0dB = 0.1V rms, R

L

= 2kΩ

40

20

0

V

O

V

z

–20

1k 10M

09040-006

OUTPUT (dB )

FREQUENCY (Hz )

10k 100k 1M

VX = 100mV DC
V

Z

= 10mV rms

V

X

= 1V DC

V

Z

= 100mV rms

V

X

= 10V DC

V

Z

= 1V rms

0dB = 1V rms, RL = 2kΩ

TYPICAL PERFORMANCE CHARACTERISTICS

Typical @ 25°C with ±VS = 15 V.

Figure 4. AC Feedthrough vs. Frequency

Figure 6. Frequency Response vs. Divider Denominator Input Voltage

Figure 5. Frequency Response as a Multiplier

Rev. C | Page 7 of 12

AD632 Data Sheet

X

1

+V

S

X

2

V

OS

OUT

Z

1

Z

2

Y

1

Y

2

–V

S

–15V

+15V

X INPUT
±10V FS
±12V PK

Y INPUT
±10V FS
±12V PK

OUTPUT, ±12V PK
(X

1

– X

2

) (Y

1

– Y

2

)

OPTIONAL SUMMING
INPUT, Z, ±10V PK;
V

OS

TERMINAL

NOT USED

10

+ Z

2

=

09040-008

X

1

+V

S

X

2

OUT

Z

1

Z

2

V

OS

Y

1

Y

2

–V

S

–15V

+15V

X INPUT
±10V FS
±12V PK

Y INPUT
±10V FS
±12V PK

OUTPUT, ±12V PK
= (X

1

– X

2

) (Y

1

– Y

2

)

(SCALE = 1)

09040-009

OPERATION AS A MULTIPLIER

Figure 7 shows the basic connection for multiplication. Note
that the circuit meets all specifications without trimming.

Figure 7. Basic Multiplier Connection

When needed, the user can reduce ac feedthrough to a minimum
(as in a suppressed carrier modulator) by applying an external
trim voltage (±30 mV range required) to the X or Y input. Figure 4
shows the typical ac feedthrough with this adjustment mode.
Note that the feedthrough of the Y input is a factor of 10 lower
than that of the X input and is to be used for applications where
null suppression is critical.

The Z

terminal of the AD632 can be used to sum an additional

2

signal into the output. In this mode, the output amplifier behaves
as a voltage follower with a 1 MHz small signal bandwidth and
a 20 V/µs slew rate. Always reference this terminal to the ground
point of the driven system, particularly if this is remote. Like­wise, reference the differential inputs to their respective signal
common potentials to realize the full accuracy of the AD632.

A much lower scaling voltage can be achieved without any reduc­tion of input signal range using a feedback attenuator, as shown
in Figure 8. In this example, the scale is such that V

= X Y, s o

OUT

that the circuit can exhibit a maximum gain of 10. This connection
results in a reduction of bandwidth to about 80 kHz without the
peaking capacitor, C

. In addition, the output offset voltage is

F

increased by a factor of 10 making external adjustments necessary
in some applications.

Feedback attenuation also retains the capability for adding a
signal to the output. Signals can be applied to the Z terminal,
where they are amplified by −10, or to the common ground
connection where they are amplified by −1. Input signals can
also be applied to the lower end of the 2.7 kΩ resistor, giving a
gain of +9.

Figure 8. Connections for Scale Factor of Unity

Rev. C | Page 8 of 12

Data Sheet AD632

X

1

+V

S

X

2

+V

S

OUT

V

OS

Z

1

–V

S

Z

2

Y

1

Y

2

–V

S

–15V

+15V

X INPUT

(DENOMINATOR)

+10V FS
+12V PK

Z INPUT

(NUMERATOR)

±10V FS, ±12V P K

OPTIONAL

SUMMING INPUT

±10V PK

+

–

+15V

–15V

2kΩ

TO

200kΩ

10 (Z

2

– Z

1

)

(X

1

– X

2

)

+ Y

1

=

OUTPUT, ±12V PK

09040-010

OPERATION AS A DIVIDER

Figure 9 shows the connection required for division. Unlike
earlier products, the AD632 provides differential operation on
both the numerator and the denominator, allowing the ratio of
two floating variables to be generated. Further flexibility results
from access to a high impedance summing input to Y
all dividers based on the use of a multiplier in a feedback loop,
the bandwidth is proportional to the denominator magnitude,
as shown in Figure 6.

The accuracy of the AD632 B-model is sufficient to maintain a
1% error over a 10 V to 1 V denominator range.

. As with

1

Figure 9. Basic Divider Connection

Rev. C | Page 9 of 12

AD632 Data Sheet

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

14

1

7

8

0.310 (7.87)

0.220 (5.59)

PIN 1

0.080 (2.03) MAX

0.005 (0.13) MIN

SEATING
PLANE

0.023 (0.58)

0.014 (0.36)

0.060 (1.52)

0.015 (0.38)

0.200 (5.08)
MAX

0.200 (5.08)

0.125 (3.18)

0.070 (1.78)

0.030 (0.76)

0.100 (2.54)
BSC

0.150
(3.81)
MIN

0.765 (19.43) MAX

0.320 (8.13)

0.290 (7.37)

0.015 (0.38)

0.008 (0.20)

CONTROLLING DIMENSIONSARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE O NLYAND ARE NO T APPROPRIATE FOR USE IN DESIGN.

DIMENSIONS PER JEDEC STANDARDS MO-006-AF

0.500 (12.70)
MIN

0.185 (4.70)

0.165 (4.19)

REFERENCE PLANE

0.050 (1.27) MAX

0.040 (1.02) MAX

0.335 (8.51)

0.305 (7.75)

0.370 (9.40)

0.335 (8.51)

0.021 (0.53)

0.016 (0.40)

1

0.034 (0.86)

0.025 (0.64)

0.045 (1.14)

0.025 (0.65)

0.160 (4.06)

0.110 (2.79)

6

2

8

7

5

4

3

0.115

(2.92)

BSC

9

10

0.230 (5.84)
BSC

BASE & SEATING PLANE

36° BSC

022306-A

OUTLINE DIMENSIONS

Figure 10. 14-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP]

Dimensions shown in inches and (millimeters)

(D-14)

Figure 11. 10-Pin Metal Header Package [TO-100]

(H-10)

Dimensions shown in inches and (millimeters)

Rev. C | Page 10 of 12

Data Sheet AD632

AD632BHZ

−25°C to +85°C

10-Pin Metal Header Package [TO-100]

H-10

ORDERING GUIDE

Model1 Temperature Range Package Description Package Option

AD632AD −25°C to +85°C 14-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] D-14
AD632ADZ −25°C to +85°C 14-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] D-14
AD632AH −25°C to +85°C 10-Pin Metal Header Package [TO-100] H-10
AD632AHZ −25°C to +85°C 10-Pin Metal Header Package [TO-100] H-10
AD632BD −25°C to +85°C 14-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] D-14
AD632BDZ −25°C to +85°C 14-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] D-14
AD632BH −25°C to +85°C 10-Pin Metal Header Package [TO-100] H-10

AD632SD −55°C to +125°C 14-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] D-14
AD632SH −55°C to +125°C 10-Pin Metal Header Package [TO-100] H-10
AD632SH/883B −55°C to +125°C 10-Pin Metal Header Package [TO-100] H-10
AD632TD −55°C to +125°C 14-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] D-14
AD632TD/883B −55°C to +125°C 14-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] D-14
AD632TH −55°C to +125°C 10-Pin Metal Header Package [TO-100] H-10
AD632TH/883B −55°C to +125°C 10-Pin Metal Header Package [TO-100] H-10

1

Z = RoHS Compliant Part.

Rev. C | Page 11 of 12

AD632 Data Sheet

NOTES

©1979–2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09040-0-12/11(C)

Rev. C | Page 12 of 12