ANALOG DEVICES AD 630 JNZ Datasheet

Balanced Modulator/Demodulator

AD630

Rev. F Document Feedback

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CM OFF

ADJ

CM OFF

ADJ

DIFF OFF

ADJ

DIFF OFF

ADJ

2.5kΩ

AMP A

2.5kΩ

AMP B

–V

10kΩ

5kΩ

COMP

RINA

CH A+ CH A–

R

IN

B

CH B+ CH B–

SEL B SEL A

COMP +V

S

V

OUT

R

B

R

F

R

A

CHANNEL STATUS B/A

–V

S

A

B

00784-001

BIAS

+V

S

Data Sheet

FEATURES

Recovers signal from 100 dB noise 2 MHz channel bandwidth 45 V/µs slew rate Low crosstalk: −120 dB at 1 kHz, −100 dB at 10 kHz Pin programmable, closed-loop gains of ±1 and ±2

0.05% closed-loop gain accuracy and match 100 µV channel offset voltage (AD630) 350 kHz full power bandwidth Chips available

APPLICATIONS

Balanced modulation and demodulation Synchronous detection Phase detection Quadrature detection Phase sensitive detection Lock in amplification Square wave multiplication

FUNCTIONAL BLOCK DIAGRAM

Figure 1.

GENERAL DESCRIPTION

The AD630 is a high precision balanced modulator/demodulator that combines a flexible commutating architecture with the accuracy and temperature stability afforded by laser wafer trimmed thin film resistors. A network of on-board applications resistors provides precision closed-loop gains of ±1 and ±2 with 0.05% accuracy (AD630B). These resistors may also be used to accurately configure multiplexer gains of 1, 2, 3, or 4. External feedback enables high gain or complex switched feedback topologies.

The AD630 can be thought of as a precision op amp with two independent differential input stages and a precision comparator that is used to select the active front end. The rapid response time of this comparator coupled with the high slew rate and fast settling of the linear amplifiers minimize switching distortion.

The AD630 is used in precision signal processing and instrumentation applications that require wide dynamic range. When used as a synchronous demodulator in a lock-in amplifier configuration, the AD630 can recover a small signal from 100 dB of interfering noise (see the Lock-In Amplifier Applications section). Although optimized for operation up to 1 kHz, the circuit is useful at frequencies up to several hundred kilohertz.

Information furnishe d by responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Other features of the AD630 include pin programmable frequency compensation; optional input bias current compensation resistors, common-mode and differential-offset voltage adjustment, and a channel status output that indicates which of the two differential inputs is active.

PRODUCT HIGHLIGHTS

1. The application flexibility of the AD630 makes it the best

choice for applications that require precisely fixed gain, switched gain, multiplexing, integrating-switching functions, and high speed precision amplification.

2. The 100 dB dynamic range of the AD630 exceeds that of

any hybrid or IC balanced modulator/demodulator and is comparable to that of costly signal processing instruments.

3. The op amp format of the AD630 ensures easy imple-

mentation of high gain or complex switched feedback functions. The application resistors facilitate the implementation of most common applications with no additional parts.

4. The AD630 can be used as a 2-channel multiplexer with gains

of 1, 2, 3, or 4. The channel separation of 100 dB at 10 kHz approaches the limit achievable with an empty IC package.

5. Laser trimming of the comparator and amplifying channel

offsets eliminate the need for external nulling in most cases.

AD630* Product Page Quick Links

Comparable Parts

View a parametric search of comparable parts

Documentation

Application Notes

• AN-214: Ground Rules for High Speed Circuits

• AN-306: Synchronous System Measures µs

• AN-307: Modem-Circuit Techniques Simplify Instrumentation Designs

• AN-308: Commutating Amp Multiplies Precisely

• AN-349: Keys to Longer Life for CMOS

• AN-683: Strain Gage Measurement Using an AC Excitation

• AN-924: Digital Quadrature Modulator Gain

Data Sheet

• AD630: Balanced Modulator/Demodulator Data Sheet

• AD630: Military Data Sheet

Last Content Update: 08/30/2016

Tools and Simulations

• AD630 SPICE Macro Model

Design Resources

• AD630 Material Declaration

• PCN-PDN Information

• Quality And Reliability

• Symbols and Footprints

Discussions

View all AD630 EngineerZone Discussions

Sample and Buy

Visit the product page to see pricing options

Technical Support

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* This page was dynamically generated by Analog Devices, Inc. and inserted into this data sheet. Note: Dynamic changes to the content on this page does not constitute a change to the revision number of the product data sheet. This content may be frequently modified.

AD630 Data Sheet

REVISION HISTORY

7/15—Rev. E to Rev. F

Updated Format .................................................................. Universal

Changes to Features Section, General Description Section,

Product Highlights Section, and Figure 1 ..................................... 1

Added Applications Section ............................................................ 1

Changes to Table 3 ............................................................................ 4

Added Table 4; Renumbered Sequentially .................................... 5

Added Figure 4; Renumbered Sequentially and Table 5 ............. 6

Added Figure 5 and Table 6 ............................................................. 7

Added Table 7 .................................................................................... 8

Changes to Figure 7, Figure 8, and Figure 9.................................. 9

Changes to Figure 13, Figure 14, and Figure 15 ......................... 10

Added Test Circuits Section and Figure 16 to Figure 19 ........... 11

Added Theory of Operation Section............................................ 12

Change to Figure 24 ....................................................................... 13

Updated Outline Dimensions ....................................................... 19

Changes to Ordering Guide .......................................................... 20

6/04—Rev. D to Rev. E

Changes to Ordering Guide ............................................................. 3

Replaced Figure 12 ............................................................................ 9

Changes to AC Bridge Section ......................................................... 9

Replaced Figure 13 ......................................................................... 10

Changes to Lock-In Amplifier Applications ............................... 10

Updated Outline Dimensions ....................................................... 11

6/01—Rev. C to Rev. D

Changes to Specification Table ........................................................ 2

Changes to Thermal Characteristics ............................................... 3

Changes to Ordering Guide ............................................................. 3

Changes to Pin Configurations ....................................................... 3

Changes to Outline Dimensions .................................................. 11

Rev. F | Page 2 of 20

Data Sheet AD630

Settling Time to 0.1% (20 V Step)

3 3 3

µs

SPECIFICATIONS

At 25°C and ±VS = ±15 V, unless otherwise noted.

Table 1.

AD630J/AD630A AD630K/AD630B AD630S

Parameter

GAIN

Open-Loop Gain 90 110 100 120 90 110 dB ±1, ±2 Closed-Loop Gain Error 0.1 0.05 0.1 % Closed-Loop Gain Match 0.1 0.05 0.1 % Closed-Loop Gain Drift 2 2 2 ppm/°C

CHANNEL INPUTS

VIN Operational Limit1 (−VS + 4) to (+VS − 1) (−VS + 4) to (+VS − 1) (−VS + 4) to (+VS − 1) V Input Offset Voltage 500 100 500 µV

T

to T

MIN

800 160 1000 µV

MAX

Input Bias Current 100 300 100 300 100 300 nA Input Offset Current 10 50 10 50 10 50 nA Channel Separation at 10 kHz 100 100 100 dB

CO MPARATO R

VIN Operational Limit1 (−VS + 3) to (+VS − 1.5) (−VS + 3) to (+VS − 1.5) (−VS + 3) to (+VS − 1.3) V Switching Window ±1.5 ±1.5 ±1.5 mV

T

to T

MIN

±2.0 ±2.0 ±2.5 mV

MAX

Input Bias Current 100 300 100 300 100 300 nA Response Time (−5 mV to +5 mV Step) 200 200 200 ns Channel Status

I

at VOL = −VS + 0.4 V2 1.6 1.6 1.6 mA

SINK

Pull-Up Voltage (−VS + 33) (−VS + 33) (−VS + 33) V

DYNAMIC PERFORMANCE

Unity Gain Bandwidth 2 2 2 MHz Slew Rate3 45 45 45 V/µs

Unit Min Typ Max Min Typ Max Min Typ Max

OPERATING CHARACTERISTICS

Common-Mode Rejection 85 105 90 110 90 110 dB Power Supply Rejection 90 110 90 110 90 110 dB Supply Voltage Range ±5 ±16.5 ±5 ±16.5 ±5 ±16.5 V Supply Current 4 5 4 5 4 5 mA

OUTPUT VOLTAGE, AT RL = 2 kΩ

T

to T

MIN

±10 ±10 ±10 V

MAX

Output Short-Circuit Current 25 25 25 mA

TEMPERATURE RANGES

N Package 0 70 0 70 °C D Package −25 +85 −25 +85 −55 +125 °C

1

If one terminal of each differential channel or comparator input is kept within these limits the other terminal may be taken to the positive supply.

2

I

at VOL = (−VS + 1 V) is typically 4 mA.

SINK

3

Pin 12 open. Slew rate with Pin 12 and Pin 13 shorted is typically 35 V/µs.

Rev. F | Page 3 of 20

AD630 Data Sheet

Maximum Junction Temperature

150°C

00784-002

14

15

16

17

18

7 8

65

4

19 20

1 2

3

13

12

0.089

(2.260)

0.99

(2.515)

1

1 10 9

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

Supply Voltage ±18 V Internal Power Dissipation 600 mW Output Short-Circuit to Ground Indefinite Storage Temperature

Ceramic Package −65°C to +150°C Plastic Package −55°C to +125°C

Lead Temperature Range (Soldering, 10 sec) 300°C

Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability.

THERMAL RESISTANCE

Table 3. Thermal Resistance

Package Type θJC θJA Unit

20-Lead PDIP (N-20) 24 61 °C/W 20-Lead SBDIP (D-20) 35 120 °C/W 20-Lead LCC (E-20-4) 35 120 °C/W 20-Lead SOIC_W (RW-20) 38 75 °C/W

CHIP AVAILABILITY

The AD630 is available in laser trimmed, passivated chip form. Figure 2 shows the AD630 metallization pattern, bonding pads, and dimensions. AD630 chips are available; consult factory for details.

Figure 2. Chip Metallization and Pinout

Dimensions shown in inches and (millimeters)

Contact factory for latest dimensions

ESD CAUTION

Rev. F | Page 4 of 20

Data Sheet AD630

00784-030

R

IN

A

1

CH A+

2

DIFF OFF ADJ

3

DIFF OFF ADJ

4

CH A–

20

CH B–

19

CH B+

18

R

IN

B

17

CM OFF ADJ

5

R

A

16

CM OFF ADJ

6

R

F

15

CHANNEL STAT US B/A

7

R

B

14

–V

S

8

V

OUT

13

SEL B

9

COMP

12

SEL A

10

+V

S

11

AD630

TOP VIEW

(Not to S cale)

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

Figure 3. 20-Lead SOIC Pin Configuration

Table 4. 20-Lead SOIC Pin Function Descriptions

Pin No. Mnemonic Description

1 RINA 2.5 kΩ Resistor to Noninverting Input of Op Amp A 2 CH A+ Noninverting Input of Op Amp A 3 DIFF OFF ADJ Differential Offset Adjustment 4 DIFF OFF ADJ Differential Offset Adjustment 5 CM OFF ADJ Common-Mode Offset Adjustment 6 CM OFF ADJ Common-Mode Offset Adjustment 7 CHANNEL STAT US B/A B or A Channel Status

8 −VS Negative Supply 9 SEL B B Channel Comparator Input 10 SEL A A Channel Comparator Input 11 +VS Positive Supply 12 COMP Pin to Connect Internal Compensation Capacitor 13 V

Output Voltage

OUT

14 RB 10 kΩ Gain Setting Resistor 15 RF 10 kΩ Feedback Resistor 16 RA 5 kΩ Feedback Resistor 17 RINB 2.5 kΩ Resistor to Noninverting Input of Op Amp B 18 CH B+ Noninverting Input of Op Amp B 19 CH B− Inverting Input of Op Amp B 20 CH A− Inverting Input of Op Amp A

Rev. F | Page 5 of 20

AD630 Data Sheet

00784-031

R

IN

A

CH A+ DIFF OFF ADJ DIFF OFF ADJ

CH A– CH B– CH B+ R

IN

B

CM OFF ADJ

R

A

CM OFF ADJ

R

F

CHANNEL STATUS B/A

R

B

–V

S

V

OUT

SEL B

COMP

SEL A

+V

S

1 2 3 4

20

19 18

17 5 6 7

16

15

14 8

13 9

12

10

1

AD630

TOP VIEW

(Not to S cale)

7

CHANNEL STATUS B/A

B or A Channel Status

18

CH B+

Noninverting Input of Op Amp B

Figure 4. 20-Lead PDIP Pin Configuration

Table 5. 20-Lead PDIP Pin Function Descriptions

Pin No. Mnemonic Description

1 RINA 2.5 kΩ Resistor to Noninverting Input of Op Amp A 2 CH A+ Noninverting Input of Op Amp A 3 DIFF OFF ADJ Differential Offset Adjustment 4 DIFF OFF ADJ Differential Offset Adjustment 5 CM OFF ADJ Common-Mode Offset Adjustment 6 CM OFF ADJ Common-Mode Offset Adjustment

8 −VS Negative Supply 9 SEL B B Channel Comparator Input 10 SEL A A Channel Comparator Input 11 +VS Positive Supply 12 COMP Pin to Connect Internal Compensation Capacitor 13 V

Output Voltage

OUT

14 RB 10 kΩ Gain Setting Resistor 15 RF 10 kΩ Feedback Resistor 16 RA 5 kΩ Feedback Resistor 17 RINB 2.5 kΩ Resistor to Noninverting Input of Op Amp B

19 CH B− Inverting Input of Op Amp B 20 CH A− Inverting Input of Op Amp A

Rev. F | Page 6 of 20

Data Sheet AD630

RINA

1

CH A+

2

–V

SEL B SEL A

3 4 5 6 7 8

S

9

10

AD630

TOP VIEW

(Not to Scale)

DIFF OFF ADJ DIFF O FF ADJ

CM OFF ADJ CM OFF ADJ

CHANNEL STATUS B/A

Figure 5. 20-Lead CERDIP Pin Configuration

Table 6. 20-Lead CERDIP Pin Function Descriptions

Pin No. Mnemonic Description

1 RINA 2.5 kΩ Resistor to Noninverting Input of Op Amp A 2 CH A+ Noninverting Input of Op Amp A 3 DIFF OFF ADJ Differential Offset Adjustment 4 DIFF OFF ADJ Differential Offset Adjustment 5 CM OFF ADJ Common-Mode Offset Adjustment 6 CM OFF ADJ Common-Mode Offset Adjustment 7

CHANNEL STATUS B/A

B or A Channel Status

8 −VS Negative Supply 9 SEL B B Channel Comparator Input 10 SEL A A Channel Comparator Input 11 +VS Positive Supply 12 COMP Pin to Connect Internal Compensation Capacitor 13 V

Output Voltage

OUT

14 RB 10 kΩ Gain Setting Resistor 15 RF 10 kΩ Feedback Resistor 16 RA 5 kΩ Feedback Resistor 17 RINB 2.5 kΩ Resistor to Noninverting Input of Op Amp B 18 CH B+ Noninverting Input of Op Amp B 19 CH B− Inverting Input of Op Amp B 20 CH A− Inverting Input of Op Amp A

20 19 18 17 16 15 14 13 12 11

CH A– CH B–

CH B+ R

B

IN

R

A

R

F

R

B

V

OUT

COMP +V

S

00784-003

Rev. F | Page 7 of 20

AD630 Data Sheet

20 19123

18

14

15

16

17

4 5 6

7 8

9 11 12 13

TOP VIEW

(Not to Scale)

AD630

DIFF OFF ADJ

CM OFF ADJ CM OFF ADJ

CHANNEL STATUS B/A

–V

S

CH B+ R

IN

B

R

A

R

F

R

B

DIFF

OFF ADJ

CH A+

R

IN

A

CH A–

CH B–

SEL B

SEL A

+V

S

COMP

V

OUT

00784-004

10

Figure 6. 20-Terminal CLCC Pin Configuration

Table 7. 20-Terminal CLCC Pin Function Descriptions

Pin No. Mnemonic Description

1 RINA 2.5 kΩ Resistor to Noninverting Input of Op Amp A 2 CH A+ Noninverting Input of Op Amp A 3 DIFF OFF ADJ Differential Offset Adjustment 4 DIFF OFF ADJ Differential Offset Adjustment 5 CM OFF ADJ Common-Mode Offset Adjustment 6 CM OFF ADJ Common-Mode Offset Adjustment 7 CHANNEL STAT US B/A B or A Channel Status 8 −VS Negative Supply 9 SEL B B Channel Comparator Input 10 SEL A A Channel Comparator Input 11 +VS Positive Supply 12 COMP Pin to Connect Internal Compensation Capacitor 13 V

Output Voltage

OUT

14 RB 10 kΩ Gain Setting Resistor 15 RF 10 kΩ Feedback Resistor 16 RA 5 kΩ Feedback Resistor 17 RINB 2.5 kΩ Resistor to Noninverting Input of Op Amp B 18 CH B+ Noninverting Input of Op Amp B 19 CH B− Inverting Input of Op Amp B 20 CH A− Inverting Input of Op Amp A

Rev. F | Page 8 of 20

Data Sheet AD630

FREQUENCY (Hz)

15

10

5

100k 1M10k1k

OUTPUT VOLTAGE (±V)

0

R

L

= 2kΩ

C

L

= 100pF

00784-005

10

15

5

RESISTIVE LOAD (Ω)

OUTPUT VOLTAGE (±V)

0

100k 1M10k1k100101

CL = 100pF f = 1kHz

00784-006

10

18

5

0 5 10 15 20

SUPPLY VOLTAGE (±V)

OUTPUT VOLTAGE (±V)

15

f = 1kHz C

L

= 100pF

0

00784-007

100k10k1k100101

FREQUENCY (Hz)

COMMON-M ODE REJECTION (dB)

120

60

0

100

80

40

20

00784-008

INPUT VOLTAGE (V)

dV

O

dt

(V/µs)

60

0

–60

–2–3–4–5 –1

1 2 3 4 50

40

20

–40

–20

UNCOMPENSATED

COMPENSATED

00784-009

dt

dV

O

FREQUENCY (Hz)

120

60

0

1M100

100

80

20

40

10 1k 10k

UNCOMPENSATED

10M

0

45

90

OPEN-LOOP GAIN (dB)

135

180

COMPENSATED

OPEN-LOOP PHASE (Degrees)

1 100k

00784-010

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 7. Output Voltage vs. Frequency (See Figure 16)

Figure 8. Output Voltage vs. Resistive Load (See Figure 16)

Figure 10. Common-Mode Rejection vs. Frequency

F

igure 11.

vs. Input Voltage

Fi

gure 9. Output Voltage Swing vs. Supply Voltage (See Figure 16)

Figure 12. Gain and Phase vs. Frequency

Rev. F | Page 9 of 20

AD630 Data Sheet

20m

V

500n

s

20mV

100

90

10

0%

20mV/DIV

(V

o

)

20mV/DIV

(V

i

)

TOP TRACE: V

o

BOTTOM TRACE: V

i

00784-011

10

0

90

10

0%

100mV

5

00ns

50mV

1mV

50mV/DIV

(V

i

)

1mV/DIV

(A)

TOP TRACE : V

i MIDDLE TRACE: SETTLING ERROR (A) BOTTOM TRACE: V

o

100mV/DIV

(V

o

)

00784-013

10

0

90

10

0

%

10V

1mV

TOP TRACE: V

i MIDDLE TRACE: SETTLING ERROR (B) BOTTOM TRACE: V

o

5µs

±10V 20kHz

(V

i

)

1mV/DIV

(B)

10V/DIV

(V

o

)

00784-012

Figure 13. Channel-to-Channel Switch-Settling Characteristic

(See Figure 17)

Figure 14. Small Signal Noninverting Step Response (See Figure 18)

Figure 15. Large Signal Inverting Step Response (See Figure 19)

Rev. F | Page 10 of 20

Data Sheet AD630

TEST CIRCUITS

10kΩ

15

10kΩ

20

CH A

2

MIDDLE

TRACE

(A)

TEKTRONIX

7A13

(See Figure 14)

15

20

CH A

2

10kΩ

HP5082-2811

(See Figure 15)

12

10kΩ

12

V

10kΩ

O

BOTTOM TRACE

V

O

BOTTOM TRACE

(B) MIDDLE TRACE

00784-113

0784-112

13

V

i

5kΩ5kΩ

V

100pF

O

0784-105

2kΩ

Figure 16. Test Circuit for Output Voltage vs. Frequecy, Resistive Load,

and Supply Voltage (See Figure 7, Figure 8, and Figure 9)

15

16

5kΩ 10kΩ

2

CH A

20

19

CH B

18

10kΩ

14

V

9

i

10

13

V

12

O

00784-111

Figure 17. Test Circuit for Channel-to-Channel Switch-Settling

Characteristic (See Figure 13)

14

V

i

TOP

TRACE

1kΩ

30pF

Figure 18. Test Circuit for Small Signal Noninverting Step Response

V

i

14

TOP

TRACE

Figure 19. Test Circuit for Large Signal Noninverting Step Response

Rev. F | Page 11 of 20

AD630 Data Sheet

11

15

2 20 19 18 17

8

7

12

14

13

9

10

R

A

5kΩ

2.5kΩ

R

F

10kΩ

1

16

2.5kΩ

+V

S

R

B

10kΩ

SEL B SEL A

CHANNEL STAT US B/A

A

B

–V

S

00784-014

A

B

R

A

5kΩ

R

F

10kΩ

V

O

R

B

10kΩ

V

i

2

20 19

18

13

1516

14

9

10

00784-015

R

A

5kΩ

R

F

10kΩ

R

B

10kΩ

V

i

V

O

= –

R

F

R

A

V

i

00784-016

R

A

5kΩ

R

F

10kΩ

R

B

10kΩ

V

i

V

O

=(1+

R

F

R

B

)

V

i

00784-017

THEORY OF OPERATION

TWO WAYS TO LOOK AT THE AD630

The functional block diagram of the AD630 (see Figure 1) shows the pin connections of the internal functions. An alternative architectural diagram is shown in Figure 20. In this diagram, the individual A and B channel preamps, the switch, and the integrator output amplifier are combined in a single op amp. This amplifier has two differential input channels, only one of which is active at a time.

Figure 20. Architectural Block Diagram

HOW THE AD630 WORKS

The basic mode of operation of the AD630 may be easier to recognize as two fixed gain stages, which can be inserted into the signal path under the control of a sensitive voltage comparator. When the circuit is switched between inverting and noninverting gain, it provides the basic modulation/demodulation function. The AD630 is unique in that it includes laser wafer trimmed thin-film feedback resistors on the monolithic chip. The configuration shown in Figure 21 yields a gain of ±2 and can be easily changed to ±1 by shifting R connection to the output.

The comparator selects one of the two input stages to complete an operational feedback connection around the AD630. The deselected input is off and has a negligible effect on operation.

from its ground

B

When Channel B is selected, the RA and RF resistors are connected for inverting feedback as shown in the inverting gain configuration diagram in Figure 22. The amplifier has sufficient loop gain to minimize the loading effect of R

at the virtual

B

ground produced by the feedback connection. When the sign of the comparator input is reversed, Input B is deselected and Input A is selected. The new equivalent circuit is the noninverting gain configuration shown in Figure 23. In this case, R

appears

A

across the op amp input terminals, but because the amplifier drives this difference voltage to zero, the closed-loop gain is unaffected.

The two closed-loop gain magnitudes are equal when R 1 + R R

, which results from making RA equal to RFRB/(RF +

F/RB

) the parallel equivalent resistance of RF and RB.

B

F/RA

=

The 5 kΩ and the two 10 kΩ resistors on the AD630 chip can be used to make a gain of 2 as shown in Figure 22 and Figure 23. By paralleling the 10 kΩ resistors to make R omitting R

, the circuit can be programmed for a gain of ±1 (as

B

equal to 5 kΩ and

F

shown in Figure 28). These and other configurations using the on-chip resistors present the inverting inputs with a 2.5 kΩ source impedance. The more complete AD630 diagrams show

2.5 kΩ resistors available at the noninverting inputs which can be conveniently used to minimize errors resulting from input bias currents.

Figure 22. Inverting Gain Configuration

Figure 23. Noninverting Gain Configuration

Figure 21. AD630 Symmetric Gain (±2)

Rev. F | Page 12 of 20

Data Sheet AD630

20

11

3

4

5

6

19

2

18

13

12

SEL A

SEL B

DIFF

OFFADJ

DIFF

OFFADJCMOFFADJCMOFFADJ

COMP

Q74

Q44

CH B– CH B+CH A+CH A–

i

55

Q4

Q3

Q28

Q31

Q30

Q32

C122

C121

i

73

22

i

23

–V

S

V

OUT

Q52

Q53

+V

S

Q65

Q34

Q33

Q62

Q35

Q36

Q67

Q70

Q25

Q24

Q29

10

9

8

00784-018

CIRCUIT DESCRIPTION

The simplified schematic of the AD630 is shown in Figure 24. It has been subdivided into three major sections, the comparator, the two input stages, and the output integrator. The comparator consists of a front end made up of Q52 and Q53, a flip-flop load formed by Q3 and Q4, and two current steering switching cells Q28, Q29 and Q30, Q31. This structure is designed so that a differential input voltage greater than 1.5 mV in magnitude applied to the comparator inputs completely selects one of the switching cells. The sign of this input voltage determines which of the two switching cells is selected.

The collectors of each switching cell connect to an input transconductance stage. The selected cell conveys bias currents i

and i23 to the input stage it controls, causing it to become

22

active. The deselected cell blocks the bias to its input stage, which, as a consequence, remains off.

The structure of the transconductance stages is such that it presents a high impedance at its input terminals and draws no bias current when deselected. The deselected input does not interfere with the operation of the selected input ensuring maximum channel separation.

Another feature of the input structure is that it enhances the slew rate of the circuit. The current output of the active stage follows a quasihyperbolic sine relationship to the differential input voltage. This means that the greater the input voltage, the harder this stage drives the output integrator, and the faster the output signal moves. This feature helps ensure rapid, symmetric settling when switching between inverting and noninverting closed loop configurations.

The output section of the AD630 includes a current mirror load (Q24 and Q25), an integrator voltage gain stage (Q32), and a complementary output buffer (Q44 and Q74). The outputs of both transconductance stages are connected in parallel to the current mirror. Because the deselected input stage produces no output current and presents a high impedance at its outputs, there is no conflict. The current mirror translates the differential output current from the active input transconductance amplifier into single-ended form for the output integrator. The complementary output driver then buffers the integrator output to produce a low impedance output.

Figure 24. AD630 Simplified Schematic

Rev. F | Page 13 of 20

AD630 Data Sheet

OTHER GAIN CONFIGURATIONS

Many applications require switched gains other than the ±1 and ±2, which the self-contained applications resistors provide. The

AD630 can be readily programmed with three external resistors

over a wide range of positive and negative gain by selecting and R

and RF to give the noninverting gain 1 + RF/RB and subse-

B

quent R inverting magnitude equals the noninverting magnitude, the value of R the parallel combination of R negative gain.

The feedback synthesis of the AD630 may also include reactive impedance. The gain magnitudes match at all frequencies if the A impedance is made to equal the parallel combination of the B and F impedances. The same considerations apply to the

AD630 as to conventional op amp feedback circuits. Virtually

any function that can be realized with simple noninverting L network feedback can be used with the AD630. A common arrangement is shown in Figure 25. The low frequency gain of this circuit is 10. The response has a pole (−3 dB) at a frequency f frequency asymptote) at about 10 times this frequency. The 2 kΩ resistor in series with each capacitor mitigates the loading effect on circuitry driving this circuit, eliminates stability problems, and has a minor effect on the pole-zero locations.

As a result of the reactive feedback, the high frequency components of the switched input signal are transmitted at unity gain while the low frequency components are amplified. This arrangement is useful in demodulators and lock-in amplifiers. It increases the circuit dynamic range when the modulation or interference is substantially larger than the desired signal amplitude. The output signal contains the desired signal multiplied by the low frequency gain (which may be several hundred for large feedback ratios) with the switching signal and interference superimposed at unity gain.

to give the desired inverting gain. Note that when the

A

is found to be RBRF/(RB + RF). That is, RA equals

A

and RF to match positive and

B

1/(2 π 100 kΩ × C) and a zero (3 dB from the high

C

2kΩ

V

i

10kΩ

11.11kΩ

SEL B

SEL A

Figure 25. AD630 with External Feedback

2kΩ

100kΩ

2

A

20

19

B

18

9

10

C

13

12

V

O

7

CHANNEL STATUS B/A

8

–V

S

00784-019

SWITCHED INPUT IMPEDANCE

The noninverting mode of operation is a high input impedance configuration while the inverting mode is a low input impedance configuration. This means that the input impedance of the circuit undergoes an abrupt change as the gain is switched under control of the comparator. If the gain is switched when the input signal is not zero, as it is in many practical cases, a transient is delivered to the circuitry driving the AD630. In most applications, this requires the AD630 circuit to be driven by a low impedance source, which remains stiff at high frequencies. This is generally a wideband buffer amplifier.

FREQUENCY COMPENSATION

The AD630 combines the convenience of internal frequency compensation with the flexibility of external compensation by means of an optional self-contained compensation capacitor.

In gain of ±2 applications, the noise gain that must be addressed for stability purposes is actually 4. In this circumstance, the phase margin of the loop is on the order of 60° without the optional compensation. This condition provides the maximum bandwidth and slew rate for closed loop gains of |2| and above.

When the AD630 is used as a multiplexer, or in other configurations where one or both inputs are connected for unity gain feedback, the phase margin is reduced to less than 20°. This may be acceptable in applications where fast slewing is a first priority, but the transient response is not optimum. For these applications, the self-contained compensation capacitor may be added by connecting Pin 12 to Pin 13. This connection reduces the closed-loop bandwidth somewhat and improves the phase margin.

For intermediate conditions, such as a gain of ±1 where the loop attenuation is 2, determine the use of the compensation by whether bandwidth or settling response must be optimized. Also, use optional compensation when the AD630 is driving capacitive loads or whenever conservative frequency compensation is desired.

Rev. F | Page 14 of 20

Data Sheet AD630

1MΩ

100kΩ

–15V

+5V

100Ω

7

8

9

10

00784-020

–15V

+5V

TTL INPUT

AD630

+15V

IN914s

6.8kΩ

22kΩ

100kΩ

2N2222

7

8

00784-021

OFFSET VOLTAGE NULLING

The offset voltages of both input stages and the comparator have been pretrimmed so that external trimming is only required in the most demanding applications. The offset adjustment of the two input channels is accomplished by means of a differential and common-mode scheme. This facilitates fine adjustment of system errors in switched gain applications. With the system input tied to 0 V, and a switching or carrier waveform applied to the comparator, a low level square wave appears at the output. The differential offset adjustment potentiometers can be used to null the amplitude of this square wave (Pin 3 and Pin 4). The common-mode offset adjustment can be used to zero the residual dc output voltage (Pin 5 and Pin 6). Implement these functions using 10 kΩ trim potentiometers with wipers connected directly to Pin 8 as shown in Figure 28 and Figure 29.

CHANNEL STATUS OUTPUT

The channel status output, Pin 7, is an open collector output referenced to −V input channels is active. The output is active (pulled low) when Channel A is selected. This output can also be used to supply positive feedback around the comparator. This produces hysteresis which serves to increase noise immunity. Figure 26 shows an example of how hysteresis may be implemented. Note that the feedback signal is applied to the inverting (−) terminal of the comparator to achieve positive feedback. This is because the open collector channel status output inverts the output sense of the internal comparator.

that can be used to indicate which of the two

S

Figure 26. Comparator Hysteresis

The channel status output may be interfaced with TTL inputs as shown in Figure 27. This circuit provides appropriate level shifting from the open-collector AD630 channel status output to TTL inputs.

Figure 27. Channel Status—TTL Interface

Rev. F | Page 15 of 20

AD630 Data Sheet

MODULA

TED OUTPUT SIGNA

L

CARRIER

INPUT

CM OFF

ADJ

DIFF OFF

ADJ

AM

P A

AMP B

–V

10kΩ

5kΩ

9

10

COM

P

1

15

7

16

14

13

12

2

20

+V

S

–V

S

AD630

A

B

2.5kΩ

19

18

17

11

8

6

5

10kΩ

4 3

10kΩ

MODUL

A

TION

INPUT

00784-022

MODULATED OUTPUT SIGNAL

CARRIER

INPUT

CM OFF ADJ

DIFF OFF ADJ

2.5kΩ

AMP A

AMP B

–V

10kΩ

5kΩ

9

10

COMP

1

15

7

16

14

13

12

2

20

+V

S

–V

S

AD630

A

B

2.5kΩ

19

18

17

11

8

6 5

10kΩ

4 3

10kΩ

MODULATION

INPUT

00784-023

5V

20µs

MODULATION INPUT

CARRIER INPUT

OUTPUT SIGNAL

10V

00784-024

APPLICATIONS INFORMATION

BALANCED MODULATOR

Perhaps the most commonly used configuration of the AD630 is the balanced modulator. The application resistors provide precise symmetric gains of ±1 and ±2. The ±1 arrangement is shown in Figure 28 and the ±2 arrangement is shown in Figure 29. These cases differ only in the connection of the 10 kΩ feedback resistor (Pin 14) and the compensation capacitor (Pin 12). Note the use of the 2.5 kΩ bias current compensation resistors in these examples. These resistors perform the identical function in the ±1 gain case. Figure 30 demonstrates the performance of the AD630 when used to modulate a 100 kHz square wave carrier with a 10 kHz sinusoid. The result is the double sideband suppressed carrier waveform.

These balanced modulator topologies accept two inputs, a signal (or modulation) input applied to the amplifying channels and a reference (or carrier) input applied to the comparator.

Figure 30. Gain-of-Two Balanced Modulator Sample Waveforms

BALANCED DEMODULATOR

The balanced modulator topology described in the Balanced Modulator section also acts as a balanced demodulator if a double sideband suppressed carrier waveform is applied to the signal input and the carrier signal is applied to the reference input. The output under these circumstances is the baseband modulation signal. Higher order carrier components that can be removed with a low-pass filter are also present. Other names for this function are synchronous demodulation and phasesensitive detection.

Figure 28. AD630 Configured as a Gain-of-One Balanced Modulator

Figure 29. AD630 Configured as a Gain-of-Two Balanced Modulator

Rev. F | Page 16 of 20

PRECISION PHASE COMPARATOR

The balanced modulator topologies of Figure 28 and Figure 29 can also be used as precision phase comparators. In this case, an ac waveform of a particular frequency is applied to the signal input and a waveform of the same frequency is applied to the reference input. The dc level of the output (obtained by lowpass filtering) is proportional to the signal amplitude and phase difference between the input signals. If the signal amplitude is held constant, the output can be used as a direct indication of the phase. When these input signals are 90° out of phase, they are said to be in quadrature and the AD630 dc output is zero.

PRECISION RECTIFIER ABSOLUTE VALUE

If the input signal is used as its own reference in the balanced modulator topologies, the AD630 acts as a precision rectifier. The high frequency performance is superior to that which can be achieved with diode feedback and op amps. There are no diode drops that the op amp must leap over with the commutating amplifier.

Data Sheet AD630

A

B

10kΩ

5kΩ

2.5kΩ

C

100kΩ

D

1µF

AD630

±2 DEMODULAT OR

AD544

FOLLOWER

B

PHASE

SHIFTER

A

E1000

SCHAEVITZ

LVDT

2.5kHz

2V p-p SINUSOIDAL EXCITATION

16

1

14 17

9

10

20 19

12

13

15

00784-025

500µs/DIV

B. 200mV/DIV

C. 200mV/DIV

3

[ T ]

T

A. 200mV/DIV

00784-027

AD8221

REF

+IN

–IN

49.9Ω

350Ω

CH B–

SEL B

CH A–

SEL A

R

A

R

F

RINA

R

IN

B

–V

S

+15V

V

OUT

+V

S

COMP

AD630AR

12

13

1 8

R

B

1410

17

16

15

19

20

9 11

–15V

4.99kΩ 4. 99kΩ 4.99kΩ

2µF 2µF 2µF

A

CB

1V

400Hz

00784-026

LVDT SIGNAL CONDITIONER

Many transducers function by modulating an ac carrier. A linear variable differential transformer (LVDT) is a transducer of this type. The amplitude of the output signal corresponds to core displacement. Figure 31 shows an accurate synchronous demodulation system, which can be used to produce a dc voltage that corresponds to the LVDT core position. The inherent precision and temperature stability of the AD630 reduce demodulator drift to a second-order effect.

Figure 31. LVDT Signal Conditioner

AC BRIDGE

Bridge circuits that use dc excitation are often plagued by errors caused by thermocouple effects, 1/f noise, dc drifts in the electronics, and line noise pick-up. One way to get around these problems is to excite the bridge with an ac waveform, amplify the bridge output with an ac amplifier, and synchronously demodulate the resulting signal. The ac phase and amplitude information from the bridge is recovered as a dc signal at the output of the synchronous demodulator. The low frequency system noise, dc drifts, and demodulator noise all get mixed to the carrier frequency and can be removed by means of a lowpass filter. Dynamic response of the bridge must be traded off against the amount of attenuation required to adequately suppress these residual carrier components in the selection of the filter.

Figure 33 is an example of an ac bridge system with the AD630 used as a synchronous demodulator. The bridge is excited by a 1 V 400 Hz excitation. Trace A in Figure 32 is the amplified bridge signal. Trace B is the output of the synchronous demodulator and Trace C is the filtered dc system output.

Figure 32. AC Bridge Waveforms (1 V Excitation)

Figure 33. AC Bridge System

Rev. F | Page 17 of 20

AD630 Data Sheet

LOCK-IN AMPLIFIER APPLICATIONS

Lock-in amplification is a technique used to separate a small, narrow-band signal from interfering noise. The lock-in amplifier acts as a detector and narrow-band filter combined. Very small signals can be detected in the presence of large amounts of uncorrelated noise when the frequency and phase of the desired signal are known.

The lock-in amplifier is basically a synchronous demodulator followed by a low-pass filter. An important measure of performance in a lock-in amplifier is the dynamic range of its demodulator. The schematic diagram of a demonstration circuit which exhibits the dynamic range of an AD630 as it might be used in a lock-in amplifier is shown in Figure 35. Figure 34 is an oscilloscope photo demonstrating the large dynamic range of the AD630. The photo shows the recovery of a signal modulated at 400 Hz from a noise signal approximately 100,000 times larger.

5V

100

90

10

0%

5V

5mV

Figure 34. Lock-In Amplifier Waveforms

5s

MODULATED SIGNAL (A) (UNATTENUAT ED)

ATTENUAT ED SIGNAL PLUS NOISE (B)

OUTPUT

00784-029

The test signal is produced by modulating a 400 Hz carrier with a 0.1 Hz sine wave. The signals produced, for example, by chopped radiation (that is, IR, optical) detectors may have similar low frequency components. A sinusoidal modulation is used for clarity of illustration. This signal is produced by a circuit similar to Figure 28 and is shown in the upper trace of Figure 34. It is attenuated 100,000 times normalized to the output, B, of the summing amplifier. A noise signal that might represent, for example, background and detector noise in the chopped radiation case, is added to the modulated signal by the summing amplifier. This signal is simply band limited, clipped white noise. Figure 34 shows the sum of attenuated signal plus noise in the center trace. This combined signal is demodulated synchronously using phase information derived from the modulator, and the result is low-pass filtered using a 2-pole simple filter which also provides a gain of 100 to the output. This recovered signal is the lower trace of Figure 34.

The combined modulated signal and interfering noise used for this illustration is similar to the signals often requiring a lock-in amplifier for detection. The precision input performance of the

AD630 provides more than 100 dB of signal range and its

dynamic response permits it to be used with carrier frequencies more than two orders of magnitude higher than in this example. A more sophisticated low-pass output filter aids in rejecting wider bandwidth interference.

CLIPPED

BAND LIMIT ED

WHITE NOISE

100dB

ATTENUATION

A

0.1Hz

MODULATED

400Hz

CARRIER

AD542

CARRIER PHASE REFERENCE

5kΩ

2.5kΩ

10kΩ

AD630

15

20

19

A

B

16

1

17

14

10

9

Figure 35. Lock-In Amplifier

10kΩ

13

R

C

100R

AD542

100R

COUTPUT

LOW-PASS FILTER

00784-028

Rev. F | Page 18 of 20

Data Sheet AD630

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

20

1

10

11

0.300 (7.62)

0.280 (7.11)

PIN 1

0.080 (2.03) MAX

0.005 (0.13) MIN

SEATING PLANE

0.023 (0.58)

0.014 (0.36)

0.060 (1.52)

0.015 (0.38)

0.200 (5.08)

MAX

0.200 (5.08)

0.125 (3.18)

0.070 (1.78)

0.030 (0.76)

0.100 (2.54)

BSC

0.150 (3.81) MIN

0.320 (8.13)

0.300 (7.62)

0.015 (0.38)

0.008 (0.20)

1.060 (28.92)

0.990 (25.15)

CONTROLLING DIMENSIONSARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE RO UNDE D- OFF INCH E QUIVALENTS FOR REFERENCE ONLYAND ARE NOT APPROPRIATE FOR USE IN DESIGN. CORNER LEADS MAY BE CONFIGURED AS WHO LE OR HALF LEADS.

COMPLIANT TO JEDEC STANDARDS MS-001

070706-A

0.022 (0.56)

0.018 (0.46)

0.014 (0.36)

0.150 (3.81)

0.130 (3.30)

0.115 (2.92)

0.070 (1.78)

0.060 (1.52)

0.045 (1.14)

20

1

10

11

0.100 (2.54) BSC

1.060 (26.92)

1.030 (26.16)

0.980 (24.89)

0.210 (5.33) MAX

SEATING PLANE

0.015 (0.38) MIN

0.005 (0.13) MIN

0.280 (7.11)

0.250 (6.35)

0.240 (6.10)

0.060 (1.52) MAX

0.430 (10.92) MAX

0.014 (0.36)

0.010 (0.25)

0.008 (0.20)

0.325 (8.26)

0.310 (7.87)

0.300 (7.62)

0.015 (0.38) GAUGE

PLANE

0.195 (4.95)

0.130 (3.30)

0.115 (2.92)

OUTLINE DIMENSIONS

Figure 36. 20-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP]

(D-20)

Dimensions shown in inches and (millimeters)

Figure 37. 20-Lead Plastic Dual In-Line P ackage [PDIP]

Narrow Body

(N-20)

Dimensions shown in inches and (millimeters)

Rev. F | Page 19 of 20

AD630 Data Sheet

CONTROLLING DIMENSIONSARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE RO UNDE D- OFF INCH E Q UIVALENTS FOR REFERENCE ONLYAND ARE NOT APPROPRIATE FOR USE IN DESIGN.

1

20

4

9

8

13

19

14

3

18

BOTTOM

VIEW

0.028 (0.71)

0.022 (0.56)

45° TYP

0.015 (0.38) MIN

0.055 (1.40)

0.045 (1.14)

0.050 (1.27) BSC

0.075 (1.91) REF

0.011 (0.28)

0.007 (0.18) R TYP

0.095 (2.41)

0.075 (1.90)

0.100 (2.54) REF

0.200 (5.08) REF

0.150 (3.81) BSC

0.075 (1.91) REF

0.358 (9.09)

0.342 (8.69) SQ

0.358

(9.09)

MAX

SQ

0.100 (2.54)

0.064 (1.63)

0.088 (2.24)

0.054 (1.37)

022106-A

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLYAND ARE NOT APPROPRIATE FOR USE IN DESIGN.

COMPLIANT TO JEDEC STANDARDS MS-013-AC

13.00 (0.5118)

12.60 (0.4961)

0.30 (0.0118)

0.10 (0.0039)

2.65 (0.1043)

2.35 (0.0925)

10.65 (0.4193)

10.00 (0.3937)

7.60 (0.2992)

7.40 (0.2913)

0.75 (0.0295)

0.25 (0.0098)

45°

1.27 (0.0500)

0.40 (0.0157)

COPLANARITY

0.10

0.33 (0.0130)

0.20 (0.0079)

0.51 (0.0201)

0.31 (0.0122)

SEATING PLANE

8° 0°

20

11

10

1

1.27

(0.0500)

BSC

06-07-2006-A

5962-8980701RA

−55°C to +125°C

20-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP]

D-20

Figure 38. 20-Terminal Ceramic Leadless Chip Carrier [LCC]

(E-20-1)

Dimensions shown in inches and (millimeters)

Figure 39. 20-Lead Standard Small Outline Package [SOIC_W]

Wide Body

(RW-20)

Dimensions shown in millimeters and (inches)

ORDERING GUIDE

Model1 Temperature Range Package Description Package Option

AD630JNZ 0°C to 70°C 20-Lead Plastic Dual In-Line Package [PDIP] N-20 AD630KNZ 0°C to 70°C 20-Lead Plastic Dual In-Line Package [PDIP] N-20 AD630ARZ −25°C to +85°C 20-Lead Standard Small Outline Package [SOIC_W] RW-20 AD630ARZ-RL −25°C to +85°C 20-Lead Standard Small Outline Package [SOIC_W], 13" Tape and Reel RW-20 AD630ADZ −25°C to +85°C 20-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] D-20 AD630BDZ −25C to +85°C 20-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] D-20 AD630SD −55°C to +125°C 20-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] D-20 AD630SD/883B −55°C to +125°C 20-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] D-20

AD630SE/883B −55°C to +125°C 20-Terminal Ceramic Leadless Chip Carrier [LCC] E-20-1 5962-89807012A −55°C to +125°C 20-Terminal Ceramic Leadless Chip Carrier [LCC] E-20-1 AD630SCHIPS −55°C to +125°C Chip

1

Z = RoHS Compliant Part.

registered trademarks are the property of their respective owners. D00784-0-7/15(F)

Rev. F | Page 20 of 20

ANALOG DEVICES AD 630 JNZ Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

FUNCTIONAL BLOCK DIAGRAM

GENERAL DESCRIPTION

PRODUCT HIGHLIGHTS

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

CHIP AVAILABILITY

ESD CAUTION

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

TEST CIRCUITS

THEORY OF OPERATION

TWO WAYS TO LOOK AT THE AD630

HOW THE AD630 WORKS

CIRCUIT DESCRIPTION

OTHER GAIN CONFIGURATIONS

SWITCHED INPUT IMPEDANCE

FREQUENCY COMPENSATION

OFFSET VOLTAGE NULLING

CHANNEL STATUS OUTPUT

APPLICATIONS INFORMATION

BALANCED MODULATOR

BALANCED DEMODULATOR

PRECISION PHASE COMPARATOR

PRECISION RECTIFIER ABSOLUTE VALUE

LVDT SIGNAL CONDITIONER

AC BRIDGE

LOCK-IN AMPLIFIER APPLICATIONS

OUTLINE DIMENSIONS

ORDERING GUIDE