Datasheet AD620 Datasheet (Analog Devices)

Low Cost Low Power

FEATURES

Easy to use

Gain set with one external resistor

(Gain range 1 to 10,000)
Wide power supply range (±2.3 V to ±18 V)
Higher performance than 3 op amp IA designs
Available in 8-lead DIP and SOIC packaging
Low power, 1.3 mA max supply current

Excellent dc performance (B grade)

50 µV max, input offset voltage

0.6 µV/°C max, input offset drift

1.0 nA max, input bias current
100 dB min common-mode rejection ratio (G = 10)

Low noise

9 nV/√Hz @ 1 kHz, input voltage noise

0.28 µV p-p noise (0.1 Hz to 10 Hz)

Excellent ac specifications

120 kHz bandwidth (G = 100)
15 µs settling time to 0.01%

APPLICATIONS

Weigh scales
ECG and medical instrumentation
Transducer interface
Data acquisition systems
Industrial process controls
Battery-powered and portable equipment

30,000

Instrumentation Amplifier

AD620

CONNECTION DIAGRAM

1

R

G

2

–IN

3

+IN

4

–V

S

AD620

TOP VIEW

Figure 1. 8-Lead PDIP (N), CERDIP (Q), and SOIC (R) Packages

PRODUCT DESCRIPTION

The AD620 is a low cost, high accuracy instrumentation
amplifier that requires only one external resistor to set gains of
1 to 10,000. Furthermore, the AD620 features 8-lead SOIC and
DIP packaging that is smaller than discrete designs and offers
lower power (only 1.3 mA max supply current), making it a
good fit for battery-powered, portable (or remote) applications.

The AD620, with its high accuracy of 40 ppm maximum
nonlinearity, low offset voltage of 50 µV max, and offset drift of

0.6 µV/°C max, is ideal for use in precision data acquisition
systems, such as weigh scales and transducer interfaces.
Furthermore, the low noise, low input bias current, and low power
of the AD620 make it well suited for medical applications, such
as ECG and noninvasive blood pressure monitors.

The low input bias current of 1.0 nA max is made possible with
the use of Superϐeta processing in the input stage. The AD620
works well as a preamplifier due to its low input voltage noise of
9 nV/√Hz at 1 kHz, 0.28 µV p-p in the 0.1 Hz to 10 Hz band,
and 0.1 pA/√Hz input current noise. Also, the AD620 is well
suited for multiplexed applications with its settling time of 15 µs
to 0.01%, and its cost is low enough to enable designs with one
in-amp per channel.

10,000

8

7

6

5

R

G

+V

S

OUTPUT

REF

00775-0-001

25,000

20,000

15,000

AD620A

10,000

R

G

5,000

TOTAL ERROR, PPM OF FULL SCALE

0

0 5 10 15 20

SUPPLY CURRENT (mA)

3 OP AMP
IN-AMP
(3 OP-07s)

00775-0-002

Figure 2. Three Op Amp IA Designs vs. AD620

Rev. G

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

RTI VOLTAGE NOISE

1,000

100

V p-p)

µ

(0.1 – 10Hz) (

10

1

0.1

TYPICAL STANDARD
BIPOLAR INPUT
IN-AMP

G = 100

SOURCE RESISTANCE (Ω)

AD620 SUPERβETA
BIPOLAR INPUT
IN-AMP

Figure 3. Total Voltage Noise vs. Source Resistance

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]
Fax: [phone] © 2004 Analog Devices, Inc. All rights reserved.

www.analog.com

100M10k1k 10M1M100k

00775-0-003

AD620

TABLE OF CONTENTS

Specifications .....................................................................................3

Input Protection..........................................................................16

Absolute Maximum Ratings ............................................................5

ESD Caution ..................................................................................5

Typical Performance Characteristics..............................................7

Theory of Operation.......................................................................13

Gain Selection..............................................................................16

Input and Output Offset Voltage ..............................................16

Reference Terminal.....................................................................16

REVISION HISTORY

12/04—Rev. F to Rev. G

Updated Format..................................................................Universal

Change to Features............................................................................1

Change to Product Description.......................................................1

Changes to Specifications.................................................................3

Added Metallization Photograph....................................................4

Replaced Figure 4-Figure 6..............................................................6

Replaced Figure 15............................................................................7

Replaced Figure 33..........................................................................10

Replaced Figure 34 and Figure 35.................................................10

Replaced Figure 37..........................................................................10

Changes to Table 3 ..........................................................................13

Changes to Figure 41 and Figure 42 .............................................14

Changes to Figure 43 ......................................................................15

Change to Figure 44........................................................................17

Changes to Input Protection section ............................................15

Deleted Figure 9...............................................................................15

Changes to RF Interference section..............................................15

Edit to Ground Returns for Input Bias Currents section...........17

Added AD620CHIPS to Ordering Guide....................................19

RF Interference............................................................................16

Common-Mode Rejection.........................................................17

Grounding....................................................................................17

Ground Returns for Input Bias Currents.................................18

Outline Dimensions........................................................................19

Ordering Guide...........................................................................20

7/03—Data Sheet changed from REV. E to REV. F

Edit to FEATURES............................................................................1

Changes to SPECIFICATIONS.......................................................2

Removed AD620CHIPS from ORDERING GUIDE................... 4

Removed METALLIZATION PHOTOGRAPH...........................4

Replaced TPCs 1–3 ...........................................................................5

Replaced TPC 12...............................................................................6

Replaced TPC 30...............................................................................9

Replaced TPCs 31 and 32...............................................................10

Replaced Figure 4............................................................................10

Changes to Table I...........................................................................11

Changes to Figures 6 and 7............................................................12

Changes to Figure 8 ........................................................................13

Edited INPUT PROTECTION section........................................13

Added new Figure 9........................................................................13

Changes to RF INTERFACE section............................................14

Edit to GROUND RETURNS FOR INPUT BIAS CURRENTS

section...............................................................................................15

Updated OUTLINE DIMENSIONS.............................................16

Rev. G | Page 2 of 20

AD620

SPECIFICATIONS

Typical @ 25°C, VS = ±15 V, and RL = 2 kΩ, unless otherwise noted.

Table 1.

AD620A AD620B

Parameter Conditions

Min Typ Max Min Typ Max Min Typ Max Unit

AD620S1

GAIN G = 1 + (49.4 kΩ/RG)

Gain Range 1 10,000 1 10,000 1 10,000

V

Gain Error2

= ±10 V

OUT

G = 1 0.03 0.10 0.01 0.02 0.03 0.10 %

G = 10 0.15 0.30 0.10 0.15 0.15 0.30 %

G = 100 0.15 0.30 0.10 0.15 0.15 0.30 %

G = 1000 0.40 0.70 0.35 0.50 0.40 0.70 %
Nonlinearity V

= −10 V to +10 V

OUT

G = 1–1000 RL = 10 kΩ 10 40 10 40 10 40 ppm

G = 1–100 RL = 2 kΩ 10 95 10 95 10 95 ppm
Gain vs. Temperature

G = 1 10 10 10 ppm/°C
Gain >12 −50 −50 −50 ppm/°C
VOLTAGE OFFSET (Total RTI Error = V

Input Offset, V

VS = ±5 V

OSI

+ V

/G)

OSI

OSO

30 125 15 50 30 125 µV

to ± 15 V

Overtemperature VS = ±5 V

185 85 225 µV

to ± 15 V

Average TC VS = ±5 V

0.3 1.0 0.1 0.6 0.3 1.0 µV/°C

to ± 15 V
Output Offset, V
V

Overtemperature VS = ±5 V

VS = ±15 V 400 1000 200 500 400 1000 µV

OSO

= ± 5 V 1500 750 1500 µV

S

2000 1000 2000 µV

to ± 15 V

Average TC VS = ±5 V

5.0 15 2.5 7.0 5.0 15 µV/°C

to ± 15 V
Offset Referred to the
Input vs. Supply (PSR) VS = ±2.3 V

to ±18 V

G = 1 80 100 80 100 80 100 dB
G = 10 95 120 100 120 95 120 dB
G = 100 110 140 120 140 110 140 dB
G = 1000 110 140 120 140 110 140 dB

INPUT CURRENT

Input Bias Current 0.5 2.0 0.5 1.0 0.5 2 nA

Overtemperature 2.5 1.5 4 nA
Average TC 3.0 3.0 8.0 pA/°C

Input Offset Current 0.3 1.0 0.3 0.5 0.3 1.0 nA

Overtemperature 1.5 0.75 2.0 nA
Average TC 1.5 1.5 8.0 pA/°C

INPUT

Input Impedance

Differential 10||2 10||2 10||2 GΩ_pF
Common-Mode 10||2 10||2 10||2 GΩ_pF

Input Voltage Range3

= ±2.3 V

S

−VS + 1.9 +VS − 1.2 −VS + 1.9 +VS − 1.2 −VS + 1.9 +VS − 1.2 V

V

to ±5 V

Overtemperature −VS + 2.1 +VS − 1.3 −VS + 2.1 +VS − 1.3 −VS + 2.1 +VS − 1.3 V

V

= ± 5 V

S

−VS + 1.9 +VS − 1.4 −VS + 1.9 +VS − 1.4 −VS + 1.9 +VS − 1.4 V

to ±18 V

Overtemperature −VS + 2.1 +VS − 1.4 −VS + 2.1 +VS + 2.1 −VS + 2.3 +VS − 1.4 V

Rev. G | Page 3 of 20

AD620

AD620A AD620B

Parameter Conditions

Min Typ Max Min Typ Max Min Typ Max Unit

AD620S

1

Common-Mode Rejection

Ratio DC to 60 Hz with
1 kΩ Source Imbalance VCM = 0 V to ± 10 V

G = 1 73 90 80 90 73 90 dB
G = 10 93 110 100 110 93 110 dB
G = 100 110 130 120 130 110 130 dB
G = 1000 110 130 120 130 110 130 dB

OUTPUT

Output Swing RL = 10 kΩ

V

Overtemperature −VS + 1.4 +VS − 1.3

= ±2.3 V

S

to ± 5 V

VS = ±5 V

−VS +

+VS − 1.2

1.1

−VS + 1.2 +VS − 1.4

−VS + 1.1

−VS + 1.4

−VS + 1.2

+VS − 1.2 −VS + 1.1 +VS − 1.2 V

+VS − 1.3 −VS + 1.6 +VS − 1.3 V
+VS − 1.4 −VS + 1.2 +VS − 1.4 V

to ± 18 V
Overtemperature −VS + 1.6 +VS – 1.5

−VS + 1.6

+VS – 1.5 –VS + 2.3 +VS – 1.5 V

Short Circuit Current ±18 ±18 ±18 mA

DYNAMIC RESPONSE

Small Signal –3 dB Bandwidth

G = 1 1000 1000 1000 kHz
G = 10 800 800 800 kHz
G = 100 120 120 120 kHz

G = 1000 12 12 12 kHz
Slew Rate 0.75 1.2 0.75 1.2 0.75 1.2 V/µs
Settling Time to 0.01% 10 V Step

G = 1–100 15 15 15 µs

G = 1000 150 150 150 µs

NOISE

Voltage Noise, 1 kHz

Input, Voltage Noise, eni
Output, Voltage Noise, e

2

ni

9 13 9 13 9 13 nV/√Hz
72 100 72 100 72 100 nV/√Hz

no

2

)/()( GeeNoiseRTITotal

+=

no

RTI, 0.1 Hz to 10 Hz

G = 1 3.0 3.0 6.0 3.0 6.0 µV p-p
G = 10 0.55 0.55 0.8 0.55 0.8 µV p-p
G = 100–1000 0.28 0.28 0.4 0.28 0.4 µV p-p

Current Noise f = 1 kHz 100 100 100 fA/√Hz

0.1 Hz to 10 Hz 10 10 10 pA p-p

REFERENCE INPUT

RIN 20 20 20 kΩ
IIN V

, V

= 0 50 60 50 60 50 60 µA

IN+

REF

Voltage Range −VS + 1.6 +VS − 1.6 −VS + 1.6 +VS − 1.6 −VS + 1.6 +VS − 1.6 V
Gain to Output 1 ± 0.0001 1 ± 0.0001 1 ± 0.0001

POWER SUPPLY

Operating Range4
Quiescent Current VS = ±2.3 V

±2.3 ±18 ±2.3 ±18 ±2.3 ±18 V

0.9 1.3 0.9 1.3 0.9 1.3 mA

to ±18 V

Overtemperature 1.1 1.6 1.1 1.6 1.1 1.6 mA

TEMPERATURE RANGE

For Specified Performance

−40 to +85 −40 to +85 −55 to +125 °C

1

See Analog Devices military data sheet for 883B tested specifications.

2

Does not include effects of external resistor RG.

3

One input grounded. G = 1.

4

This is defined as the same supply range that is used to specify PSR.

Rev. G | Page 4 of 20

AD620

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

Supply Voltage ±18 V
Internal Power Dissipation1 650 mW
Input Voltage (Common-Mode) ±VS
Differential Input Voltage 25 V
Output Short-Circuit Duration Indefinite
Storage Temperature Range (Q) −65°C to +150°C
Storage Temperature Range (N, R) −65°C to +125°C
Operating Temperature Range

AD620 (A, B) −40°C to +85°C
AD620 (S) −55°C to +125°C

Lead Temperature Range

(Soldering 10 seconds) 300°C

1

Specification is for device in free air:

8-Lead Plastic Package: θ
8-Lead CERDIP Package: θ
8-Lead SOIC Package: θ

= 95°C

JA

= 110°C

JA

= 155°C

JA

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other condition s above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. G | Page 5 of 20

AD620

00775-0-004

Figure 4. Metallization Photograph.

Dimensions shown in inches and (mm).

Contact sales for latest dimensions.

Rev. G | Page 6 of 20

AD620

TYPICAL PERFORMANCE CHARACTERISTICS

(@ 25°C, VS = ±15 V, RL = 2 kΩ, unless otherwise noted.)

50

SAMPLE SIZE = 360

40

30

20

PERCENTAGE OF UNITS

10

0

–80

–40 0 40 80

INPUT OFFSET VOLTAGE (µV)

Figure 5. Typical Distribution of Input Offset Voltage

50

SAMPLE SIZE = 850

40

30

20

00775-0-005

2.0

1.5

1.0

0.5

0

–0.5

–1.0

INPUT BIAS CURRENT (nA)

–1.5

–2.0

2.0

1.5

1.0

+I

B

1257525–25

–75

–I

B

TEMPERATURE (°C)

Figure 8. Input Bias Current vs. Temperature

175

00775-0-008

PERCENTAGE OF UNITS

10

0

–1200 1200

–600 0 600

INPUT BIAS CURRENT (pA)

Figure 6. Typical Distribution of Input Bias Current

50

SAMPLE SIZE = 850

40

30

20

PERCENTAGE OF UNITS

10

0

–400

–200 0 200 400

INPUT OFFSET CURRENT (pA)

Figure 7. Typical Distribution of Input Offset Current

00775-0-006

00775-0-007

0.5

CHANGE IN OFFSET VOLTAGE (µV)

0

01

WARM-UP TIME (Minutes)

432

5

Figure 9. Change in Input Offset Voltage vs. Warm-Up Time

1000

GAIN = 1

100

GAIN = 10

10

VOLTAGE NOISE (nV/ Hz)

GAIN = 100, 1,000

1

1 100k

10

FREQUENCY (Hz)

GAIN = 1000
BW LIMIT

10k1k100

Figure 10. Voltage Noise Spectral Density vs. Frequency (G = 1−1000)

00775-0-009

00775-0-010

Rev. G | Page 7 of 20

AD620

1000

100

CURRENT NOISE (fA/ Hz)

10

1

10

FREQUENCY (Hz)

100

Figure 11. Current Noise Spectral Density vs. Frequency

V/DIV)

µ

RTI NOISE (2.0

TIME (1 SEC/DIV)

Figure 12. 0.1 Hz to 10 Hz RTI Voltage Noise (G = 1)

1000

00775-0-011

00775-0-012

Figure 14. 0.1 Hz to 10 Hz Current Noise, 5 pA/Div

100,000

V)

µ

10,000

C, RTI (

°

C TO 85

°

1000

100

TOTAL DRIFT FROM 25

10

1k 10M

10k 1M100k

SOURCE RESISTANCE (

FET INPUT
IN-AMP

Ω

)

Figure 15. Total Drift vs. Source Resistance

AD620A

00775-0-014

00775-0-015

V/DIV)

µ

RTI NOISE (0.1

TIME (1 SEC/DIV)

Figure 13. 0.1 Hz to 10 Hz RTI Voltage Noise (G = 1000)

00775-0-013

Rev. G | Page 8 of 20

160

140

120

100

CMR (dB)

G = 1000

G = 100

G = 10

G = 1

80

60

40

20

0

0.1

1

FREQUENCY (Hz)

100k10k1k10010

1M

Figure 16. Typical CMR vs. Frequency, RTI, Zero to 1 kΩ Source Imbalance

00775-0-016

AD620

180

160

140

120

100

PSR (dB)

80

60

40

20

0.1

1

FREQUENCY (Hz)

G = 1000

G = 100

G = 10

G = 1

100k10k1k10010

1M

00775-0-017

35

G = 10, 100, 1000

30

25

20

15

10

OUTPUT VOLTAGE (V p-p)

5

0

G = 1

G = 1000

1k

BW LIMIT

G = 100

10k

FREQUENCY (Hz)

100k

1M

00775-0-020

Figure 17. Positive PSR vs. Frequency, RTI (G = 1−1000)

180

160

140

120

100

PSR (dB)

80

60

40

20

0.1

1

FREQUENCY (Hz)

Figure 18. Negative PSR vs. Frequency, RTI (G = 1−1000)

1000

100

G = 1000

G = 100

G = 10

G = 1

100k10k1k10010

1M

00775-0-018

Figure 20. Large Signal Frequency Response

+VS–0.0

–0.5

–1.0

–1.5

+1.5

+1.0

INPUT VOLTAGE LIMIT (V)

(REFERRED TO SUPPLY VOLTAGES)

+0.5

+0.0

–V

S

50

SUPPLY VOLTAGE

± Volts

Figure 21. Input Voltage Range vs. Supply Voltage, G = 1

+V

–0.0

S

–0.5

–1.0

RL = 2k

–1.5

Ω

RL = 10k

1510

Ω

20

00775-0-021

10

GAIN (V/V)

1

0.1
100 10M

1k

FREQUENCY (Hz)

100k 1M10k

Figure 19. Gain vs. Frequency

00775-0-019

Rev. G | Page 9 of 20

OUTPUT VOLTAGE SWING (V)

(REFERRED TO SUPPLY VOLTAGES)

–V

+1.5

+1.0

+0.5

+0.0

S

0

5

SUPPLY VOLTAGE ± Volts

RL = 10k

RL = 2k

Ω

Ω

Figure 22. Output Voltage Swing vs. Supply Voltage, G = 10

1510

20

00775-0-022

AD620

30

VS = ±15V
G = 10

20

10

OUTPUT VOLTAGE SWING (V p-p)

0

0

100 1k
LOAD RESISTANCE (

Ω)

Figure 23. Output Voltage Swing vs. Load Resistance

............................ ............

10k

00775-0-023

.................... ....................

.................... ....................

00775-0-026

Figure 26. Large Signal Response and Settling Time, G = 10 (0.5 mV = 0.01%)

........ ................................

............................ ............

Figure 24. Large Signal Pulse Response and Settling Time

G = 1 (0.5 mV = 0.01%)

.................... ....................

.................... ....................

Figure 25. Small Signal Response, G = 1, R

= 2 kΩ, CL = 100 pF

L

00775-0-024

00775-0-025

........ ................................

00775-0-027

Figure 27. Small Signal Response, G = 10, R

= 2 kΩ, CL = 100 pF

L

........................ ................

........................ ................

00775-0-030

Figure 28. Large Signal Response and Settling Time, G = 100 (0.5 mV = 0.01%)

Rev. G | Page 10 of 20

AD620

20

............................ ............

............................ ............

Figure 29. Small Signal Pulse Response, G = 100, R

........................ ................

........................ ................

00775-0-029

= 2 kΩ, CL = 100 pF

L

15

10

SETTLING TIME (µs)

5

0

02

5

OUTPUT STEP SIZE (V)

TO 0.01%

TO 0.1%

10 0

15

00775-0-032

Figure 32. Settling Time vs. Step Size (G = 1)

1000

s)

100

µ

(

10

SETTLING TIME

Figure 30. Large Signal Response and Settling Time,

G = 1000 (0.5 mV = 0.01% )

............................ ............

............................ ............

Figure 31. Small Signal Pulse Response, G = 1000, R

00775-0-030

00775-0-031

= 2 kΩ, CL = 100 pF

L

1

1 1000

10 100

GAIN

Figure 33. Settling Time to 0.01% vs. Gain, for a 10 V Step

............................ ............

............................ ............

Figure 34. Gain Nonlinearity, G = 1, R

= 10 kΩ (10 µV = 1 ppm)

L

00775-0-033

00775-0-034

Rev. G | Page 11 of 20

AD620

Ω

.................... ............ ........

.................... ............ ........

Figure 35. Gain Nonlinearity, G = 100, R

= 10 kΩ

L

(100 µV = 10 ppm)

........ ................................

00775-0-035

INPUT

10V p-p

100k

Ω

11kΩ1kΩ100

G = 1000

49.9

*ALL RESISTORS 1% TOLERANCE

Figure 37. Settling Time Test Circuit

Ω

Ω

G=100

499

Ω

10kΩ*

G=1

G=10

5.49k

1k

2

1

AD620

Ω

8
3

10T

10k

Ω

V

OUT

+V

S

7

6

5

4

–V

S

00775-0-037

........ ................................

00775-0-036

Figure 36. Gain Nonlinearity, G = 1000, R

= 10 kΩ

L

(1 mV = 100 ppm)

Rev. G | Page 12 of 20

AD620

Ω

Ω

THEORY OF OPERATION

– IN

R3

400Ω

20µA

I1

Q1

Figure 38. Simplified Schematic of AD620

A1 A2

C1

R1

GAIN

SENSE

R

–V

V

B

G

S

R2

GAIN

SENSE

20µA

C2

I2

10kΩ

10kΩ

A3

10kΩ

Q2

R4

400Ω

10kΩ

+IN

OUTPUT

REF

The AD620 is a monolithic instrumentation amplifier based on
a modification of the classic three op amp approach. Absolute
value trimming allows the user to program gain accurately
(to 0.15% at G = 100) with only one resistor. Monolithic
construction and laser wafer trimming allow the tight matching
and tracking of circuit components, thus ensuring the high level
of performance inherent in this circuit.

00775-0-038

The input transistors Q1 and Q2 provide a single differential­pair bipolar input for high precision (Figure 38), yet offer 10×
lower input bias current thanks to Superϐeta processing.
Feedback through the Q1-A1-R1 loop and the Q2-A2-R2 loop
maintains constant collector current of the input devices Q1
and Q2, thereby impressing the input voltage across the external
gain setting resistor R
inputs to the A1/A2 outputs given by G = (R1 + R2)/R

. This creates a differential gain from the

G

+ 1. The

G

unity-gain subtractor, A3, removes any common-mode signal,
yielding a single-ended output referred to the REF pin potential.

The value of R
preamp stage. As R

also determines the transconductance of the

G

is reduced for larger gains, the

G

transconductance increases asymptotically to that of the input
transistors. This has three important advantages: (a) Open-loop
gain is boosted for increasing programmed gain, thus reducing
gain related errors. (b) The gain-bandwidth product
(determined by C1 and C2 and the preamp transconductance)
increases with programmed gain, thus optimizing frequency
response. (c) The input voltage noise is reduced to a value of
9 nV/√Hz, determined mainly by the collector current and base
resistance of the input devices.

The internal gain resistors, R1 and R2, are trimmed to an
absolute value of 24.7 kΩ, allowing the gain to be programmed
accurately with a single external resistor.

The gain equation is then

4.49

k

1

=

G

=

R

G

+

R

G

G

k

4.49
1

−

Make vs. Buy: a Typical Bridge Application Error Budget

The AD620 offers improved performance over “homebrew”
three op amp IA designs, along with smaller size, fewer
components, and 10× lower supply current. In the typical
application, shown in Figure 39, a gain of 100 is required to
amplify a bridge output of 20 mV full-scale over the industrial
temperature range of −40°C to +85°C. Table 3 shows how to
calculate the effect various error sources have on circuit
accuracy.

Rev. G | Page 13 of 20

AD620

R

Regardless of the system in which it is being used, the AD620
provides greater accuracy at low power and price. In simple
systems, absolute accuracy and drift errors are by far the most
significant contributors to error. In more complex systems
with an intelligent processor, an autogain/autozero cycle will
remove all absolute accuracy and drift errors, leaving only the
resolution errors of gain, nonlinearity, and noise, thus allowing
full 14-bit accuracy.

Note that for the homebrew circuit, the OP07 specifications for
input voltage offset and noise have been multiplied by √2. This
is because a three op amp type in-amp has two op amps at its
inputs, both contributing to the overall input error.

R = 350

Ω

R = 350

Ω

PRECISION BRIDGE TRANSDUCE

10V

R = 350

R = 350

R

G

Ω

Ω

00775-0-039

499

SUPPLY CURRENT = 1.3mA MAX

AD620A

Ω

AD620A MONOLITHIC
INSTRUMENTATION
AMPLIFIER, G = 100

REFERENCE

00775-0-040

100

OP07D

Ω

**

OP07D

"HOMEBREW" IN-AMP, G = 100
*0.02% RESISTOR MATCH, 3ppm/
**DISCRETE 1% RESISTOR, 100ppm/
SUPPLY CURRENT = 15mA MAX

10k

10k

Ω

**

10k

Ω

**

10k

Ω

*

Ω

*

°

C TRACKING

10k

Ω

OP07D

Ω

10k

°

C TRACKING

*

*

00775-0-041

Figure 39. Make vs. Buy

Table 3. Make vs. Buy Error Budget

Error, ppm of Full Scale
Error Source AD620 Circuit Calculation “Homebrew” Circuit Calculation AD620 Homebrew

ABSOLUTE ACCURACY at TA = 25°C
Input Offset Voltage, µV 125 µV/20 mV (150 µV × √2)/20 mV 6,250 10,607
Output Offset Voltage, µV 1000 µV/100 mV/20 mV ((150 µV × 2)/100)/20 mV 500 150
Input Offset Current, nA 2 nA ×350 Ω/20 mV (6 nA ×350 Ω)/20 mV 18 53
CMR, dB 110 dB(3.16 ppm) ×5 V/20 mV (0.02% Match × 5 V)/20 mV/100 791 500

Total Absolute Error 7,559 11,310
DRIFT TO 85°C
Gain Drift, ppm/°C (50 ppm + 10 ppm) ×60°C 100 ppm/°C Track × 60°C 3,600 6,000
Input Offset Voltage Drift, µV/°C 1 µV/°C × 60°C/20 mV (2.5 µV/°C × √2 × 60°C)/20 mV 3,000 10,607
Output Offset Voltage Drift, µV/°C 15 µV/°C × 60°C/100 mV/20 mV (2.5 µV/°C × 2 × 60°C)/100 mV/20 mV 450 150

Total Drift Error 7,050 16,757
RESOLUTION
Gain Nonlinearity, ppm of Full Scale 40 ppm 40 ppm 40 40
Typ 0.1 Hz to 10 Hz Voltage Noise, µV p-p 0.28 µV p-p/20 mV (0.38 µV p-p × √2)/20 mV 14 27
Total Resolution Error 54 67
Grand Total Error 14,663 28,134

G = 100, VS = ±15 V.
(All errors are min/max and referred to input.)

Rev. G | Page 14 of 20

AD620

5V

7

3k

3k

Ω

3k

Ω

1.7mA 0.10mA

Ω

G = 100

3k

499

Ω

3
8

1
2

1.3mA

AD620B

5

4

MAX

Ω

Figure 40. A Pressure Monitor Circuit that Operates on a 5 V Single Supply

Pressure Measurement

Although useful in many bridge applications, such as weigh
scales, the AD620 is especially suitable for higher resistance
pressure sensors powered at lower voltages where small size and
low power become more significant.

Figure 40 shows a 3 kΩ pressure transducer bridge powered
from 5 V. In such a circuit, the bridge consumes only 1.7 mA.
Adding the AD620 and a buffered voltage divider allows the
signal to be conditioned for only 3.8 mA of total supply current.

Small size and low cost make the AD620 especially attractive for
voltage output pressure transducers. Since it delivers low noise
and drift, it will also serve applications such as diagnostic
noninvasive blood pressure measurement.

20k

Ω

REF

6

10k

Ω

20k

AD705

Ω

0.6mA
MAX

IN

AGND

ADC

DIGITAL
DATA
OUTPUT

00775-0-042

Medical ECG

The low current noise of the AD620 allows its use in ECG
monitors (Figure 41) where high source resistances of 1 MΩ or
higher are not uncommon. The AD620’s low power, low supply
voltage requirements, and space-saving 8-lead mini-DIP and
SOIC package offerings make it an excellent choice for battery­powered data recorders.

Furthermore, the low bias currents and low current noise,
coupled with the low voltage noise of the AD620, improve the
dynamic range for better performance.

The value of capacitor C1 is chosen to maintain stability of
the right leg drive loop. Proper safeguards, such as isolation,
must be added to this circuit to protect the patient from
possible harm.

PATIENT/CIRCUIT

PROTECTION/ISOLATION

R1

C1

Ω

10k

R4

1M

Ω

R3

24.9k

R2

24.9k

Ω

R

G

8.25k

Ω

Ω

+3V

AD620A

G = 7

0.03Hz
HIGH-

PASS

FILTER

G = 143

OUTPUT

AMPLIFIER

OUTPUT
1V/mV

AD705J

–3V

00775-0-043

Figure 41. A Medical ECG Monitor Circuit

Rev. G | Page 15 of 20

AD620

Precision V-I Converter

The AD620, along with another op amp and two resistors,
makes a precision current source (Figure 42). The op amp
buffers the reference terminal to maintain good CMR. The
output voltage, V
converts it to a current. This current, less only the input bias
current of the op amp, then flows out to the load.

V

IN+

R

V

IN–

Figure 42. Precision Voltage-to-Current Converter (Operates on 1.8 mA, ±3 V)

GAIN SELECTION

The AD620’s gain is resistor-programmed by RG, or more
precisely, by whatever impedance appears between Pins 1 and 8.
The AD620 is designed to offer accurate gains using 0.1% to 1%
resistors. Table 4 shows required values of R
Note that for G = 1, the R
any arbitrary gain, R

, of the AD620 appears across R1, which

X

+V

S

7

3
8

G

AD620

1

I =

2

L

4

–V

S

[(V ) – (V )] G

V

x

IN+

=

R1

G

R1

pins are unconnected (RG = ∞). For

G

can be calculated by using the formula:

6

5

AD705

IN–

+ V –

X

R1

I

LOAD

for various gains.

G

L

00775-0-044

INPUT AND OUTPUT OFFSET VOLTAGE

The low errors of the AD620 are attributed to two sources,
input and output errors. The output error is divided by G when
referred to the input. In practice, the input errors dominate at
high gains, and the output errors dominate at low gains. The
total V

for a given gain is calculated as

OS

Total Error RTI = input error + (output error/G)

Total Error RTO = (input error × G) + output error

REFERENCE TERMINAL

The reference terminal potential defines the zero output voltage
and is especially useful when the load does not share a precise
ground with the rest of the system. It provides a direct means of
injecting a precise offset to the output, with an allowable range
of 2 V within the supply voltages. Parasitic resistance should be
kept to a minimum for optimum CMR.

INPUT PROTECTION

The AD620 features 400 Ω of series thin film resistance at its
inputs and will safely withstand input overloads of up to ±15 V
or ±60 mA for several hours. This is true for all gains and power
on and off, which is particularly important since the signal
source and amplifier may be powered separately. For longer
time periods, the current should not exceed 6 mA

≤ VIN/400 Ω). For input overloads beyond the supplies,

(I

IN

clamping the inputs to the supplies (using a low leakage diode
such as an FD333) will reduce the required resistance, yielding
lower noise.

R

G

1

G

4.49−Ω

k

=

To minimize gain error, avoid high parasitic resistance in series

; to minimize gain drift, RG should have a low TC—less

with R

G

than 10 ppm/°C—for the best performance.

Table 4. Required Values of Gain Resistors

1% Std Table
Value of R

(Ω)

G

Calculated
Gain

0.1% Std Table
Value of RG(Ω )

Calculated
Gain

49.9 k 1.990 49.3 k 2.002

12.4 k 4.984 12.4 k 4.984

5.49 k 9.998 5.49 k 9.998

2.61 k 19.93 2.61 k 19.93

1.00 k 50.40 1.01 k 49.91
499 100.0 499 100.0
249 199.4 249 199.4
100 495.0 98.8 501.0

49.9 991.0 49.3 1,003.0

RF INTERFERENCE

All instrumentation amplifiers rectify small out of band signals.
The disturbance may appear as a small dc voltage offset. High
frequency signals can be filtered with a low pass R-C network
placed at the input of the instrumentation amplifier. Figure 43
demonstrates such a configuration. The filter limits the input
signal according to the following relationship:

FilterFreq

FilterFreq

where C

C

≥10CC.

D

affects the difference signal. CC affects the common-mode

D

DIFF

CM

=

=

2

1

D

1

RC

π

C

signal. Any mismatch in R × C
CMRR. To avoid inadvertently reducing CMRR-bandwidth
performance, make sure that C
smaller than C
larger C

. The effect of mismatched CCs is reduced with a

D

ratio.

D:CC

)2(2

CCR

+π

C

will degrade the AD620’s

C

is at least one magnitude

C

Rev. G | Page 16 of 20

AD620

+15V

0.1µ F1µ F0

C

C

R

C

R

C

+IN

+

AD620

499Ω

D

–

–IN

C

0.1µ F1µ F0

–15V

REF

V

OUT

00775-0-045

Figure 43. Circuit to Attenuate RF Interference

COMMON-MODE REJECTION

Instrumentation amplifiers, such as the AD620, offer high
CMR, which is a measure of the change in output voltage when
both inputs are changed by equal amounts. These specifications
are usually given for a full-range input voltage change and a
specified source imbalance.

For optimal CMR, the reference terminal should be tied to a
low impedance point, and differences in capacitance and
resistance should be kept to a minimum between the two
inputs. In many applications, shielded cables are used to
minimize noise; for best CMR over frequency, the shield
should be properly driven. Figure 44 and Figure 45 show active
data guards that are configured to improve ac common-mode
rejections by “bootstrapping” the capacitances of input cable
shields, thus minimizing the capacitance mismatch between the
inputs.

+V

S

AD620

–V

S

REFERENCE

V

OUT

100

100

AD648

Ω

Ω

– INPUT

–V

+ INPUT

R

G

S

Figure 44. Differential Shield Driver

+V

100Ω

– INPUT

AD548

+ INPUT

R

G

2

R

G

2

AD620

–V

S

S

REFERENCE

V

OUT

Figure 45. Common-Mode Shield Driver

GROUNDING

Since the AD620 output voltage is developed with respect to the
potential on the reference terminal, it can solve many
grounding problems by simply tying the REF pin to the
appropriate “local ground.”

To isolate low level analog signals from a noisy digital
environment, many data-acquisition components have separate
analog and digital ground pins (Figure 46). It would be
convenient to use a single ground line; however, current
through ground wires and PC runs of the circuit card can cause
hundreds of millivolts of error. Therefore, separate ground
returns should be provided to minimize the current flow from
the sensitive points to the system ground. These ground returns
must be tied together at some point, usually best at the ADC
package shown in Figure 46.

ANALOG P.S.

+15V C –15V

DIGITAL P.S.

+5VC

00775-0-046

00775-0-047

Rev. G | Page 17 of 20

0.1µF

AD620

0.1µF

AD585

S/H

1µF

µ

F

1

AD574A

ADC

Figure 46. Basic Grounding Practice

1µF

+

DIGITAL
DATA
OUTPUT

00775-0-048

AD620

GROUND RETURNS FOR INPUT BIAS CURRENTS

Input bias currents are those currents necessary to bias the
input transistors of an amplifier. There must be a direct return
path for these currents. Therefore, when amplifying “floating”
input sources, such as transformers or ac-coupled sources, there
must be a dc path from each input to ground, as shown in
Figure 47, Figure 48, and Figure 49. Refer to A Designer’s Guide
to Instrumentation Amplifiers (free from Analog Devices) for
more information regarding in-amp applications.

+V

AD620

–V

S

S

REFERENCE

LOAD

TO POWER

SUPPLY

GROUND

V

OUT

– INPUT

R

G

+ INPUT

Figure 47. Ground Returns for Bias Currents with Transformer-Coupled Inputs

+V

AD620

–V

S

S

REFERENCE

V

LOAD

TO POWER

SUPPLY

GROUND

OUT

00775-0-050

– INPUT

+ INPUT

R

G

Figure 48. Ground Returns for Bias Currents with Thermocouple Inputs

+V

AD620

–V

S

S

REFERENCE

LOAD

TO POWER

SUPPLY

GROUND

V

OUT

00775-0-051

– INPUT

R

G

00775-0-049

+ INPUT

100k

Ω

100k

Ω

Figure 49. Ground Returns for Bias Currents with AC-Coupled Inputs

Rev. G | Page 18 of 20

AD620

OUTLINE DIMENSIONS

0.400 (10.16)

0.365 (9.27)

0.355 (9.02)

8

5

0.280 (7.11)

4

0.250 (6.35)

0.240 (6.10)

0.015
(0.38)
MIN

SEATING
PLANE

0.005 (0.13)
MIN

0.060 (1.52)
MAX

0.015 (0.38)
GAUGE

PLANE

1

PIN 1

0.100 (2.54)

0.210
(5.33)

MAX

0.150 (3.81)

0.130 (3.30)

0.115 (2.92)

0.022 (0.56)

0.018 (0.46)

0.014 (0.36)

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.

BSC

0.070 (1.78)

0.060 (1.52)

0.045 (1.14)

COMPLIANT TO JEDEC STANDARDS MS-001-BA

Figure 50. 8-Lead Plastic Dual In-Line Package [PDIP]

Narrow Body (N-8).

Dimensions shown in inches and (millimeters)

0.325 (8.26)

0.310 (7.87)

0.300 (7.62)

0.430 (10.92)
MAX

0.195 (4.95)

0.130 (3.30)

0.115 (2.92)

0.014 (0.36)

0.010 (0.25)

0.008 (0.20)

5.00 (0.1968)

4.80 (0.1890)

4.00 (0.1574)

3.80 (0.1497)

0.25 (0.0098)

0.10 (0.0040)

COPLANARITY

0.10

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

85

1.27 (0.0500)
BSC

0.51 (0.0201)

SEATING

COMPLIANT TO JEDEC STANDARDS MS-012AA

0.31 (0.0122)

PLANE

Figure 52. 8-Lead Standard Small Outline Package [SOIC]

Dimensions shown in millimeters and (inches)

6.20 (0.2440)

5.80 (0.2284)

41

1.75 (0.0688)

1.35 (0.0532)

0.25 (0.0098)

0.17 (0.0067)

Narrow Body (R-8)

0.50 (0.0196)

0.25 (0.0099)

8°

1.27 (0.0500)

0°

0.40 (0.0157)

× 45°

0.005 (0.13)

PIN 1

0.200 (5.08)
MAX

0.200 (5.08)

0.125 (3.18)

0.023 (0.58)

0.014 (0.36)

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

0.055 (1.40)

MIN

0.100 (2.54) BSC

0.405 (10.29) MAX

MAX

85

0.310 (7.87)

4

0.070 (1.78)

0.030 (0.76)

0.220 (5.59)

0.060 (1.52)

0.015 (0.38)

1

0.150 (3.81)
MIN

SEATING
PLANE

0.320 (8.13)

0.290 (7.37)

15°

0°

0.015 (0.38)

0.008 (0.20)

Figure 51. 8-Lead Ceramic Dual In-Line Package [CERDIP] (Q-8)

Dimensions shown in inches and (millimeters)

Rev. G | Page 19 of 20

AD620

ORDERING GUIDE

Model Temperature Range Package Option1

AD620AN −40°C to +85°C N-8
AD620ANZ2 −40°C to +85°C N-8
AD620BN −40°C to +85°C N-8
AD620BNZ2 −40°C to +85°C N-8
AD620AR −40°C to +85°C R-8
AD620ARZ2 −40°C to +85°C R-8
AD620AR-REEL −40°C to +85°C 13" REEL
AD620ARZ-REEL2 −40°C to +85°C 13" REEL
AD620AR-REEL7 −40°C to +85°C 7" REEL
AD620ARZ-REEL72 −40°C to +85°C 7" REEL
AD620BR −40°C to +85°C R-8
AD620BRZ2 −40°C to +85°C R-8
AD620BR-REEL −40°C to +85°C 13" REEL
AD620BRZ-RL2 −40°C to +85°C 13" REEL
AD620BR-REEL7 −40°C to +85°C 7" REEL
AD620BRZ-R72 −40°C to +85°C 7" REEL
AD620ACHIPS −40°C to +85°C Die Form
AD620SQ/883B −55°C to +125°C Q-8

1

N = Plastic DIP; Q = CERDIP; R = SOIC.

2

Z = Pb-free part.

© 2004 Analog Devices, Inc. All rights reserved. Trademarks
and

registered trademarks are the property of their respective owners.

C00775–0–12/04(G)

Rev. G | Page 20 of 20