Analog Devices AD6121 b Datasheet

CDMA 3 V Receiver IF Subsystem

a

FEATURES
Fully Compliant with IS98A and PCS Specifications
CDMA, W-CDMA, AMPS, and TACS Operation
Linear IF Amplifier

5.9 dB Noise Figure
–47.5 dB to +47 dB Linear-in-dB Gain Control

Quadrature Demodulator

Demodulates IFs from 50 MHz to 350 MHz

Integral Low Dropout Regulator

200 mV Voltage Drop
Accepts 2.9 V to 4.2 V Input from Battery

Low Power

10 mA at Midgain
<1 ␮A Sleep Mode Operation

Companion Transmitter IF Chip Available (AD6122)

APPLICATIONS
CDMA, W-CDMA, AMPS, and TACS Operation
QPSK Receivers

with Integrated Voltage Regulator

AD6121

GENERAL DESCRIPTION

The AD6121 is a low power receiver IF subsystem specifically
designed for CDMA applications. It consists of high dynamic
range IF amplifiers with voltage controlled gain, a divide-by-two
quadrature generator, an I and Q demodulator, and a power­down control input. An integral low dropout regulator allows
operation from battery voltages from 2.9 V to 4.2 V.

The gain control input accepts an external gain control voltage
input from a DAC. It provides 94.5 dB of gain control with a
nominal 52.5 dB/V scale factor when using an internal voltage
reference. The gain control interface reference input can be
connected to either the internal reference or an external reference.

The I and Q demodulator provides differential quadrature base­band outputs to interface with CDMA baseband converters. A
divide-by-two quadrature generator followed by dual polyphase
filters ensures maximum ±2.5° quadrature accuracy.

The AD6121 IF Subsystem is fabricated using a 25 GHz f
BiCMOS silicon process and is packaged in a 28-lead SSOP
and a 32-leadless LPCC chip scale package (5 mm × 5 mm).

t

CDMA
INPUT

FM

INPUT

INPUT STAGE

CDMA/FM

SELECT

FUNCTIONAL BLOCK DIAGRAM

IF AMPLIFIERS

PTAT

TEMPERATURE

COMPENSATION

IF

OUTPUT

GAIN
CONTROL
VOLTAGE

INPUT

ROOFING

FILTER

AD6121

GAIN CONTROL
SCALE FACTOR

GAIN
CONTROL
VOLTAGE

REFERENCE

INPUT

DEMODULATOR
INPUT

I

2

Q

QUADRATURE DEMODULATOR

VREG

1.23V

REFERENCE

OUTPUT

LOW

DROPOUT

REGULATOR

POWER­DOWN 2

POWER­DOWN 1

IOUT

IOUT

LOCAL
OSCILLATOR
INPUT

QOUT

QOUT

VPOS

REV. B

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 2000

(TA = +25ⴗC, VCC = 3.0 V, LO = 2 ⴛ IF, REFIN = 1.23 V, LDO Enabled, unless otherwise

AD6121–SPECIFICATIONS

Specification Conditions Min Typ Max Units

TOTAL GAIN

Maximum Gain IF Amplifiers and Demodulator Powered Up +47 dB

IF Amplifiers Powered Up and Demodulator Powered Down +41.4 dB

Minimum Gain IF Amplifier and Demodulator Powered Up –47.5 dB

IF AMPLIFIER

CDMA and FM Input IF = 85.38 MHz

Noise Figure Maximum Gain 5.9 dB
Input Third-Order Intercept Maximum Gain –42.8 dBm
Input 1 dB Compression Point Maximum Gain –51.6 dBm
Gain Flatness IF ± 630 kHz, CDMA Mode ± 0.25 dB
CDMA Input Capacitance Differential 2.8 pF
CDMA Input Resistance Differential 850 Ω
FM Input Capacitance Differential 2.3 pF
FM Input Resistance Differential 670 Ω
Output Capacitance Differential 1.35 pF
Output Resistance Differential 1.1 kΩ

GAIN CONTROL INTERFACE

Gain Scaling Using Internal Reference 52.5 dB/V
Gain Scaling Accuracy Within a Gain Control Range of 90 dB ± 3 dB/V
Gain Control Response Time Minimum Gain to Maximum Gain 695 ns
Input Resistance at REFIN 10 MΩ
Input Resistance at VGAIN 100 kΩ

DEMODULATOR LO = 172.76 MHz , –15 dBm Referred to 50 Ω,

Baseband Frequency = 1 MHz
Differential Input Impedance 1kΩ
Differential Input Capacitance at

Demodulator Input 2.9 pF
Input Third Order Intercept –6.1 dBm
Demodulation Gain 5.6 dB
I/Q Output

Differential Output Voltage 10 kΩ, 2 pF Differential Parallel Load Impedance 700 mV p-p

Bandwidth –3 dB 16 MHz

Resistance Single-Ended 630 Ω

Quadrature Accuracy ± 2.5 Degree

Amplitude Balance ± 0.1 ± 0.35 dB
LO Input Impedance Differential 1.5 kΩ
LO Input Capacitance Differential 4.16 pF

CONTROL INTERFACES

Logic Threshold High 1.34 V
Logic Threshold Low 1.30 V
Input Current for Logic High 0.1 µA
Mode Control Response Time CDMA/FM Pin High Selects CDMA, Low Selects FM 430 ns
Turn-On Response Time PD1 and PD2 Pins Low Select IC ON, High Selects IC OFF 2.8 µs
Turn-Off Response Time To 200 µA Supply Current 6.8 µs

LOW DROPOUT REGULATOR External PNP Pass Transistor, VCE

h
Input Range 2.9 4.2 V
Nominal Output 2.70 V
Voltage Drop 200 mV
Reference Output 1.23 V

POWER SUPPLY

Supply Range Using Internal LDO Supply Input at Pin LDOE 2.9–5.0 V
Supply Range Bypassing Internal LDO Supply Input at Pins DVCC, IFVCC, LDOC 2.7–3.6 V
Supply Current VGAIN = 1.5 V 10 mA
Standby Current 0.78 µA

OPERATING TEMPERATURE

T

to T

MIN

Specifications subject to change without notice.

MAX

FE

noted) Note: All power measurements in dBm are referred to 1 k⍀ unless ZIN is noted.

= –0.4 V Max

= 100/300 Min/Max

SAT

–40 +85 °C

–2–

REV. B

AD6121

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS

Supply Voltage VPS1, VPS2 to COM1, COM2 . . . . . . . +5 V

Internal Power Dissipation

2

. . . . . . . . . . . . . . . . . . . 600 mW

1

Operating Temperature Range . . . . . . . . . . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Lead Temperature Range (Soldering 60 sec) . . . . . . . . +300°C

PIN CONFIGURATION

SSOP Package LPCC Package

CDMA/FM

CDMAIPP

CDMAIPN

IFGND

FMIPP

FMIPN

IFVCC

DGND

LOIPP

LOIPN

DVCC

LDOC

LDOB

LDOE

1

2

3

4

5

6

AD6121

7

TOP VIEW

(Not to Scale)

8

9

10

11

12

13

14

28

27

26

25

24

23

22

21

20

19

18

17

16

15

IFOPP

IFOPN

DEMIPN

DEMIPP

LDOGND

IOPP

IOPN

QOPP

QOPN

PD1

REFOUT

REFIN

VGAIN

PD2

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

2

Thermal Characteristics: 28-lead SSOP Package: θJA = 115.25°C/W.

IFOPN

IFGND

IFGND

FMIPP

FMIPN

IFVCC

LOIPP

CDMAIPP

CDMA/FM

CDMAIPN

32

1

2

3

4

AD6121 Top View

5

6

7

8

(Not to Scale)

10311130122913281427152616

9

NC

DVCC

LDOC

IFOPP

LDOB

LDOE

NC

DEMIPN

DEMIPP

25

24

LDOGND

23

LDOGND

22

IOPP

21

IOPN

20

QOPP

19DGND

QOPN

18

PD1

17LOIPN

REFOUT

PD2

REFIN

VGAIN

NC = NO CONNECT

ORDERING GUIDE

Temperature Package Package

Model Range Description Option

AD6121ARS –40°C to +85°C Shrink Small Outline Package (SSOP) RS-28
AD6121ARSRL –40°C to +85°C 28-Lead SSOP on Tape and Reel
AD6121ACP –40°C to +85°C Chip Scale Package (LPCC) CP-32
AD6121ACPRL –40°C to +85°C 32-Leadless LPCC on Tape and Reel

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD6121 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

REV. B

–3–

AD6121

PIN FUNCTION DESCRIPTIONS

SSOP LPCC
Pin Pin
Number Number Pin Label Description Function

1 30 CDMA/FM Selects CDMA or FM Input CMOS-compatible; HIGH = CDMA, LOW = FM.
2 31 CDMAIPP CDMA “Positive” Input AC-coupled, IF input from CDMA SAW filter.
3 32 CDMAIPN CDMA “Negative” Input AC-coupled, IF input from CDMA SAW filter.
4 1, 2 IFGND IF Ground Ground.
5 3 FMIPP FM “Positive” Input AC-coupled, IF input from FM SAW filter.
6 4 FMIPN FM “Negative” Input AC-coupled, IF input from FM SAW filter.
7 5 IFVCC IF VCC VCC for IF AGC amplifiers.
8 6 DGND Digital Ground Ground.
9 7 LOIPP Local Oscillator “Positive” Input AC-coupled, Differential Local Oscillator Input.
10 8 LOIPN Local Oscillator “Negative” Input AC-coupled, Differential Local Oscillator Input.

9, 25 NC No Connect
11 10 DVCC Digital VCC VCC for control logic.
12 11 LDOC Low Dropout Regulator Pass Connects to collector of external PNP pass transistor.

Transistor Collector Connection

13 12 LDOB Low Dropout Regulator Pass Connects to base of external PNP pass transistor.

Transistor Base Connection

14 13 LDOE Low Dropout Regulator Pass Connects to emitter of external PNP pass transistor

Transistor Emitter Connection and DVCC, IFVCC.

15 14 PD2 Demodulator Power-Down Demodulator Power-Down Control Input CMOS-

Control Input compatible; HIGH = Modulator Off, LOW = Modulator On.

16 15 VGAIN Gain Control Voltage Input Accepts gain control input voltage from external DAC.

Max Gain = 2.5 V. Min Gain = 0.5 V.

17 16 REFIN Gain Control Reference Input Accepts 1.23 V reference input from REFOUT (Pin 17)

or external reference.

18 17 REFOUT Reference Output Provides 1.23 V reference output to REFIN (Pin 18) and

CDMA baseband IC reference input so that gain control
DAC and AD6121 use same reference.

19 18 PD1 IF Amplifier Power-Down IF Amplifier Power-Down Control Input, CMOS com-

Control Input patible; HIGH = Entire IC Powers Down, LOW = IF

Amplifier On.
20 19 QOPN Q Output “Negative” Connects to Q “Negative” Input of baseband IC.
21 20 QOPP Q Output “Positive” Connects to Q “Positive” Input of baseband IC.
22 21 IOPN I Output “Negative” Connects to I “Negative” Input of baseband IC.
23 22 IOPP I Output “Positive” Connects to I “Positive” Input of baseband IC.
24 23, 24 LDOGND Ground Ground.
25 26 DEMIPP Demodulator “Positive” IF Input Demodulator input from roofing filter.
26 27 DEMIPN Demodulator “Negative” IF Input Demodulator input from roofing filter.
27 28 IFOPN IF Amplifier “Negative” IF Output IF output to roofing filter.
28 29 IFOPP IF Amplifier “Positive” IF Output IF output to roofing filter.

–4–

REV. B

Test Figures

AD6121

SOURCE

RF

SOURCE

RF

1:8

909⍀

110⍀

110⍀

10nF

10nF

1k⍀

CDMAIPP

CDMAIPN

AD6121

10nF

10nF

453⍀

453⍀

205⍀

IFOPP

IFOPN

INDUCTOR CHOSEN FOR PEAK RESPONSE
AT THE TEST FREQUENCY (SEE TEXT)

4:1

a. CDMA Input Port Characterization Impedance Match

RF

SOURCE

50⍀

453⍀

10nF

10nF

FMIPP

FMIPN

AD6121

IFOPP

IFOPN

b. FM Input Port Characterization Impedance Match

Figure 1. Quadrature Modulator Characterization Input and Output Impedance Matches

V–1

V–1

V–1

V–1

V

V

V

V

0.1␮F

P

N

0.1␮F

P

N

A=1

0.1␮F

A=1

0.1␮F

OUT

AD830

OUT

AD830

50⍀

50⍀

1:4

LO

SOURCE

ALL SIGNAL PATHS MUST BE EQUAL
LENGTHS FOR I/Q MEASUREMENTS

205⍀

453⍀

453⍀

10nF

10nF

10nF

10nF

DEMIPP

DEMIPN

AD6121

QUADRATURE

DEMODULATOR

LOIPP

LOIPN

IOPP

IOPN

QOPP

QOPN

+15V

X1

X2

Y1

Y2

–15V

+15V

X1

X2

Y1

Y2

–15V

TO
SPECTRUM
ANALYZER

I CHANNEL

Q CHANNEL

REV. B

R & S

SMT03

SYNC

REFERENCE

R & S

SMT03

SYNC

REFERENCE

R & S

SMT03

Figure 2. IF Amplifier Characterization Input and Output Impedance Matches

RF

RF

RF

HPE3610

POWER SUPPLY

CDMA
IN

IF OUT

AD6121

FM IN

DEMOD
IN

LO
INPUT

& SWITCH CONTROL

ALL DC MEASUREMENT

AND CONTROL SIGNALS

I CHANNEL

Q CHANNEL

DC I/O

HP34970A

DATA ACQUISITION

50⍀
TERMINATOR

Figure 3. General Test Set

–5–

CH1

HP8508A
VECTOR

VOLTMETER

CH2

RF INPUT

R&S FSEA
SPECTRUM
ANALYZER