Datasheet AD603 Datasheet (ANALOG DEVICES)

Low Noise, 90 MHz

www.BDTIC.com/ADI

FEATURES

Linear-in-dB gain control
Pin-programmable gain ranges

−11 dB to +31 dB with 90 MHz bandwidth
9 dB to 51 dB with 9 MHz bandwidth

Any intermediate range, for example −1 dB to +41 dB

with 30 MHz b

Bandwidth independent of variable gain

1.3 nV/√Hz input noise spectral density
±0.5 dB typical gain accuracy

APPLICATIONS

RF/IF AGC amplifiers
Video gain controls
A/D range extensions
Signal measurements

GENERAL DESCRIPTION

The AD603 is a low noise, voltage-controlled amplifier for use
in RF and IF AGC systems. It provides accurate, pin-selectable
gains of −11 dB to +31 dB with a bandwidth of 90 MHz or +9 dB to
51+ dB with a bandwidth of 9 MHz. Any intermediate gain
range may be arranged using one external resistor. The input
referred noise spectral density is only 1.3 nV/√Hz, and power
consumption is 125 mW at the recommended ±5 V supplies.

andwidth

Variable Gain Amplifier

AD603

The decibel gain is linear in dB, accurately calibrated, and stable

ver temperature and supply. The gain is controlled at a high

o
impedance (50 MΩ), low bias (200 nA) differential input; the
scaling is 25 mV/dB, requiring a gain control voltage of only
1 V to span the central 40 dB of the gain range. An overrange
and underrange of 1 dB is provided whatever the selected range.
The gain control response time is less than 1 μs for a 40 dB change.

The differential gain control interface allows the use of either

ferential or single-ended positive or negative control voltages.

dif
Several of these amplifiers may be cascaded and their gain
control gains offset to optimize the system SNR.

The AD603 can drive a load impedance as low as 100 Ω with
lo

w distortion. For a 500 Ω load in shunt with 5 pF, the total
harmonic distortion for a ±1 V sinusoidal output at 10 MHz is
typically −60 dBc. The peak specified output is ±2.5 V minimum
into a 500 Ω load.

The AD603 uses a patented proprietary circuit topology—the
X-AM

P®. The X-AMP comprises a variable attenuator of 0 dB
to −42.14 dB followed by a fixed-gain amplifier. Because of the
attenuator, the amplifier never has to cope with large inputs and
can use negative feedback to define its (fixed) gain and dynamic
performance. The attenuator has an input resistance of 100 Ω,
laser trimmed to ±3%, and comprises a 7-stage R-2R ladder
network, resulting in an attenuation between tap points of

6.021 dB. A proprietary interpolation technique provides a
continuous gain control function that is linear in dB.

The AD603 is specified for operation from −40°C to +85°C.

FUNCTIONAL BLOCK DIAGRAM

8

VPOS

6

VNEG

1

GPOS

2

GNEG

3

VINP

4

COMM

*NOMINAL VALUES.

Rev. H

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

SCALING

REFERENCE

V

G

GAIN-

CONTROL

INTERFACE

0dB –6.02dB –12.04dB –18.06dB –24.08dB –30.1dB –36.12dB –42.14dB

RRRRRRR

2R 2R 2R 2R 2R 2R R

R-2R LADDER NETWORK

PRECISION PASSIVE
INPUT ATTENUATOR

FIXED-GAIN

AMPLIFIER

7

VOUT

AD603

Figure 1.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2007 Analog Devices, Inc. All rights reserved.

6.44kΩ*

694Ω*

20Ω*

5

FDBK

00539-001

AD603

www.BDTIC.com/ADI

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

General Description......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Absolute Maximum Ratings............................................................ 4

ESD Caution.................................................................................. 4

Pin Configurations and Function Descriptions ...........................5

Typical Performance Characteristics ............................................. 6

Theory of Operation ...................................................................... 11

Noise Performance .....................................................................11

The Gain Control Interface....................................................... 12

REVISION HISTORY

5/07—Rev. G to Rev. H

Changes to Layout...........................................................................14

Changes to Layout...........................................................................15

Changes to Layout...........................................................................16

Inserted Evaluation Board Section, and Figure 48 to

Figure 51 ...........................................................................................19

Inserted Figure 52 and Table 4.......................................................20

Changes to Ordering Guide...........................................................21

3/05—Rev. F to Rev. G

U

pdated Format.................................................................. Universal

Change to Features............................................................................1

Changes to General Description .....................................................1

Change to Figure 1 ............................................................................1

Changes to Specifications.................................................................3

New Figure 4 and Renumbering Subsequent Figures...................6

Change to Figure 10 ..........................................................................7

Change to Figure 23 ..........................................................................9

Change to Figure 29 ........................................................................12

Updated Outline Dimensions........................................................20

Programming the Fixed-Gain Amplifier Using

Pin Strapping............................................................................... 12

Using the AD603 in Cascade........................................................ 14

Sequential Mode (Optimal SNR)............................................. 14

Parallel Mode (Simplest Gain Control Interface) .................. 16

Low Gain Ripple Mode (Minimum Gain Error) ................... 16

Applications Information.............................................................. 17

A Low Noise AGC Amplifier.................................................... 17

Caution........................................................................................ 18

Evaluation Board ............................................................................ 19

Outline Dimensions .......................................................................21

Ordering Guide .......................................................................... 21

4/04—Rev. E to Rev. F

hanges to Specifications.................................................................2

C

Changes to Ordering Guide............................................................. 3

8/03—Rev. D to Rev E

pdated Format.................................................................. Universal

U

Changes to Specifications.................................................................2

Changes to TPCs 2, 3, 4....................................................................4

Changes to Sequential Mode (Optimal S/N Ratio) section.........9

Change to Figure 8..........................................................................10

Updated Outline Dimensions........................................................14

Rev. H | Page 2 of 24

AD603

www.BDTIC.com/ADI

SPECIFICATIONS

@ TA = 25°C, VS = ±5 V, –500 mV ≤ VG ≤ +500 mV, GNEG = 0 V, –10 dB to +30 dB gain range, RL = 500 Ω, and CL = 5 pF, unless
otherwise noted.

Table 1.

Parameter Conditions Min Typ Max Unit

INPUT CHARACTERISTICS

Input Resistance Pin 3 to Pin 4 97 100 103 Ω
Input Capacitance 2 pF
Input Noise Spectral Density
Noise Figure f = 10 MHz, gain = maximum, RS = 10 Ω 8.8 dB
1 dB Compression Point f = 10 MHz, gain = maximum, RS = 10 Ω −11 dBm
Peak Input Voltage ±1.4 ±2 V

OUTPUT CHARACTERISTICS

−3 dB Bandwidth V
Slew Rate RL ≥ 500 Ω 275 V/μs
Peak Output

2

Output Impedance f ≤ 10 MHz 2 Ω
Output Short-Circuit Current 50 mA
Group Delay Change vs. Gain f = 3 MHz; full gain range ±2 ns
Group Delay Change vs. Frequency VG = 0 V; f = 1 MHz to 10 MHz ±2 ns
Differential Gain 0.2 %
Differential Phase 0.2 Degree
Total Harmonic Distortion f = 10 MHz, V
Third-Order Intercept f = 40 MHz, gain = maximum, RS = 50 Ω 15 dBm

ACCURACY

Gain Accuracy, f = 100 kHz; Gain (dB) = (40 VG + 10) dB −500 mV ≤ VG ≤ +500 mV −1 ±0.5 +1 dB

T

to T

MIN

MAX

Gain, f = 10.7 MHz VG = -0.5 V −10.3 −9.0 −8.0 dB
V
V
Output Offset Voltage

T

to T

MIN

MAX

Output Offset Variation vs. V

T

to T

MIN

MAX

GAIN CONTROL INTERFACE

Gain Scaling Factor 100 kHz 39.4 40 40.6 dB/V

T

to T

MIN

MAX

10.7 MHz 38.7 39.3 39.9 dB/V
GNEG, GPOS Voltage Range
Input Bias Current 200 nA
Input Offset Current 10 nA
Differential Input Resistance Pin 1 to Pin 2 50 MΩ
Response Rate Full 40 dB gain change 80 dB/μs

POWER SUPPLY

Specified Operating Range ±4.75 ±6.3 V
Quiescent Current 12.5 17 mA

T

to T

MIN

1

Typical open or short-circuited input; noise is lower when system is set to maximum gain and input is short-circuited. This figure includes the effects of both voltage

and current noise sources.

2

Using resistive loads of 500 Ω or greater or with the addition of a 1 kΩ pull-down resistor when driving lower loads.

3

The dc gain of the main amplifier in the AD603 is ×35.7; therefore, an input offset of 100 μV becomes a 3.57 mV output offset.

4

GNEG and GPOS, gain control, and voltage range are guaranteed to be within the range of −VS + 4.2 V to +VS − 3.4 V over the full temperature range of −40°C to +85°C.

MAX

1

Input short-circuited 1.3 nV/√Hz

= 100 mV rms 90 MHz

OUT

RL ≥ 500 Ω ±2.5 ±3.0 V

= 1 V rms −60 dBc

OUT

−1.5 +1.5 dB

= 0.0 V +9.5 +10.5 +11.5 dB

G

= 0.5 V +29.3 +30.3 +31.3 dB

3

G

VG = 0 V −20 +20 mV

−30 +30 mV

G

−500 mV ≤ VG ≤ +500 mV −20 +20 mV

−30 +30 mV

38 42 dB/V

4

−1.2 +2.0 V

20 mA

Rev. H | Page 3 of 24

AD603

www.BDTIC.com/ADI

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

Supply Voltage ±V
Internal Voltage VINP (Pin 3) ±2 V Continuous

±VS for 10 ms

GPOS, GNEG (Pin 1 and Pin2) ±V
Internal Power Dissipation 400 mW
Operating Temperature Range

AD603A −40°C to +85°C

AD603S −55°C to +125°C
Storage Temperature Range −65°C to +150°C
Lead Temperature (Soldering, 60 sec) 300°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

S

±7.5 V

S

Table 3. Thermal Characteristics

Package Type θ

8-Lead SOIC 155 33 °C/W
8-Lead CERDIP 140 15 °C/W

JA

θ

JC

Unit

ESD CAUTION

Rev. H | Page 4 of 24

AD603

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PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

1

GPOS

GNEG

VINP

COMM

AD603

2

3

TOP VIEW

(Not to Scale)

4

Figure 2. 8-Lead SOIC Pin Configuration

8

7

6

5

VPOS

VOUT

VNEG

FDBK

GPOS

GNEG

VINP

00539-002

COMM

Figure 3. 8-Lead CERDIP Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1 GPOS Gain Control Input High (Positive Voltage Increases Gain).
2 GNEG Gain Control Input Low (Negative Voltage Increases Gain).
3 VINP
4 COMM
5 FDBK
6 VNEG
7 VOUT

Amplifier Input.
Amplifier Ground.
Connection to Feedback Network.
Negative Supply Input.
Amplifier Output.

8 VPOS Positive Supply Input.

1

AD603

2

TOP VIEW

3

(Not to Scale)

4

8

7

6

5

VPOS

VOUT

VNEG

FDBK

00539-003

Rev. H | Page 5 of 24

AD603

L

A

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TYPICAL PERFORMANCE CHARACTERISTICS

@ TA = 25°C, VS = ±5 V, –500 mV ≤ VG ≤ +500 mV, GNEG = 0 V, –10 dB to +30 dB gain range, RL = 500 Ω, and CL = 5 pF, unless
otherwise noted.

40

30

20

10

GAIN (dB)

0

–10

10.7MHz

Figure 4. Gain vs. V

100kHz

VG (V)

at 100 kHz and 10.7 MHz

G

2.5

2.0

1.5

1.0

0.5

0

GAIN ERROR (d B)

–0.5

–1.0

–1.5

45MHz

70MHz

10.7MHz

455kHz

70MHz

GAIN VOLTAGE (V)

Figure 5. Gain Error vs. Gain Control Voltage at 455 kHz,

10.

7 MHz, 45 MHz, 70 MHz

4

3

2

1

0

–1

–2

GAIN (dB)

–3

–4

–5

–6

100k 1M 10M 100M

GAIN

PHASE

FREQUENCY ( Hz)

Figure 6. Frequency and Phase Response vs. Gain

(Gain

= −10 dB, P

= −30 dBm)

IN

0.6–0.6 –0.4 –0.2 0 0.2 0.4

0.5–0.5 –0.4 –0.3 –0.2 –0.1 0 0.1 0.2 0.3 0.4

225

180

135

90

45

0

–45

–90

–135

–180

–225

00539-004

00539-005

PHASE (Degrees)

00539-006

4

3

2

1

0

–1

–2

GAIN (dB)

–3

–4

–5

–6

100k 1M 10M 100M

GAIN

PHASE

FREQUENCY ( Hz)

Figure 7. Frequency and Phase Response vs. Gain

n = 10 dB, P

(Gai

4

3

2

1

0

–1

–2

GAIN (dB)

–3

–4

–5

–6

100k 1M 10M 100M

GAIN

PHASE

FREQUENCY ( Hz)

= −30 dBm)

IN

Figure 8. Frequency and Phase Response vs. Gain

(Gai

n = 30 dB, P

7.6

7.4

7.2

Y (ns)

7.0

6.8

GROUP DE

6.6

6.4

GAIN CONTRO L VOLTAGE (V)

= −30 dBm)

IN

Figure 9. Group Delay vs. Gain Control Voltage

0.6–0.6 –0.4 –0.2 0 0.2 0.4

225

180

135

90

45

0

–45

–90

–135

–180

–225

225

180

135

90

45

0

–45

–90

–135

–180

–225

PHASE (Degrees)

00539-007

PHASE (Degrees)

00539-008

00539-009

Rev. H | Page 6 of 24

AD603

G
A

–

(

(

www.BDTIC.com/ADI

0.1µF

+5V

HP3326A

DUAL-

CHANNEL

SYNTHESIZER

100Ω

0.1µF

3

AD603

4

–5V

8

6

DVC 8500

1

DATEL

5

2

10×

7

PROBE

511Ω

Figure 10. Third-Order Intermodulation Distortion Test Setup

10dB/DIV

HP3585A

SPECTRUM

ANALYZER

00539-010

1.0

–1.2

–1.4

–1.6

–1.8

–2.0

–2.2

–2.4

–2.6

TIVE OUTPUT VOLTAGE (V)

–2.8

–3.0

NE

–3.2

–3.4

0 50 100 200 500 1000 2000

LOAD RESISTANCE (Ω)

Figure 13. Typical Output Voltage Swing vs. Load Resistance

(Nega

tive Output Swing Limits First)

102

100

Ω)

00539-013

Figure 11. Third-Order Intermodulation Distortion at 455 kHz

0× Probe Used to HP3585A Spectrum Analyzer, Gain = 0 dB, P

(1

10dB/DIV

Figure 12. Third-Order Intermodulation Distortion at 10.7 MHz

(1

0× Probe Used to HP3585A Spectrum Analyzer, Gain = 0 dB, P

00539-011

= 0 dBm)

IN

00539-012

= 0 dBm)

IN

98

96

INPUT IMP EDANCE

94

FREQUENCY (Hz)

100M100k 1M 10M

00539-014

Figure 14. Input Impedance vs. Frequency (Gain = −10 dB)

102

100

Ω)

98

96

INPUT IMP EDANCE

94

FREQUENCY (Hz)

100M100k 1M 10M

00539-015

Figure 15. Input Impedance vs. Frequency (Gain = 10 dB)

Rev. H | Page 7 of 24

AD603

(

V

V

V

V

V

V

www.BDTIC.com/ADI

3

102

100

Ω)

98

96

INPUT IMP EDANCE

94

FREQUENCY (Hz)

Figure 16. Input Impedance vs. Frequency (Gain = 30 dB)

1V

100

90

10

0%

1V

200ns

Figure 17. Gain Control Channel Response Time

4.5

INPUT GND

100MV/DIV

1V

OUTPUT GND

1V/DIV

100M100k 1M 10M

00539-016

–2V

Figure 19. Output Stage Ove

rload Recovery Time

451ns–49ns 50ns

00539-019

(Input Is 500 ns Period, 50% Duty-Cycle Square Wave,

Output Is Captured Using Tektronix 11402 Digitizing Oscilloscope)

3.5

INPUT

500mV/DIV

GND

500m

OUTPUT

500mV/DIV

–1.5V

00539-017

GND

456ns–44ns 50ns

00539-020

Figure 20. Transient Response, G = 0 dB

(Input

Is 500 ns Period, 50% Duty-Cycle Square Wave,

Output Is Captured Using Tektronix 11402 Digitizing Oscilloscope)

3.5

INPUT GND

1V/DIV

500mV

–500mV

OUTPUT GND

500mV/DIV

451ns–49ns 50ns

00539-018

500m

–1.5V

Figure 18. Input Stage Overload Recovery Time

Is 500 ns Period, 50% Duty-Cycle Square Wave,

(Input

Output Is Captured Using Tektronix 11402 Digitizing Oscilloscope)

Output Is Captured Using Tektronix 11402 Digitizing Oscilloscope)

INPUT GND

100mV/DIV

OUTPUT GND

500mV/DIV

Figure 21. Transient Response, G = 20 dB

Is 500 ns Period, 50% Duty-Cycle Square Wave,

(Input

Rev. H | Page 8 of 24

456ns–44ns 50ns

00539-021

AD603

www.BDTIC.com/ADI

21

0

–10

–20

–30

–40

–50

PSRR (dB)

–60

19

17

15

13

11

NOISE FI GURE (dB)

9

7

10MHz

20MHz

TA = 25°C
R

= 50Ω

S

TEST SETUP FIGURE 23

FREQUENCY (Hz)

100M100k 1M 1 0M

Figure 22. PSRR vs. Frequency

(Wors

t Case Is Negative Supply PSRR, Shown Here)

0.1µF

+5V

HP3326A

DUAL-

CHANNEL

SYNTHESIZER

100Ω

0.1µF

8

3

AD603

4

6

–5V

5

2

1

DATEL

DVC 8500

7

SPECTRUM

ANALYZER

HP3585A

50Ω

Figure 23. Test Setup Used for: Noise Figure, Third-Order Intercept, and

ompression Point Measurements

1 dB C

23

21

19

17

15

13

11

NOISE FI GURE (dB)

9

7

5

70MHz

30MHz

GAIN (dB)

Figure 24. Noise Figure in −

TA = 25°C
R

= 50V

S

TEST SETUP FIGURE 23

50MHz

10MHz

10 dB/+30 dB Mode

3020 21 22 23 24 25 26 27 28 29

5

00539-022

GAIN (dB)

4030 31 32 33 34 35 36 37 38 39

00539-025

Figure 25. Noise Figure in 0 dB/40 dB Mode

0

–5

–10

–15

INPUT LEVEL (dBm)

–20

–25

00539-023

INPUT FREQUENCY (MHz)

TA = 25°C
TEST SETUP FIGURE 23

7010 30 50

00539-026

Figure 26. 1 dB Compression Point, −10 dB/+30 dB Mode, Gain = 30 dB

20

18

16

14

12

OUTPUT LEVEL (dBm)

10

0

00539-024

30MHz

40MHz

70MHz

INPUT LEVEL (dBm)

Figure 27. Third-Order Intercept −10 d

TA = 25°C
TEST SETUP FIGURE 23

0–20 –10

B/+30 dB Mode, Gain = 10 dB

00539-027

Rev. H | Page 9 of 24

AD603

www.BDTIC.com/ADI

20

18

30MHz

16

40MHz

14

12

OUTPUT LEVEL (dBm)

10

70MHz

TA = 25°C
R

= 50Ω

S

R

= 50Ω

IN

R

= 100Ω

L

TEST SETUP FIGURE 23

8

INPUT LEVEL (dBm)

Figure 28. Third-Order Intercept −10 d

–20–40 –30

B/+30 dB Mode, Gain = 30 dB

00539-028

Rev. H | Page 10 of 24

AD603

www.BDTIC.com/ADI

THEORY OF OPERATION

The AD603 comprises a fixed-gain amplifier, preceded by a
broadband passive attenuator of 0 dB to 42.14 dB, having a gain
control scaling factor of 40 dB per volt. The fixed gain is laser­trimmed in two ranges, to either 31.07 dB (×35.8) or 50 dB
(×358), or it may be set to any range in between using one
external resistor between Pin 5 and Pin 7. Somewhat higher
gain can be obtained by connecting the resistor from Pin 5 to
common, but the increase in output offset voltage limits the
maximum gain to about 60 dB. For any given range, the
bandwidth is independent of the voltage-controlled gain. This
system provides an underrange and overrange of 1.07 dB in all
cases; for example, the overall gain is −11.07 dB to +31.07 dB in
the maximum bandwidth mode (Pin 5 and Pin 7 strapped).

This X-AMP structure has many advantages over former
m

ethods of gain control based on nonlinear elements. Most
importantly, the fixed-gain amplifier can use negative feedback
to increase its accuracy. Because large inputs are first attenuated,
the amplifier input is always small. For example, to deliver a
±1 V output in the −1 dB/+41 dB mode (that is, using a fixed
amplifier gain of 41.07 dB), its input is only 8.84 mV; therefore,
the distortion can be very low. Equally important, the small­signal gain and phase response, and thus the pulse response, are
essentially independent of gain.

Figure 29 is a simplified schematic. The input attenuator is a
7-s

ection R-2R ladder network, using untrimmed resistors of
nominally R = 62.5 Ω, which results in a characteristic resistance of
125 Ω ± 20%. A shunt resistor is included at the input and laser
trimmed to establish a more exact input resistance of 100 Ω ± 3%,
which ensures accurate operation (gain and HP corner frequency)
when used in conjunction with external resistors or capacitors.

The nominal maximum signal at input VINP is 1 V rms
(±1.4 V p
although operation to ±2 V peak is permissible with some
increase in HF distortion and feedthrough. Pin 4 (COMM)
must be connected directly to the input ground; significant
impedance in this connection reduces the gain accuracy.

The signal applied at the input of the ladder network is attenuated
b

y 6.02 dB by each section; therefore, the attenuation to each of

the taps is progressively 0 dB, 6.02 dB, 12.04 dB, 18.06 dB,

24.08 dB, 30.1 dB, 36.12 dB, and 42.14 dB. A unique circuit
technique is employed to interpolate between these tap points,
indicated by the slider in

ttenuation from 0 dB to 42.14 dB. It helps in understanding the

a
AD603 to think in terms of a mechanical means for moving this
slider from left to right; in fact, its position is controlled by the
voltage between Pin 1 and Pin 2. The details of the gain control
interface are in the

eak) when using the recommended ±5 V supplies,

Figure 29, thus providing continuous

The Gain Control Interface section.

The gain is at all times very exactly determined, and a linear-in­d

B relationship is automatically guaranteed by the exponential
nature of the attenuation in the ladder network (the X-AMP
principle). In practice, the gain deviates slightly from the ideal
law, by about ±0.2 dB peak (see, for example,

Figure 5).

NOISE PERFORMANCE

An important advantage of the X-AMP is its superior noise
performance. The nominal resistance seen at inner tap points is

41.7 Ω (one third of 125 Ω), which exhibits a Johnson noise
spectral density (NSD) of 0.83 nV/√Hz (that is, √4kTR) at 27°C,
which is a large fraction of the total input noise. The first stage
of the amplifier contributes a further 1 nV/√Hz, for a total input
noise of 1.3 nV/√Hz. It is apparent that it is essential to use a
low resistance in the ladder network to achieve the very low
specified noise level. The source impedance of the signal
forms a voltage divider with the 100 Ω input resistance of the
AD603. In some applications, the resulting attenuation may
be unacceptable, requiring the use of an external buffer or
preamplifier to match a high impedance source to the low
impedance AD603.

The noise at maximum gain (that is, at the 0 dB tap) depends on
w

hether the input is short-circuited or open-circuited. When
short-circuited, the minimum NSD of slightly over 1 nV/√Hz is
achieved. When open-circuited, the resistance of 100 Ω looking
into the first tap generates 1.29 nV/√Hz, so the noise increases
to 1.63 nV/√Hz. (This last calculation would be important if the
AD603 were preceded by, for example, a 900 Ω resistor to allow
operation from inputs up to 10 V rms.) As the selected tap
moves away from the input, the dependence of the noise on
source impedance quickly diminishes.

Apart from the small variations just discussed, the signal-to­n

oise (SNR) at the output is essentially independent of the
attenuator setting. For example, on the −11 dB/+31 dB range,
the fixed gain of ×35.8 raises the output NSD to 46.5 nV/√Hz.
Therefore, for the maximum undistorted output of 1 V rms and
a 1 MHz bandwidth, the output SNR would be 86.6 dB, that is,
20 log(1 V/46.5 μV).

Rev. H | Page 11 of 24

AD603

www.BDTIC.com/ADI

8

VPOS

VNEG

GPOS

GNEG

VINP

COMM

6

1

2

3

4

SCALING

REFERENCE

V

G

GAIN-

CONTROL

INTERFACE

0dB –6.02dB –12.04dB –18.06dB –24.08dB –30.1dB –36.12dB –42.14dB

RRRRRRR

2R 2R 2R 2R 2R 2R R

R-2R LADDER NETWO RK

PRECISION PASSIVE
INPUT ATTENUATOR

AD603

FIXED-GAIN

AMPLIFIER

6.44kΩ*

694Ω*

20Ω*

7

5

VOUT

FDBK

*NOMINAL VALUES.

Figure 29. Simplified Block Diagram

THE GAIN CONTROL INTERFACE

The attenuation is controlled through a differential, high
impedance (50 MΩ) input, with a scaling factor that is laser­trimmed to 40 dB per volt, that is, 25 mV/dB. An internal band
gap reference ensures stability of the scaling with respect to
supply and temperature variations.

When the differential input voltage V
slider is centered, providing an attenuation of 21.07 dB. For the
maximum bandwidth range, this results in an overall gain of
10 dB (= −21.07 dB + 31.07 dB). When the control input is

−500 mV, the gain is lowered by +20 dB (= 0.500 V × 40 dB/V)
to −10 dB; when set to +500 mV, the gain is increased by
+20 dB to +30 dB. When this interface is overdriven in either
direction, the gain approaches either −11.07 dB (= − 42.14 dB +
+31.07 dB) or 31.07 dB (= 0 + 31.07 dB), respectively. The only
constraint on the gain control voltage is that it be kept within
the common-mode range (−1.2 V to +2.0 V assuming +5 V
supplies) of the gain control interface.

The basic gain of the AD603 can therefore be calculated by

Gain (dB) = 40 V

where V

is in volts. When Pin 5 and Pin 7 are strapped (see the

G

+10 (1)

G

Programming the Fixed-Gain Amplifier Using Pin Strapping

on), the gain becomes

secti

Gain (dB) = 40 V

+ 20 for 0 to +40 dB

G

and

Gain (dB) = 40 V

+ 30 for +10 to +50 dB (2)

G

The high impedance gain control input ensures minimal
lo

ading when driving many amplifiers in multiple channel
or cascaded applications. The differential capability provides
flexibility in choosing the appropriate signal levels and
polarities for various control schemes.

= 0 V, the attenuator

G

00539-029

For example, if the gain is to be controlled by a DAC providing
a p

ositive-only, ground-referenced output, the gain control low
(GNEG) pin should be biased to a fixed offset of 500 mV to set
the gain to −10 dB when gain control high (GPOS) is at zero,
and to 30 dB when at 1.00 V.

It is a simple matter to include a voltage divider to achieve other

caling factors. When using an 8-bit DAC having an FS output

s
of 2.55 V (10 mV/bit), a divider ratio of 2 (generating 5 mV/bit)
results in a gain-setting resolution of 0.2 dB/bit. The use of such
offsets is valuable when two AD603s are cascaded, when
various options exist for optimizing the signal-to-noise profile,
as is shown in the

Sequential Mode (Optimal SNR) section,

PROGRAMMING THE FIXED-GAIN AMPLIFIER
USING PIN STRAPPING

Access to the feedback network is provided at Pin 5 (FDBK).
The user may program the gain of the output amplifier of the
AD603 using this pin, as shown in Figure 30, Figure 31, and
Figure 32. There are three modes: in the default mode, FDBK
is un

connected, providing the range +9 dB/+51 dB; when V
and FDBK are shorted, the gain is lowered to −11 dB/+31 dB;
and, when an external resistor is placed between V

OUT

FDBK, any intermediate gain can be achieved, for example,

−1 dB/+41 dB.

ernal resistor for this mode.

ext

VIN

Figure 33 shows the nominal maximum gain vs.

1

2

3

4

GPOS

AD603

GNEG

VINP

COMM

VC1

VC2

Figure 30. −10 dB to +30 dB; 90 MHz Bandwidth

VPOS

VOUT

VNEG

FDBK

8

VPOS

7

6

VNEG

5

and

VOUT

OUT

00539-030

Rev. H | Page 12 of 24

AD603

V

www.BDTIC.com/ADI

Optionally, when a resistor is placed from FDBK to COMM,

higher gains can be achieved. This fourth mode is of limited

value because of the low bandwidth and the elevated output

offsets; it is thus not included in

Figure 30, Figure 31, or

Figure 32.

The gain of this amplifier in the first two modes is set by the

ra

tio of on-chip laser-trimmed resistors. While the ratio of these
resistors is very accurate, the absolute value of these resistors
can vary by as much as ±20%. Therefore, when an external
resistor is connected in parallel with the nominal 6.44 kΩ ± 20%
internal resistor, the overall gain accuracy is somewhat poorer.
The worst-case error occurs at about 2 kΩ (see

1.2

1.0

0.8

0.6

0.4

0.2

0

–0.2

GAIN ERROR (d B)

–0.4

–0.6

–0.8

–1.0

Figure 34. Worst-Case Gain Error, Assuming Internal Resistors Have a

mum Tolerance of −20% (Top Curve) or = 20% (Bottom Curve)

Maxi

–1:VdB (OUT) – (–1):VdB (O

VdB (OUT) – VdB (O

R

(Ω)

EXT

Figure 34).

REF

REF

)

)

1M10 100 1k 10k 100k

00539-034

While the gain bandwidth product of the fixed-gain amplifier is
about 4 GHz, the actual bandwidth is not exactly related to the
maximum gain. This is because there is a slight enhancing of
the ac response magnitude on the maximum bandwidth range,
due to higher order poles in the open-loop gain function; this
mild peaking is not present on the higher gain ranges.

Figure 30,
Figure 31, and Figure 32 show how an optional capacitor may
b

e added to extend the frequency response in high gain modes.

IN

VIN

52

50

48

46

44

42

40

GAIN (dB)

38

36

34

32

30

Figure 33. Gain vs. R

VC1

1

GPOS

VPOS

8

VPOS

AD603

VC2

2

3

4

GNEG

VINP

COMM

VOUT

VNEG

FDBK

7

6

VNEG

2.15kΩ

5

5.6pF

Figure 31. 0 dB to 40 dB; 30 MHz Bandwidth

VC1

1

GPOS

VPOS

8

VPOS

AD603

VC2

2

GNEG

3

VINP

4 5

COMM

VOUT

VNEG

FDBK

7

6

VNEG

18pF

Figure 32. 10 dB to 50 dB; 9 MHz to Set Gain

–1:VdB (OUT)

VdB (OUT)

–2:VdB (OUT)

R

(Ω)

EXT

, Showing Worst-Case Limits Assuming Internal

EXT

Resistors Have a Maximum Tolerance of 20%

VOUT

VOUT

1M10 100 1k 10k 100k

00539-031

00539-032

00539-033

Rev. H | Page 13 of 24

AD603

–

V

–

V

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USING THE AD603 IN CASCADE

Two or more AD603s can be connected in series to achieve
higher gain. Invariably, ac coupling must be used to prevent the
dc offset voltage at the output of each amplifier from overloading
the following amplifier at maximum gain. The required high­pass coupling network is usually just a capacitor, chosen to set
the desired corner frequency in conjunction with the well­defined 100 Ω input resistance of the following amplifier.

For two AD603s, the total gain control range becomes 84 dB
(2 × 42.14 dB); th

e overall −3 dB bandwidth of cascaded stages
is somewhat reduced. Depending on the pin strapping, the gain
and bandwidth for two cascaded amplifiers can range from

−22 dB to +62 dB (with a bandwidth of about 70 MHz) to
+22 dB to +102 dB (with a bandwidth of about 6 MHz).

There are several ways of connecting the gain control inputs
i

n cascaded operation. The choice depends on whether it is
important to achieve the highest possible instantaneous signal­to-noise ratio (ISNR), or, alternatively, to minimize the ripple
in the gain error. The following examples feature the AD603
programmed for maximum bandwidth; the explanations apply
to other gain/bandwidth combinations with appropriate
changes to the arrangements for setting the maximum gain.

SEQUENTIAL MODE (OPTIMAL SNR)

In the sequential mode of operation, the ISNR is maintained at
its highest level for as much of the gain control range as possible.

A1

–40.00dB –51.07dB

Figure 35 shows the SNR over a gain range of −22 dB to +62 dB,
assumin

g an output of 1 V rms and a 1 MHz bandwidth. Figure 36,
Figure 37, and Figure 38 show the general connections to
a

ccomplish this. Here, both the positive gain control inputs
(GPOS) are driven in parallel by a positive-only, ground-referenced
source with a range of 0 V to 2 V, while the negative gain
control inputs (GNEG) are biased by stable voltages to provide
the needed gain offsets. These voltages may be provided by
resistive dividers operating from a common voltage reference.

90

85

80

75

70

SNR (dB)

65

60

55

50

VC (V)

Figure 35. SNR vs. Control Voltage, Seq

A2

uential Control (1 MHz Bandwidth)

2.2–0.2 0.60.2 1.41.0 1.8

00539-035

INPUT

0dB

V

C

= 0V

–42.14dB

GPOS GNEG

V

G1

VO1 = 0.473V VO2 = 1.526V

31.07dB

Figure 36. AD603 Gain Control Input Calculat

–8.93dB

–42.14dB

GPOS GNEG

V

G2

31.07dB

ions for Sequential Control Operation V

OUTPUT
–20dB

= 0 V

C

00539-036

0dB

INPUT

0dB

= 1.0V

C

0dB

GPOS GNEG

V

G1

VO1 = 0.473V VO2 = 1.526V

31.07dB

31.07dB

GPOS GNEG

Figure 37. AD603 Gain Control Calculations for Sequential Control Operation V

0dB

INPUT

0dB

= 2.0V

C

0dB

GPOS GNEG

V

G1

VO1 = 0.473V VO2 = 1.526V

31.07dB

31.07dB

GPOS GNEG

Figure 38. AD603 Gain Control Input Calculations for Sequential Operation V

–42.14dB

V

G2

–2.14dB

V

G2

11.07dB

28.93dB

31.07dB

31.07dB

OUTPUT
20dB

= 1.0 V

C

OUTPUT
60dB

= 2.0 V

C

00539-037

00539-038

Rev. H | Page 14 of 24

AD603

m

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The gains are offset (Figure 39) such that the gain of A2 is
increased only after the gain of A1 has reached its maximum
value. Note that for a differential input of –600 mV or less, the
gain of a single amplifier (A1 or A2) is at its minimum value of

−11.07 dB; for a differential input of 600 mV or more, the gain
is at its maximum value of 31.07 dB. Control inputs beyond
these limits do not affect the gain and can be tolerated without
damage or foldover in the response. This is an important aspect
of the gain control response of the AD603. (See the

ection for more details on the allowable voltage range.) The

s

Specifications

gain is now

Gain (dB) = 40 V

+ GO (3)

G

where:
V

is the applied control voltage.

G

G

is determined by the gain range chosen.

O

In the explanatory notes that follow, it is assumed that

he maximum bandwidth connections are used, for which

t
G

is −20 dB.

O

+31.07dB

+10dB

–8.93dB

GAIN

–22.14

(dB)

*GAIN OF FSET O F 1.07dB, OR 26.75

A1 A2

–11.07dB

0.473 1.52 6

–20

0

0.5
0

+31.07dB +28.96dB

*

*

1.0
20

V.

1.50
40

–11.07dB

2.060V

(V)

C

62.14

Figure 39. Explanation of Offset Calibration for Sequential Control

With reference to Figure 36, Figure 37, and Figure 38, note that
V

refers to the differential gain control input to A1, and VG2

G1

refers to the differential gain control input to A2. When V
0 V, V

= −473 mV and thus the gain of A1 is −8.93 dB (recall

G1

is

G

that the gain of each individual amplifier in the maximum
bandwidth mode is –10 dB for V
= 0 V); meanwhile, V

= −1.908 V so the gain of A2 is pinned

G2

= −500 mV and 10 dB for VG

G

at −11.07 dB. The overall gain is therefore –20 dB (see Figure 36).
When V

= 1.00 V, VG1 = 1.00 V − 0.473 V = 0.526 V, which sets

G

the gain of A1 to nearly its maximum value of +31.07 dB, while
V

= 1.00 V − 1.526 V = 0.526 V, which sets the gain of A2 to

G2

nearly its minimum value of −11.07 dB. Close analysis shows
that the degree to which neither AD603 is completely pushed to
its maximum nor minimum gain exactly cancels in the overall
gain, which is now 20 dB (see

When V

= 2.0 V, the gain of A1 is pinned at 31.07 dB and that

G

Figure 37).

of A2 is near its maximum value of 28.93 dB, resulting in an
overall gain of 60 dB (see

urther clarified in Figure 40, which is a plot of the separate

f

ins of A1 and A2 and the overall gain vs. the control voltage.

ga

Figure 38). This mode of operation is

00539-039

Figure 41 is a plot of the SNR of the cascaded amplifiers vs. the

ontrol voltage. Figure 42 is a plot of the gain error of the

c
cas

caded stages vs. the control voltages.

70

60

50

40

30

20

10

0

OVERALL GAIN (dB)

–10

–20

–30

A1

VC (V)

COMBINED

A2

2.0–0.2 0.2 0.6 1. 0 1. 4 1 .8

00539-040

Figure 40. Plot of Separate and Overall Gains in Sequential Control

90

80

70

60

50

SNR (dB)

40

30

20

10

Figure 41. SNR for Cascaded St

2.0

1.5

1.0

0.5

0

–0.5

GAIN ERROR (d B)

–1.0

–1.5

–2.0

VC (V)

ages—Sequential Control

VC (V)

2.0–0.2 0.2 0.6 1. 0 1. 4 1 .8

00539-041

2.2–0.2 0 0.2 0.4 0.6 0.8 1.0 1. 2 1.4 1.6 1.8 2. 0

00539-042

Figure 42. Gain Error for Cascaded Stages–Sequential Control

Rev. H | Page 15 of 24

AD603

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PARALLEL MODE (SIMPLEST GAIN CONTROL INTERFACE)

In this mode, the gain control of voltage is applied to both
inputs in parallel: the GPOS pins of both A1 and A2 are
connected to the control voltage and the GNEW inputs are
grounded. The gain scaling is then doubled to 80 dB/V,
requiring only a 1.00 V change for an 80 dB change of gain

Gain = (dB) = 80 V

where, as before, G
in the maximum bandwidth mode, G
the GNEG pins may be connected to an offset voltage of

0.500 V, in which case G
The amplitude of the gain ripple in this case is also doubled, as

n Figure 43, while the ISNR at the output of A2 now

shown i
de

creases linearly as the gain increases, as shown in Figure 44.

2.0

1.5

1.0

0.5

0

–0.5

GAIN ERROR (d B)

–1.0

–1.5

–2.0

Figure 43. Gain Error for Cascaded Stages—Parallel Control

90

85

80

+ GO (4)

G

depends on the range selected; for example,

O

is 20 dB. Alternatively,

O

is −20 dB.

O

VC (V)

2.2–0.2 0 0.2 0.4 0.6 1.0 1.20.8 1.6 1.8 2.01.4

00539-043

LOW GAIN RIPPLE MODE (MINIMUM GAIN ERROR)

As can be seen in Figure 42 and Figure 43, the error in the gain
is periodic, that is, it shows a small ripple. (Note that there is
also a variation in the output offset voltage, which is due to the
gain interpolation, but this is not exact in amplitude.) By
offsetting the gains of A1 and A2 by half the period of the ripple,
that is, by 3 dB, the residual gain errors of the two amplifiers
can be made to cancel.

hen configured in this manner. Figure 46 plots the ISNR as a

w
f

unction of gain; it is very similar to that in the parallel mode.

3.0

2.5

2.0

1.5

1.0

0.5

0

–0.5

–1.0

GAIN ERROR (d B)

–1.5

–2.0

–2.5

–3.0

Figure 45. Gain Error for Cascaded Stages—Low Ripple Mode

90

85

80

75

70

ISNR (dB)

65

60

Figure 45 shows much lower gain ripple

VC (V)

1.1–0.1 0 0.1 0. 2 0.3 0.4 0.5 0. 6 0.7 0.8 0.9 1. 0

00539-045

75

70

ISNR (dB)

65

55

50

Figure 46. ISNR vs. Control Voltage—Low Ripple Mode

60

55

50

VC (V)

1.2–0.2 0 0.2 0.4 0.6 0.8 1. 0

00539-044

Figure 44. ISNR for Cascaded Stages—Parallel Control

Rev. H | Page 16 of 24

VC(V)

1.2–0.2 0 0.2 0.4 0.6 0.8 1. 0

00539-046

AD603

V

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APPLICATIONS INFORMATION

A LOW NOISE AGC AMPLIFIER

Figure 47 shows the ease with which the AD603 can be
connected as an AGC amplifier. The circuit illustrates many of
the points previously discussed: it uses few parts, has linear-in­dB gain, operates from a single supply, uses two cascaded amplifiers
in sequential gain mode for maximum SNR, and an external
resistor programs each gain of the amplifier. It also uses a
simple temperature-compensated detector.

The circuit operates from a single 10 V supply. Resistors R1, R2,
R3, a

nd R4 bias the common pins of A1 and A2 at 5 V. The
common pin is a low impedance point and must have a low
impedance path to ground, provided here by the 100 μF tantalum
capacitors and the 0.1 μF ceramic capacitors.

The cascaded amplifiers operate in sequential gain. Here, the

ffset voltage between Pin 2 (GNEG) of A1 and A2 is 1.05 V

o
(42.14 dB × 25 mV/dB), provided by a voltage divider consisting of
Resistors R5, R6, and R7. Using standard values, the offset is not
exact, but it is not critical for this application.

The gain of both A1 and A2 is programmed by Resistors R13

14, respectively, to be about 42 dB; therefore, the maximum

and R
gain of the circuit is twice that, or 84 dB. The gain control range
can be shifted up by as much as 20 dB by appropriate choices of
R13 and R14.

The circuit operates as follows:

nd A2 are cascaded.

• A1 a

pacitor C1 and the 100 Ω of resistance at the input of A1

• Ca

form a time constant of 10 μs.

locks the small dc offset voltage at the output of A1

• C2 b

(which might otherwise saturate A2 at its maximum gain)
and introduces a high-pass corner at about 16 kHz,
eliminating low frequency noise.

A half-wave detector is used, based on Q1 and R8. The current
i

nto capacitor, C

, is the difference between the collector

AV

current of Q2 (biased to be 300 μA at 300 K, 27°C) and the
collector current of Q1, which increases with the amplitude
of the output signal.

The automatic gain control voltage, V
of this error current. For V

(and thus the gain) to remain

AGC

, is the time integral

AGC

insensitive to short-term amplitude fluctuations in the output
signal, the rectified current in Q1 must, on average, exactly
balance the current in Q2. If the output of A2 is too small to
do this, V

increases, causing the gain to increase until Q1

AGC

conducts sufficiently.
Consider the case where R8 is zero and the output voltage V

OUT

is a square wave at, for example, 455 kHz, which is well above
the corner frequency of the control loop.

10

C7

0.1µF

C1

0.1µF

10V

R2

2.49kΩ

5.49kΩ

3

4

J1

2

C3

100µFC40.1µF

1

RT

100Ω

R1

2.49kΩ

+

1

RT PROVIDES A 50Ω INPUT IMPEDANC E.

2

C3 AND C5 ARE TANTALUM.

10V

R13

8

A1

AD603

1

R5

2.49kΩ

6

5

7

2

C5

100µFC60.1µF

5.5V 6.5V

C2

0.1µF

2

+

1V OFFSET FOR

SEQUENTIAL GAIN

R3

2.49kΩ

R6

1.05kΩ

C8

0.1µF

10V

Figure 47. A Low Noise AGC Amplifier

R4

2.49kΩ

THIS CAPACITOR SETS

AGC TI ME CONSTANT

10V

8

6

3

AD603

4

5

A2

2

1

R14

2.49kΩ

7

0.1µF

R7

3.48kΩ

V

AGC

C

AV

AGC LINE

10V

1.54kΩ

2N3906

2N3904

806Ω

Q2

Q1

R9

R8

R10

1.24kΩ

R11

3.83kΩ
5V

R12

4.99kΩ

C10

0.1µF

C11

0.1µF

C9

0.1µF

J2

00539-047

Rev. H | Page 17 of 24

AD603

www.BDTIC.com/ADI

During the time V
voltage of Q1, Q1 conducts; when V
Because the average collector current of Q1 is forced to be
300 μA, and the square wave has a duty cycle of 1:1, Q1’s
collector current when conducting must be 600 μA. With R8
omitted, the peak amplitude of V
of Q1 at 600 μA, typically about 700 mV, or 2 V
This voltage, the amplitude at which the output stabilizes, has a
strong negative temperature coefficient (TC), typically −1.7 mV/°C.
Although this may not be troublesome in some applications, the
correct value of R8 renders the output stable with temperature.

To understand this, note that the current in Q2 is made to be

ortional to absolute temperature (PTAT). For the moment,

prop
continue to assume that the signal is a square wave.

When Q1 is conducting, V
voltage that is PTAT and that can be chosen to have an equal
but opposite TC to that of the V
than an application of the band gap voltage reference principle.
When R8 is chosen such that the sum of the voltage across it
and the V
V

OUT

course, that Q1 and Q2 share the same thermal environment.
Because the average emitter current is 600 μA during each half

c

ycle of the square wave, a resistor of 833 Ω adds a PTAT
voltage of 500 mV at 300 K, increasing by 1.66 mV/°C. In
practice, the optimum value depends on the type of transistor
used and, to a lesser extent, on the waveform for which the
temperature stability is to be optimized; for the inexpensive
2N3904/2N3906 pair and sine wave signals, the recommended
value is 806 Ω.

of Q1 is close to the band gap voltage of about 1.2 V,

BE

is stable over a wide range of temperatures, provided, of

is negative with respect to the base

OUT

is positive, it is cut off.

OUT

is forced to be just the VBE

OUT

BE

is now the sum of VBE and a

OUT

. This is actually nothing more

BE

peak-to-peak.

This resistor also serves to lower the peak current in Q1 when
more

typical signals (usually sinusoidal) are involved, and the

1.8 kHz LP filter it forms with C
due to ripple in V
wave conditions is higher than for a square wave because the
average value of the current for an ideal rectifier is 0.637 times
as large, causing the output amplitude to be 1.88 (= 1.2/0.637) V,
or 1.33 V rms. In practice, the somewhat nonideal rectifier
results in the sine-wave output being regulated to about

1.4 V rms, or 3.6 V p-p.
The bandwidth of the circuit exceeds 40 MHz. At 10.7 MHz, the

GC threshold is 100 μV (−67 dBm) and its maximum gain is

A
83 dB (20 log 1.4 V/100 μV). The circuit holds its output at

1.4 V rms for inputs as low as −67 dBm to +15 dBm (82 dB),
where the input signal exceeds the maximum input rating of the
AD603. For a 30 dBm input at 10.7 MHz, the second harmonic
is 34 dB down from the fundamental, and the third harmonic is
35 dB down from the fundamental.

. Note that the output amplitude under sine

AGC

helps to minimize distortion

AV

CAUTION

Careful component selection, circuit layout, power supply
decoupling, and shielding are needed to minimize the susceptibility
of the AD603 to interference from signals such as those from
radio and TV stations. In bench evaluation, it is recommended
to place all of the components into a shielded box and use
feedthrough decoupling networks for the supply voltage. Circuit
layout and construction are also critical because stray capacitances
and lead inductances can form resonant circuits and are a
potential source of circuit peaking, oscillation, or both.

Rev. H | Page 18 of 24

AD603

VOUT

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EVALUATION BOARD

The evaluation board of the AD603 enables simple bench-top
experimenting to be performed with easy control of the
AD603. Built-in flexibility allows convenient configuration to
accommodate most operating configurations.
p

hotograph of the AD603 evaluation board.

Figure 48. AD603 Evaluation Board

Figure 48 is a

00539-048

Any dual-polarity power supply capable of providing 20 mA is
all that is required, in addition to whatever test equipment the
user wishes to perform the intended tests.

Referring to the schematic in Figure 49, the input to the VGA is

ingle-ended, ac-coupled, and terminated in 50 Ω to accommodate

s
most commonly available signal generators.

V+

V–

G1 G4G2 G3GND

The output is also ac-coupled and includes a 453 Ω series
resistor. The gain of the AD603 is adjusted by connecting a
voltage source between the GNEG and GPOS test loops. A 0 Ω
resistor, R5, is provided, permitting ground reference of the
differential gain control inputs. For other gain configurations, a
signal generator may be connected to the test loops, or the
GNEG and/or GPOS pins may be biased. Either pin may be
driven to either polarity within the common-mode limits of

−1.2 V to +2.0 V; therefore, to invert the gain slope, simply
consider the GPOS as the reference and drive the GNEG pin
positively with respect to GPOS.

The AD603 includes built-in gain resistors selectable at the
F

DBK pin. The board is shipped with the gain at minimum,
with a 0 Ω resistor installed in R3. For maximum gain, simply
remove R3. Because of the architecture of the AD603, the
bandwidth decreases by 10, but the gain range remains at 40 dB.
Intermediate gain values may be selected by installing a resistor
between the VOUT and FDBK pins.

Figure 50, Figure 51, and Figure 52 show the component and

cuit side copper patterns and silkscreen. A bill of materials is

cir
shown in

Table 5.

GPOS

GNEG

R6

R2
100Ω

V+

C8
10µF

+

25V

R7

AD603

1

GPOS

2

GNEG

3

VINP VNEG

4

COMM FDBK

VPOS

VOUT

8

7

6

5

10µF

25V

0.1µF

C7

+

V+ V–

C1

C4

VIN

W2

R1

R5
0Ω

C5

0.1µF

Figure 49. Schematic of the AD603 Evaluation Board

V+

C6

0.1µF

R3
0Ω

C9

C2

0.1µF

R4

453Ω

W1

C3

0.1µF

VO

00539-050

Figure 50. Component Side Copper

V–

00539-049

Figure 51. Circuit Side Copper

Rev. H | Page 19 of 24

00539-051

AD603

www.BDTIC.com/ADI

G1 G4

V–V+

GND

+

GPOS

GNEG

VIN

W2

C7

R7

R1

C1

R6

C4

R5

C5

R2

DUT

C2

C9

C8

+

R3

C6

C3

W1

VO

R4

VOUT

Pb

G2

Figure 52. Component Side Silk Screen

AD603ARZ

EVALUATION BOARD

G3

RoHS

00539-052

Table 5. Bill of Materials

Qty Name Description Reference Designator Manufacturer Mfg Part Number

5 Capacitors 0.1 μF, 16 V, 0603, X7R C1, C2, C3, C5, C6 KEMET C0603C104K4RACTU
2 Capacitors 10 μF, 25 V, C size tantalum C7, C8 Nichicon F931E106MCC
1 IC Variable gain amplifier DUT Analog Devices, Inc. AD603ARZ
5 Test Loops 0.125” diameter, black G1, G2, G3, G4, GND Components Corp. TP-104-01-00
3 Test Loops 0.125” diameter, purple GNEG, GPOS, VO Components Corp. TP-104-01-07
1 Resistor 100 Ω, 1%, 1/16 W, 0603 R2 Panasonic ERJ-3EKF1000V
2 Resistors 0 Ω, 5%, 1/10 W, 0603 R3, R5 Panasonic ERJ-2GE0R00X
1 Resistor 453 Ω, 1/16 W, 1%, 0603 R4 Panasonic ERJ-3EKF4530V
1 Test Loop 0.125” diameter, red +5V Components Corp. TP-104-01-02
1 Test Loop 0.125” diameter, green −5 V Components Corp. TP-104-01-05
2 Connectors SMA female PC mount, RA VIN, VOUT Amphenol 901-143-6RFX
2 Headers 2-pin 025" sq., 0.1" spacing W1, W2 Molex 22-11-2032
Not inserted C4, C9, R1, R6, R7

Rev. H | Page 20 of 24

AD603

www.BDTIC.com/ADI

OUTLINE DIMENSIONS

0.005 (0.13)

0.200 (5.08)
MAX

0.200 (5.08)

0.125 (3.18)

0.023 (0.58)

0.014 (0.36)

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 53. 8-Lead Ceramic Dual In-Line Package [CERDIP]

Dim

0.055 (1.40)

MIN

14

0.100 (2.54) BSC

0.405 (10.29) MAX

MAX

0.070 (1.78)

0.030 (0.76)

58

0.310 (7.87)

0.220 (5.59)

0.060 (1.52)

0.015 (0.38)

0.150 (3.81)
MIN

SEATING
PLANE

15°
0°

(Q-8)

ensions shown in inches and (millimeters)

5.00 (0.1968)

4.80 (0.1890)

0.320 (8.13)

0.290 (7.37)

0.015 (0.38)

0.008 (0.20)

4.00 (0.1574)

3.80 (0.1497)

0.25 (0.0098)

0.10 (0.0040)

COPLANARITY

0.10

CONTROLL ING DIMENSI ONS ARE IN MILLIMETERS; INCH DI MENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRI ATE FOR USE IN DES IGN.

85

1

1.27 (0.0500)

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MS-012-A A

BSC

6.20 (0.2441)

5.80 (0.2284)

4

1.75 (0.0688)

1.35 (0.0532)

0.51 (0.0201)

0.31 (0.0122)

8°
0°

0.25 (0.0098)

0.17 (0.0067)

0.50 (0.0196)

0.25 (0.0099)

1.27 (0.0500)

0.40 (0.0157)

45°

012407-A

Figure 54. 8-Lead Standard Small Outline Package [SOIC-N]

Narrow B

ody (R-8)

Dimensions shown in millimeters and (inches)

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD603AR −40°C to +85°C 8-Lead SOIC R-8
AD603AR-REEL −40°C to +85°C 8-Lead SOIC, 13" Reel R-8
AD603AR-REEL7 −40°C to +85°C 8-Lead SOIC, 7" Reel R-8
AD603ARZ
AD603ARZ-REEL
AD603ARZ-REEL7
AD603AQ −40°C to +85°C 8-Lead CERDIP Q-8
AD603SQ/883B
AD603-EVALZ
AD603ACHIPS DIE

1

Z = RoHS Compliant Part.

2

Refer to AD603 Military data sheet. Also available as 5962-9457203MPA.

1

1

1

2

1

−40°C to +85°C 8-Lead SOIC R-8

−40°C to +85°C 8-Lead SOIC, 13" Reel R-8

−40°C to +85°C 8-Lead SOIC, 7" Reel R-8

−55°C to +125°C 8-Lead CERDIP Q-8
Evaluation Board

Rev. H | Page 21 of 24

AD603

www.BDTIC.com/ADI

NOTES

Rev. H | Page 22 of 24

AD603

www.BDTIC.com/ADI

NOTES

Rev. H | Page 23 of 24

AD603

www.BDTIC.com/ADI

NOTES

©2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C00539-0-5/07(H)

T

Rev. H | Page 24 of 24

TTT