ANALOG DEVICES AD5933 Service Manual

1 MSPS, 12-Bit Impedance

A

V

Data Sheet

FEATURES

Programmable output peak-to-peak excitation voltage

to a maximum frequency of 100 kHz

Programmable frequency sweep capability with

Frequency resolution of 27 bits (<0.1 Hz)
Impedance measurement range from 1 kΩ to 10 MΩ
Capable of measuring of 100 Ω to 1 kΩ with additional

Internal temperature sensor (±2°C)
Internal system clock option
Phase measurement capability
System accuracy of 0.5%

2.7 V to 5.5 V power supply operation
Temperature range: −40°C to +125°C
16-lead SSOP package

APPLICATIONS

Electrochemical analysis
Bioelectrical impedance analysis
Impedance spectroscopy
Complex impedance measurement
Corrosion monitoring and protection equipment
Biomedical and automotive sensors
Proximity sensing
Nondestructive testing
Material property analysis
Fuel/battery cell condition monitoring

2

serial I

circuitry

C interface

Converter, Network Analyzer

AD5933

GENERAL DESCRIPTION

The AD5933 is a high precision impedance converter system
solution that combines an on-board frequency generator with
a 12-bit, 1 MSPS, analog-to-digital converter (ADC). The
frequency generator allows an external complex impedance to
be excited with a known frequency. The response signal from
the impedance is sampled by the on-board ADC and a discrete
Fourier transform (DFT) is processed by an on-board DSP
engine. The DFT algorithm returns a real (R) and imaginary (I)
data-word at each output frequency.

Once calibrated, the magnitude of the impedance and relative
phase of the impedance at each frequency point along the sweep
is easily calculated. This is done off chip using the real and
imaginary register contents, which can be read from the serial

2

I

C interface.

A similar device, also available from Analog Devices, Inc., is the

AD5934, a 2.7 V to 5.5 V, 250 kSPS, 12-bit impedance converter,

with an internal temperature sensor and is packaged in a 16­lead SSOP.

FUNCTIONAL BLOCK DIAGRAM

DDMCLK

OSCILLATOR

SCL

SDA

REGISTER

Rev. D

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

I2C

INTERFACE

REAL

IMAGINARY

REGIS TER

1024-POINT DFT

ADC

(12 BITS)

AGND DGND

DVDD

DDS

CORE

(27 BITS)

TEMPERATURE

SENSOR

AD5933

LPF

DAC

R

OUT

GAIN

VDD/2

Figure 1.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2005–2011 Analog Devices, Inc. All rights reserved.

VOUT

Z(ω)

RFB

VIN

05324-001

AD5933 Data Sheet

TABLE OF CONTENTS

Features.............................................................................................. 1

Applications....................................................................................... 1

General Description......................................................................... 1

Functional Block Diagram ..............................................................1

Revision History ...............................................................................3

Specifications..................................................................................... 4

I2C Serial Interface Timing Characteristics ..............................6

Absolute Maximum Ratings............................................................ 7

ESD Caution.................................................................................. 7

Pin Configuration and Descriptions.............................................. 8

Typical Performance Characteristics ............................................. 9

Terminology .................................................................................... 12

System Description......................................................................... 13

Transmit Stage............................................................................. 14

Frequency Sweep Command Sequence................................... 15

Receive Stage............................................................................... 15

DFT Operation ...........................................................................15

System Clock............................................................................... 16

Temperature Sensor ...................................................................16

Temperature Conversion Details.............................................. 16

Temperature Value Register ......................................................16

Temperature Conversion Formula........................................... 16

Impedance Calculation.................................................................. 17

Magnitude Calculation.............................................................. 17

Gain Factor Calculation ............................................................17

Impedance Calculation Using Gain Factor............................. 17

Gain Factor Variation with Frequency.................................... 17

Two-Point Calibration ............................................................... 18

Two-Point Gain Factor Calculation......................................... 18

Gain Factor Setup Configuration............................................. 18

Gain Factor Recalculation......................................................... 18

Gain Factor Temperature Variation......................................... 19

Impedance Error......................................................................... 19

Measuring the Phase Across an Impedance ........................... 19

Performing a Frequency Sweep ....................................................22

Register Map ................................................................................... 23

Control Register (Register Address 0x80, Register Address

0x81)............................................................................................. 23

Start Frequency Register (Register Address 0x82, Register

Address 0x83, Register Address 0x84)..................................... 24

Frequency Increment Register (Register Address 0x85,

Register Address 0x86, Register Address 0x87) .....................25

Number of Increments Register (Register Address 0x88,

Register Address 0x89).............................................................. 25

Number of Settling Time Cycles Register (Register Address

0x8A, Register Address 0x8B) ................................................. 25

Status Register (Register Address 0x8F).................................. 26

Temperature Data Register (16 Bits—Register Address 0x92,

Register Address 0x93).............................................................. 26

Real and Imaginary Data Registers (16 Bits—Register
Address 0x94, Register Address 0x95, Register Address 0x96,

Register Address 0x97).............................................................. 26

Serial Bus Interface......................................................................... 27

General I2C Timing.................................................................... 27

Writing/Reading to the AD5933.............................................. 28

Block Write.................................................................................. 28

Read Operations......................................................................... 29

Typical Applications....................................................................... 30

Measuring Small Impedances................................................... 30

Biomedical: Noninvasive Blood Impedance Measurement.. 32

Sensor/Complex Impedance Measurement............................ 32

Electro-Impedance Spectroscopy............................................. 33

Choosing a Reference for the AD5933........................................ 34

Layout and Configuration............................................................. 35

Power Supply Bypassing and Grounding................................ 35

Evaluation Board............................................................................ 36

Using the Evaluation Board ...................................................... 36

Prototyping Area........................................................................ 36

Crystal Oscillator (XO) vs. External Clock............................. 36

Schematics................................................................................... 37

Outline Dimensions....................................................................... 41

Ordering Guide .......................................................................... 41

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











Rev. D | Page 2 of 44

Data Sheet AD5933

REVISION HISTORY

12/11—Rev. C to Rev. D

Changes to Impedance Error Section...........................................19

Removed Figure 26 and Figure 27;

Renumbered Sequentially ..............................................................19

Removed Figure 28, Figure 29, Figure 30, Figure 31..................20

Changes to Figure 39 ......................................................................37

Changes to Figure 40 ......................................................................38

Changes to Figure 41 ......................................................................39

Changes to Figure 42 ......................................................................40

8/10—Rev. B to Rev. C

Changes to Impedance Error Section...........................................19

Changes to Figure 45 ......................................................................38

Changes to U4 Description in Table 19........................................42

2/10—Rev. A to Rev. B

Changes to General Description.....................................................1

5/08—Rev. 0 to Rev. A

Changes to Layout.............................................................. Universal

Changes to Figure 1 ..........................................................................1

Changes to Table 1 ............................................................................4

Changes to Figure 17......................................................................13

Changes to System Description Section ......................................13

Changes to Figure 19......................................................................14

Changes to Figure 24......................................................................18

Changes to Impedance Error Section...........................................19

Added Measuring the Phase Across an Impedance Section .....21

Changes to Register Map Section .................................................24

Added Measuring Small Impedances Section.............................31

Changes to Table 18 ........................................................................35

Added Evaluation Board Section..................................................37

Changes to Ordering Guide...........................................................43

9/05—Revision 0: Initial Version

Rev. D | Page 3 of 44

AD5933 Data Sheet

SPECIFICATIONS

VDD = 3.3 V, MCLK = 16.776 MHz, 2 V p-p output excitation voltage @ 30 kHz, 200 kΩ connected between Pin 5 and Pin 6; feedback
resistor = 200 kΩ connected between Pin 4 and Pin 5; PGA gain = ×1, unless otherwise noted.

Table 1.

Y Version1

Parameter

Min Typ Max

SYSTEM

Impedance Range 1 K 10 M Ω

Total System Accuracy 0.5 %

System Impedance Error Drift 30 ppm/°C

TRANSMIT STAGE

Output Frequency Range

2

1

100 kHz

Output Frequency Resolution 0.1 Hz

MCLK Frequency 16.776 MHz Maximum system clock frequency
Internal Oscillator Frequency3 16.776 MHz Frequency of internal clock
Internal Oscillator Temperature Coefficient 30 ppm/°C

TRANSMIT OUTPUT VOLTAGE

Range 1

AC Output Excitation Voltage

4

1.98 V p-p

DC Bias5 1.48 V

DC Output Impedance 200 Ω TA = 25°C
Short-Circuit Current to Ground at VOUT ±5.8 mA TA = 25°C

Range 2

AC Output Excitation Voltage4 0.97 V p-p See Figure 6

5

DC Bias

0.76 V

DC Output Impedance 2.4 kΩ
Short-Circuit Current to Ground at VOUT ±0.25 mA

Range 3

AC Output Excitation Voltage

5

DC Bias

4

0.383 V p-p See Figure 8

0.31 V

DC Output Impedance 1 kΩ
Short-Circuit Current to Ground at VOUT ±0.20 mA

Range 4

AC Output Excitation Voltage

5

DC Bias

4

0.198 V p-p See Figure 10

0.173 V

DC Output Impedance 600 Ω
Short-Circuit Current to Ground at VOUT ±0.15 mA

SYSTEM AC CHARACTERISTICS

Signal-to-Noise Ratio 60 dB
Total Harmonic Distortion −52 dB
Spurious-Free Dynamic Range
Wide Band (0 MHz to 1 MHz) −56 dB
Narrow Band (±5 kHz) −85 dB

Unit Test Conditions/Comments

100 Ω to 1 kΩ requires extra buffer
circuitry, see the Measuring Small
Impedances section

2 V p-p output excitation voltage at
30 kHz, 200 kΩ connected between
Pin 5 and Pin 6

<0.1 Hz resolution achievable using
DDS techniques

See Figure 4 for output voltage
distribution

DC bias of the ac excitation signal;
see Figure 5

DC bias of output excitation signal;
see Figure 7

DC bias of output excitation signal;
see Figure 9

DC bias of output excitation signal.
See Figure 11

Rev. D | Page 4 of 44

Data Sheet AD5933

Y Version1

Parameter

Min Typ Max

RECEIVE STAGE

Input Leakage Current 1 nA To VIN pin
Input Capacitance

6

0.01 pF Pin capacitance between VIN and GND

Feedback Capacitance (CFB) 3 pF

ANALOG-TO-DIGITAL CONVERTER

Resolution
Sampling Rate

6

12 Bits
250 kSPS ADC throughput rate

TEMPERATURE SENSOR

Accuracy ±2.0 °C −40°C to +125°C temperature range
Resolution 0.03 °C
Temperature Conversion Time 800 s

LOGIC INPUTS

Input High Voltage (VIH) 0.7 × VDD
Input Low Voltage (VIL) 0.3 × VDD
Input Current

7

1 µA TA = 25°C

Input Capacitance 7 pF TA = 25°C

POWER REQUIREMENTS

VDD 2.7 5.5 V
IDD (Normal Mode ) 10 15 mA VDD = 3.3 V
17 25 mA VDD = 5.5 V
IDD (Standby Mode) 11 mA

16 mA VDD = 5.5 V
IDD (Power-Down Mode) 0.7 5 µA VDD = 3.3 V

1 8 µA VDD = 5.5 V

1

Temperature range for Y version = −40°C to +125°C, typical at 25°C.

2

The lower limit of the output excitation frequency can be lowered by scaling the clock supplied to the AD5933.

3

Refer to Figure 14, Figure 15, and Figure 16 for the internal oscillator frequency distribution with temperature.

4

The peak-to-peak value of the ac output excitation voltage scales with supply voltage according to the following formula:

Output Excitation Voltage (V p-p) = [2/3.3] × VDD
where VDD is the supply voltage.

5

The dc bias value of the output excitation voltage scales with supply voltage according to the following formula:

Output Excitation Bias Voltage (V) = [2/3.3] × VDD
where VDD is the supply voltage.

6

Guaranteed by design or characterization, not production tested. Input capacitance at the VOUT pin is equal to pin capacitance divided by open-loop gain of current-

to-voltage amplifier.

7

The accumulation of the currents into Pin 8, Pin 15, and Pin 16.

Unit Test Conditions/Comments

Feedback capacitance around current­to-voltage amplifier; appears in
parallel with feedback resistor

Conversion time of single temperature
measurement

VDD = 3.3 V; see the Control Register
(Register Address 0X80, Register
Address 0X81) section

Rev. D | Page 5 of 44

AD5933 Data Sheet

S

I2C SERIAL INTERFACE TIMING CHARACTERISTICS

VDD = 2.7 V to 5.5 V. All specifications T

MIN

to T

, unless otherwise noted.1

MAX

Table 2.

Parameter

f

400 kHz max SCL clock frequency

SCL

2

Limit at T

MIN

, T

MAX

Unit Description

t1 2.5 µs min SCL cycle time
t2 0.6 µs min t
t3 1.3 µs min t
t4 0.6 µs min t
t5 100 ns min t

3

t

6

0.9 µs max t
0 µs min t
t7 0.6 µs min t
t8 0.6 µs min t
t9 1.3 µs min t

, SCL high time

HIGH

, SCL low time

LOW

, start/repeated start condition hold time

HD, STA

, data setup time

SU, DAT

, data hold time

HD, DAT

, data hold time

HD, DAT

, setup time for repeated start

SU, STA

, stop condition setup time

SU, STO

, bus free time between a stop and a start condition

BUF

t10 300 ns max tF, rise time of SDA when transmitting
0 ns min tR, rise time of SCL and SDA when receiving (CMOS compatible)
t11 300 ns max tF, fall time of SCL and SDA when transmitting
0 ns min tF, fall time of SDA when receiving (CMOS compatible)
250 ns max tF, fall time of SDA when receiving
20 + 0.1 C

4

b

ns min tF, fall time of SCL and SDA when transmitting

Cb 400 pF max Capacitive load for each bus line

1

See Figure 2.

2

Guaranteed by design and characterization, not production tested.

3

A master device must provide a hold time of at least 300 ns for the SDA signal (referred to V

4

Cb is the total capacitance of one bus line in picofarads. Note that tR and tF are measured between 0.3 VDD and 0.7 VDD.

of the SCL signal) to bridge the undefined falling edge of SCL.

IH MIN

DA

t

SCL

9

START

CONDITION

t

3

t

4

t

10

t

6

t

11

Figure 2. I

t

2

2

C Interface Timing Diagram

t

t

5

7

t

4

REPEATED

START

CONDITIO N

t

1

t

8

STOP

CONDITIO N

05324-002

Rev. D | Page 6 of 44

Data Sheet AD5933

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 3.

Parameter Rating

DVDD to GND −0.3 V to +7.0 V
AVDD1 to GND −0.3 V to +7.0 V
AVDD2 to GND −0.3 V to +7.0 V
SDA/SCL to GND −0.3 V to VDD + 0.3 V
VOUT to GND −0.3 V to VDD + 0.3 V
VIN to GND −0.3 V to VDD + 0.3 V
MCLK to GND −0.3 V to VDD + 0.3 V
Operating Temperature Range

Extended Industrial (Y Grade) −40°C to +125°C
Storage Temperature Range −65°C to +160°C
Maximum Junction Temperature 150°C

SSOP Package, Thermal Impedance

θJA 139°C/W
θJC 136°C/W

Reflow Soldering (Pb-Free)

Peak Temperature 260°C
Time at Peak Temperature 10 sec to 40 sec

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

Rev. D | Page 7 of 44

AD5933 Data Sheet

PIN CONFIGURATION AND DESCRIPTIONS

NC

1

NC

2

NC

3

RFB

VIN

VOUT

NC

MCLK

NOTES:

IT IS RECO MMENDED TO TIE ALL SUPPLY

1.
CONNECTIONS (PIN 9, PIN 10, AND PIN 11)
AND RUN FROM A SINGLE SUPPLY BETWEEN

2.7V AND 5.5V. IT IS ALSO RECOMMENDED TO
CONNECT ALL GROUND SIGNALS TOGETHER
(PIN 12, PI N 13, AND PIN 14).

AD5933

4

TOP VIEW

5

(Not to Scale)

6

7

8

NC = NO CONNECT

Figure 3. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1, 2, 3, 7 NC No Connect.
4 RFB

External Feedback Resistor. Connected from Pin 4 to Pin 5 and used to set the gain of the current-to-voltage

amplifier on the receive side.
5 VIN Input to Receive Transimpedance Amplifier. Presents a virtual earth voltage of VDD/2.
6 VOUT Excitation Voltage Signal Output.
8 MCLK The master clock for the system is supplied by the user.
9 DVDD Digital Supply Voltage.
10 AVDD1 Analog Supply Voltage 1.
11 AVDD2 Analog Supply Voltage 2.
12 DGND Digital Ground.
13 AGND1 Analog Ground 1.
14 AGND2 Analog Ground 2.
15 SDA I2C Data Input. Open-drain pins requiring 10 kΩ pull-up resistors to VDD.
16 SCL I2C Clock Input. Open-drain pins requiring 10 kΩ pull-up resistors to VDD.

16

15

14

13

12

11

10

9

SCL

SDA

AGND2

AGND1

DGND

AVDD2

AVDD1

DVDD

05324-003

Rev. D | Page 8 of 44

Data Sheet AD5933

TYPICAL PERFORMANCE CHARACTERISTICS

35

30

25

20

15

NUMBER OF DEVICES

10

MEAN = 1.9824
SIGMA = 0.0072

30

25

20

15

10

NUMBER OF DEVI CES

MEAN = 0.7543
SIGMA = 0.0099

5

0

1.92 1.94 1.96 1.98 2.00 2. 02 2.04

VOLTAGE (V)

2.06

Figure 4. Range 1 Output Excitation Voltage Distribution, VDD = 3.3 V

30

MEAN = 1.4807
SIGMA = 0.0252

25

20

15

10

NUMBER OF DEVI CES

5

0

1.30

1.35 1.40 1.45 1.50 1.55 1.60 1.65 1.70

VOLTAGE (V)

1.75

Figure 5. Range 1 DC Bias Distribution, VDD = 3.3 V

30

MEAN = 0.9862
SIGMA = 0.0041

25

5

0

0.68

0.70 0.72 0.74 0.76 0.78 0.80 0.82 0.84

05324-004

VOLTAGE (V)

0.86

05324-007

Figure 7. Range 2 DC Bias Distribution, VDD = 3.3 V

30

MEAN = 0.3827
SIGMA = 0.00167

25

20

15

10

NUMBER OF DEVICES

5

0

0.370

05324-005

0.375 0. 380 0.385 0.390 0.395

VOLTAGE (V)

0.400

05324-008

Figure 8. Range 3 Output Excitation Voltage Distribution, VDD = 3.3 V

30

MEAN = 0.3092
SIGMA = 0.0014

25

20

15

10

NUMBER OF DEVI CES

5

0

0.95 0.96 0.97 0.98 0.99 1. 00 1.01 1.02

VOLTAGE (V)

Figure 6. Range 2 Output Excitation Voltage Distribution, VDD = 3.3 V

05324-006

Rev. D | Page 9 of 44

20

15

10

NUMBER OF DEVI CES

5

0

0.290

0.295 0. 300 0.305 0.310 0.315

VOLTAGE (V)

Figure 9. Range 3 DC Bias Distribution, VDD = 3.3 V

0.320

05324-009

AD5933 Data Sheet

30

MEAN = 0.1982
SIGMA = 0.0008

25

20

15

10

NUMBER OF DEVICES

5

0

0.192 0.194 0.196 0.198 0.200 0.202 0.204 0.206

VOLTAGE (V)

Figure 10. Range 4 Output Excitation Voltage Distribution, VDD = 3.3 V

30

MEAN = 0.1792
SIGMA = 0.0024

25

20

15

10

NUMBER OF DEVICES

5

15.8
AVDD1, AVDD2, DVDD CONNECTED TOG ETHER.
OUTPUT EXCITAT ION FREQUENCY = 30kHz

15.3
RFB, Z

14.8

14.3

13.8

13.3

IDD (mA)

12.8

12.3

11.8

11.3

10.8

05324-010

CALIBR AT ION

0

246810121416

= 100kΩ

MCLK FREQUENCY (MHz)

18

05324-012

Figure 12. Typical Supply Current vs. MCLK Frequency

0.4

0.2

0

–0.2

–0.4

–0.6

PHASE ERROR (Degrees)

–0.8

VDD = 3.3V

= 25°C

T

A

f = 32kHz

0

0.160

0.165 0.170 0.175 0.180 0.185 0.190 0.195 0. 200

VOLTAGE (V)

Figure 11. Range 4 DC Bias Distribution, VDD = 3.3 V

0.205

–1.0

0

50 100 150 200 250 300 350

05324-011

PHASE (Degrees)

400

05324-013

Figure 13. Typical Phase Error

Rev. D | Page 10 of 44

Data Sheet AD5933

12

N = 106
MEAN = 16.8292

12

SD = 0.142904
TEMP = –40°C

10

8

6

COUNT

4

N = 100
MEAN = 16.7257
SD = 0.137633
TEMP = 125°C

10

8

6

COUNT

4

2

0

16.4 16.6 16.8 17. 0

OSCILLATOR FREQUENCY (MHz)

17.2

05324-014

2

0

16.4 16.6 16.8 17. 0

OSCILLATOR FREQUENCY (MHz)

Figure 14. Frequency Distribution of Internal Oscillator at −40°C Figure 16. Frequency Distribution of Internal Oscillator at 125°C

16

N = 100
MEAN = 16.78 11
SD = 0.0881565

14

TEMP = 25°C

12

10

8

COUNT

6

4

2

0

16.4 16.6 16.8 17. 0

OSCILLATOR FREQUENCY (MHz)

17.2

05324-015

Figure 15. Frequency Distribution of Internal Oscillator at 25°C

17.2

05324-016

Rev. D | Page 11 of 44

AD5933 Data Sheet

TERMINOLOGY

Tot a l S ys t em A cc ur ac y

The AD5933 can accurately measure a range of impedance
values to less than 0.5% of the correct impedance value for
supply voltages between 2.7 V to 5.5 V.

Spurious-Free Dynamic Range (SFDR)

Along with the frequency of interest, harmonics of the funda­mental frequency and images of these frequencies are present at
the output of a DDS device. The spurious-free dynamic range
refers to the largest spur or harmonic present in the band of
interest. The wideband SFDR gives the magnitude of the largest
harmonic or spur relative to the magnitude of the fundamental
frequency in the 0 Hz to Nyquist bandwidth. The narrow-band
SFDR gives the attenuation of the largest spur or harmonic in a
bandwidth of ±200 kHz, about the fundamental frequency.

Signal-to-Noise Ratio (SNR)

SNR is the ratio of the rms value of the measured output signal
to the rms sum of all other spectral components below the
Nyquist frequency. The value for SNR is expressed in decibels.

Total Harmonic Distortion (THD)

THD is the ratio of the rms sum of harmonics to the funda­mental, where V1 is the rms amplitude of the fundamental
and V2, V3, V4, V5, and V6 are the rms amplitudes of the
second through the sixth harmonics. For the AD5933, THD
is defined as

22222

5

+++

THD

log20(dB)

=

V1

V6VV4V3V2

Rev. D | Page 12 of 44

Data Sheet AD5933

SYSTEM DESCRIPTION

MCLK

DDS

MICROCONTRO LLER

SCL

SDA

OSCILLATOR

I2C

INTERFACE

CORE

(27 BITS)

COS SIN

TEMPERATURE

SENSOR

DAC

R

OUT

VOUT

Z(ω)

REAL

REGISTER

IMAGINARY

REGISTER

MAC CORE

(1024 DFT)

WINDOWI NG

OF DATA

MCLK

ADC

(12 BITS)

Figure 17. Block Overview

The AD5933 is a high precision impedance converter system
solution that combines an on-board frequency generator with a
12-bit, 1 MSPS ADC. The frequency generator allows an external
complex impedance to be excited with a known frequency. The
response signal from the impedance is sampled by the on-board
ADC and DFT processed by an on-board DSP engine. The DFT
algorithm returns both a real (R) and imaginary (I) data-word at
each frequency point along the sweep. The impedance magnitude
and phase are easily calculated using the following equations:

22

IRMagnitude +=

Phase

= tan−1(I/R)

To characterize an impedance profile Z(

ω), generally a frequency

sweep is required, like that shown in Figure 18.

IMPEDANCE

FREQUENCY

Figure 18. Impedance vs. Frequency Profile

05324-018

AD5933

RFB

PROGRAMMABLE

LPF

GAIN AMPLIFIER

×5
×1

VDD/2

VIN

The AD5933 permits the user to perform a frequency sweep with
a user-defined start frequency, frequency resolution, and number
of points in the sweep. In addition, the device allows the user to
program the peak-to-peak value of the output sinusoidal signal as
an excitation to the external unknown impedance connected
between the VOUT and VIN pins.

Table 5 gives the four possible output peak-to-peak voltages and
the corresponding dc bias levels for each range for 3.3 V. These
values are ratiometric with VDD. So for a 5 V supply

98.1 −=×=1RangeforVoltageExcitationOutput

48.1 −=×=1RangeforVoltageBiasDCOutput

0.5

3.3

0.5

3.3

Table 5. Voltage Levels Respective Bias Levels for 3.3 V

Output Excitation

Range

Voltage Amplitude Output DC Bias Level

1 1.98 V p-p 1.48 V
2 0.97 V p-p 0.76 V
3 383 mV p-p

0.31 V

4 198 mV p-p 0.173 V

The excitation signal for the transmit stage is provided on-chip
using DDS techniques that permit subhertz resolution. The receive
stage receives the input signal current from the unknown impedance,
performs signal processing, and digitizes the result. The clock for
the DDS is generated from either an external reference clock,
which is provided by the user at MCLK, or by the internal
oscillator. The clock for the DDS is determined by the status of
Bit D3 in the control register (see Register Address 0x81 in the
Register Map section).

05324-017

ppV3

ppV24.2

Rev. D | Page 13 of 44

AD5933 Data Sheet

=

TRANSMIT STAGE

As shown in Figure 19, the transmit stage of the AD5933 is made
up of a 27-bit phase accumulator DDS core that provides the
output excitation signal at a particular frequency. The input to
the phase accumulator is taken from the contents of the start
frequency register (see Register Address 0x82, Register Address
0x83, and Register Address 0x84). Although the phase accumu­lator offers 27 bits of resolution, the start frequency register has
the three most significant bits (MSBs) set to 0 internally; therefore,
the user has the ability to program only the lower 24 bits of the
start frequency register.

R(GAIN)

PHASE

ACCUMULATOR

(27 BITS)

The AD5933 offers a frequency resolution programmable by the
user down to 0.1 Hz. The frequency resolution is programmed
via a 24-bit word loaded serially over the I
frequency increment register.

The frequency sweep is fully described by the programming of
three parameters: the start frequency, the frequency increment,
and the number of increments.

Start Frequency

This is a 24-bit word that is programmed to the on-board RAM
at Register Address 0x82, Register Address 0x83, and Register
Address 0x84 (see the Register Map section). The required code
loaded to the start frequency register is the result of the formula
shown in Equation 1, based on the master clock frequency and the
required start frequency output from the DDS.

⎛
⎜

⎜
⎜
⎜

⎝

⎛
⎜
⎝

For example, if the user requires the sweep to begin at 30 kHz and
has a 16 MHz clock signal connected to MCLK, the code that
needs to be programmed is given by

The user programs the value of 0x0F to Register Address 0x82, the
value of 0x5C to Register Address 0x83, and the value of 0x28 to
Register Address 0x84.

DAC

V

BIAS

Figure 19. Transmit Stage

=

CodeFrequencyStart

FrequencyStartOutputRequired

MCLK

⎞
⎟
⎠

⎛
⎜

kHz30

⎜

=CodeFrequencyStart

⎜

MHz16

⎛

⎜

⎜

⎜

4

⎝

⎝

VOUT

5324-019

2

C interface to the

⎞
⎟

(1)

27

⎟

24×

⎟
⎟

⎠

⎞
⎟

⎟

27

0x0F5C282

≡×

⎟

⎞

⎟

⎟

⎟

⎠

⎠

Frequency Increment

This is a 24-bit word that is programmed to the on-board RAM
at Register Address 0x85, Register Address 0x86, and Register
Address 0x87 (see the Register Map). The required code loaded
to the frequency increment register is the result of the formula
shown in Equation 2, based on the master clock frequency and the
required increment frequency output from the DDS.

CodeIncrementFrequency

⎛
⎜

Re

⎜
⎜
⎜

⎝

MCLK

⎛
⎜
⎝

IncrementFrequencyquired

⎞
⎟

4

⎠

⎞
⎟

(2)

27

⎟

×

2

⎟
⎟

⎠

For example, if the user requires the sweep to have a resolution
of 10 Hz and has a 16 MHz clock signal connected to MCLK, the
code that needs to be programmed is given by

⎛
⎜

⎜

=CodeIncrementFrequency

⎜

⎛

⎜

⎜

⎜

⎝

⎝

⎞
⎟

Hz10

⎟

0x00014F

≡

⎟

MHz16

⎞

⎟

⎟

⎟

4

⎠

⎠

The user programs the value of 0x00 to Register Address 0x85,
the value of 0x01 to Register Address 0x86, and the value of 0x4F
to Register Address 0x87.

Number of Increments

This is a 9-bit word that represents the number of frequency
points in the sweep. The number is programmed to the on-board
RAM at Register Address 0x88 and Register Address 0x89 (see the
Register Map section). The maximum number of points that can
be programmed is 511.

For example, if the sweep needs 150 points, the user programs
the value of 0x00 to Register Address 0x88 and the value of 0x96
to Register Address 0x89.

Once the three parameter values have been programmed, the
sweep is initiated by issuing a start frequency sweep command to
the control register at Register Address 0x80 and Register Address
0x81 (see the Register Map section). Bit D2 in the status register
(Register Address 0x8F) indicates the completion of the frequency
measurement for each sweep point. Incrementing to the next
frequency sweep point is under the control of the user. The
measured result is stored in the two register groups that follow:
0x94, 0x95 (real data) and 0x96, 0x97 (imaginary data) that should
be read before issuing an increment frequency command to the
control register to move to the next sweep point. There is the
facility to repeat the current frequency point measurement by
issuing a repeat frequency command to the control register. This
has the benefit of allowing the user to average successive readings.
When the frequency sweep has completed all frequency points,
Bit D3 in the status register is set, indicating completion of the
sweep

. Once this bit is set, further increments are disabled.

Rev. D | Page 14 of 44