How it Works
ANALOG DEVICES
Loading...
AD5791-EP
Service Manual
20 pgs1.27 Mb0
Table of contents
Loading...

ANALOG DEVICES AD5791-EP Service Manual

1 ppm, 20-Bit,
±1 LSB INL, Voltage Output DAC
AD5791-EP
A1
6.8kΩ
6kΩ
6.8kΩ
R1 R
FB
20-BIT
DAC
DAC REG
20
20
INPUT SHIFT
REGISTER
AND
CONTROL
LOGIC
POWER-ON RESET AND CLEAR LOG IC
AD5791-EP
IOV
CC
SDIN
V
CC
V
DD
V
REFPF
V
REFPS
V
REFNF
AGNDV
SS
DGND V
REFNS
SCLK SYNC
SDO
LDAC
CLR
RESET
R
FB
INV
V
OUT
10455-001
Enhanced Product

FEATURES

1 ppm resolution 1 ppm INL
7.5 nV/√Hz noise spectral density
0.19 LSB long-term linearity stability <0.05 ppm/°C temperature drift 1 µs settling time
1.4 nV-sec glitch impulse 20-lead TSSOP package Wide power supply range up to ±16.5 V 35 MHz Schmitt triggered digital interface
1.8 V compatible digital interface Extended automotive operating temperature range: −55°C
to +125°C

ENHANCED PRODUCT FEATURES

Supports defense and aerospace applications (AQEC
standard) Military temperature range (−55°C to +125°C) Controlled manufacturing baseline One assembly/test site One fabrication site Enhanced product change notification Qualification data available on request

APPLICATIONS

Medical instrumentation Test and measurement Industrial control High end scientific and aerospace instrumentation

FUNCTIONAL BLOCK DIAGRAM

Figure 1.

COMPANION PRODUCTS

Ultra precision op amps: AD8675, AD8676 High voltage op amp: ADA4898-1
Additional companion products on the AD5791 product page
Table 1. Related Device
Part No. Description
AD5781 18-bit, 0.5 LSB INL, voltage output DAC

GENERAL DESCRIPTION

The AD5791-EP1 is a single 20-bit, unbuffered voltage-output DAC that operates from a bipolar supply of up to 33 V. T he AD5791 accepts a positive reference input in the range 5 V to V
− 2.5 V and a negative reference input in the range VSS +
DD
2.5 V to 0 V. T h e AD5791-EP offers a relative accuracy specification of ±1 LSB max, and operation is guaranteed monotonic with a ±1 LSB DNL maximum specification.
The part uses a versatile 3-wire serial interface that operates at clock rates up to 35 MHz and that is compatible with standard SPI, QSPI™, MICROWIRE™, and DSP interface standards. The part incorporates a power-on reset circuit that ensures the DAC output powers up to 0 V in a known output impedance state and remains in this state until a valid write to the device takes
1
Protected by U.S. Patents No. 7,884,747 and 8,089,380. Other patents pending.
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
place. The part provides an output clamp feature that places the output in a defined load state.
The AD5791-EP is available in a compact, 20-lead TSSOP package and operates at the extended automotive temperature range of −55°C to +125°C. Additional application and technical information can be found in the AD5791 data sheet.

PRODUCT HIGHLIGHTS

1. 1 ppm Accuracy.
2. Wide Power Supply Range up to ±16.5 V.
3. Operating Temperature Range: −55°C to +125°C.
4. Low 7.5 nV/√Hz Noise Spectral Density.
5. Low 0.05 ppm/°C Temperature Drift.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com
AD5791-EP Enhanced Product
TABLE OF CONTENTS
Features .............................................................................................. 1
Enhanced Product Features ............................................................ 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
Companion Products ....................................................................... 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2

REVISION HISTORY

2/12—Revision 0: Initial Version
Specifications .....................................................................................3
Timing Characteristics .................................................................5
Absolute Maximum Ratings ............................................................8
ESD Caution...................................................................................8
Pin Configuration and Function Descriptions ..............................9
Typical Performance Characteristics ........................................... 10
Outline Dimensions ....................................................................... 18
Ordering Guide .......................................................................... 18
Rev. 0 | Page 2 of 20
Enhanced Product AD5791-EP
Full-Scale Error
−7
±0.1
+7
LSB
±0.04
ppm FSR/°C

SPECIFICATIONS

VDD = 12.5 V to 16.5 V, VSS = −16.5 V to −12.5 V, V R
= unloaded, CL = unloaded, all specifications T
L
Table 2.
Parameter1 Min Typ Max Unit Test Conditions/Comments
STATIC PERFORMANCE2
Resolution 20 Bits Integral Nonlinearity Error (Relative Accuracy) −1 ±0.25 +1 LSB V
−1.5 ±0.25 +1.5 LSB V
−1.5 ±0.5 +1.5 LSB V
−3 ±1 +3 LSB Differential Nonlinearity Error −1 ±0.5 +1 LSB V
−1.5 ±0.75 +1.5 LSB V
−2.5 ±1 +2.5 LSB V Linearity Error Long-Term Stability4 0.16 LSB After 500 hours at TA = 125°C
0.19 LSB After 1000 hours at TA = 125°C
0.11 LSB After 1000 hours at TA = 100°C
−11 ±0.25 +11 LSB
−21 ±0.8 +21 LSB
−4 ±0.1 +4 LSB
−4 ±0.25 +4 LSB
−6 ±0.8 +6 LSB Full-Scale Error Temperature Coefficient ±0.02 ppm FSR/°C Zero-Scale Error −7 ±0.1 +7 LSB
−10 ±0.15 +10 LSB
−21 ±0.75 +21 LSB
−4 ±0.1 +4 LSB
−4 ±0.15 +4 LSB
−6 ±0.75 +6 LSB Zero-Scale Error Temperature Coefficient3 Gain Error −6 ±0.3 +6 ppm FSR
−10 ±0.4 +10 ppm FSR
−20 ±0.4 +20 ppm FSR
−6 ±0.3 +6 ppm FSR
−6 ±0.4 +6 ppm FSR
−7 ±0.4 +7 ppm FSR Gain Error Temperature Coefficient3 R1, RFB Matching 0.01 %
OUTPUT CHARACTERISTICS3
Output Voltage Range V Output Slew Rate 50 V/µs Output Voltage Settling Time 1 µs 10 V step to 0.02%, using the AD845 buffer
1 µs 500 code step to ±1 LSB5 Output Noise Spectral Density 7.5 nV/√Hz at 1 kHz, DAC code = midscale
7.5 nV/√Hz at 10 kHz, DAC code = midscale
7.5 nV/√Hz At 100 kHz, DAC code = midscale Output Voltage Noise 1.1 µV p-p DAC code = midscale, 0.1 Hz to 10 Hz
MIN
REFP
to T
= 10 V, V
MAX
= −10 V, VCC = 2.7 V to +5.5 V, IOVCC = 1.71 V to 5.5 V,
REFN
, unless otherwise noted.
±0.04 ppm FSR/°C
V
REFN
V
REFP
= +10 V, V
REFP
= 0°C to 105°C
T
A
= +10 V, V
REFP
= 10 V, V
REFP
V
= 5 V, V
REFP
= +10 V, V
REFP
= 10 V, V
REFP
= 5 V, V
REFP
V
= +10 V, V
REFP
V
= 10 V, V
REFP
V
= 5 V, V
REFP
V
= +10 V, V
REFP
V
= 10 V, V
REFP
V
= 5 V, V
REFP
V
= +10 V, V
REFP
V
= 10 V, V
REFP
V
= 5 V, V
REFP
V
= +10 V, V
REFP
V
= 10 V, V
REFP
V
= 5 V, V
REFP
V
= +10 V, V
REFP
V
= 10 V, V
REFP
V
= 5 V, V
REFP
V
= +10 V, V
REFP
V
= 10 V, V
REFP
V
= 5 V, V
REFP
REFN
REFN
= 0 V3
REFN
= 0 V3
REFN
REFN
= 0 V
REFN
= 0 V
REFN
REFN
= 0 V3
REFN
= 0 V3
REFN
= −10 V3, TA = 0°C to 105°C
REFN
= 0 V3, TA = 0°C to 105°C
REFN
= 0 V3, TA = 0°C to 105°C
REFN
REFN
= 0 V3
REFN
= 0 V3
REFN
= −10 V3, TA = 0°C to 105°C
REFN
= 0 V3, TA = 0°C to 105°C
REFN
= 0 V3, TA = 0°C to 105°C
REFN
REFN
= 0 V3
REFN
= 0 V3
REFN
= −10 V3, TA = 0°C to 105°C
REFN
= 0 V3, TA = 0°C to 105°C
REFN
= 0 V3, TA = 0°C to 105°C
REFN
in unity-gain mode
6
bandwidth
= −10 V,
= −10 V
= −10 V
= −10 V3
= −10 V3
= −10 V3
Rev. 0 | Page 3 of 20
AD5791-EP Enhanced Product
Spurious Free Dynamic Range
100 dB
1 kHz tone, 10 kHz sample rate
Output High Voltage, VOH
IOVCC − 0.5 V
V
IOVCC = 1.71 V to 5.5 V, sourcing 1 mA
High Impedance Leakage Current
±1
µA
95 dB
VDD ± 200 mV, 50 Hz/60 Hz, V
= −15 V
Parameter1 Min Typ Max Unit Test Conditions/Comments
Midscale Glitch Impulse7 3.1 nV-sec V
1.7 nV-sec V
1.4 nV-sec V MSB Segment Glitch Impulse7
9.1 nV-sec V
3.6 nV-sec V
1.9 nV-sec V Output Enabled Glitch Impulse 45 nV-sec On removal of output ground clamp Digital Feedthrough 0.4 nV-sec DC Output Impedance (Normal Mode) 3.4 kΩ DC Output Impedance (Output Clamped
6 kΩ
to Ground)
Total Harmonic Distortion 97 dB 1 kHz tone, 10 kHz sample rate
REFERENCE INPUTS3
V
Input Range 5 VDD − 2.5 V V
REFP
V
Input Range VSS + 2.5 V 0
REFN
DC Input Impedance 5 6.6 kΩ V
Input Capacitance 15 pF V
LOGIC INPUTS3
Input Current8 −1 +1 µA Input Low Voltage, VIL 0.3 × IOVCC V IOVCC = 1.71 V to 5.5 V Input High Voltage, VIH 0.7 × IOVCC V IOVCC = 1.71 V to 5.5 V Pin Capacitance 5 pF
LOGIC OUTPUT (SDO)3
Output Low Voltage, VOL 0.4 V IOVCC = 1.71 V to 5.5 V, sinking 1 mA
= +10 V, V
REFP
= 10 V, V
REFP
= 5 V, V
REFP
= +10 V, V
REFP
= 10 V, V
REFP
= 5 V, V
REFP
, V
REFP
REFN
= −10 V
REFN
= 0 V
REFN
= 0 V
REFN
= −10 V, see Figure 43
REFN
= 0 V, see Figure 44
REFN
= 0 V, see Figure 45
REFN
, code dependent,
typical at midscale code
, V
REFP
REFN
High Impedance Output Capacitance 3 pF
POWER REQUIREMENTS All digital inputs at DGND or IOVCC
VDD 7.5 VSS + 33 V VSS VDD − 33 −2.5 V VCC 2.7 5.5 V IOVCC 1.71 5.5 V IOVCC ≤ VCC IDD 4.2 5.2 mA ISS 4 4.9 mA ICC 600 900 µA IOICC 52 140 µA SDO disabled DC Power Supply Rejection Ratio
3, 9
±0.6 µV/V V
± 10%, V
DD
= 15 V
SS
±0.6 µV/V VSS ± 10%, VDD = 15 V AC Power Supply Rejection Ratio3
SS
95 dB ∆VSS ± 200 mV, 50 Hz/60 Hz, VDD = 15 V
1
Temperature range: −55°C to +125°C, typical at +25°C and VDD = +15 V, VSS = −15 V, V
2
Performance characterized with AD8676BRZ voltage reference buffers and AD8675ARZ output buffer.
3
Guaranteed by design and characterization; not production tested.
4
Linearity error refers to both INL error and DNL error, either parameter can be expected to drift by the amount specified after the length of time specified.
5
AD5791-EP configured in ×2 gain mode, 25 pF compensation capacitor on AD797.
6
Includes noise contribution from AD8676BRZ voltage reference buffers.
7
The AD5791-EP is configured in bias compensation mode with a low-pass RC filter on the output. R = 300 Ω, C = 143 pF (total capacitance seen by the output buffer,
lead capacitance, and so forth).
8
Current flowing in an individual logic pin.
9
Includes PSRR of AD8676BRZ voltage reference buffers.
= +10 V, V
REFP
= −10 V.
REFN
Rev. 0 | Page 4 of 20
Enhanced Product AD5791-EP
t3 9 5
ns min
SCLK low time
t9
12 7 ns min
Data hold time
t20 0 0
ns min
SYNC rising edge to SCLK rising edge ignore

TIMING CHARACTERISTICS

VCC = 2.7 V to 5.5 V; all specifications T
MIN
to T
, unless otherwise noted.
MAX
Table 3.
1
Limit
Parameter
2
t
40 28 ns min SCLK cycle time
1
IOVCC = 1.71 V to 3.3 V IOVCC = 3.3 V to 5.5 V
Unit Test Conditions/Comments
92 60 ns min SCLK cycle time (readback and daisy-chain modes) t2 15 10 ns min SCLK high time
t4 5 5 ns min t5 2 2 ns min t6 48 40 ns min t7 8 6 ns min
SYNC to SCLK falling edge setup time SCLK falling edge to Minimum
SYNC high time
SYNC rising edge hold time
SYNC rising edge to next SCLK falling edge ignore
t8 9 7 ns min Data setup time
t10 13 10 ns min t11 20 16 ns min t12 14 11 ns min t13 130 130 ns typ t14 130 130 ns typ t15 50 50 ns min t16 140 140 ns typ t17 0 0 ns min t18 65 60 ns max
LDAC falling edge to SYNC falling edge SYNC rising edge to LDAC falling edge LDAC pulse width low LDAC falling edge to output response time SYNC rising edge to output response time (LDAC tied low) CLR pulse width low CLR pulse activation time SYNC falling edge to first SCLK rising edge SYNC rising edge to SDO tristate (CL = 50 pF)
t19 62 45 ns max SCLK rising edge to SDO valid (CL = 50 pF)
t21 35 35 ns typ t22 150 150 ns typ
1
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of IOVCC) and timed from a voltage level of (VIL + VIH)/2.
2
Maximum SCLK frequency is 35 MHz for write mode and 16 MHz for readback and daisy-chain modes.
RESET pulse width low RESET pulse activation time
Rev. 0 | Page 5 of 20
AD5791-EP Enhanced Product
t
7
2421
DB23 DB0
t
10
t
8
t
4
t
6
t
5
t
3
t
1
t
2
t
9
t
11
t
12
t
13
t
14
t
15
t
16
t
21
t
22
V
OUT
V
OUT
V
OUT
V
OUT
RESET
CLR
LDAC
SDIN
SYNC
SCLK
10455-002
DB23 DB0
NOP CONDITION
REGISTER CONTENTS CLOCKED OUT
t
1
t
17
t
2
t
5
t
17
t
5
t
19
t
18
t
20
t
3
t
4
t
8
t
9
t
6
t
7
24221 24 1
DB23 DB0
INPUT WORD SPECIFIES
REGISTER TO BE READ
SDO
SDIN
SYNC
SCLK
10455-003
Figure 2. Write Mode Timing Diagram
Figure 3. Readback Mode Timing Diagram
Rev. 0 | Page 6 of 20
Loading...
+ 14 hidden pages
Buy Points How it Works FAQ Contact Us Questions and Suggestions Privacy Policy Cookie Policy Terms of Use