1 ppm 20-Bit,
VCCVDDV
Data Sheet
FEATURES
1 ppm resolution
1 ppm INL
7.5 nV/√Hz noise spectral density
0.19 LSB long-term linearity stability
<0.05 ppm/°C temperature drift
1 μs settling time
1.4 nV-sec glitch impulse
Operating temperature range: −40°C to +125°C
20-lead TSSOP package
Wide power supply range up to ±16.5 V
35 MHz Schmitt triggered digital interface
1.8 V compatible digital interface
APPLICATIONS
Medical instrumentation
Test and measurement
Industrial control
High end scientific and aerospace instrumentation
±1 LSB INL, Voltage Output DAC
AD5791
FUNCTIONAL BLOCK DIAGRAM
REFPFVREFPS
6.8kΩ
6kΩ
R1 R
6.8kΩ
FB
R
INV
V
FB
OUT
IOV
CC
SDIN
SCLK
SYNC
SDO
LDAC
CLR
RESET
DGND V
AD5791
INPUT
SHIFT
REGISTER
AND
CONTROL
LOGIC
POWER-ON-RESET
AND CLEAR LOG IC
20
SS
DAC
REG
AGNDV
20
Figure 1.
Table 1. Complementary Devices
Part No. Description
AD8675
Ultra precision, 36 V, 2.8 nV/√Hz rail-to-rail
output op amp
AD8676
Ultra precision, 36 V, 2.8 nV/√Hz dual rail-torail output op amp
ADA4898-1
High voltage, low noise, low distortion, unity
gain stable, high speed op amp
V
20-BIT
DAC
REFNF
A1
REFNS
08964-001
GENERAL DESCRIPTION
The AD57911 is a single 20-bit, unbuffered voltage-output DAC
that operates from a bipolar supply of up to 33 V. The AD5791
accepts a positive reference input in the range 5 V to V
and a negative reference input in the range V
+ 2.5 V to 0 V.
SS
The AD5791 offers a relative accuracy specification of ±1 LSB
max, and operation is guaranteed monotonic with a ±1 LSB
DNL maximum specification.
The part uses a versatile 3-wire serial interface that operates at
clock rates up to 35 MHz and that is compatible with standard
SPI, QSPI™, MICROWIRE™, and DSP interface standards. The
part incorporates a power-on reset circuit that ensures the DAC
1
Protected by U.S. Patent No. 7,884,747. Other patents pending.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
− 2.5 V
DD
Table 2. Related Device
Part No. Description
AD5781 18-bit, 0.5 LSB INL, voltage output DAC
output powers up to 0 V and in a known output impedance
state and remains in this state until a valid write to the device
takes place. The part provides an output clamp feature that
places the output in a defined load state.
PRODUCT HIGHLIGHTS
1. 1 ppm Accuracy.
2. Wide Power Supply Range up to ±16.5 V.
3. Operating Temperature Range: −40°C to +125°C.
4. Low 7.5 nV/√Hz Noise Spectral Density.
5. Low 0.05 ppm/°C Temperature Drift.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2010–2011 Analog Devices, Inc. All rights reserved.
AD5791 Data Sheet
TABLE OF CONTENTS
Features.............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram ..............................................................1
General Description......................................................................... 1
Product Highlights........................................................................... 1
Revision History ...............................................................................2
Specifications..................................................................................... 3
Timing Characteristics ................................................................ 5
Absolute Maximum Ratings............................................................ 8
ESD Caution.................................................................................. 8
Pin Configuration and Function Descriptions............................. 9
Typical Performance Characteristics........................................... 10
Terminology.................................................................................... 18
Theory of Operation ......................................................................20
REVISION HISTORY
11/11—Rev. B to Rev. C
Added Figure 48; Renumbered Sequentially .............................. 17
Change to Ideal Transfer Function Equation.............................. 22
9/11—Rev. A to Rev. B
Added Patent Note ........................................................................... 1
Changes to Table 3............................................................................ 3
Changes to OPGND Description Column, Table 12................. 23
Change to Figure 51 ....................................................................... 25
DAC Architecture....................................................................... 20
Serial Interface............................................................................ 20
Hardware Control Pins.............................................................. 21
On-Chip Registers...................................................................... 22
AD5791 Features............................................................................ 25
Power-On to 0 V......................................................................... 25
Configuring the AD5791 .......................................................... 25
DAC Output State ...................................................................... 25
Linearity Compensation............................................................ 25
Output Amplifier Configuration.............................................. 25
Applications Information.............................................................. 27
Typical Operating Circuit ......................................................... 27
Outline Dimensions....................................................................... 28
Ordering Guide .......................................................................... 28
8/11—Rev. 0 to Rev. A
Change to Features Section..............................................................1
Changes to Specifications Section, Table 3....................................3
Deleted t
Subsequent Timing Parameters Sequentially ................................5
Changes to Figure 2 and Figure 3....................................................6
Changes to Figure 4...........................................................................7
Changes to Figure 42...................................................................... 16
Changes to Figure 43...................................................................... 16
Added Figure 44, Figure 45, and Figure 46, Renumbered
Sequentially .....................................................................................16
7/10—Revision 0: Initial Version
Timing Specification in Table 4, Renumbered
14
Rev. C | Page 2 of 28
Data Sheet AD5791
SPECIFICATIONS
VDD = 12.5 V to 16.5 V, VSS = −16.5 V to −12.5 V, V
R
= unloaded, CL = unloaded, all specifications T
L
MIN
REFP
to T
= 10 V, V
MAX
= −10 V, VCC = 2.7 V to +5.5 V, IOVCC = 1.71 V to 5.5 V,
REFN
, unless otherwise noted.
Table 3.
A, B Version
Parameter Min Typ Max Unit Test Conditions/Comments
STATIC PERFORMANCE2
Resolution 20 Bits
Integral Nonlinearity Error (Relative Accuracy) −1 ±0.25 +1 LSB B version, V
−1.5 ±0.25 +1.5 LSB B version, V
−1.5 ±0.5 +1.5 LSB B version, V
−3 ±1 +3 LSB B version, V
−4 ±2 +4 LSB A version4
Differential Nonlinearity Error −1 ±0.5 +1 LSB V
−1.5 ±0.75 +1.5 LSB V
−2.5 ±1 +2.5 LSB V
Linearity Error Long Term Stability5 0.16 LSB After 500 hours at TA = 125°C
0.19 LSB After 1000 hours at TA = 125°C
0.11 LSB After 1000 hours at TA = 100°C
Full-Scale Error −7 ±0.1 +7 LSB V
−11 ±0.25 +11 LSB V
−21 ±0.8 +21 LSB V
−4 ±0.1 +4 LSB V
−4 ±0.25 +4 LSB V
−6 ±0.8 +6 LSB V
Full-Scale Error Temperature Coefficient ±0.02 ppm FSR/°C
Zero-Scale Error −7 ±0.1 +7 LSB V
−10 ±0.15 +10 LSB V
−21 ±0.75 +21 LSB V
−4 ±0.1 +4 LSB V
−4 ±0.15 +4 LSB V
−6 ±0.75 +6 LSB V
Zero-Scale Error Temperature Coefficient3 ±0.04 ppm FSR/°C
Gain Error −6 ±0.3 +6 ppm FSR V
−10 ±0.4 +10 ppm FSR V
−20 ±0.4 +20 ppm FSR V
−6 ±0.3 +6 ppm FSR V
−6 ±0.4 +6 ppm FSR V
−7 ±0.4 +7 ppm FSR V
Gain Error Temperature Coefficient3 ±0.04 ppm FSR/°C
R1, RFB Matching 0.01 %
OUTPUT CHARACTERISTICS3
Output Voltage Range V
V
REFN
Output Slew Rate 50 V/μs
Output Voltage Settling Time 1 μs 10 V step to 0.02%, using the AD845 buffer
1 μs 500 code step to ±1 LSB6
Output Noise Spectral Density 7.5 nV/√Hz at 1 kHz, DAC code = midscale
7.5 nV/√Hz at 10 kHz, DAC code = midscale
7.5 nV/√Hz At 100 kHz, DAC code = midscale
Output Voltage Noise 1.1 μV p-p DAC code = midscale, 0.1 Hz to 10 Hz
1
V
REFP
= +10 V, V
= 0°C to 105°C
T
A
REFP
REFP
REFP
REFP
REFP
REFP
REFP
REFP
REFP
REFP
REFP
REFP
REFP
REFP
REFP
REFP
REFP
REFP
REFP
REFP
REFP
REFP
REFP
REFP
REFP
= +10 V, V
= 10 V, V
= 5 V, V
= +10 V, V
= 10 V, V
= 5 V, V
= +10 V, V
= 10 V, V
= 5 V, V
= +10 V, V
= 10 V, V
= 5 V, V
= +10 V, V
= 10 V, V
= 5 V, V
= +10 V, V
= 10 V, V
= 5 V, V
= +10 V, V
= 10 V, V
= 5 V, V
= +10 V, V
= 10 V, V
= 5 V, V
REFN
= 0 V
REFN
= 0 V
REFN
REFN
= 0 V3
REFN
= 0 V3
REFN
= −10 V3, TA = 0°C to 105°C
REFN
= 0 V3, TA = 0°C to 105°C
REFN
= 0 V3, TA = 0°C to 105°C
REFN
REFN
= 0 V3
REFN
= 0 V3
REFN
= −10 V3, TA = 0°C to 105°C
REFN
= 0 V3, TA = 0°C to 105°C
REFN
= 0 V3, TA = 0°C to 105°C
REFN
REFN
= 0 V3
REFN
= 0 V3
REFN
= −10 V3, TA = 0°C to 105°C
REFN
= 0 V3, TA = 0°C to 105°C
REFN
= 0 V3, TA = 0°C to 105°C
REFN
in unity-gain mode
7
bandwidth
REFN
REFN
REFN
REFN
= −10 V
= −10 V3
= −10 V3
= −10 V3
= −10 V,
= −10 V
= 0 V3
= 0 V3
Rev. C | Page 3 of 28
AD5791 Data Sheet
A, B Version
1
Parameter Min Typ Max Unit Test Conditions/Comments
Midscale Glitch Impulse8 3.1 nV-sec V
1.7 nV-sec V
1.4 nV-sec V
MSB Segment Glitch Impulse8 9.1 nV-sec V
3.6 nV-sec V
1.9 nV-sec V
= +10 V, V
REFP
= 10 V, V
REFP
= 5 V, V
REFP
= +10 V, V
REFP
= 10 V, V
REFP
= 5 V, V
REFP
= −10 V
REFN
= 0 V
REFN
= 0 V
REFN
= −10 V, see Figure 43
REFN
= 0 V, see Figure 44
REFN
= 0 V, see Figure 45
REFN
Output Enabled Glitch Impulse 45 nV-sec On removal of output ground clamp
Digital Feedthrough 0.4 nV-sec
DC Output Impedance (Normal Mode) 3.4 kΩ
DC Output Impedance (Output Clamped
6 kΩ
to Ground)
Spurious Free Dynamic Range 100 dB 1 kHz tone, 10 kHz sample rate
Total Harmonic Distortion 97 dB 1 kHz tone, 10 kHz sample rate
REFERENCE INPUTS3
V
Input Range 5 VDD − 2.5 V V
REFP
V
Input Range VSS + 2.5 V 0
REFN
DC Input Impedance 5 6.6 kΩ V
, V
, code dependent,
REFP
REFN
typical at midscale code
Input Capacitance 15 pF V
REFP
, V
REFN
LOGIC INPUTS3
Input Current9 −1 +1 μA
Input Low Voltage, VIL 0.3 × IOVCC V IOVCC = 1.71 V to 5.5 V
Input High Voltage, VIH 0.7 × IOVCC V IOVCC = 1.71 V to 5.5 V
Pin Capacitance 5 pF
LOGIC OUTPUT (SDO)3
Output Low Voltage, VOL 0.4 V IOVCC = 1.71 V to 5.5 V, sinking 1 mA
Output High Voltage, VOH IOVCC − 0.5 V V IOVCC = 1.71 V to 5.5 V, sourcing 1 mA
High Impedance Leakage Current ±1 μA
High Impedance Output Capacitance 3 pF
POWER REQUIREMENTS All digital inputs at DGND or IOVCC
VDD 7.5 VSS + 33 V
VSS V
− 33 −2.5 V
DD
VCC 2.7 5.5 V
IOVCC 1.71 5.5 V IOVCC ≤ VCC
IDD 4.2 5.2 mA
ISS 4 4.9 mA
ICC 600 900 μA
IOICC 52 140 μA SDO disabled
DC Power Supply Rejection Ratio
3, 10
±0.6 μV/V VDD ± 10%, V
= 15 V
SS
±0.6 μV/V VSS ± 10%, VDD = 15 V
AC Power Supply Rejection Ratio3 95 dB VDD ± 200 mV, 50 Hz/60 Hz, V
= −15 V
SS
95 dB ∆VSS ± 200 mV, 50 Hz/60 Hz, VDD = 15 V
1
Temperature range: −40°C to +125°C, typical at +25°C and VDD = +15 V, VSS = −15 V, V
2
Performance characterized with AD8676BRZ voltage reference buffers and AD8675ARZ output buffer.
3
Guaranteed by design and characterization, not production tested.
4
Valid for all voltage reference spans.
5
Linearity error refers to both INL error and DNL error, either parameter can be expected to drift by the amount specified after the length of time specified.
6
AD5791 configured in X2 gain mode, 25 pF compensation capacitor on AD797.
7
Includes noise contribution from AD8676BRZ voltage reference buffers.
8
The AD5791 is configured in bias compensation mode with a low-pass RC filter on the output. R = 300 Ω, C = 143 pF.(total capacitance seen by the output buffer, lead
capacitance, and so forth).
9
Current flowing in an individual logic pin.
10
Includes PSRR of AD8676BRZ voltage reference buffers.
= +10 V, V
REFP
= −10 V.
REFN
Rev. C | Page 4 of 28
Data Sheet AD5791
TIMING CHARACTERISTICS
VCC = 2.7 V to 5.5 V; all specifications T
Table 4.
Parameter
2
t
40 28 ns min SCLK cycle time
1
IOVCC = 1.71 V to 3.3 V IOVCC = 3.3 V to 5.5 V
92 60 ns min SCLK cycle time (readback and daisy-chain modes)
t2 15 10 ns min SCLK high time
t3 9 5 ns min SCLK low time
t4 5 5 ns min
t5 2 2 ns min
t6 48 40 ns min
t7 8 6 ns min
t8 9 7 ns min Data setup time
t9 12 7 ns min Data hold time
t10 13 10 ns min
t11 20 16 ns min
t12 14 11 ns min
t13 130 130 ns typ
t14 130 130 ns typ
t15 50 50 ns min
t16 140 140 ns typ
t17 0 0 ns min
t18 65 60 ns max
t19 62 45 ns max SCLK rising edge to SDO valid (CL = 50 pF)
t20 0 0 ns min
t21 35 35 ns typ
t22 150 150 ns typ
1
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of IOVCC) and timed from a voltage level of (VIL + VIH)/2.
2
Maximum SCLK frequency is 35 MHz for write mode and 16 MHz for readback and daisy-chain modes.
MIN
Limit1
to T
, unless otherwise noted.
MAX
Unit Test Conditions/Comments
to SCLK falling edge setup time
SYNC
SCLK falling edge to SYNC
Minimum SYNC
rising edge to next SCLK falling edge ignore
SYNC
falling edge to SYNC falling edge
LDAC
rising edge to LDAC falling edge
SYNC
pulse width low
LDAC
falling edge to output response time
LDAC
rising edge to output response time (LDAC tied low)
SYNC
pulse width low
CLR
pulse activation time
CLR
falling edge to first SCLK rising edge
SYNC
rising edge to SDO tristate (CL = 50 pF)
SYNC
rising edge to SCLK rising edge ignore
SYNC
pulse width low
RESET
pulse activation time
RESET
high time
rising edge hold time
Rev. C | Page 5 of 28
AD5791 Data Sheet
SCLK
t
3
t
9
t
15
16
SYNC
SDIN
LDAC
V
OUT
V
OUT
CLR
t
6
t
4
t
8
DB23 DB0
t
10
t
t
1
t
2
t
7
2421
t
5
t
t
11
t
14
12
t
13
SCLK
SYNC
SDIN
SDO
V
OUT
RESET
V
OUT
t
21
t
22
08964-002
Figure 2. Write Mode Timing Diagram
t
t
17
t
6
t
4
t
t
8
DB23 DB0
9
INPUT WORD SPECIFIES
REGISTER TO BE READ
t
1
t
3
t
2
t
7
24221241
t
t
5
17
NOP CONDIT ION
DB23 DB0
REGISTER CONTENTS CLOCKED OUT
t
19
20
t
5
t
18
08964-003
Figure 3. Readback Mode Timing Diagram
Rev. C | Page 6 of 28
Data Sheet AD5791
t
20
t
5
t
18
08964-004
SCLK
SYNC
SDIN
SDO
t
t
17
12 24 4825
t
6
t
4
t
8
DB23
INPUT WORD FOR DAC N
DB23
t
3
t
9
UNDEFINED
1
26
t
2
DB0 DB23 DB0
INPUT WORD FOR DAC N – 1
t
19
DB0 DB23 DB0
INPUT WORD FOR DAC N
Figure 4. Daisy-Chain Mode Timing Diagram
Rev. C | Page 7 of 28
AD5791 Data Sheet
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted. Transient currents of up to
100 mA do not cause SCR latch-up.
Table 5.
Parameter Rating
VDD to AGND −0.3 V to +34 V
VSS to AGND −34 V to +0.3 V
VDD to VSS −0.3 V to +34 V
VCC to DGND −0.3 V to +7 V
IOVCC to DGND
−0.3 V to V
+ 0.3 V or +7 V
CC
(whichever is less)
Digital Inputs to DGND
−0.3 V to IOV
+ 0.3 V or
CC
+7 V (whichever is less)
V
to AGND −0.3 V to VDD + 0.3 V
OUT
V
to AGND −0.3 V to VDD + 0.3 V
REFPF
V
to AGND −0.3 V to VDD + 0.3 V
REFPS
V
to AGND VSS − 0.3 V to + 0.3 V
REFNF
V
to AGND VSS − 0.3 V to + 0.3 V
REFNS
DGND to AGND −0.3 V to +0.3 V
Operating Temperature Range, TA
Industrial −40°C to + 125°C
Storage Temperature Range −65°C to +150°C
Maximum Junction Temperature,
max
T
J
150°C
Power Dissipation (TJ max − TA)/θJA
TSSOP Package
θJA Thermal Impedance 143°C/W
θJC Thermal Impedance 45°C/W
Lead Temperature JEDEC industry standard
Soldering J-STD-020
ESD (Human Body Model) 1.5 kV
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
This device is a high performance integrated circuit with an
ESD rating of 1.5 kV, and it is ESD sensitive. Proper precautions
should be taken for handling and assembly.
ESD CAUTION
Rev. C | Page 8 of 28
Data Sheet AD5791
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
INV
V
OUT
V
REFPS
V
REFPF
V
RESET
CLR
LDAC
V
IOV
DD
CC
CC
1
2
3
4
(Not to Scale)
5
6
7
8
9
10
AD5791
TOP VIEW
20
R
FB
19
AGND
18
V
SS
17
V
REFNS
16
V
REFNF
15
DGND
14
SYNC
13
SCLK
12
SDIN
11
SDO
08964-005
Figure 5. Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Mnemonic Description
1 INV Connection to Inverting Input of External Amplifier. See the AD5791 Features section for further details.
2 V
3 V
Analog Output Voltage.
OUT
REFPS
Positive Reference Sense Voltage Input. A voltage range of 5 V to V
amplifier must be connected at this pin in conjunction with the V
− 2.5 V can be connected. A unity gain
DD
pin. See the AD5791 Features section for
REFPF
further details.
4 V
REFPF
Positive Reference Force Voltage Input. A voltage range of 5 V to V
amplifier must be connected at this pin in conjunction with the V
− 2.5 V can be connected. A unity gain
DD
pin. See the AD5791 Features section for
REFPS
further details.
5 VDD
Positive Analog Supply Connection. A voltage range of 7.5 V to 16.5 V can be connected, V
should be decoupled
DD
to AGND.
6
7
RESET
Active Low Clear Logic Input Pin. Asserting this pin sets the DAC register to a user defined value (see Table 13) and
CLR
Active Low Reset Logic Input Pin. Asserting this pin returns the AD5791 to its power-on status.
updates the DAC output. The output value depends on the DAC register coding that is being used, either binary
or twos complement.
8
Active Low Load DAC Logic Input Pin. This is used to update the DAC register and consequently, the analog
LDAC
output. When tied permanently low, the output is updated on the rising edge of SYNC
. If LDAC is held high during
the write cycle, the input register is updated, but the output update is held off until the falling edge of LDAC. The
LDAC pin should not be left unconnected.
9 VCC Digital Supply Connection. A voltage range of 2.7 V to 5.5 V can be connected. VCC should be decoupled to DGND.
10 IOVCC
Digital Interface Supply Pin. Digital threshold levels are referenced to the voltage applied to this pin. A voltage in
the range of 1.71 V to 5.5 V can be connected. IOV
should not be allowed to exceed V
CC
CC.
11 SDO Serial Data Output Pin. Data is clocked out on the rising edge of the serial clock input.
12 SDIN
Serial Data Input Pin. This device has a 24-bit shift register. Data is clocked into the register on the falling edge of
the serial clock input.
13 SCLK
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can
be transferred at clock rates of up to 35 MHz.
14
Active Low Digital Interface Synchronization Input Pin. This is the frame synchronization signal for the input data.
SYNC
When SYNC is low, it enables the input shift register, and data is then transferred in on the falling edges of the
following clocks. The input shift register is updated on the rising edge of SYNC
.
15 DGND Ground Reference Pin for Digital Circuitry.
16 V
REFNF
Negative Reference Force Voltage Input. A voltage range of V
amplifier must be connected at this pin, in conjunction with the V
+ 2.5 V to 0 V can be connected. A unity gain
SS
pin. See the AD5791 Features section for
REFNS
further details.
17 V
REFNS
Negative Reference Sense Voltage Input. A voltage range of V
amplifier must be connected at this pin, in conjunction with the V
+ 2.5 V to 0 V can be connected. A unity gain
SS
pin. See the AD5791 Features section for
REFNF
further details.
18 VSS
Negative Analog Supply Connection. A voltage range of −16.5 V to −2.5 V can be connected. V
should be
SS
decoupled to AGND.
19 AGND Ground Reference Pin for Analog Circuitry.
20 RFB Feedback Connection for External Amplifier. See the AD5791 Features section for further details.
Rev. C | Page 9 of 28
AD5791 Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
1.0
AD8676 REFERENCE BUFF ERS
0.8
AD8675 OUTPUT BUF FER
0.6
0.4
0.2
0
–0.2
INL ERROR (LSB)
–0.4
V
–0.6
–0.8
–1.0
= +10V
REFP
V
= –10V
REFN
V
= +15V
DD
V
= –15V
SS
0 200000 400000 600000 800000 1000000
DAC CODE
TA = +125°C
T
= +25°C
A
T
= –40°C
A
Figure 6. Integral Nonlinearity Error vs. DAC Code, ±10 V Span
1.5
TA = +125°C
T
= +25°C
A
T
= –40°C
A
1.0
0.5
0
INL ERROR (LSB)
–0.5
V
= +10V
REFP
–1.0
V
= 0V
REFN
V
= +15V
DD
V
= –15V
SS
–1.5
0 200000 400000 600000 800000 1000000
AD8676 REFERENCE BUFF ERS
AD8675 OUTPUT BUF FER
DAC CODE
Figure 7. Integral Nonlinearity Error vs. DAC Code, 10 V Span
2.5
2.0
1.5
1.0
0.5
0
–0.5
INL ERROR (LSB)
–1.0
–1.5
V
= +5V
REFP
V
= 0V
REFN
–2.0
V
= +15V
DD
V
= –15V
SS
–2.5
0 200000 400000 600000 800000 1000000
TA = +125°C
T
= +25°C
A
T
= –40°C
A
AD8676 REFE RENCE BUF FERS
AD8675 OUTPUT BUF FER
DAC CODE
Figure 8. Integral Nonlinearity Error vs. DAC Code, 5 V Span
08964-006
08964-007
08964-008
0.8
AD8676 REFERENCE BUFF ERS
AD8675 OUTPUT BUF FER
0.6
0.4
0.2
0
–0.2
INL ERROR (LSB)
–0.4
V
= +10V
REFP
V
= 0V
REFN
–0.6
V
= +15V
DD
V
= –15V
SS
–0.8
0 200000 400000 600000 800000 1000000
TA = –40°C
T
= +125°C
A
T
= +25°C
A
DAC CODE
08964-009
Figure 9. Integral Nonlinearity Error vs. DAC Code, ±10 V Span, X2 Gain Mode
1.0
AD8676 REFE RENCE BUF FERS
AD8675 OUTPUT BUF FER
0.8
0.6
0.4
0.2
0
–0.2
DNL ERROR (LSB)
–0.4
–0.6
–0.8
–1.0
TA = +125°C
T
= +25°C
A
T
= –40°C
A
0 200000 400000 600000 800000 1000000
DAC CODE
V
V
V
V
REFP
REFN
DD
SS
= +10V
= –10V
= +15V
= –15V
08964-010
Figure 10. Differential Nonlinearity Error vs. DAC Code, ±10 V Span
1.5
1.0
0.5
–0.5
DNL ERROR (LSB)
–1.0
–1.5
AD8676 REFE RENCE BUF FERS
AD8675 OUTPUT BUF FER
0
TA = +125°C
T
= +25°C
A
T
= –40°C
A
0 200000 400000 600000 800000 1000000
DAC CODE
V
V
V
V
REFP
REFN
DD
SS
= +10V
= 0V
= +15V
= –15V
08964-011
Figure 11. Differential Nonlinearity Error vs. DAC Code, 10 V Span
Rev. C | Page 10 of 28
Data Sheet AD5791
2.0
TA = +125°C
T
= +25°C
A
1.5
T
= –40°C
A
1.0
0.5
0
–0.5
DNL ERROR (LSB)
–1.0
–1.5
AD8676 REFERENCE BUFF ERS
AD8675 OUTPUT BUF FER
–2.0
0 200000 400000 600000 800000 1000000
V
REFP
V
REFN
V
= +15V
DD
V
= –15V
SS
DAC CODE
= +5V
= 0V
Figure 12. Differential Nonlinearity Error vs. DAC Code, 5 V Span
1.0
AD8676 REFERENCE BUFF ERS
AD8675 OUTPUT BUFF ER
0.8
V
= +10V
REFP
V
= 0V
REFN
0.6
V
= +15V
DD
V
= –15V
SS
0.4
0.2
0
–0.2
DNL ERROR (LSB)
–0.4
–0.6
–0.8
–1.0
0 200000 400000 600000 800000 1000000
DAC CODE
TA = +25°C
T
= –40°C
A
T
= +125°C
A
Figure 13. Differential Nonlinearity Error vs. DAC Code, ±10 V Span,
X2 Gain Mode
2.0
1.5
1.0
0.5
0
INL ERROR (L SB)
–0.5
–1.0
–1.5
–55 –35 –15 5 25 45 65 85 105 125
±10V SPAN MAX INL
+5V SPAN MAX INL
+10V SPAN MIN INL
AD8676 REFERENCE BUFF ERS
AD8675 OUTPUT BUF FER
V
= +15V
DD
V
= –15V
SS
TEMPERATURE (° C)
+10V SPAN MAX INL
±10V SPAN MIN INL
+5V SPAN MIN INL
Figure 14. Integral Nonlinearity Error vs. Temperature
1.0
±10V SPAN MAX DNL
+5V SPAN MAX DNL
+10V SPAN MIN DNL
0.5
0
–0.5
DNL ERROR (LSB)
AD8676 REFERENCE BUFF ERS
–1.0
AD8675 OUTPUT BUF FER
V
= +15V
DD
V
= –15V
SS
–1.5
–55 –35 –15 5 25 45 65 85 105 125
08964-012
+10V SPAN MAX DNL
±10V SPAN MIN DNL
+5V SPAN MIN DNL
TEMPERATURE (° C)
08964-015
Figure 15. Differential Nonlinearity Error vs. Temperature
0.6
V
DD
INL MAX
INL MIN
/|VSS| (V)
08964-016
0.5
0.4
0.3
TA = 25°C
V
0.2
0.1
INL ERROR (L SB)
–0.1
–0.2
–0.3
08964-013
= +10V
REFP
V
= –10V
REFN
AD8676 REFERENCE BUFFERS
AD8675 OUTPUT BUF FER
0
12.5 13.0 13. 5 14.0 14.5 15.0 15.5 16.0 16.5
Figure 16. Integral Nonlinearity Error vs. Supply Voltage, ±10 V Span
1.5
V
DD
V
SS
INL MAX
INL MIN
(V)
(V)
08964-017
1.0
TA = 25°C
0.5
V
= +5V
REFP
V
= 0V
REFN
AD8676 REFERENCE BUFF ERS
0
AD8675 OUTPUT BUF FER
INL ERRO R (LS B)
–0.5
–1.0
–1.5
7.5 8.5 9.5 10. 5 11. 5 12. 5 13.5 14.5 15.5 16.5
08964-014
–2.5 –3.9 –5.3 –6.7 –9. 1 –10.5 –12.9 –14.2 –15.5 –16.5
Figure 17. Integral Nonlinearity Error vs. Supply Voltage, 5 V Span
Rev. C | Page 11 of 28
AD5791 Data Sheet
0.4
0.3
0.2
0.1
TA = 25°C
V
= +10V
REFP
V
= –10V
0
REFN
AD8676 REFERENCE BUFF ERS
AD8675 OUTPUT BUF FER
–0.1
DNL ERROR (LSB)
–0.2
–0.3
–0.4
12.5 13.0 13. 5 14.0 14.5 15.0 15.5 16.0 16.5
DNL MAX
DNL MIN
V
/|VSS| (V)
DD
Figure 18. Differential Nonlinearity Error vs. Supply Voltage, ±10 V Span
0.4
0.2
0
TA = 25°C
V
–0.2
–0.4
DNL ERROR (LSB)
–0.6
–0.8
= +5V
REFP
V
= 0V
REFN
AD8676 REFERENCE BUF FERS
AD8675 OUTPUT BUFFER
DNL MAX
DNL MIN
08964-018
0.6
TA = 25°C
V
= +5V
REFP
V
0.5
0.4
0.3
0.2
ZERO-SCALE ERROR (LSB)
0.1
0
–2.5 –3.9 –5.3 –6.7 –9. 1 –10.5 –12.9 –14.2 –15. 5 –16.5
= 0V
REFN
AD8676 REFERENCE BUFF ERS
AD8675 OUTPUT BUF FER
7.5 8. 5 9.5 10. 5 11. 5 12. 5 13.5 14.5 15.5 16. 5
(V)
V
DD
V
(V)
SS
Figure 21. Zero-Scale Error vs. Supply Voltage, 5 V Span
0.20
TA = 25°C
V
= +10V
REFP
V
= –10V
REFN
AD8676 REFERENCE BUFF ERS
AD8675 OUTPUT BUF FER
0
MIDSCALE ERROR (LSB)
0.15
0.10
0.05
–0.05
–0.10
08964-021
–1.0
7.5 8. 5 9.5 10. 5 11. 5 12. 5 13.5 14.5 15.5 16. 5
–2.5 –3.9 –5.3 –6.7 –9. 1 –10.5 –12.9 –14.2 –15.5 –16.5
V
(V)
DD
V
(V)
SS
Figure 19. Differential Nonlinearity Error vs. Supply Voltage, 5 V Span
0.6
0.5
0.4
0.3
TA = 25°C
V
= +10V
REFP
0.2
V
= –10V
REFN
AD8676 REFERENCE BUFF ERS
ZERO-SCALE ERROR (LSB)
AD8675 OUTPUT BUF FER
0.1
0
12.5 13.0 13. 5 14.0 14.5 15.0 15.5 16.0 16.5
V
DD
/|VSS| (V)
Figure 20. Zero-Scale Error vs. Supply Voltage, ±10 V Span
–0.15
12.5 13.0 13. 5 14.0 14.5 15.0 15.5 16.0 16.5
08964-019
V
DD
/|VSS| (V)
08964-022
Figure 22. Midscale Error vs. Supply Voltage, ±10 V Span
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
MIDSCALE ERROR (LSB)
–0.5
–0.6
–0.7
7.5 8. 5 9.5 10. 5 11. 5 12.5 13.5 14.5 15.5 16. 5
08964-020
–2.5 –3.9 –5.3 –6.7 –9. 1 –10.5 –12.9 –14. 2 –15.5 –16.5
TA = 25°C
V
= +5V
REFP
V
= 0V
REFN
AD8676 REFERENCE BUFF ERS
AD8675 OUTPUT BUF FER
(V)
V
DD
V
(V)
SS
08964-023
Figure 23. Midscale Error vs. Supply Voltage, 5 V Span
Rev. C | Page 12 of 28
Data Sheet AD5791
–
–
0.015
TA = 25°C
V
= +10V
REFP
–0.035
V
= –10V
REFN
AD8676 REFERENCE BUFF ERS
–0.055
AD8675 OUTPUT BUF FER
–0.075
–0.095
–0.115
–0.135
FULL-SCAL E ERROR (LSB)
–0.155
–0.175
–0.195
12.5 13.0 13. 5 14.0 14.5 15.0 15.5 16.0 16.5
V
DD
/|VSS| (V)
Figure 24. Full-Scale Error vs. Supply Voltage, ±10 V Span
0.25
08964-024
0.10
0.05
0
–0.05
–0.10
–0.15
–0.20
–0.25
GAIN ERROR (ppm FSR)
–0.30
–0.35
–0.40
7.5 8.5 9.5 10. 5 11. 5 12. 5 13.5 14.5 15.5 16. 5
–2.5 –3.9 –5.3 –6.7 –9. 1 –10.5 –12.9 –14.2 –15.5 –16.5
TA = 25°C
V
= +5V
REFP
V
= 0V
REFN
AD8676 REFERENCE BUFF ERS
AD8675 OUTPUT BUF FER
V
(V)
DD
V
(V)
SS
Figure 27. Gain Error vs. Supply Voltage, 5 V Span
0.6
08964-027
0.20
0.15
0.10
0.05
FULL-SCALE ERROR (LSB)
0
–0.05
7.5 8.5 9.5 10. 5 11. 5 12. 5 13.5 14.5 15.5 16.5
–2.5 –3.9 –5.3 –6.7 –9. 1 –10.5 –12.9 –14.2 –15. 5 –16.5
TA = 25°C
V
= +5V
REFP
V
= 0V
REFN
AD8676 REFERENCE BUFF ERS
AD8675 OUTPUT BUF FER
(V)
V
DD
V
(V)
SS
Figure 25. Full-Scale Error vs. Supply Voltage, 5 V Span
0.30
TA = 25°C
V
= +10V
REFP
–0.35
V
= –10V
REFN
AD8676 REFERENCE BUFF ERS
AD8675 OUTPUT BUF FER
–0.40
–0.45
–0.50
–0.55
GAIN ERROR (pp m FSR)
–0.60
–0.65
12.5 13.0 13. 5 14.0 14.5 15.0 15. 5 16.0 16.5
V
DD
/|VSS| (V)
Figure 26. Gain Error vs. Supply Voltage, ±10 V Span
0.4
0.2
TA = 25°C
V
= +15V
DD
V
= –15V
SS
0
AD8676 REFERENCE BUFF ERS
AD8675 OUTPUT BUF FER
INL ERROR (LSB)
–0.2
–0.4
–0.6
5.0 5.5 6.0 6.5 7.0 7. 5 8.0 8.5 9.0 9.5 10.0
08964-025
V
REFP
INL MAX
INL MIN
/|V
REFN
| (V)
08964-028
Figure 28. Integral Nonlinearity Error vs. Reference Voltage
0.4
V
REFP
DNL MAX
DNL MIN
/|V
REFN
| (V)
08964-029
0.3
0.2
0.1
TA = 25°C
0
V
= +15V
DD
V
–0.1
–0.2
DNL ERROR (LSB)
–0.3
–0.4
–0.5
–0.6
08964-026
5.0 5.5 6.0 6.5 7.0 7. 5 8.0 8.5 9.0 9.5 10.0
= –15V
SS
AD8676 REFERENCE BUFF ERS
AD8675 OUTPUT BUF FER
Figure 29. Differential Nonlinearity Error vs. Reference Voltage
Rev. C | Page 13 of 28
AD5791 Data Sheet
–
0.60
0.55
0.50
0.30
TA = 25°C
V
= +15V
DD
V
–0.35
–0.40
= –15V
SS
AD8676 REFERENCE BUFF ERS
AD8675 OUTPUT BUF FER
0.45
TA = 25°C
V
= +15V
DD
0.40
V
= –15V
SS
ZERO-SCALE ERROR (LSB)
AD8676 REFERENCE BUFF ERS
AD8675 OUTPUT BUF FER
0.35
0.30
5.0 5.5 6.0 6.5 7.0 7. 5 8.0 8.5 9.0 9.5 10.0
V
REFP
/|V
| (V)
REFN
Figure 30. Zero-Scale Error vs. Reference Voltage
0.15
0.10
0.05
0
–0.05
–0.10
MIDSCALE ERROR (LSB)
–0.15
–0.20
5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0
TA = 25°C
V
= +15V
DD
V
= –15V
SS
AD8676 REFERENCE BUFF ERS
AD8675 OUTPUT BUFFER
V
/|V
REFN
| (V)
REFP
Figure 31. Midscale Error vs. Reference Voltage
0.15
0.10
0.05
0
–0.05
TA = 25°C
V
FULL-SCAL E ERROR (LSB)
–0.10
–0.15
–0.20
= +15V
DD
V
= –15V
SS
AD8676 REFERENCE BUFF ERS
AD8675 OUTPUT BUFF ER
5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0
V
REFP
/|V
| (V)
REFN
Figure 32. Full-Scale Error vs. Reference Voltage
–0.45
–0.50
GAIN ERROR (ppm FSR)
–0.55
–0.60
5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0
08964-030
V
REFP
/|V
| (V)
REFN
08964-033
Figure 33. Gain Error vs. Reference Voltage
2.0
AD8676 REFERENCE BUFF ERS
1.5
AD8675 OUTPUT BUF FER
V
= +15V
DD
V
= –15V
1.0
SS
0.5
0
–0.5
–1.0
–1.5
FULL-SCAL E ERROR (LSBs)
–2.0
–2.5
–3.0
–55 –35 –15 5 25 45 65 85 105 125
08964-031
TEMPERATURE (° C)
±10V SPAN
+10V SPAN
+5V SPAN
08964-034
Figure 34. Full-Scale Error vs. Temperature
2.0
1.8
1.6
1.4
1.2
1
0.8
0.6
MIDSCALE ERROR (LSBs)
AD8676 REFERENCE BUFF ERS
0.4
AD8675 OUTPUT BUF FER
V
= +15V
DD
0.2
V
= –15V
SS
0
–55 –35 –15 5 25 45 65 85 105 125
08964-032
TEMPERATURE (° C)
±10V SPAN
+10V SPAN
+5V SPAN
08964-035
Figure 35. Midscale Error vs. Temperature
Rev. C | Page 14 of 28
Data Sheet AD5791
5
4
3
2
1
0
–1
–2
ZERO-SCAL E ERROR (LSBs)
AD8676 REFERENCE BUFF ERS
–3
AD8675 OUTPUT BUF FER
V
= +15V
DD
–4
V
= –15V
SS
–5
–55 –35 –15 5 25 45 65 85 105 125
TEMPERATURE (°C)
Figure 36. Zero-Scale Error vs. Temperature
4
AD8676 REFERENCE BUFF ERS
AD8675 OUTPUT BUF FER
3
= +15V
V
DD
= –15V
V
SS
2
1
0
–1
–2
GAIN ERROR (ppm FSR)
–3
±10V SPAN
+10V SPAN
+5V SPAN
±10V SPAN
+10V SPAN
+5V SPAN
5
TA = 25°C
4
3
2
1
(mA)
0
SS
, I
DD
–1
I
–2
–3
–4
–5
–20 –15 –10 –5 0 5 10 15 20
08964-036
I
SS
(V)
V
DD/VSS
I
DD
08964-039
Figure 39. Power Supply Currents vs. Power Supply Voltages
VDD = +15V
V
= –15V
SS
V
= +10V
3
REFP
V
= –10V
REFN
AD8676 REFERENCE BUFF ERS
OUTPUT UNBUFF ERED
LOAD = 10MΩ|| 20pF
–4
–5
–55 –35 –15 5 25 45 65 85 105 125
TEMPERATURE ( °C)
Figure 37. Gain Error vs. Temperature
900
= 25°C
T
A
800
700
600
500
(µA)
CC
400
IOI
300
200
100
0
01
2345
LOGIC INPUT VOLTAGE (V)
Figure 38. IOI
IOVCC = 5V, LOGIC VOLTAGE
INCREASING
IOV
= 5V, LOGIC VOLTAGE
CC
DECREASING
IOV
= 3V, LOGIC VOLTAGE
CC
INCREASING
IOV
= 3V, LOGIC VOLTAGE
CC
DECREASING
vs. Logic Input Voltage
CC
08964-037
6
08964-038
4
CH3 5V CH4 5V 200ns
Figure 40. Rising Full-Scale Voltage Step
VDD = +15V
V
= –15V
SS
V
REFP
V
REFN
AD8676 REFERENCE BUFF ERS
OUTPUT UNBUFFERED
LOAD = 10MΩ|| 20pF
3
4
CH3 5V CH4 5V 200ns
Figure 41. Falling Full-Scale Voltage Step
= +10V
= –10V
08964-040
08964-041
Rev. C | Page 15 of 28
AD5791 Data Sheet
10.8
10.6
10.4
10.2
(mV)
OUT
10.0
V
9.8
9.6
±10V V
REF
OUTPUT GAIN OF 1
BIAS COMPENSATIO N MODE
20pF COMPE NSATION CAPACITOR
RC LOW-PASS FILTER
3.0
5V V
REF
OUTPUT GAIN OF 1
2.6
BIAS COMPENSATIO N MODE
20pF COMPE NSATION CAPACITOR
RC LOW-PASS FILTER
2.2
POSITIVE CODE
CHANGE
OUTPUT G LITCH ( nV–sec)
1.8
1.4
1.0
0.6
0.2
NEGATIVE CO DE
CHANGE
9.4
01 5432
TIME (µs)
Figure 42. 500 Code Step Settling Time
10
5V V
REF
OUTPUT GAIN OF 1
9
BIAS COMPENSATIO N MODE
20pF COMPE NSATION CAPACITOR
8
RC LOW-PASS FILTER
7
6
OUTPUT G LITCH ( nV–sec)
5
4
3
2
1
0
16384
65536
114688
POSITIVE CODE
CHANGE
163840
212992
262144
311296
360448
409600
458752
CODE
507904
557056
606208
Figure 43. 6 MSB Segment Glitch Energy for ±10 V V
4.0
10V V
REF
OUTPUT GAIN OF 1
3.5
BIAS COMPENSATIO N MODE
20pF COMPE NSATION CAPACITOR
RC LOW-PASS FILTER
OUTPUT G LITCH ( nV–sec)
3.0
2.5
2.0
1.5
1.0
0.5
NEGATIVE CODE
CHANGE
NEGATIVE CO DE
CHANGE
655360
704512
753664
802816
POSITIVE CODE
CHANGE
851968
901120
REF
950272
999424
–0.2
088964-063
(mV)
OUT
V
08964-059
65536
16384
114688
163840
212992
262144
311296
360448
409600
458752
507904
557056
606208
655360
CODE
Figure 45. 6 MSB Segment Glitch Energy for +5 V V
40
30
20
10
0
–10
–20
–1.0 –0. 5 2.01.51.00.50
±10V V
REF
OUTPUT GAIN OF 1
BIAS COMPENSATION MO DE
20pF COMPE NSATION CAPACITOR
RC LOW-PASS FILTER
CX = 143pF + 0p F
C
X
C
X
C
X
TIME (µs)
704512
753664
802816
851968
901120
950272
REF
= 143pF + 220pF
= 143pF + 470pF
= 143pF + 1, 000pF
999424
08964-061
088964-062
Figure 46. Midscale Peak-to-Peak Glitch for ±10 V
800
OUTPUT VOLTAGE (nV)
600
400
200
–200
–400
TA = 25°C
V
V
V
V
0
DD
SS
REFP
REFN
= +15V
= –15V
= +10V
= –10V
MIDSCALE CODE LOADED
OUTPUT UNBUFFERED
AD8676 REFERENCE BUFF ERS
0
65536
16384
114688
163840
212992
262144
311296
360448
409600
458752
507904
557056
606208
655360
704512
753664
802816
CODE
Figure 44. 6 MSB Segment Glitch Energy for +10 V V
851968
901120
REF
950272
999424
08964-060
Rev. C | Page 16 of 28
–600
012345678 910
TIME (Seconds)
Figure 47. Voltage Output Noise, 0.1 Hz to 10 Hz Bandwidth
08964-044
Data Sheet AD5791
100
10
NSD (nV/ Hz)
1
0.1 100k
1 10 100 1k 10k
FREQUENCY (Hz)
VDD = +15V
V
= –15V
SS
V
REFP
V
REFN
CODE = MI DSCALE
Figure 48. Noise Spectral Density vs. Frequency
350
300
250
200
150
100
OUTPUT VOL TAGE (mV)
50
TA = 25°C
V
= +15V
DD
V
= –15V
SS
V
= +10V
REFP
V
= –10V
REFN
AD8675 OUTPUT BUF FER
= +10V
= –10V
08964-064
0
–50
01–1 2 3 4 5 6
TIME (µs)
Figure 49. Glitch Impulse on Removal of Output Clamp
08964-049
Rev. C | Page 17 of 28
AD5791 Data Sheet
TERMINOLOGY
Relative Accuracy
Relative accuracy, or integral nonlinearity (INL), is a measure of
the maximum deviation, in LSB, from a straight line passing
through the endpoints of the DAC transfer function. A typical
INL error vs. code plot is shown in Figure 6.
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ±1 LSB maximum
ensures monotonicity. This DAC is guaranteed monotonic. A
typical DNL error vs. code plot is shown in Figure 10.
Linearity Error Long Term Stability
Linearity error long term stability is a measure of the stability of
the linearity of the DAC over a long period of time. It is specified
in LSB for a time period of 500 hours and 1000 hours at an
elevated ambient temperature.
Zero-Scale Error
Zero-scale error is a measure of the output error when zero-scale
code (0x00000) is loaded to the DAC register. Ideally, the output
voltage should be V
. Zero-scale error is expressed in LSBs.
REFNS
Zero-Scale Error Temperature Coefficient
Zero-scale error temperature coefficient is a measure of the
change in zero-scale error with a change in temperature. It is
expressed in ppm FSR/°C.
Full-Scale Error
Full-scale error is a measure of the output error when fullscale code (0x3FFFF) is loaded to the DAC register. Ideally,
the output voltage should be V
− 1 LSB. Full-scale error is
REFPS
expressed in LSBs.
Full-Scale Error Temperature Coefficient
Full-scale error temperature coefficient is a measure of the
change in full-scale error with a change in temperature. It is
expressed in ppm FSR/°C.
Gain Error
Gain error is a measure of the span error of the DAC. It is the
deviation in slope of the DAC transfer characteristic from ideal,
expressed in ppm of the full-scale range.
Gain Error Temperature Coefficient
Gain error temperature coefficient is a measure of the change in
gain error with a change in temperature. It is expressed in ppm
FSR/°C.
Midscale Error
Midscale error is a measure of the output error when midscale
code (0x20000) is loaded to the DAC register. Ideally, the output
voltage should be (V
REFPS
− V
REFNS
)/2 +V
. Midscale error is
REFNS
expressed in LSBs.
Rev. C | Page 18 of 28
Midscale Error Temperature Coefficient
Midscale error temperature coefficient is a measure of the
change in midscale error with a change in temperature. It is
expressed in ppm FSR/°C.
Output Slew Rate
Slew rate is a measure of the limitation in the rate of change of
the output voltage. The slew rate of the AD5791 output voltage
is determined by the capacitive load presented to the V
pin. The
OUT
capacitive load in conjunction with the 3.4 kΩ output impedance
of the AD5791 set the slew rate. Slew rate is measured from 10%
to 90% of the output voltage change and is expressed in V/μs.
Output Voltage Settling Time
Output voltage settling time is the amount of time it takes for
the output voltage to settle to a specified level for a specified
change in voltage. For fast settling applications, a high speed
buffer amplifier is required to buffer the load from the 3.4 kΩ
output impedance of the AD5791, in which case it is the
amplifier that determines the settling time.
Digital-to-Analog Glitch Impulse
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is specified as the area of the glitch in nV-sec and is
measured when the digital input code is changed by 1 LSB at
the major carry transition (see Figure 43).
Output Enabled Glitch Impulse
Output enabled glitch impulse is the impulse injected into the
analog output when the clamp to ground on the DAC output is
removed. It is specified as the area of the glitch in nV-sec (see
Figure 49).
Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into
the analog output of the DAC from the digital inputs of the
DAC but is measured when the DAC output is not updated. It is
specified in nV-sec and measured with a full-scale code change
on the data bus, that is, from all 0s to all 1s, and vice versa.
Spurious Free Dynamic Range (SFDR)
Spurious free dynamic range is the usable dynamic range of a
DAC before spurious noise interferes or distorts the fundamental
signal. It is measured by the difference in amplitude between
the fundamental and the largest harmonically or nonharmonically
related spur from dc to full Nyquist bandwidth (half the DAC
sampling rate, or f
/2). SFDR is measured when the signal is a
S
digitally generated sine wave.
Total Harmonic Distortion (THD)
Total harmonic distortion is the ratio of the rms sum of the
harmonics of the DAC output to the fundamental value Only
the second to fifth harmonics are included.
Data Sheet AD5791
DC Power Supply Rejection Ratio
DC power supply rejection ratio is a measure of the rejection of
the output voltage to dc changes in the power supplies applied
to the DAC. It is measured for a given dc change in power
supply voltage and is expressed in μV/V.
AC Power Supply Rejection Ratio (AC PSRR)
AC power supply rejection ratio is a measure of the rejection of
the output voltage to ac changes in the power supplies applied
to the DAC. It is measured for a given amplitude and frequency
change in power supply voltage and is expressed in decibels.
Rev. C | Page 19 of 28
AD5791 Data Sheet
THEORY OF OPERATION
The AD5791 is a high accuracy, fast settling, single, 20-bit,
serial input, voltage output DAC. It operates from a V
voltage of 7.5 V to 16.5 V and a V
supply of −16.5 V to −2.5 V.
SS
Data is written to the AD5791 in a 24-bit word format via a 3-wire
serial interface. The AD5791 incorporates a power-on reset
circuit that ensures the DAC output powers up to 0 V with the
V
pin clamped to AGND through a ~6 kΩ internal resistor.
OUT
DAC ARCHITECTURE
The architecture of the AD5791 consists of two matched DAC
sections. A simplified circuit diagram is shown in Figure 50.
The six MSBs of the 20-bit data-word are decoded to drive 63
switches, E0 to E62. Each of these switches connects one of 63
matched resistors to either the V
remaining 14 bits of the data-word drive the S0 to S13 switched
of a 14-bit voltage mode R-2R ladder network. To ensure
performance to specification, the reference inputs must be force
sensed with external amplifiers.
REFP
or V
voltage. The
REFN
supply
DD
R
V
V
V
V
REFPF
REFPS
REFNF
REFNS
RR
.....................
2R
2R
S0
14-BIT R-2R L ADDER
2R
.....................
S1
Figure 50. DAC Ladder Structure
2R
S11
SIX MSBs DECODED INTO
63 EQUAL SEGMENTS
2R
E622RE61
..........
..........
V
OUT
2R
E0
SERIAL INTERFACE
The AD5791 has a 3-wire serial interface (
SDIN) that is compatible with SPI, QSPI, and MICROWIRE
interface standards, as well as most DSPs (see for a
timing diagram).
Input Shift Register
The input shift register is 24 bits wide. Data is loaded into the
device MSB first as a 24-bit word under the control of a serial
clock input, SCLK, which can operate at up to 50 MHz. The
input register consists of a R/
twenty register bits as shown in . The timing diagram for
this operation is shown in .
W
bit, three address bits, and
Table 7
Figure 2
SYNC
Figure 2
, SCLK, and
08964-050
Table 7. Input Shift Register Format
MSB LSB
DB23 DB22 DB21 DB20 DB19 DB0
R/W
Register address Register data
Table 8. Decoding the Input Shift Register
R/W Register Address Description
X1 0 0 0 No operation (NOP; used in readback operations
0 0 0 1 Write to the DAC register
0 0 1 0
0 0 1 1
0 1 0 0
1 0 0 1
1 0 1 0
Write to the control register
Write to the clearcode register
Write to the software control register
Read from the DAC register
Read from the control register
1 0 1 1 Read from the clearcode register
1
X is don’t care.
Rev. C | Page 20 of 28
Data Sheet AD5791
Standalone Operation
The serial interface works with both a continuous and noncontinuous serial clock. A continuous SCLK source can be used
SYNC
only if
is held low for the correct number of clock cycles.
In gated clock mode, a burst clock containing the exact number
of clock cycles must be used, and
SYNC
must be taken high
after the final clock to latch the data. The first falling edge of
SYNC
starts the write cycle. Exactly 24 falling clock edges must
be applied to SCLK before
SYNC
is brought high before the 24th falling SCLK edge, the
SYNC
is brought high again. If
data written is invalid. If more than 24 falling SCLK edges are
SYNC
applied before
is brought high, the input data is also
invalid. The input shift register is updated on the rising edge of
SYNC
. For another serial transfer to take place,
SYNC
must be
brought low again. After the end of the serial data transfer, data
is automatically transferred from the input shift register to the
addressed register. Once the write cycle is complete, the output
can be updated by taking
LDAC
low while
SYNC
is high.
Daisy-Chain Operation
For systems that contain several devices, the SDO pin can be
used to daisy chain several devices together. Daisy-chain mode
can be useful in system diagnostics and in reducing the number
of serial interface lines. The first falling edge of
SYNC
starts the
write cycle. SCLK is continuously applied to the input shift
SYNC
register when
is low. If more than 24 clock pulses are
applied, the data ripples out of the shift register and appears on
the SDO line. This data is clocked out on the rising edge of
SCLK and is valid on the falling edge. By connecting the SDO
of the first device to the SDIN input of the next device in the
chain, a multidevice interface is constructed. Each device in the
system requires 24 clock pulses. Therefore, the total number of
clock cycles must equal 24 × N, where N is the total number of
AD5791
devices is complete,
devices in the chain. When the serial transfer to all
SYNC
is taken high. This latches the input
data in each device in the daisy chain and prevents any further
data from being clocked into the input shift register. The serial
clock can be a continuous or a gated clock.
A continuous SCLK source can be used only if
SYNC
is held
low for the correct number of clock cycles. In gated clock mode,
a burst clock containing the exact number of clock cycles must
be used, and
SYNC
must be taken high after the final clock to
latch the data.
In any one daisy-chain sequence, writes to the DAC register
should not be mixed with writes to any of the other registers.
All writes to the daisy-chained parts should be either writes to
the DAC registers or writes to the control, clearcode, or
software control registers.
Rev. C | Page 21 of 28
CONTROLL ER
DATA OUT
SERIAL CLOCK
CONTROL O UT
DATA IN
*ADDITIONAL PINS OMITTED FO R CLARITY.
Figure 51. Daisy-Chain Block Diagram
Readback
The contents of all the on-chip registers can be read back via the
SDO pin. Tabl e 8 outlines how the registers are decoded. After a
register has been addressed for a read, the next 24 clock cycles
clock the data out on the SDO pin. The clocks must be applied
while
SYNC
is low. When
SYNC
is returned high, the SDO pin
is placed in tristate. For a read of a single register, the NOP
function can be used to clock out the data. Alternatively, if more
than one register is to be read, the data of the first register to be
addressed can be clocked out at the same time the second register
to be read is being addressed. The SDO pin must be enabled to
complete a readback operation. The SDO pin is enabled by
default.
HARDWARE CONTROL PINS
Load DAC Function (
After data has been transferred into the input register of the
DAC, there are two ways to update the DAC register and DAC
output. Depending on the status of both
of two update modes is selected: synchronous DAC updating or
asynchronous DAC updating
Synchronous DAC Update
In this mode,
LDAC
the input shift register. The DAC output is updated on the rising
SYNC
edge of
.
LDAC
)
is held low while data is being clocked into
AD5781*
SDIN
SCLK
SYNC
AD5781*
SCLK
SYNC
AD5781*
SCLK
SYNC
SYNC
SDO
SDIN
SDO
SDIN
SDO
and
08964-058
LDAC
, one
AD5791 Data Sheet
Asynchronous DAC Update
In this mode,
LDAC
is held high while data is being clocked
into the input shift register. The DAC output is asynchronously
updated by taking
LDAC
low after
The update now occurs on the falling edge of
Reset Function (
RESET
)
SYNC
has been taken high.
LDAC
.
The AD5791 can be reset to its power-on state by two means:
RESET
either by asserting the
RESET control function (see ). If the Table 14
used, it should be hardwired to IOV
pin or by utilizing the software
RESET
pin is not
.
CC
Table 9. Hardware Control Pins Truth Table
LDAC
X1 XX1 0 The AD5791 is in reset mode. The device cannot be programmed.
X1 XX1
0 0 1
0 1 1
1 0 1
1
0
1
0
1
X is don’t care.
CLR
1 1
0 1
1 1
0 1
RESET
Functio n
1 The DAC register is loaded with the clearcode register value and the output is set accordingly.
1
1 The output remains at the clear code value
1 The output is set according to the DAC register value.
The AD5791 is returned to its power-on state. All registers are set to their default values.
The DAC register is loaded with the clearcode register value and the output is set accordingly.
The output is set according to the DAC register value.
The DAC register is loaded with the clearcode register value and the output is set accordingly.
The output is set according to the DAC register value.
The output remains at the clear code value.
The output remains set according to the DAC register value.
The output remains at the clear code value.
The DAC register is loaded with the clearcode register value and the output is set accordingly.
ON-CHIP REGISTERS
DAC Register
Table 10 outlines how data is written to and read from the DAC register.
Asynchronous Clear Function (CLR)
CLR
The
pin is an active low clear that allows the output to
be cleared to a user defined value. The 20-bit clear code value
is programmed to the clearcode register (see ). It is
necessary to maintain
CLR
low for a minimum amount of time
to complete the operation (see ).When the Figure 2
is returned high the output remains at the clear value (if
Table 13
CLR
signal
LDAC
is high) until a new value is loaded to the DAC register. The
output cannot be updated with a new value while the
CLR
pin is
low. A clear operation can also be performed by setting the CLR
bit in the software control register (see ). Table 1 4
Table 10. DAC Register
MSB LSB
DB23 DB22 DB21 DB20 DB19 DB0
R/W
R/W
0 0 1 20-bits of data
Register address DAC register data
The following equation describes the ideal transfer function of the DAC:
()
V +
=
OUT
20
DVV
×−
REFNREFP
−
12
V
REFN
where:
V
is the negative voltage applied at the V
REFN
V
is the positive voltage applied at the V
REFP
input pins.
REFN
input pins.
REFP
D is the 20-bit code programmed to the DAC.
Rev. C | Page 22 of 28
Data Sheet AD5791
Control Register
The control register controls the mode of operation of the AD5791.
Table 11. Control Register
MSB LSB
DB23 DB22 DB21 DB20 DB19…DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Register address Control register data
R/W
0 1 0 Reserved Reserved LIN COMP SDODIS BIN/2sC DACTRI OPGND RBUF Reserved
R/W
Table 12. Control Register Functions
Function Description
Reserved These bits are reserved and should be programmed to zero.
RBUF Output amplifier configuration control.
0: internal amplifier, A1, is powered up and Resistor R
an external amplifier to be connected in a gain of two configurations. See the AD5791 Features section for further details.
1: (default) internal amplifier, A1, is powered down and Resistor R
that the resistance between the R
and INV pins is 3.4 kΩ, equal to the resistance of the DAC. This allows the RFB and INV pins to
FB
be used for input bias current compensation for an external unity gain amplifier. See the AD5791 Features section for
further details.
OPGND Output ground clamp control.
0: DAC output clamp to ground is removed and the DAC is placed in normal mode.
1: (default) DAC output is clamped to ground through a ~6 kΩ resistance, and the DAC is placed in tristate mode.
Resetting the part puts the DAC in OPGND mode, where the output ground clamp is enabled and the DAC is tristated.
Setting the OPGND bit to 1 in the control register overrules any write to the DACTRI bit.
DACTRI DAC tristate control.
0: DAC is in normal operating mode.
1: (default) DAC is in tristate mode.
BIN/2sC DAC register coding select.
0: (default) DAC register uses twos complement coding.
1: DAC register uses offset binary coding.
SDODIS SDO pin enable/disable control.
0: (default) SDO pin is enabled.
1: SDO pin is disabled (tristate).
LIN COMP Linearity error compensation for varying reference input spans. See the AD5791 Features section for further details.
0 0 0 0 (Default) reference input span up to 10 V.
1 0 0 1 Reference input span between 10 V and 12 V.
1 0 1 0 Reference input span between 12 V and 16 V.
1 0 1 1 Reference input span between16 V and 19 V.
1 1 0 0 Reference input span between 19 V and 20 V.
R/W
Read/write select bit.
0: AD5791 is addressed for a write operation.
1: AD5791 is addressed for a read operation.
Clearcode Register
The clearcode register sets the value to which the DAC output is set when the
on the DAC coding that is being used, either binary or twos complement. The default register value is 0.
and R1 are connected in series as shown in Figure 54. This allows
FB
and R1 are connected in parallel as shown in Figure 53 so
FB
pin or CLR bit is asserted. The output value depends
CLR
Table 13. Clearcode Register
MSB LSB
DB23 DB22 DB21 DB20 DB19 DB0
R/W
R/W
0 1 1 20-bits of data
Register address Clearcode register data
Rev. C | Page 23 of 28
AD5791 Data Sheet
Software Control Register
This is a write only register in which writing a 1 to a particular bit has the same effect as pulsing the corresponding pin low.
Table 14. Software Control Register
MSB LSB
DB23 DB22 DB21 DB20 DB19 DB3 DB2 DB1 DB0
R/W
0 1 0 0 Reserved RESET CLR1 LDAC2
1
The CLR function has no effect if the
2
The LDAC function has no effect if the
Table 15. Software Control Register Functions
Function Description
LDAC Setting this bit to a 1 updates the DAC register and consequently the DAC output.
CLR
Setting this bit to a 1 sets the DAC register to a user defined value (see Table 13) and updates the DAC output. The output
value depends on the DAC register coding that is being used, either binary or twos complement.
RESET Setting this bit to a 1 returns the AD5791 to its power-on state.
Register address Software control register data
LDAC
pin is low.
CLR
pin is low.
Rev. C | Page 24 of 28
Data Sheet AD5791
V
V
AD5791 FEATURES
POWER-ON TO 0 V
The AD5791 contains a power-on reset circuit that, as well as
resetting all registers to their default values, controls the output
voltage during power-up. Upon power-on the DAC is placed in
tristate (its reference inputs are disconnected) and its output is
clamped to ground through a ~6 kΩ resistor. The DAC remains
in this state until programmed otherwise via the control
register. This is a useful feature in applications where it is
important to know the state of the DAC output while it is in the
process of powering up.
CONFIGURING THE AD5791
After power-on the AD5791 must be configured to put it into
normal operating mode before programming the output. To do
this, the control register must be programmed. The DAC is
removed from tristate by clearing the DACTRI bit, and the
output clamp is removed by clearing the OPGND bit. At this
point, the output goes to V
, unless an alternative value is
REFN
first programmed to the DAC register.
DAC OUTPUT STATE
The DAC output can be placed in one of three states, controlled
by the DACTRI and OPGND bits of the control register, as
shown in Tabl e 16 .
Table 16. AD5791 Output State Truth Table
DACTRI OPGND Output State
0 0 Normal operating mode
0 1 Output is clamped via ~6 kΩ to AGND
1 0 Output is in tristate
1 1 Output is clamped via ~6 kΩ to AGND
LINEARITY COMPENSATION
The integral nonlinearity (INL) of the AD5791 can vary according
to the applied reference voltage span, the LIN COMP bits of
the control register can be programmed to compensate for
this variation in INL. The specifications in this data sheet are
obtained with LIN COMP = 0000 for reference spans up to
and including 10 V and with LIN COMP = 1100 for a reference
span of 20 V. The default value of the LIN COMP bits is 0000.
Intermediate LIN COMP values can be programmed for reference
spans between 10 V and 20 V as shown in Table 12.
OUTPUT AMPLIFIER CONFIGURATION
There are a number of different ways that an output amplifier
can be connected to the AD5791, depending on the voltage
references applied and the desired output voltage span.
Unity Gain Configuration
Figure 52 shows an output amplifier configured for unity gain,
in this configuration the output spans from V
REFP
1/2 AD8676
REFN
20-BIT
DAC
V
REFPS
V
REFNS
A1
R
R1
FB
6.8kΩ 6.8kΩ
AD5791
R
FB
INV
V
OUT
V
REFPF
V
REFNF
1/2 AD8676
V
Figure 52. Output Amplifier in Unity Gain Configuration
to V
REFN
AD8675,
ADA4898-1
REFP
.
V
OUT
08964-051
A second unity gain configuration for the output amplifier is
one that removes an offset from the input bias currents of the
amplifier. It does this by inserting a resistance in the feedback
path of the amplifier that is equal to the output resistance of the
DAC. The DAC output resistance is 3.4 kΩ, by connecting R1
in parallel, a resistance equal to the DAC resistance is
and R
FB
available on chip. Because the resistors are all on one piece of
silicon, they are temperature coefficient matched. To enable this
mode of operation the RBUF bit of the control register must be
set to Logic 1. Figure 53 shows how the output amplifier is
connected to the AD5791. In this configuration, the output
amplifier is in unity gain and the output spans from V
. This unity gain configuration allows a capacitor to be placed
V
REFP
REFN
to
in the amplifier feedback path to improve dynamic performance.
REFP
1/2 AD8676
V
REFPF
V
REFNF
20-BIT
DAC
V
REFPS
V
REFNS
R
6.8kΩ6.8kΩR1
FB
AD5791
R
FB
10pF
AD8675,
ADA4898-1
V
OUT
INV
V
OUT
1/2 AD8676
V
REFN
08964-052
Figure 53. Output Amplifier in Unity Gain with Amplifier Input Bias Current
Compensation
Rev. C | Page 25 of 28
AD5791 Data Sheet
V
Gain of Two Configuration
Figure 54 shows an output amplifier configured for a gain of
two. The gain is set by the internal matched 6.8 kΩ resistors,
which are exactly twice the DAC resistance, having the effect of
removing an offset from the input bias current of the external
amplifier. In this configuration, the output spans from 2 ×
− V
V
REFN
REFP
to V
. This configuration is used to generate a
REFP
bipolar output span from a single ended reference input with
= 0 V. For this mode of operation, the RBUF bit of the
V
REFN
control register must be cleared to Logic 0.
REFP
1/2 AD8676
20-BIT
DAC
= 0V
V
REFPS
V
REFNS
A1
R
1RFB
6.8kΩ 6.8kΩ
AD5791
R
FB
INV
V
OUT
V
REFPF
V
REFNF
1/2 AD8676
V
REFN
Figure 54. Output Amplifier in Gain of Two Configuration
10pF
AD8675,
ADA4898-1
V
OUT
08964-053
Rev. C | Page 26 of 28
Data Sheet AD5791
APPLICATIONS INFORMATION
TYPICAL OPERATING CIRCUIT
Figure 55. Typical Operating Circuit
Figure 55 shows a typical operating circuit for the AD5791
using an AD8676 for reference buffers and an AD8675 as an
output buffer. To meet the specified linearity, force sense buffers
Rev. C | Page 27 of 28
must be used on the reference inputs. Because the output
impedance of the AD5791 is 3.4 kΩ, an output buffer is
required for driving low resistive, high capacitance loads.
08964-054
AD5791 Data Sheet
Y
OUTLINE DIMENSIONS
6.60
6.50
6.40
PIN 1
0.15
0.05
COPLANARIT
20
1
0.65
BSC
0.30
0.19
0.10
COMPLIANT TO JEDEC STANDARDS MO-153-AC
1.20 MAX
11
10
SEATING
PLANE
4.50
4.40
4.30
6.40 BSC
0.20
0.09
8°
0°
0.75
0.60
0.45
Figure 56. 20-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-20)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range INL Package Description Package Option
AD5791BRUZ −40°C to +125°C ±1.5 LSB 20-Lead TSSOP RU-20
AD5791ARUZ −40°C to +125°C ±4 LSB 20-Lead TSSOP RU-20
EVAL-AD5791SDZ
1
Z = RoHS Compliant Part.
Evaluation Board
©2010–2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08964-0-11/11(C)
Rev. C | Page 28 of 28
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