ANALOG DEVICES AD5791 Service Manual

1 ppm 20-Bit,

VCCVDDV

Data Sheet

FEATURES

1 ppm resolution 1 ppm INL

7.5 nV/√Hz noise spectral density

0.19 LSB long-term linearity stability <0.05 ppm/°C temperature drift 1 μs settling time

1.4 nV-sec glitch impulse Operating temperature range: −40°C to +125°C 20-lead TSSOP package Wide power supply range up to ±16.5 V 35 MHz Schmitt triggered digital interface

1.8 V compatible digital interface

APPLICATIONS

Medical instrumentation Test and measurement Industrial control High end scientific and aerospace instrumentation

±1 LSB INL, Voltage Output DAC

AD5791

FUNCTIONAL BLOCK DIAGRAM

REFPFVREFPS

6.8kΩ

6kΩ

R1 R

6.8kΩ

FB

R

INV

V

FB

OUT

IOV

CC

SDIN

SCLK

SYNC

SDO

LDAC

CLR

RESET

DGND V

AD5791

INPUT

SHIFT

REGISTER

AND

CONTROL

LOGIC

POWER-ON-RESET AND CLEAR LOG IC

20

SS

DAC REG

AGNDV

20

Figure 1.

Table 1. Complementary Devices

Part No. Description

AD8675

Ultra precision, 36 V, 2.8 nV/√Hz rail-to-rail output op amp

AD8676

Ultra precision, 36 V, 2.8 nV/√Hz dual rail-torail output op amp

ADA4898-1

High voltage, low noise, low distortion, unity gain stable, high speed op amp

V

20-BIT

DAC

REFNF

A1

REFNS

08964-001

GENERAL DESCRIPTION

The AD57911 is a single 20-bit, unbuffered voltage-output DAC that operates from a bipolar supply of up to 33 V. The AD5791 accepts a positive reference input in the range 5 V to V and a negative reference input in the range V

+ 2.5 V to 0 V.

SS

The AD5791 offers a relative accuracy specification of ±1 LSB max, and operation is guaranteed monotonic with a ±1 LSB DNL maximum specification.

The part uses a versatile 3-wire serial interface that operates at clock rates up to 35 MHz and that is compatible with standard SPI, QSPI™, MICROWIRE™, and DSP interface standards. The part incorporates a power-on reset circuit that ensures the DAC

1

Protected by U.S. Patent No. 7,884,747. Other patents pending.

Rev. C

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

− 2.5 V

DD

Table 2. Related Device

Part No. Description

AD5781 18-bit, 0.5 LSB INL, voltage output DAC

output powers up to 0 V and in a known output impedance state and remains in this state until a valid write to the device takes place. The part provides an output clamp feature that places the output in a defined load state.

PRODUCT HIGHLIGHTS

1. 1 ppm Accuracy.

2. Wide Power Supply Range up to ±16.5 V.

3. Operating Temperature Range: −40°C to +125°C.

4. Low 7.5 nV/√Hz Noise Spectral Density.

5. Low 0.05 ppm/°C Temperature Drift.

AD5791 Data Sheet

REVISION HISTORY

11/11—Rev. B to Rev. C

Added Figure 48; Renumbered Sequentially .............................. 17

Change to Ideal Transfer Function Equation.............................. 22

9/11—Rev. A to Rev. B

Added Patent Note ........................................................................... 1

Changes to Table 3............................................................................ 3

Changes to OPGND Description Column, Table 12................. 23

Change to Figure 51 ....................................................................... 25

DAC Architecture....................................................................... 20

Serial Interface............................................................................ 20

Hardware Control Pins.............................................................. 21

On-Chip Registers...................................................................... 22

AD5791 Features............................................................................ 25

Power-On to 0 V......................................................................... 25

Configuring the AD5791 .......................................................... 25

DAC Output State ...................................................................... 25

Linearity Compensation............................................................ 25

Output Amplifier Configuration.............................................. 25

Applications Information.............................................................. 27

Typical Operating Circuit ......................................................... 27

Outline Dimensions....................................................................... 28

Ordering Guide .......................................................................... 28

8/11—Rev. 0 to Rev. A

Change to Features Section..............................................................1

Changes to Specifications Section, Table 3....................................3

Deleted t

Subsequent Timing Parameters Sequentially ................................5

Changes to Figure 2 and Figure 3....................................................6

Changes to Figure 4...........................................................................7

Changes to Figure 42...................................................................... 16

Changes to Figure 43...................................................................... 16

Added Figure 44, Figure 45, and Figure 46, Renumbered

Sequentially .....................................................................................16

7/10—Revision 0: Initial Version

Timing Specification in Table 4, Renumbered

14

Rev. C | Page 2 of 28

Data Sheet AD5791

SPECIFICATIONS

VDD = 12.5 V to 16.5 V, VSS = −16.5 V to −12.5 V, V R

= unloaded, CL = unloaded, all specifications T

L

MIN

REFP

to T

= 10 V, V

MAX

= −10 V, VCC = 2.7 V to +5.5 V, IOVCC = 1.71 V to 5.5 V,

REFN

, unless otherwise noted.

Table 3.

A, B Version Parameter Min Typ Max Unit Test Conditions/Comments

STATIC PERFORMANCE2

Resolution 20 Bits Integral Nonlinearity Error (Relative Accuracy) −1 ±0.25 +1 LSB B version, V

−1.5 ±0.25 +1.5 LSB B version, V

−1.5 ±0.5 +1.5 LSB B version, V

−3 ±1 +3 LSB B version, V

−4 ±2 +4 LSB A version4 Differential Nonlinearity Error −1 ±0.5 +1 LSB V

−1.5 ±0.75 +1.5 LSB V

−2.5 ±1 +2.5 LSB V Linearity Error Long Term Stability5 0.16 LSB After 500 hours at TA = 125°C

0.19 LSB After 1000 hours at TA = 125°C

0.11 LSB After 1000 hours at TA = 100°C Full-Scale Error −7 ±0.1 +7 LSB V

−11 ±0.25 +11 LSB V

−21 ±0.8 +21 LSB V

−4 ±0.1 +4 LSB V

−4 ±0.25 +4 LSB V

−6 ±0.8 +6 LSB V Full-Scale Error Temperature Coefficient ±0.02 ppm FSR/°C Zero-Scale Error −7 ±0.1 +7 LSB V

−10 ±0.15 +10 LSB V

−21 ±0.75 +21 LSB V

−4 ±0.1 +4 LSB V

−4 ±0.15 +4 LSB V

−6 ±0.75 +6 LSB V Zero-Scale Error Temperature Coefficient3 ±0.04 ppm FSR/°C Gain Error −6 ±0.3 +6 ppm FSR V

−10 ±0.4 +10 ppm FSR V

−20 ±0.4 +20 ppm FSR V

−6 ±0.3 +6 ppm FSR V

−6 ±0.4 +6 ppm FSR V

−7 ±0.4 +7 ppm FSR V Gain Error Temperature Coefficient3 ±0.04 ppm FSR/°C R1, RFB Matching 0.01 %

OUTPUT CHARACTERISTICS3

Output Voltage Range V

V

REFN

Output Slew Rate 50 V/μs Output Voltage Settling Time 1 μs 10 V step to 0.02%, using the AD845 buffer

1 μs 500 code step to ±1 LSB6 Output Noise Spectral Density 7.5 nV/√Hz at 1 kHz, DAC code = midscale

7.5 nV/√Hz at 10 kHz, DAC code = midscale

7.5 nV/√Hz At 100 kHz, DAC code = midscale Output Voltage Noise 1.1 μV p-p DAC code = midscale, 0.1 Hz to 10 Hz

1

V

REFP

= +10 V, V

= 0°C to 105°C

T

A

REFP

= +10 V, V = 10 V, V = 5 V, V

= +10 V, V = 10 V, V

= 5 V, V = +10 V, V = 10 V, V

= 5 V, V

= +10 V, V

= 10 V, V

= 5 V, V = +10 V, V = 10 V, V

= 5 V, V

= +10 V, V

= 10 V, V

= 5 V, V = +10 V, V = 10 V, V

= 5 V, V

= +10 V, V = 10 V, V = 5 V, V

REFN

= 0 V

REFN

= 0 V

REFN

= 0 V3

REFN

= 0 V3

REFN

= −10 V3, TA = 0°C to 105°C

REFN

= 0 V3, TA = 0°C to 105°C

REFN

= 0 V3, TA = 0°C to 105°C

REFN

= 0 V3

REFN

= 0 V3

REFN

= −10 V3, TA = 0°C to 105°C

REFN

= 0 V3, TA = 0°C to 105°C

REFN

= 0 V3, TA = 0°C to 105°C

REFN

= 0 V3

REFN

= 0 V3

REFN

= −10 V3, TA = 0°C to 105°C

REFN

= 0 V3, TA = 0°C to 105°C

REFN

= 0 V3, TA = 0°C to 105°C

REFN

in unity-gain mode

7

bandwidth

REFN

= −10 V

= −10 V3

= −10 V,

= −10 V

= 0 V3

Rev. C | Page 3 of 28

AD5791 Data Sheet

A, B Version

1

Parameter Min Typ Max Unit Test Conditions/Comments

Midscale Glitch Impulse8 3.1 nV-sec V

1.7 nV-sec V

1.4 nV-sec V MSB Segment Glitch Impulse8 9.1 nV-sec V

3.6 nV-sec V

1.9 nV-sec V

= +10 V, V

REFP

= 10 V, V

REFP

= 5 V, V

REFP

= +10 V, V

REFP

= 10 V, V

REFP

= 5 V, V

REFP

= −10 V

REFN

= 0 V

REFN

= 0 V

REFN

= −10 V, see Figure 43

REFN

= 0 V, see Figure 44

REFN

= 0 V, see Figure 45

REFN

Output Enabled Glitch Impulse 45 nV-sec On removal of output ground clamp Digital Feedthrough 0.4 nV-sec DC Output Impedance (Normal Mode) 3.4 kΩ DC Output Impedance (Output Clamped

6 kΩ

to Ground) Spurious Free Dynamic Range 100 dB 1 kHz tone, 10 kHz sample rate Total Harmonic Distortion 97 dB 1 kHz tone, 10 kHz sample rate

REFERENCE INPUTS3

V

Input Range 5 VDD − 2.5 V V

REFP

V

Input Range VSS + 2.5 V 0

REFN

DC Input Impedance 5 6.6 kΩ V

, V

, code dependent,

REFP

REFN

typical at midscale code

Input Capacitance 15 pF V

REFP

, V

REFN

LOGIC INPUTS3

Input Current9 −1 +1 μA Input Low Voltage, VIL 0.3 × IOVCC V IOVCC = 1.71 V to 5.5 V Input High Voltage, VIH 0.7 × IOVCC V IOVCC = 1.71 V to 5.5 V Pin Capacitance 5 pF

LOGIC OUTPUT (SDO)3

Output Low Voltage, VOL 0.4 V IOVCC = 1.71 V to 5.5 V, sinking 1 mA Output High Voltage, VOH IOVCC − 0.5 V V IOVCC = 1.71 V to 5.5 V, sourcing 1 mA High Impedance Leakage Current ±1 μA High Impedance Output Capacitance 3 pF

POWER REQUIREMENTS All digital inputs at DGND or IOVCC

VDD 7.5 VSS + 33 V VSS V

− 33 −2.5 V

DD

VCC 2.7 5.5 V IOVCC 1.71 5.5 V IOVCC ≤ VCC IDD 4.2 5.2 mA ISS 4 4.9 mA ICC 600 900 μA IOICC 52 140 μA SDO disabled DC Power Supply Rejection Ratio

3, 10

±0.6 μV/V VDD ± 10%, V

= 15 V

SS

±0.6 μV/V VSS ± 10%, VDD = 15 V AC Power Supply Rejection Ratio3 95 dB VDD ± 200 mV, 50 Hz/60 Hz, V

= −15 V

SS

95 dB ∆VSS ± 200 mV, 50 Hz/60 Hz, VDD = 15 V

1

Temperature range: −40°C to +125°C, typical at +25°C and VDD = +15 V, VSS = −15 V, V

2

Performance characterized with AD8676BRZ voltage reference buffers and AD8675ARZ output buffer.

3

Guaranteed by design and characterization, not production tested.

4

Valid for all voltage reference spans.

5

Linearity error refers to both INL error and DNL error, either parameter can be expected to drift by the amount specified after the length of time specified.

6

AD5791 configured in X2 gain mode, 25 pF compensation capacitor on AD797.

7

Includes noise contribution from AD8676BRZ voltage reference buffers.

8

The AD5791 is configured in bias compensation mode with a low-pass RC filter on the output. R = 300 Ω, C = 143 pF.(total capacitance seen by the output buffer, lead

capacitance, and so forth).

9

Current flowing in an individual logic pin.

10

Includes PSRR of AD8676BRZ voltage reference buffers.

= +10 V, V

REFP

= −10 V.

REFN

Rev. C | Page 4 of 28

Data Sheet AD5791

TIMING CHARACTERISTICS

VCC = 2.7 V to 5.5 V; all specifications T

Table 4.

Parameter

2

t

40 28 ns min SCLK cycle time

1

IOVCC = 1.71 V to 3.3 V IOVCC = 3.3 V to 5.5 V

92 60 ns min SCLK cycle time (readback and daisy-chain modes)

t2 15 10 ns min SCLK high time

t3 9 5 ns min SCLK low time

t4 5 5 ns min

t5 2 2 ns min

t6 48 40 ns min

t7 8 6 ns min

t8 9 7 ns min Data setup time

t9 12 7 ns min Data hold time

t10 13 10 ns min

t11 20 16 ns min

t12 14 11 ns min

t13 130 130 ns typ

t14 130 130 ns typ

t15 50 50 ns min

t16 140 140 ns typ

t17 0 0 ns min

t18 65 60 ns max

t19 62 45 ns max SCLK rising edge to SDO valid (CL = 50 pF)

t20 0 0 ns min

t21 35 35 ns typ

t22 150 150 ns typ

1

All input signals are specified with tR = tF = 1 ns/V (10% to 90% of IOVCC) and timed from a voltage level of (VIL + VIH)/2.

2

Maximum SCLK frequency is 35 MHz for write mode and 16 MHz for readback and daisy-chain modes.

MIN

Limit1

to T

, unless otherwise noted.

MAX

Unit Test Conditions/Comments

to SCLK falling edge setup time

SYNC SCLK falling edge to SYNC Minimum SYNC

rising edge to next SCLK falling edge ignore

SYNC

falling edge to SYNC falling edge

LDAC

rising edge to LDAC falling edge

SYNC

pulse width low

LDAC

falling edge to output response time

LDAC

rising edge to output response time (LDAC tied low)

SYNC

pulse width low

CLR

pulse activation time

CLR

falling edge to first SCLK rising edge

SYNC

rising edge to SDO tristate (CL = 50 pF)

SYNC

rising edge to SCLK rising edge ignore

SYNC

pulse width low

RESET

pulse activation time

RESET

high time

rising edge hold time

Rev. C | Page 5 of 28

AD5791 Data Sheet

SCLK

t

3

t

9

t

15

16

SYNC

SDIN

LDAC

V

OUT

V

OUT

CLR

t

6

t

4

t

8

DB23 DB0

t

10

t

1

t

2

t

7

2421

t

5

t

11

t

14

12

t

13

SCLK

SYNC

SDIN

SDO

V

OUT

RESET

V

OUT

t

21

t

22

08964-002

Figure 2. Write Mode Timing Diagram

t

17

t

6

t

4

t

8

DB23 DB0

9

INPUT WORD SPECIFIES

REGISTER TO BE READ

t

1

t

3

t

2

t

7

24221241

t

5

17

NOP CONDIT ION

DB23 DB0

REGISTER CONTENTS CLOCKED OUT

t

19

20

t

5

t

18

08964-003

Figure 3. Readback Mode Timing Diagram

Rev. C | Page 6 of 28

Data Sheet AD5791

t

20

t

5

t

18

08964-004

SCLK

SYNC

SDIN

SDO

t

17

12 24 4825

t

6

t

4

t

8

DB23

INPUT WORD FOR DAC N

DB23

t

3

t

9

UNDEFINED

1

26

t

2

DB0 DB23 DB0

INPUT WORD FOR DAC N – 1

t

19

DB0 DB23 DB0

INPUT WORD FOR DAC N

Figure 4. Daisy-Chain Mode Timing Diagram

Rev. C | Page 7 of 28

AD5791 Data Sheet

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted. Transient currents of up to 100 mA do not cause SCR latch-up.

Table 5.

Parameter Rating

VDD to AGND −0.3 V to +34 V VSS to AGND −34 V to +0.3 V VDD to VSS −0.3 V to +34 V VCC to DGND −0.3 V to +7 V IOVCC to DGND

−0.3 V to V

+ 0.3 V or +7 V

CC

(whichever is less)

Digital Inputs to DGND

−0.3 V to IOV

+ 0.3 V or

CC

+7 V (whichever is less)

V

to AGND −0.3 V to VDD + 0.3 V

OUT

V

to AGND −0.3 V to VDD + 0.3 V

REFPF

V

to AGND −0.3 V to VDD + 0.3 V

REFPS

V

to AGND VSS − 0.3 V to + 0.3 V

REFNF

V

to AGND VSS − 0.3 V to + 0.3 V

REFNS

DGND to AGND −0.3 V to +0.3 V Operating Temperature Range, TA

Industrial −40°C to + 125°C

Storage Temperature Range −65°C to +150°C Maximum Junction Temperature,

max

T

J

150°C

Power Dissipation (TJ max − TA)/θJA TSSOP Package

θJA Thermal Impedance 143°C/W θJC Thermal Impedance 45°C/W

Lead Temperature JEDEC industry standard

Soldering J-STD-020

ESD (Human Body Model) 1.5 kV

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

This device is a high performance integrated circuit with an ESD rating of 1.5 kV, and it is ESD sensitive. Proper precautions should be taken for handling and assembly.

ESD CAUTION

Rev. C | Page 8 of 28

Data Sheet AD5791

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

INV

V

OUT

V

REFPS

V

REFPF

V

RESET

CLR

LDAC

V

IOV

DD

CC

1

2

3

4

(Not to Scale)

5

6

7

8

9

10

AD5791

TOP VIEW

20

R

FB

19

AGND

18

V

SS

17

V

REFNS

16

V

REFNF

15

DGND

14

SYNC

13

SCLK

12

SDIN

11

SDO

08964-005

Figure 5. Pin Configuration

Table 6. Pin Function Descriptions

Pin No. Mnemonic Description

1 INV Connection to Inverting Input of External Amplifier. See the AD5791 Features section for further details.

2 V

3 V

Analog Output Voltage.

OUT

REFPS

Positive Reference Sense Voltage Input. A voltage range of 5 V to V amplifier must be connected at this pin in conjunction with the V

− 2.5 V can be connected. A unity gain

DD

pin. See the AD5791 Features section for

REFPF

further details.

4 V

REFPF

Positive Reference Force Voltage Input. A voltage range of 5 V to V amplifier must be connected at this pin in conjunction with the V

− 2.5 V can be connected. A unity gain

DD

pin. See the AD5791 Features section for

REFPS

further details.

5 VDD

Positive Analog Supply Connection. A voltage range of 7.5 V to 16.5 V can be connected, V

should be decoupled

DD

to AGND. 6 7

RESET

Active Low Clear Logic Input Pin. Asserting this pin sets the DAC register to a user defined value (see Table 13) and

CLR

Active Low Reset Logic Input Pin. Asserting this pin returns the AD5791 to its power-on status.

updates the DAC output. The output value depends on the DAC register coding that is being used, either binary

or twos complement. 8

Active Low Load DAC Logic Input Pin. This is used to update the DAC register and consequently, the analog

LDAC

output. When tied permanently low, the output is updated on the rising edge of SYNC

. If LDAC is held high during the write cycle, the input register is updated, but the output update is held off until the falling edge of LDAC. The LDAC pin should not be left unconnected.

9 VCC Digital Supply Connection. A voltage range of 2.7 V to 5.5 V can be connected. VCC should be decoupled to DGND. 10 IOVCC

Digital Interface Supply Pin. Digital threshold levels are referenced to the voltage applied to this pin. A voltage in the range of 1.71 V to 5.5 V can be connected. IOV

should not be allowed to exceed V

CC

CC.

11 SDO Serial Data Output Pin. Data is clocked out on the rising edge of the serial clock input. 12 SDIN

Serial Data Input Pin. This device has a 24-bit shift register. Data is clocked into the register on the falling edge of the serial clock input.

13 SCLK

Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at clock rates of up to 35 MHz.

14

Active Low Digital Interface Synchronization Input Pin. This is the frame synchronization signal for the input data.

SYNC

When SYNC is low, it enables the input shift register, and data is then transferred in on the falling edges of the following clocks. The input shift register is updated on the rising edge of SYNC

. 15 DGND Ground Reference Pin for Digital Circuitry. 16 V

REFNF

Negative Reference Force Voltage Input. A voltage range of V amplifier must be connected at this pin, in conjunction with the V

+ 2.5 V to 0 V can be connected. A unity gain

SS

pin. See the AD5791 Features section for

REFNS

further details.

17 V

REFNS

Negative Reference Sense Voltage Input. A voltage range of V amplifier must be connected at this pin, in conjunction with the V

+ 2.5 V to 0 V can be connected. A unity gain

SS

pin. See the AD5791 Features section for

REFNF

further details.

18 VSS

Negative Analog Supply Connection. A voltage range of −16.5 V to −2.5 V can be connected. V

should be

SS

decoupled to AGND. 19 AGND Ground Reference Pin for Analog Circuitry. 20 RFB Feedback Connection for External Amplifier. See the AD5791 Features section for further details.

Rev. C | Page 9 of 28

ANALOG DEVICES AD5791 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

FUNCTIONAL BLOCK DIAGRAM

GENERAL DESCRIPTION

PRODUCT HIGHLIGHTS

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

TIMING CHARACTERISTICS

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS