ANALOG DEVICES AD5764R Service Manual

Complete Quad, 16-Bit, High Accuracy,

Serial Input, Bipolar Voltage Output DAC

Data Sheet

FEATURES

Complete quad, 16-bit digital-to-analog converter (DAC) Programmable output range: ±10 V, ±10.2564 V, or ±10.5263 V ±1 LSB maximum INL error, ±1 LSB maximum DNL error Low noise: 60 nV/√Hz Settling time: 10 μs maximum Integrated reference buffers Internal reference: 10 ppm/°C maximum On-chip die temperature sensor Output control during power-up/brownout Programmable short-circuit protection Simultaneous updating via Asynchronous Digital offset and gain adjust Logic output control pins DSP-/microcontroller-compatible serial interface Temperature range: −40°C to +85°C iCMOS process technology

to zero code

CLR

APPLICATIONS

Industrial automation Open-loop/closed-loop servo control Process control Data acquisition systems Automatic test equipment Automotive test and measurement High accuracy instrumentation

LDAC

AD5764R

GENERAL DESCRIPTION

The AD5764R is a quad, 16-bit, serial input, bipolar voltage output DAC that operates from supply voltages of ±11.4 V to ±16.5 V. Nominal full-scale output range is ±10 V. The AD5764R provides integrated output amplifiers, reference buffers, and proprietary power-up/power-down control circuitry. The part also features a digital I/O port, programmed via the serial interface, and an analog temperature sensor. The part incorporates digital offset and gain adjust registers per channel.

The AD5764R is a high performance converter that provides guaranteed monotonicity, integral nonlinearity (INL) of ±1 LSB, low noise, and 10 μs settling time. The AD5764R includes an on-chip 5 V reference with a reference temperature coefficient of 10 ppm/°C maximum. During power-up when the supply voltages are changing, VOUTx is clamped to 0 V via a low impedance path.

The AD5764R is based on the iCMOS® technology platform, which is designed for analog systems designers within industrial/ instrumentation equipment OEMs who need high performance ICs at higher voltage levels. iCMOS enables the development of analog ICs capable of 30 V and operation at ±15 V supplies, while allowing reductions in power consumption and package size, coupled with increased ac and dc performance.

The AD5764R uses a serial interface that operates at clock rates of up to 30 MHz and is compatible with DSP and microcontroller interface standards. Double buffering allows the simultaneous updating of all DACs. The input coding is programmable to either twos complement or offset binary formats. The asynchronous clear function clears all data registers to either bipolar zero or zero scale, depending on the coding used. The AD5764R is ideal for both closed-loop servo control and open-loop control applications. The AD5764R is available in a 32-lead TQFP and offers guaranteed specifications over the −40°C to +85°C industrial temperature range (see Figure 1 for the functional block diagram).

Rev. D

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

AD5764R Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Functional Block Diagram .............................................................. 3

Specifications ..................................................................................... 4

AC Performance Characteristics ................................................ 6

Timing Characteristics ................................................................ 7

Absolute Maximum Ratings .......................................................... 10

Thermal Resistance .................................................................... 10

ESD Caution ................................................................................ 10

Pin Configuration and Function Descriptions ........................... 11

Typical Performance Characteristics ........................................... 13

Terminology .................................................................................... 19

Theory of Operation ...................................................................... 21

DAC Architecture ....................................................................... 21

Reference Buffers ........................................................................ 21

Serial Interface ............................................................................ 21

Simultaneous Updating via

Transfer Function ....................................................................... 23

Asynchronous Clear (

Registers ........................................................................................... 24

LDAC

........................................... 22

CLR

) ....................................................... 23

Function Register ....................................................................... 24

Data Register ............................................................................... 25

Coarse Gain Register ................................................................. 25

Fine Gain Register ...................................................................... 25

Offset Register ............................................................................ 26

Offset and Gain Adjustment Worked Example ...................... 26

Design Features ............................................................................... 27

Analog Output Control ............................................................. 27

Digital Offset and Gain Control ............................................... 27

Programmable Short-Circuit Protection ................................ 27

Digital I/O Port ........................................................................... 27

Die Temperature Sensor ............................................................ 27

Local Ground Offset Adjust ...................................................... 27

Applications Information .............................................................. 28

Typical Operating Circuit ......................................................... 28

Layout Guidelines ........................................................................... 30

Galvanically Isolated Interface ................................................. 30

Microprocessor Interfacing ....................................................... 30

Evaluation Board ........................................................................ 31

Outline Dimensions ....................................................................... 32

Ordering Guide .......................................................................... 32

REVISION HISTORY

10/11—Rev. C to Re v. D

Changed 50 MHz to 30 MHz ....................................... Throughout

Changes to t

7/11—Rev. B t o R e v. C

Changed 30 MHz to 50 MHz Throughout.................................... 1

Changes to t

8/09—Rev. A to Re v. B

Deleted Endnote 1 in Table 1 .......................................................... 4

Deleted Endnote 1 in Table 2 .......................................................... 6

Deleted Endnote 1 and Changes t

Changes to Ordering Guide .......................................................... 32

, t2, and t3 Parameters, Table 3 .................................. 7

Parameter i n Tab l e 3 ............ 7

Rev. D | Page 2 of 32

2/09—Rev. 0 to R e v. A

Changes to Table 1 Tes t Conditions/Comments and

Added Endnote to Ta ble 1 ................................................................ 4

Added Endnote to Table 2 ................................................................ 6

Added Endnote to Table 3 ................................................................ 7

10/08—Revision 0: Initial Version

Data Sheet AD5764R

INPUT REG C

GAIN REG C

OFFSET REG C

DATA

REG C

DAC C

INPUT REG D

GAIN REG D

OFFSET REG D

DATA

REG D

DAC D

INPUT REG B

GAIN REG B

OFFSET REG B

DATA

REG B

DAC B

INPUT REG A

GAIN REG A

OFFSET REG A

DATA

REFERENCE

REG A

DAC A

LDAC REFCD

RSTINRSTOUT

REFABREFGND

AGNDD

VOUTD

AGNDC

VOUTC

AGNDB

VOUTB

AGNDA

VOUTA

ISCC

REFERENCE

BUFFERS

SDIN SCLK SYNC

SDO

BIN/2sCOMP

CLR

PGND

DGND

AVSSAV

INPUT SHIFT

AND

CONTROL

LOGIC

VOLTAGE MONITOR

AND

CONTROL

REFERENCE

BUFFERS

TEMP

SENSOR

TEMP

REFOUT

AD5764R

06064-001

FUNCTIONAL BLOCK DIAGRAM

Figure 1.

Rev. D | Page 3 of 32

AD5764R Data Sheet

ACCURACY

Outputs unloaded

Zero-Scale Tempco2

±2

ppm FSR/°C max

Power Supply Sensitivity2

300

µV/V typ

Load Current

±1

mA max

For specified performance

SPECIFICATIONS

AVDD = 11.4 V to 16.5 V, AVSS = −11.4 V to −16.5 V, AGND = DGND = REFGND = PGND = 0 V; REFAB = REFCD = 5 V external; DV

= 2.7 V to 5.25 V, R

Table 1.

Parameter B Grade1 C Grade1 Unit Test Conditions/Comments

Resolution 16 16 Bits Relative Accuracy (INL) ±2 ±1 LSB max Differential Nonlinearity (DNL) ±1 ±1 LSB max Guaranteed monotonic Bipolar Zero Error ±2 ±2 mV max

±3 ±3 mV max Bipolar Zero Tempco2 ±2 ±2 ppm FSR/°C max Zero-Scale Error ±2 ±2 mV max

±2.5 ±2.5 mV max

Gain Error ±0.02 ±0.02 % FSR max Gain Tempco2 ±2 ±2 ppm FSR/°C max DC Crosstalk2 0.5 0.5 LSB max

REFERENCE INPUT/OUTPUT

Reference Input2

Reference Input Voltage 5 5 V nominal ±1% for specified performance DC Input Impedance 1 1 MΩ min Typically 100 MΩ Input Current ±10 ±10 µA max Typically ±30 nA Reference Range 1/7 1/7 V min/V max

Reference Output

Output Voltage 4.995/5.005 4.995/5.005 V min/V max At 25°C, AVDD/AVSS = ±13.5 V Reference Tempco2 ±10 ±10 ppm/°C max Typically 1.7ppm/°C

1 1 MΩ min

LOAD

= 10 kΩ, CL = 200 pF. All specifications T

LOAD

MIN

to T

, unless otherwise noted.

MAX

25°C; error at other temperatures obtained using bipolar zero tempco

25°C; error at other temperatures obtained using zero-scale tempco

Output Noise2 18 18 µV p-p typ 0.1 Hz to 10 Hz Noise Spectral Density2 75 75 nV/√Hz typ At 10 kHz Output Voltage Drift vs. Time2 ±40 ±40 ppm/500 hr typ ±50 ±50 ppm/1000 hr typ Thermal Hysteresis2 70 70 ppm typ First temperature cycle 30 30 ppm typ Subsequent temperature cycles

OUTPUT CHARACTERISTICS2

Output Voltage Range3 ±10.5263 ±10.5263 V min/V max AVDD/AVSS = ±11.4 V, V ±14 ±14 V min/V max AVDD/AVSS = ±16.5 V, V Output Voltage Drift vs. Time ±13 ±13 ppm FSR/500 hr typ ±15 ±15

ppm FSR/1000 hr

typ

Short-Circuit Current 10 10 mA typ R

= 6 kΩ, see Figure 31

ISCC

Capacitive Load Stability

= ∞ 200 200 pF max

LOAD

= 10 kΩ 1000 1000 pF max

LOAD

DC Output Impedance 0.3 0.3 Ω max

Rev. D | Page 4 of 32

REFIN

= 5 V = 7 V

Data Sheet AD5764R

Pin Capacitance

pF max

Per pin

Output High Voltage

DVCC − 1

V min

DVCC = 5 V ± 5%, sourcing 200 µA

High Impedance Output Capacitance

pF typ

SDO only

∆V

/∆ΑVDD

−85

dB typ

Parameter B Grade1 C Grade1 Unit Test Conditions/Comments

DIGITAL INPUTS2 DVCC = 2.7 V to 5.25 V

Input High Voltage, VIH 2.4 2.4 V min Input Low Voltage, VIL 0.8 0.8 V max Input Current ±1.2 ±1.2 µA max Per pin

DIGITAL OUTPUTS (D0, D1, SDO)2

Output Low Voltage 0.4 0.4 V max DVCC = 5 V ± 5%, sinking 200 µA

Output Low Voltage 0.4 0.4 V max

= 2.7 V to 3.6 V,

sinking 200 µA

Output High Voltage DVCC − 0.5 DVCC − 0.5 V min

= 2.7 V to 3.6 V,

sourcing 200 µA

High Impedance Leakage Current ±1 ±1 µA max SDO only

DIE TEMPERATURE SENSOR2

Output Voltage at 25°C 1.47 1.47 V typ Die temperature Output Voltage Scale Factor 5 5 mV/°C typ Output Voltage Range 1.175/1.9 1.175/1.9 V min/V max −40°C to +105°C Output Load Current 200 200 µA max Current source only Power-On Time 10 10 ms typ

POWER REQUIREMENTS

AVDD/AVSS 11.4/16.5 11.4/16.5 V min/V max DVCC 2.7/5.25 2.7/5.25 V min/V max Power Supply Sensitivity

OUT

AIDD 3.55 3.55 mA/channel max Outputs unloaded

AISS 2.8 2.8 mA/channel max Outputs unloaded DICC 1.2 1.2 mA max VIH = DVCC, VIL = DGND, 750 µA typ Power Dissipation 275 275 mW typ ±12 V operation output unloaded

Temperature range: −40°C to +85°C; typical at +25°C. Device functionality is guaranteed to +105°C with degraded performance.

Guaranteed by design and characterization; not production tested.

Output amplifier headroom requirement is 1.4 V minimum.

Rev. D | Page 5 of 32

AD5764R Data Sheet

Slew Rate

V/µs typ

Digital Feedthrough

nV-sec typ

Effect of input bus activity on DAC outputs

AC PERFORMANCE CHARACTERISTICS

AVDD = 11.4 V to 16.5 V, AVSS = −11.4 V to −16.5 V, AGND = DGND = REFGND = PGND = 0 V; REFAB = REFCD = 5 V external; DV

= 2.7 V to 5.25 V, R

Table 2.

Parameter B Grade C Grade Unit Test Conditions/Comments

DYNAMIC PERFORMANCE1

Output Voltage Settling Time 8 8 µs typ Full-scale step to ±1 LSB 10 10 µs max 2 2 µs typ 512 LSB step settling

Digital-to-Analog Glitch Energy 8 8 nV-sec typ

Glitch Impulse Peak Amplitude 25 25 mV max

Channel-to-Channel Isolation 80 80 dB typ

DAC-to-DAC Crosstalk 8 8 nV-sec typ

Digital Crosstalk 2 2 nV-sec typ

Output Noise (0.1 Hz to 10 Hz) 0.1 0.1 LSB p-p typ

Output Noise (0.1 Hz to 100 kHz) 45 45 µV rms max

1/f Corner Frequency 1 1 kHz typ

Output Noise Spectral Density 60 60 nV/√Hz typ Measured at 10 kHz

Complete System Output Noise Spectral Density2 80 80 nV/√Hz typ Measured at 10 kHz

Guaranteed by design and characterization; not production tested.

Includes noise contributions from integrated reference buffers, a 16-bit DAC, and an output amplifier.

= 10 kΩ, CL = 200 pF. All specifications T

LOAD

MIN

to T

, unless otherwise noted.

MAX

Rev. D | Page 6 of 32

Data Sheet AD5764R

t10

ns min

TIMING CHARACTERISTICS

AVDD = 11.4 V to 16.5 V, AVSS = −11.4 V to −16.5 V, AGND = DGND = REFGND = PGND = 0 V; REFAB = REFCD = 5 V external; DV

= 2.7 V to 5.25 V, R

= 10 kΩ, CL = 200 pF. All specifications T

LOAD

MIN

to T

, unless otherwise noted.

MAX

Table 3.

Parameter

1, 2, 3

Limit at T

MIN

, T

Unit Description

MAX

t1 33 ns min SCLK cycle time t2 13 ns min SCLK high time t3 13 ns min SCLK low time t4 13 ns min

13 ns min

t6 90 ns min

SYNC falling edge to SCLK falling edge setup time

SCLK falling edge to SYNC rising edge

24 Minimum

SYNC high time t7 2 ns min Data setup time t8 5 ns min Data hold time t9 1.7 µs min 480 ns min

SYNC rising edge to LDAC falling edge (all DACs updated) SYNC rising edge to LDAC falling edge (single DAC updated) LDAC pulse width low

t11 500 ns max

LDAC falling edge to DAC output response time t12 10 µs max DAC output settling time t13 10 ns min t14 2 µs max

5, 6

25 ns max SCLK rising edge to SDO valid

t16 13 ns min t17 2 µs max t18 170 ns min

Guaranteed by design and characterization; not production tested.

All input signals are specified with tR = tF = 5 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V.

See Figure 2, Figure 3, and Figure 4.

Standalone mode only.

Measured with the load circuit of Figure 5.

Daisy-chain mode only.

CLR pulse width low

CLR pulse activation time

SYNC rising edge to SCLK falling edge

SYNC rising edge to DAC output response time (LDAC = 0)

LDAC falling edge to SYNC rising edge

Rev. D | Page 7 of 32

AD5764R Data Sheet

DB23

SCLK

SYNC

SDIN

LDAC

LDAC = 0

CLR

1 2 24

DB0

VOUTx

06064-002

LDAC

SDO

SDIN

SYNC

SCLK

24 48

DB23 DB0 DB23 DB0

DB23

INPUT WORD FOR DAC NUNDEFINED

INPUT WORD FOR DAC N – 1INPUT WORD FOR DAC N

DB0

06064-003

Timing Diagrams

Figure 2. Serial Interface Timing Diagram

Figure 3. Daisy-Chain Timing Diagram

Rev. D | Page 8 of 32

Data Sheet AD5764R

SDO

SDIN

SYNC

SCLK

24 48

DB23 DB0 DB23 DB0

DB23

UNDEFINED

NOP CONDITION

DB0

INPUT WORD SPECIFIES

REGIST E R TO BE READ

SELECTED REGISTER DATA

CLOCKED OUT

06064-004

200µA I

(MIN) OR

(MAX)

TO OUTPUT

50pF

06064-005

Figure 4. Readback Timing Diagram

Figure 5. Load Circuit for SDO Timing Diagram

Rev. D | Page 9 of 32

AD5764R Data Sheet

AVDD to AGND, DGND

−0.3 V to +17 V

Operating Temperature Range

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted. Transient currents of up to 100 mA do not cause SCR latch-up.

Table 4.

Parameter Rating

AVSS to AGND, DGND +0.3 V to −17 V DVCC to DGND −0.3 V to +7 V Digital Inputs to DGND

Digital Outputs to DGND −0.3 V to DVCC + 0.3 V REFAB, REFCD to AGND, PGND −0.3 V to AVDD + 0.3 V REFOUT to AGND AVSS to AVDD TEMP AVSS to AVDD VOUTx to AGND AVSS to AVDD AGND to DGND −0.3 V to +0.3 V

Industrial −40°C to +85°C Storage Temperature Range −65°C to +150°C Junction Temperature (TJ max) 150°C Lead Temperature (Soldering) JEDEC industry standard J-STD-020

−0.3 V to (DV whichever is less

+ 0.3 V) or +7 V,

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages.

Table 5. Thermal Resistance

Package Type θJA θJC Unit

32-Lead TQFP 65 12 °C/W

ESD CAUTION

Rev. D | Page 10 of 32

Data Sheet AD5764R

SYNC SCLK

SDIN

SDO

CLR

LDAC

AGNDA VOUTA VOUTB AGNDB AGNDC VOUTC VOUTD AGNDD

RSTOUT

RSTIN

DGND

CCAVDD

PGND

ISCC

BIN/2sCOMP

AVDDAVSSTEMP

REFGND

REFOUT

REFCD

REFAB

1 2 3 4 5 6 7 8

23 22 21

PIN 1

9 10 11

12 13

15 16

30 29

28 27

AD5764R

TOP VIEW

(Not to S cale)

06064-006

SDO

Serial Data Output. This pin is used to clock data from the serial register in daisy-chain or readback mode.

13, 31

AVDD

Positive Analog Supply Pins. Voltage ranges from 11.4 V to 16.5 V.

AGNDB

Ground Reference Pin for DAC B Output Amplifier.

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Figure 6. Pin Configuration

Table 6. Pin Function Descriptions

Pin No. Mnemonic Description

SYNC Active Low Input. This is the frame synchronization signal for the serial interface. While SYNC is low, data is

transferred in on the falling edge of SCLK.

2 SCLK

Serial Clock Input. Data is clocked into the input shift register on the falling edge of SCLK. This operates at clock speeds of up to 30 MHz.

3 SDIN Serial Data Input. Data must be valid on the falling edge of SCLK.

5 6

CLR LDAC Load DAC. This logic input is used to update the data registers and, consequently, the analog outputs. When

Negative Edge Triggered Input.

Asserting this pin sets the data registers to 0x0000.

tied permanently low, the addressed data register is updated on the rising edge of during the write cycle, the DAC input register is updated but the output update is held off until the falling edge of

LDAC. In this mode, all analog outputs can be updated simultaneously on the falling edge of LDAC. The LDAC

pin must not be left unconnected.

7, 8 D0, D1

Digital I/O Port. D0 and D1 form a digital I/O port. The user can set up these pins as inputs or outputs that are configurable and readable over the serial interface. When configured as inputs, these pins have weak internal pull-ups to DV

RSTOUT Reset Logic Output. This is the output from the on-chip voltage monitor used in the reset circuit. If desired, it

. When programmed as outputs, D0 and D1 are referenced by DVCC and DGND.

can be used to control other system components.

RSTIN Reset Logic Input. This input allows external access to the internal reset logic. Applying a Logic 0 to this input

clamps the DAC outputs to 0 V. In normal operation,

RSTIN should be tied to Logic 1. Register values remain

unchanged. 11 DGND Digital Ground Pin. 12 DVCC Digital Supply Pin. Voltage ranges from 2.7 V to 5.25 V.

SYNC. If LDAC is held high

14 PGND Ground Reference Point for Analog Circuitry. 15, 30 AVSS Negative Analog Supply Pins. Voltage ranges from –11.4 V to –16.5 V. 16 ISCC

This pin is used in association with an optional external resistor to AGND to program the short-circuit current

of the output amplifiers. Refer to the Design Features section for more information. 17 AGNDD Ground Reference Pin for DAC D Output Amplifier. 18 VOUTD

19 VOUTC

20 AGNDC Ground Reference Pin for DAC C Output Amplifier.

Analog Output Voltage of DAC D. Buffered output with a nominal full-scale output range of ±10 V. The output

amplifier is capable of directly driving a 10 kΩ, 200 pF load.

Analog Output Voltage of DAC C. Buffered output with a nominal full-scale output range of ±10 V. The output

amplifier is capable of directly driving a 10 kΩ, 200 pF load.

Rev. D | Page 11 of 32

AD5764R Data Sheet

Pin No. Mnemonic Description

22 VOUTB

23 VOUTA

24 AGNDA Ground Reference Pin for DAC A Output Amplifier. 25 REFAB

26 REFCD

27 REFOUT

28 REFGND Reference Ground Return for the Reference Generator and Buffers. 29 TEMP

Internal pull-up device on this logic input. Therefore, it can be left floating; and it defaults to a logic high condition.

2sCOMP This pin determines the DAC coding. This pin should be hardwired to either DVCC or DGND. When hardwired to

BIN/

Analog Output Voltage of DAC B. Buffered output with a nominal full-scale output range of ±10 V. The output amplifier is capable of directly driving a 10 kΩ, 200 pF load.

Analog Output Voltage of DAC A. Buffered output with a nominal full-scale output range of ±10 V. The output amplifier is capable of directly driving a 10 kΩ, 200 pF load.

External Reference Voltage Input for Channel A and Channel B. The reference input range is 1 V to 7 V, and it programs the full-scale output voltage. V

= 5 V for specified performance.

REFIN

External Reference Voltage Input for Channel C and Channel D. The reference input range is 1 V to 7 V, and it programs the full-scale output voltage. V

= 5 V for specified performance.

REFIN

Reference Output. This is the reference output from the internal voltage reference. The internal reference is 5 V ± 3 mV at 25°C, with a reference temperature coefficient of 10 ppm/°C.

This pin provides an output voltage proportional to temperature. The output voltage is 1.47 V typical at 25°C die temperature; variation with temperature is 5 mV/°C.

, input coding is offset binary (see Table 7). When hardwired to DGND, input coding is twos complement

(see Table 8).

Rev. D | Page 12 of 32

Data Sheet AD5764R

1.0

–1.0

–0.8

–0.6

–0.4

–0.2

0.2

0.4

0.6

0.8

0 10,000 20,000 30,000 40,000 50,000 60,000

INL ERROR ( LSB)

DAC CODE

= 25°C

= ±15V

REFIN

= 5V

06064-007

1.0

–1.0

–0.8

–0.6

–0.4

–0.2

0.2

0.4

0.6

0.8

0 10,000 20,000 30,000 40,000 50,000 60,000

INL ERROR ( LSB)

DAC CODE

TA = 25°C V

DD/VSS

= ±12V

REFIN

= 5V

06064-008

1.0

–1.0

–0.8

–0.6

–0.4

–0.2

0.2

0.4

0.6

0.8

0 10,000 20,000 30,000 40,000 50,000 60,000

DNL ERROR (L S B)

DAC CODE

TA = 25°C V

DD/VSS

= ±15V

REFIN

= 5V

06064-011

1.0

–1.0

–0.8

–0.6

–0.4

–0.2

0.2

0.4

0.6

0.8

0 10,000 20,000 30,000 40,000 50,000 60,000

DNL ERROR (L S B)

DAC CODE

= 25°C

= ±12V

REFIN

= 5V

06064-012

0.5

0.4

0.3

0.2

0.1

–0.2

–0.1

–40 100–20 0 20 40 60 80

INL ERROR ( LSB)

TEMPERATURE (°C)

= 25°C

= ±15V

REFIN

= 5V

06064-015

0.5

0.4

0.3

0.2

0.1

–0.1

–40 100–20 0 20 40 60 80

INL ERROR ( LSB)

TEMPERATURE (°C)

TA = 25°C V

/VSS = ±12V

REFIN

= 5V

06064-016

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 7. Integral Nonlinearity Error vs. DAC Code,

= ±15 V

DD/VSS

Figure 8. Integral Nonlinearity Error vs. DAC Code,

= ±12 V

DD/VSS

Figure 10. Differential Nonlinearity Error vs. DAC Code,

= ±12 V

DD/VSS

Figure 11. Integral Nonlinearity Error vs. Temperature,

= ±15 V

DD/VSS

Figure 9. Differential Nonlinearity Error vs. DAC Code,

DD/VSS

= ±15 V

Figure 12. Integral Nonlinearity Error vs. Temperature,

= ±12 V

DD/VSS

Rev. D | Page 13 of 32

AD5764R Data Sheet

0.15

0.10

0.05

–0.25

–0.20

–0.15

–0.10

–0.05

–40 100–20 0 20 40 60 80

DNL ERROR (L S B)

TEMPERATURE (°C)

TA = 25°C V

DD/VSS

= ±15V

REFIN

= 5V

06064-019

0.15

0.10

0.05

–0.25

–0.20

–0.15

–0.10

–0.05

–40 100–20 0 20 40 60 80

DNL ERROR (L S B)

TEMPERATURE (°C)

= 25°C

= ±12V

REFIN

= 5V

06064-020

0.5

0.4

0.3

0.2

0.1

–0.2

–0.1

11.4 16.415.414.413.412.4

INL ERROR ( LSB)

SUPPLY VOLTAGE (V)

= 25°C

REFIN

= 5V

06064-023

0.15

–0.25

–0.20

–0.15

–0.10

–0.05

0.05

0.10

11.4 16.415.414.413.412.4

DNL ERROR (L S B)

SUPPLY VOLTAGE (V)

TA = 25°C V

REFIN

= 5V

06064-025

0.8

–1.0

–0.8

–0.6

–0.4

–0.2

0.2

0.4

0.6

1 75 6432

INL ERROR ( LSB)

REFERENCE VOLTAGE (V)

TA = 25°C

06064-027

0.4

0.3

0.2

0.1

–0.4

–0.3

–0.2

–0.1

1 75 6432

DNL ERROR (L S B)

REFERENCE VOLTAGE (V)

TA = 25°C

06064-031

Figure 13. Differential Nonlinearity Error vs. Temperature,

= ±15 V

DD/VSS

Figure 14. Differential Nonlinearity Error vs. Temperature,

= ±12 V

DD/VSS

Figure 16. Differential Nonlinearity Error vs. Supply Voltage

Figure 17. Integral Nonlinearity Error vs. Reference Voltage,

= ±16.5 V

DD/VSS

Figure 15. Integral Nonlinearity Error vs. Supply Voltage

Figure 18. Differential Nonlinearity Error vs. Reference Voltage,

= ±16.5 V

DD/VSS

Rev. D | Page 14 of 32

Data Sheet AD5764R

0.6

–1.6

–1.4

–1.2

–1.0

–0.8

–0.6

–0.4

–0.2

0.2

0.4

1 75 6432

TUE (mV)

REFERENCE VOLTAGE (V)

TA = 25°C

06064-073

11.4 16.415.414.413.412.4

CURRENT (mA)

DD/VSS

(V)

TA = 25°C V

REFIN

= 5V

06064-037

0.25

–0.25

–0.20

–0.15

–0.10

–0.05

0.05

0.10

0.15

0.20

–40 100806040200–20

ZERO-SCALE ERROR (mV)

TEMPERATURE (°C)

REFIN

= 5V

VDD/V

= ±15V

/VSS = ±12V

06064-038

0.8

0.6

0.4

–0.4

–0.2

0.2

–40 100806040200–20

BIPOLAR ZERO ERROR (mV )

TEMPERATURE (°C)

REFIN

= 5V

VDD/V

= ±15V

DD/VSS

= ±12V

06064-039

1.4

0.6

0.8

1.0

1.2

0.4

–0.2

0.2

–40 100806040200–20

GAIN ERROR ( mV )

TEMPERATURE (°C)

REFIN

= 5V

VDD/VSS = ±15V

DD/VSS

= ±12V

06064-040

0.0014

0.0013

0.0012

0.0011

0.0010

0.0009

0.0008

0.0007

0.0006 0 5.04.54.03.53.02.52.01.51.00.5

(mA)

LOGIC

(V)

TA = 25°C

06064-041

Figure 19. Total Unadjusted Error vs. Reference Voltage,

= ±16.5 V

DD/VSS

Figure 20. IDD/ISS vs. VDD/VSS

Figure 22. Bipolar Zero Error vs. Temperature

Figure 23. Gain Error vs. Temperature

Figure 21. Zero-Scale Error vs. Temperature

Figure 24. DICC vs. Logic Input Voltage

Rev. D | Page 15 of 32

AD5764R Data Sheet

7000

3000

4000

5000

6000

2000

–1000

1000

–10 1050–5

OUTPUT VOLTAGE DELTA (µV)

SOURCE/SINK CURRENT (mA)

= 25°C

REFIN

= 5V

DD/VSS

= ±15V

DD/VSS

= ±12V

06064-042

10,000

7000

8000

9000

3000

4000

5000

6000

2000

–1000

1000

–12 83–2–7

OUTPUT VOLTAGE DELTA (µV)

SOURCE/SINK CURRENT (mA)

= 25°C

REFIN

= 5V

06064-043

= ±15V

= ±12V

CH1 3.00V M1.00µs CH1 –120mV

VDD/VSS = ±15V T

= 25°C

REFIN

= 5V

1µs/DIV

06064-044

–4 –6

–8 –10 –12 –14 –16 –18 –20 –22 –24 –26

–2.0–1.5–1.0–0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

OUT

(mV)

TIME (µs)

= ±12V,

REFIN

= 5V,

= 25°C, 0x8000 TO 0x7FF F, 500ns/DIV

06064-047

CH4 50.0µV M1.00s CH4 26µV

VDD/V

= ±15V MIDSCALE LOADED V

REFIN

= 0V

50µV/DIV

06064-048

CH1 10.0V

CH3 10.0mV

T 29.60%

CH2 10.0V M100µs A CH1 7.80mV

1 2

DD/VSS

= ±12V,

REFIN

= 5V, T

= 25°C,

RAMP TIME = 100µs,

LOAD = 200p F||10kΩ

06064-055

Figure 25. Source and Sink Capability of Output Amplifier with

Positive Full Scale Loaded

Figure 26. Source and Sink Capability of Output Amplifier with

Negative Full Scale Loaded

Figure 28. Major Code Transition Glitch Energy, VDD/VSS = ±12 V

Figure 29. Peak-to-Peak Noise (100 kHz Bandwidth)

Figure 27. Full-Scale Settling Time

Figure 30. VOUTx vs. VDD/VSS on Power-Up

Rev. D | Page 16 of 32

Data Sheet AD5764R

0 12010080604020

SHORT-CI RCUIT CURRENT (mA)

ISCC

(kΩ)

DD/VSS

= ±15V

= 25°C

REFIN

= 5V

06064-050

CH1 10.0V

CH3 5.00V

T 29.60%

CH2 10.0V M400µs A CH1 7.80mV

1 2

= ±12V

= 25°C

06064-054

CH1 50.0µV M1.00s A CH1 15µV

DD/VSS

= ±12V T

= 25°C,

10µF CAPACIT OR ON REFO UT

50µV/DIV

06064-052

M1.00s A CH1 18mV

VDD/V

= ±12V T

= 25°C

5µV/DIV

06064-053

REFERENCE OUTPUT VOLTAGE (V)

LOAD CURRENT ( µ A)

06064-032

0 20 40 60 80 100 120 140 160

180 200

TA = 25°C V

DD/VSS

= ±15V

1.0

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

1.9

–40 –20 0 20 40 60 80 100

TEMPERATURE OUTPUT VOLTAGE (V)

TEMPERATURE (°C)

06064-033

TA = 25°C V

DD/VSS

= ±15V

Figure 31. Short-Circuit Current vs. R

Figure 32. REFOUT Turn-On Transient

ISCC

Figure 34. REFOUT Output Noise 0.1 Hz to 10 Hz

Figure 35. REFOUT Load Regulation

Figure 33. REFOUT Output Noise 100 kHz Bandwidth

Figure 36. Temperature Output Voltage vs. Temperature

Rev. D | Page 17 of 32

AD5764R Data Sheet

06064-070

TEMPERATURE (°C)

REFERENCE OUTPUT VOLTAGE (V)

4.997

4.998

4.999

5.000

5.001

5.002

5.003

–40 –20 0 20 40 60 80 100

20 DEVICES SHOWN

06064-072

TEMPERATURE DRIFT (ppm/°C)

POPULATION (%)

0.5 1.5 2.5 3.5 4.5 5.5 6.5 7.5 8.5 9.5

MAX: 10ppm/°C TYP: 1.7ppm/°C

Figure 37. Reference Output Voltage vs. Temperature

Figure 38. Reference Output Temperature Drift (−40°C to +85°C)

Rev. D | Page 18 of 32

Data Sheet AD5764R

TERMINOLOGY

Relative Accuracy or Integral Nonlinearity (INL)

For the DAC, a measure of the maximum deviation, in LSBs, from a straight line passing through the endpoints of the DAC transfer function.

Differential Nonlinearity (DNL)

The difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ±1 LSB maximum ensures monotonicity. This DAC is guaranteed monotonic.

Monotonicity

A DAC is monotonic if the output either increases or remains constant for increasing digital input code. The AD5744R is monotonic over its full operating temperature range.

Bipolar Zero Error

The deviation of the analog output from the ideal half-scale output of 0 V when the DAC register is loaded with 0x8000 (offset binary coding) or 0x0000 (twos complement coding). Figure 22 shows a plot of bipolar zero error vs. temperature.

Bipolar Zero Temperature Coefficient

The measure of the change in the bipolar zero error with a change in temperature. It is expressed as parts per million of full-scale range per degree Celsius (ppm FSR/°C).

Full-Scale Error

The measure of the output error when full-scale code is loaded to the data register. Ideally, the output voltage should be 2 × V

− 1 LSB. Full-scale error is expressed as a percentage of

REFIN

full-scale range (% FSR).

Negative Full-Scale Error/Zero-Scale Error

The error in the DAC output voltage when 0x0000 (offset binary coding) or 0x8000 (twos complement coding) is loaded to the data register. Ideally, the output voltage should be −2 × V Figure 21 shows a plot of zero-scale error vs. temperature.

Output Voltage Settling Time

The amount of time it takes for the output to settle to a specified level for a full-scale input change.

Slew Rate

A limitation in the rate of change of the output voltage. The output slewing speed of a voltage-output DAC is usually limited by the slew rate of the amplifier used at its output. Slew rate is measured from 10% to 90% of the output signal and is given in volts per microsecond (V/µs).

Gain Error

A measure of the span error of the DAC. It is the deviation in slope of the DAC transfer characteristic from the ideal, expressed as a percentage of the full-scale range (% FSR). Figure 23 shows a plot of gain error vs. temperature.

REFIN

Total Unadjusted Error (TUE)

A measure of the output error, considering all the various errors. Figure 19 shows a plot of total unadjusted error vs. reference voltage.

Zero-Scale Error Temperature Coefficient

A measure of the change in zero-scale error with a change in temperature. It is expressed as parts per million of full-scale range per degree Celsius (ppm FSR/°C).

Gain Error Temperature Coefficient

A measure of the change in gain error with changes in temperature. It is expressed as parts per million of full-scale range per degree Celsius (ppm FSR/°C).

Digital-to-Analog Glitch Energy

The impulse injected into the analog output when the input code in the data register changes state. It is normally specified as the area of the glitch in nanovolt-seconds (nV-sec) and is measured when the digital input code is changed by 1 LSB at the major carry transition (0x7FFF to 0x8000), as seen in Figure 28.

Digital Feedthrough

A measure of the impulse injected into the analog output of the DAC from the digital inputs of the DAC, but measured when the DAC output is not updated. It is specified in nanovolt-seconds (nV-sec) and measured with a full-scale code change on the data bus, that is, from all 0s to all 1s, and vice versa.

Power Supply Sensitivity

Indicates how the output of the DAC is affected by changes in the power supply voltage.

DC Crosstalk

The dc change in the output level of one DAC in response to a change in the output of another DAC. It is measured with a fullscale output change on one DAC while monitoring another DAC, and is expressed in least significant bits (LSBs).

DAC-to-DAC Crosstalk

The glitch impulse transferred to the output of one DAC due to a digital code change and subsequent output change of another DAC. This includes both digital and analog crosstalk. It is measured by loading one of the DACs with a full-scale code change (from all 0s to all 1s, and vice versa) with monitoring the output of another DAC. The energy of the glitch is expressed in nanovolt-seconds (nV-sec).

Channel-to-Channel Isolation

The ratio of the amplitude of the signal at the output of one DAC to a sine wave on the reference input of another DAC. It is measured in decibels (dB).

Reference Temperature Coefficient

A measure of the change in the reference output voltage with a change in temperature. It is expressed in parts per million per degree Celsius (ppm/°C).

LDAC

low and

Rev. D | Page 19 of 32

AD5764R Data Sheet

Digital Crosstalk

A measure of the impulse injected into the analog output of one DAC from the digital inputs of another DAC but is measured when the DAC output is not updated. It is specified in nanovoltseconds (nV-sec) and measured with a full-scale code change on the data bus; that is, from all 0s to all 1s, and vice versa.

Thermal Hysteresis

The change of reference output voltage after the device is cycled through temperatures from −40°C to +85°C and back to −40°C. This is a typical value from a sample of parts put through such a cycle.

Rev. D | Page 20 of 32

Data Sheet AD5764R

06064-060

E15

REF

E14 E1

S11

R R R

S10

12-BIT, R-2R LADDER4 MSBs DECODED INTO

15 EQUAL SEG M E NTS

VOUTx

AGNDx

R/8

OUT

THEORY OF OPERATION

The AD5764R is a quad, 16-bit, serial input, bipolar voltage output DAC that operates from supply voltages of ±11.4 V to ±16.5 V and has a buffered output voltage of up to ±10.5263 V. Data is written to the AD5764R in a 24-bit word format via a 3-wire serial interface. The AD5764R also offers an SDO pin that is available for daisy chaining or readback.

The AD5764R incorporates a power-on reset circuit that ensures that the data registers are loaded with 0x0000 at power-up. The

AD5764R features a digital I/O port that can be programmed via

the serial interface, an analog die temperature sensor, on-chip 10 ppm/°C voltage reference, on-chip reference buffers, and per channel digital gain and offset registers.

DAC ARCHITECTURE

The DAC architecture of the AD5764R consists of a 16-bit, current mode, segmented R-2R DAC. The simplified circuit diagram for the DAC section is shown in Figure 39.

Figure 39. DAC Ladder Structure

The four MSBs of the 16-bit data-word are decoded to drive 15 switches, E1 to E15. Each of these switches connects one of the 15 matched resistors to either AGNDx or I

OUT

. The remaining 12 bits of the data-word drive Switch S0 to Switch S11 of the 12-bit R-2R ladder network.

REFERENCE BUFFERS

The AD5764R can operate with either an external or an internal reference. The reference inputs (REFAB and REFCD) have an input range of up to 7 V. This input voltage is then used to provide a buffered positive and negative reference for the DAC cores. The positive reference is given by

= 2 × V

REF

The negative reference to the DAC cores is given by

−V

= −2 × V

REF

These positive and negative reference voltages (along with the gain register values) define the output ranges of the DACs.

REFIN

SERIAL INTERFACE

The AD5764R is controlled over a versatile 3-wire serial interface that operates at clock rates of up to 30 MHz and is compatible with SPI, QSPI™, MICROWIRE™, and DSP standards.

Input Shift Register

The input shift register is 24 bits wide. Data is loaded into the device, MSB first, as a 24-bit word under the control of a serial clock input, SCLK. The input register consists of a read/write bit, a reserved bit that must be set to 0, three register select bits, three DAC address bits, and 16 data bits, as shown in Tab l e 9. The timing diagram for this operation is shown in Figure 2.

Upon power-up, the data registers are loaded with zero code (0x0000) and the outputs are clamped to 0 V via a low impedance path. The outputs can be updated with the zero code value by asserting either

LDAC

depends on the state of the BIN/ pin is tied to DGND, the data coding is twos complement and the outputs update to 0 V. If the BIN/ DV

, the data coding is offset binary and the outputs update to

negative full scale. To have the outputs power up with zero code loaded to the outputs, hold the

Standalone Operation

The serial interface works with both a continuous and noncontinuous serial clock. A continuous SCLK source can be used only

SYNC

is held low for the correct number of clock cycles. In gated clock mode, a burst clock containing the exact number of clock cycles must be used, and the final clock to latch the data. The first falling edge of starts the write cycle. Exactly 24 falling clock edges must be applied to SCLK before brought high before the 24 written is invalid. If more than 24 falling SCLK edges are applied

SYNC

before

is brought high, the input data is also invalid. The input register addressed is updated on the rising edge of For another serial transfer to take place, low again. After the end of the serial data transfer, data is automatically transferred from the input shift register to the addressed register.

When the data has been transferred into the chosen register of the addressed DAC, all data registers and outputs can be updated by taking

LDAC

low.

CLR

. The corresponding output voltage

2sCOMP

pin. If the BIN/

2sCOMP

CLR

pin low during power-up.

SYNC

must be taken high after

SYNC

is brought high again. If

falling SCLK edge, then the data

SYNC

2sCOMP

pin is tied to

SYNC

must be brought

Rev. D | Page 21 of 32

AD5764R Data Sheet

68HC11*

MISO

SYNC

SDIN SCLK

MOSI

SCK

PC7 PC6

LDAC

SDO

SYNC

SCLK

LDAC

SDO

SYNC

SCLK

LDAC

SDO

SDIN

*ADDITIONAL PINS OMITTED FOR CLARITY.

AD5764R*

06064-061

SYNC

is held

Figure 4

LDAC

and

, and after

is held low while data

LDAC

is held high

Figure 40. Daisy-Chaining the AD5764R

Daisy-Chain Operation

For systems that contain several devices, the SDO pin can be used to daisy-chain several devices together. This daisy-chain mode can be useful in system diagnostics and in reducing the number of serial interface lines. The first falling edge of starts the write cycle. The SCLK is continuously applied to the input shift register when

SYNC

is low. If more than 24 clock pulses are applied, the data ripples out of the input shift register and appears on the SDO line. This data is clocked out on the rising edge of SCLK and is valid on the falling edge. By connecting the SDO of the first device to the SDIN input of the next device in the chain, a multidevice interface is constructed.

Each device in the system requires 24 clock pulses. Therefore, the total number of clock cycles must equal 24n, where n is the total number of AD5764R devices in the chain. When the serial transfer to all devices is complete, latches the input data in each device in the daisy chain and prevents any further data from being clocked into the input shift register. The serial clock can be a continuous or a gated clock.

SYNC

is taken high. This

SYNC

A continuous SCLK source can be used only if low for the correct number of clock cycles. In gated clock mode, a burst clock containing the exact number of clock cycles must be used, and

SYNC

must be taken high after the final clock to

latch the data.

Readback Operation

Before a readback operation is initiated, the SDO pin must be enabled by writing to the function register and clearing the SDO disable bit; this bit is cleared by default. Readback mode is invoked by setting the R/

set to 1, Bit A2 to Bit A0, in association with Bit REG2 to

bit to 1 in the serial input register write. With

Bit REG0, select the register to be read. The remaining data bits in the write sequence are don’t care. During the next SPI write, the data appearing on the SDO output contains the data from the previously addressed register. For a read of a single register, the NOP command can be used in clocking out the data from the selected register on SDO. The readback diagram in shows the readback sequence. For example, to read back the fine gain register of Channel A, implement the following sequence:

1. Write 0xA0XXXX to the input shift register. This write

configures the AD5764R for read mode with the fine gain register of Channel A selected. Note that all the data bits, DB15 to DB0, are don’t care.

2. Follow with a second write: an NOP condition, 0x00XXXX.

During this write, the data from the fine gain register is clocked out on the SDO line; that is, data clocked out contains the data from the fine gain register in Bit DB5 to Bit DB0.

SIMULTANEOUS UPDATING VIA LDAC

Depending on the status of both

SYNC data has been transferred into the input register of the DACs, there are two ways to update the data registers and DAC outputs.

Individual DAC Updating

In individual DAC updating mode,

LDAC is being clocked into the input shift register. The addressed DAC output is updated on the rising edge of

SYNC

Simultaneous Updating of All DACs

In simultaneous updating of all DACs mode, while data is being clocked into the input shift register. All DAC outputs are updated by taking

LDAC

low any time after

has been taken high. The update then occurs on the falling edge

LDAC

SYNC

Rev. D | Page 22 of 32

Data Sheet AD5764R

VOUTx

DATA

INTERFACE

LOGIC

OUTPUT

I/V AMPLIFIER

LDAC

SDO

SDIN

16-BIT

DAC

REFAB, REF CD

SYNC

INPUT

SCLK

06064-062

MSB

LSB

See Figure 41 for a simplified block diagram of the DAC load circuitry.

Figure 41. Simplified Serial Interface of Input Loading Circuitry

for One DAC Channel

TRANSFER FUNCTION

Tabl e 7 and Tab l e 8 show the ideal input code to output voltage relationship for offset binary data coding and twos complement data coding, respectively.

The output voltage expression for the AD5764R is given by

OUT

×+×−=



VVV

REFINREFIN

 

 

536,65



where:

D is the decimal equivalent of the code loaded to the DAC. V

is the reference voltage applied at the REFAB and

REFIN

REFCD pins.

ASYNCHRONOUS CLEAR (CLR)

CLR

is a negative edge triggered clear that allows the outputs to be cleared to either 0 V (twos complement coding) or negative full scale (offset binary coding). It is necessary to maintain low for a minimum amount of time for the operation to complete (see

Figure 2). When the

CLR

signal is returned high, the output

remains at the cleared value until a new value is programmed.

CLR

is at 0 V at power-on, all DAC outputs are updated with the clear value. A clear can also be initiated through software by writing the command of 0x04XXXX.

CLR

Table 7. Ideal Output Voltage to Input Code Relationship—Offset Binary Data Coding

Digital Input Analog Output

OUT

1111 1111 1111 1111 +2 V 1000 0000 0000 0001 +2 V

× (32,767/32,768)

REFIN

× (1/32,768)

REFIN

1000 0000 0000 0000 0 V 0111 1111 1111 1111 −2 V 0000 0000 0000 0000 −2 V

× (1/32,768)

REFIN

× (32,767/32,768)

REFIN

Table 8. Ideal Output Voltage to Input Code Relationship—Twos Complement Data Coding

Digital Input Analog Output

MSB LSB V

0111 1111 1111 1111 +2 V 0000 0000 0000 0001 +2 V

OUT

× (32,767/32,768)

REFIN

× (1/32,768)

REFIN

0000 0000 0000 0000 0 V 1111 1111 1111 1111 −2 V 1000 0000 0000 0000 −2 V

× (1/32,768)

REFIN

× (32,767/32,768)

REFIN

Rev. D | Page 23 of 32

AD5764R Data Sheet

0 0 0 Function register

Channel Address

0 0 1 DAC B

REGISTERS

Table 9. Input Shift Register Format

MSB LSB DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 to DB1 DB0

R/W

Table 10. Input Shift Register Bit Function Descriptions

R/W REG2, REG1, REG0

0 1 0 Data register 0 1 1 Coarse gain register 1 0 0 Fine gain register 1 0 1 Offset register A2, A1, A0 Decodes the DAC channels

0 0 0 DAC A

0 REG2 REG1 REG0 A2 A1 A0 Data

Indicates a read from or a write to the addressed register Used in association with the address bits, determines if a read or write operation is to the data register, offset register,

gain registers, or function register

REG2 REG1 REG0 Function

0 1 0 DAC C 0 1 1 DAC D 1 0 0 All DACs Data Data bits

FUNCTION REGISTER

The function register is addressed by setting the three REG bits to 000. The values written to the address bits and the data bits determine the function addressed. The functions available via the function register are outlined in Ta ble 11 and Ta b le 12.

Table 11. Function Register Options

REG2 REG1 REG0 A2 A1 A0 DB15 to DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 0 0 0 0 0 0 0 0 1 Don’t care

0 0 0 1 0 0 0 0 0 1 0 1

Local ground offset adjust

Table 12. Explanation of Function Register Options

Option Description

NOP No operation instruction used in readback operations. Local Ground

Offset Adjust D0, D1

Direction D0, D1 Value

SDO Disable Set by the user to disable the SDO output. Cleared by the user to enable the SDO output (default). Clear Addressing this function resets the DAC outputs to 0 V in twos complement mode and negative full scale in binary mode. Load Addressing this function updates the DAC registers and consequently the analog outputs.

Set by the user to enable the local ground offset adjust function. Cleared by the user to disable the local ground offset adjust function (default). See the Design Features section for more information.

Set by the user to enable the D0 and D1 pins as outputs. Cleared by the user to enable the D0 and D1 pins as inputs (default). See the Design Features section for more information.

I/O port status bits. Logic values written to these locations determine the logic outputs on the D0 and D1 pins when configured as outputs. These bits indicate the status of the D0 and D1 pins when the I/O port is active as an input. When enabled as inputs, these bits are don’t cares during a write operation.

NOP, data = don’t care

D1 direction

Clear, data = don’t care Load, data = don’t care

D1 value

D0 direction

D0 value

SDO disable

Rev. D | Page 24 of 32

Data Sheet AD5764R

DATA REGISTER

The data register is addressed by setting the three REG bits to 010. The DAC address bits select the DAC channel with which the data transfer takes place (see Ta b le 10). The data bits are positioned in DB15 to DB0, as shown in Tabl e 13.

Table 13. Programming the Data Register

REG2 REG1 REG0 A2 A1 A0 DB15 to DB0

0 1 0 DAC address 16-bit DAC data

COARSE GAIN REGISTER

The coarse gain register is addressed by setting the three REG bits to 011. The DAC address bits select the DAC channel with which the data transfer takes place (see Table 10). The coarse gain register is a 2-bit register that allows the user to select the output range of each DAC, as shown in Ta bl e 15.

Table 14. Programming the Coarse Gain Register

REG2 REG1 REG0 A2 A1 A0 DB15 to DB2 DB1 DB0

0 1 1 DAC address Don’t care CG1 CG0

Table 15. Output Range Selection

Output Range CG1 CG0

±10 V (Default) 0 0 ±10.2564 V 0 1 ±10.5263 V 1 0

FINE GAIN REGISTER

The fine gain register is addressed by setting the three REG bits to 100. The DAC address bits select the DAC channel with which the data transfer takes place (see Ta b le 10). The AD5764R fine gain register is a 6-bit register that allows the user to adjust the gain of each DAC channel by −32 LSBs to +31 LSBs in 1 LSB steps, as shown in Table 16 and Tabl e 17. The adjustment is made to both the positive full-scale points and the negative full-scale points simultaneously, with each point adjusted by one-half of one step. The fine gain register coding is twos complement.

Table 16. Programming the Fine Gain Register

REG2 REG1 REG0 A2 A1 A0 DB15 to DB6 DB5 DB4 DB3 DB2 DB1 DB0

1 0 0 DAC address Don’t care FG5 FG4 FG3 FG2 FG1 FG0

Table 17. Fine Gain Register Options

Gain Adjustment FG5 FG4 FG3 FG2 FG1 FG0

+31 LSBs 0 1 1 1 1 1 +30 LSBs 0 1 1 1 1 0 No Adjustment (Default) 0 0 0 0 0 0

−31 LSBs 1 0 0 0 0 1

−32 LSBs 1 0 0 0 0 0

Rev. D | Page 25 of 32

AD5764R Data Sheet

−15.875 LSBs

1 0 0 0 0 0 0

µV14.38

µV614

SizeStepOffset

ValueOffsetMeasured

µV59.152

mV2.1

SizeStepGain

ValueGainMeasured

OFFSET REGISTER

The offset register is addressed by setting the three REG bits to 101. The DAC address bits select the DAC channel with which the data transfer takes place (see Ta b le 10). The AD5764R offset register is an 8-bit register that allows the user to adjust the offset of each channel by −16 LSBs to +15.875 LSBs in steps of one-eighth LSB, as shown in Table 18 and Tab l e 19. The offset register coding is twos complement.

Table 18. Programming the Offset Register

REG2 REG1 REG0 A2 A1 A0 DB15 to DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

1 0 1 DAC address Don’t care OF7 OF6 OF5 OF4 OF3 OF2 OF1 OF0

Table 19. Offset Register Options

Offset Adjustment OF7 OF6 OF5 OF4 OF3 OF2 OF1 OF0

+15.875 LSBs 0 1 1 1 1 1 1 1 +15.75 LSBs 0 1 1 1 1 1 1 0 No Adjustment (Default) 0 0 0 0 0 0 0 0

−16 LSBs 1 0 0 0 0 0 0 0

OFFSET AND GAIN ADJUSTMENT WORKED EXAMPLE

Using the information provided in the Offset Register section, the following worked examples demonstrate how the AD5764R functions can be used to eliminate both offset and gain errors. Because the AD5764R is factory calibrated, offset and gain errors should be negligible. However, errors can be introduced by the system within which the AD5764R is operating. For example, a voltage reference value that is not equal to 5 V introduces a gain error. An output range of ±10 V and twos complement data coding are assumed.

Removing Offset Error

The AD5764R can eliminate an offset error in the range of

−4.88 mV to +4.84 mV with a step size of one-eighth of a 16-bit LSB.

1. Calculate the step size of the offset adjustment, using the

following equation:

The required offset register value can be calculated as follows:

1. Convert the adjustment value to binary: 00010000.

2. Convert this binary value to a negative twos complement

number by inverting all bits and adding 1: 11110000.

3. Program this value, 11110000, to the offset register.

Note that this twos complement conversion is not necessary in the case of a positive offset adjustment. The value to be programmed to the offset register is simply the binary representation of the adjustment value.

Removing Gain Error

The AD5764R can eliminate a gain error at negative full-scale output in the range of −9.77 mV to +9.46 mV with a step size of one-half of a 16-bit LSB.

1. Calculate the step size of the gain adjustment, using the

following equation:

Gain Adjust Step Size =

= 152.59 µV

2. Measure the offset error by programming 0x0000 to the

3. Determine how many offset adjustment steps this value

Number of Steps =

Offset Adjust Step Size =

= 38.14 µV

data register and measuring the resulting output voltage. For this example, the measured value is 614 µV.

represents, using the following equation:

= 16 Steps

The offset error measured is positive; therefore, a negative adjustment of 16 steps is required. The offset register is eight bits wide, and the coding is twos complement.

Rev. D | Page 26 of 32

2. Measure the gain error by programming 0x8000 to the

data register and measuring the resulting output voltage. The gain error is the difference between this value and −10 V. For this example, the gain error is −1.2 mV.

3. Determine how many gain adjustment steps this value

represents, using the following equation:

Number of Steps =

= 8 Steps

The gain error measured is negative (in terms of magnitude). Therefore, a positive adjustment of eight steps is required. The gain register is six bits wide, and the coding is twos complement. The required gain register value can be determined as follows:

1. Convert the adjustment value to binary: 001000.

2. Program this binary number to the gain register.

Data Sheet AD5764R

RSTOUT

RSTIN

VOUTA

AGNDA

VOLTAGE MONITOR

AND

CONTROL

06064-063

DESIGN FEATURES

ANALOG OUTPUT CONTROL

In many industrial process control applications, it is vital that the output voltage be controlled during power-up and during brownout conditions. When the supply voltages are changing, the VOUTx pins are clamped to 0 V via a low impedance path. To prevent the output amp from being shorted to 0 V during this time, Transmission Gate G1 is also opened (see Figure 42).

Figure 42. Analog Output Control Circuitry

These conditions are maintained until the power supplies stabilize and a valid word is written to the data register. G2 then opens, and G1 closes. Both transmission gates are also externally controllable by using the reset in (

RSTIN

) control input. For example, if

is driven from a battery supervisor chip, the

RSTIN

input is driven

RSTIN

low to open G1 and close G2 on power-off or during a brownout. Conversely, the on-chip voltage detector output (

RSTOUT

) is also available to the user to control other parts of the system. The basic transmission gate functionality is shown in

Figure 42.

DIGITAL OFFSET AND GAIN CONTROL

The AD5764R incorporates a digital offset adjust function with a ±16 LSB adjust range and 0.125 LSB resolution. The gain register allows the user to adjust the AD5764R full-scale output range. The full-scale output can be programmed to achieve full-scale ranges of ±10 V, ±10.25 V, and ±10.5 V. A fine gain trim is also available.

PROGRAMMABLE SHORT-CIRCUIT PROTECTION

The short-circuit current (ISC) of the output amplifiers can be programmed by inserting an external resistor between the ISCC pin and the PGND pin. The programmable range for the current is 500 µA to 10 mA, corresponding to a resistor range of 120 kΩ to 6 kΩ. The resistor value is calculated as follows:

If the ISCC pin is left unconnected, the short circuit current limit defaults to 5 mA. It should be noted that limiting the short-circuit current to a small value can affect the slew rate of the output when driving into a capacitive load. Therefore, the value of the short-circuit current that is programmed should take into account the size of the capacitive load being driven.

DIGITAL I/O PORT

The AD5764R contains a 2-bit digital I/O port (D1 and D0). These bits can be configured independently as inputs or outputs and can be driven or have their values read back via the serial interface. The I/O port signals are referenced to DV

and DGND. When

configured as outputs, they can be used as control signals to multiplexers or can be used to control calibration circuitry elsewhere in the system. When configured as inputs, the logic signals from limit switches, for example, can be applied to D0 and D1 and can be read back using the digital interface.

DIE TEMPERATURE SENSOR

The on-chip die temperature sensor provides a voltage output that is linearly proportional to the Celsius temperature scale. Its nominal output voltage is 1.47 V at +25°C die temperature, varying at 5 mV/°C, giving a typical output range of 1.175 V to

1.9 V over the full temperature range. Its low output impedance, and linear output simplify interfacing to temperature control circuitry and analog-to-digital converters (ADCs). The temperature sensor is provided as more of a convenience than as a precise feature; it is intended for indicating a die temperature change for recalibration purposes.

LOCAL GROUND OFFSET ADJUST

The AD5764R incorporates a local ground offset adjust feature that, when enabled in the function register, adjusts the DAC outputs for voltage differences between the individual DAC ground pins and the REFGND pin, ensuring that the DAC output voltages are always referenced to the local DAC ground pin. For example, if the AGNDA pin is at +5 mV with respect to the REFGND pin, and VOUTA is measured with respect to AGNDA, a −5 mV error results, enabling the local ground offset adjust feature to adjust VO UTA by + 5 m V, thereby eliminating the error.

R ≈

Rev. D | Page 27 of 32

AD5764R Data Sheet

Initial Accuracy

Long-Term Drift

Temperature Drift

0.1 Hz to 10 Hz Noise

APPLICATIONS INFORMATION

TYPICAL OPERATING CIRCUIT

Figure 43 shows the typical operating circuit for the AD5764R . The only external components needed for this precision 16-bit DAC are decoupling capacitors on the supply pins and reference inputs, and an optional short-circuit current setting resistor. Because the AD5764R incorporates a voltage reference and reference buffers, it eliminates the need for an external bipolar reference and associated buffers, resulting in an overall savings in both cost and board space.

In Figure 43, AVDD is connected to +15 V, and AVSS is connected to −15 V, but AV from ±11.4 V to ±16.5 V. In Figure 43, AGNDx is connected to REFGND.

Precision Voltage Reference Selection

To achieve the optimum performance from the AD5764R over its full operating temperature range, an external voltage reference must be used. Care must be taken in the selection of a precision voltage reference. The AD5764R has two reference inputs, REFAB and REFCD. The voltages applied to the reference inputs are used to provide a buffered positive and negative reference for the DAC cores. Therefore, any error in the voltage reference is reflected in the outputs of the device.

There are four possible sources of error to consider when choosing a voltage reference for high accuracy applications: initial accuracy, temperature coefficient of the output voltage, long term drift, and output voltage noise.

and AVSS can operate with supplies

Initial accuracy error on the output voltage of an external reference could lead to a full-scale error in the DAC. Therefore, to minimize these errors, a reference with low initial accuracy error specification is preferred. Choosing a reference with an output trim adjustment, such as the ADR425, allows a system designer to trim system errors out by setting the reference voltage to a voltage other than the nominal. The trim adjustment can also be used at temperature to trim out any error.

Long-term drift is a measure of how much the reference output voltage drifts over time. A reference with a tight long-term drift specification ensures that the overall solution remains relatively stable over its entire lifetime.

The temperature coefficient of a reference output voltage affects INL, DNL, and TUE. A reference with a tight temperature coefficient specification should be chosen to reduce the dependence of the DAC output voltage on ambient conditions.

In high accuracy applications, which have a relatively low noise budget, reference output voltage noise must be considered. It is important to choose a reference with as low an output noise voltage as practical for the system resolution that is required. Precision voltage references, such as the ADR435 (XFET® design), produce low output noise in the 0.1 Hz to 10 Hz region. However, as the circuit bandwidth increases, filtering the output of the reference may be required to minimize the output noise.

Table 20. Some Precision References Recommended for Use with the AD5764R

Part No.

ADR435 ±6 30 3 3.5 ADR425 ±6 50 3 3.4 ADR02 ±5 50 3 10 ADR395 ±6 50 25 5 AD586 ±2.5 15 10 4

(mV Maximum)

(p pm Ty pical)

(ppm/°C Maximum)

(µV p-p Ty pical)

Rev. D | Page 28 of 32

Data Sheet AD5764R

1 2 3 4 5 6 7 8

23 22 21

9 10

11 12 13

14 15 16

30 29 28 27 26 25

AD5764R

SYNC SCLK SDIN SDO

LDAC

CLR

VOUTA

VOUTB

AGNDB

VOUTD

VOUTC

AGNDC

AGNDA

AGNDD

RSTOUT

RSTIN

DGND

AVDDPGND

ISCC

BIN/2sCOMP

TEMP

REFGND

REFOUT

REFCD

REFAB

SYNC

SCLK

SDIN

SDO

LDAC

D0 D1

RSTOUT

RSTIN

BIN/2sCOMP

+5V

+15V –15V

VOUTA VOUTB

VOUTC VOUTD

100nF

10µF

100nF

10µF

TEMP

10µF

06064-064

Figure 43. Typical Operating Circuit

Rev. D | Page 29 of 32

AD5764R Data Sheet

SERIAL CL OCK OUT TO SCLK

ENCODE

DECODE

SERIAL DAT A OUT TO SDIN

ENCODE DECODE

SYNC OUT TO SYNC

ENCODE DECODE

CONTROL OUT TO LDAC

ENCODE DECODE

MICROCONTROLLER

ADuM1400*

*ADDITIONAL PINS OMITTED FOR CLARITY.

06064-065

LAYOUT GUIDELINES

In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. Design the PCB on which the

AD5764R is mounted such that the analog and digital sections

are separated and confined to certain areas of the board. If the

AD5764R is in a system where multiple devices require an

AGNDx-to-DGND connection, establish the connection at one point only. Establish the star ground point as close as possible to the device. The AD5764R should have ample supply bypassing of 10 µF in parallel with 0.1 µF on each supply located as close to the package as possible, ideally right up against the device. The 10 µF capacitors are of the tantalum bead type. The 0.1 µF capacitor should have low effective series resistance (ESR) and low effective series inductance (ESI), such as the common ceramic types that provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching.

The power supply lines of the AD5764R should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Shield fast-switching signals, such as clocks, with digital ground to avoid radiating noise to other parts of the board; they should never be run near the reference inputs. A ground line routed between the SDIN and SCLK lines helps reduce cross talk between them. (A ground line is not required on a multilayer board because it has a separate ground plane; however, it is helpful to separate the lines.) It is essential to minimize noise on the reference inputs because it couples through to the DAC output. Avoid crossover of digital and analog signals. Run traces on opposite sides of the board at right

angles to each other to reduce the effects of feedthrough on the board. A microstrip technique is recommended but not always possible with a double-sided board. In this technique, the component side of the board is dedicated to the ground plane, and the signal traces are placed on the solder side.

GALVANICALLY ISOLATED INTERFACE

In many process control applications, it is necessary to provide an isolation barrier between the controller and the unit being controlled to protect and isolate the controlling circuitry from any hazardous common-mode voltages that may occur. Isocouplers provide voltage isolation in excess of 2.5 kV. The serial loading structure of the AD5764R makes it ideal for isolated interfaces because the number of interface lines is kept to a minimum. Figure 44 shows a 4-channel isolated interface to the

AD5764R using an ADuM1400 iCoupler® product. For more

information on iCoupler products, refer to www.analog.com.

MICROPROCESSOR INTERFACING

Microprocessor interfacing to the AD5764R is accomplished via a serial bus that uses standard protocol that is compatible with microcontrollers and DSP processors. The communication channel is a 3-wire (minimum) interface consisting of a clock signal, a data signal, and a synchronization signal. The AD5764R requires a 24-bit data-word with data valid on the falling edge of SCLK.

For all the interfaces, a DAC output update can be performed automatically when all the data is clocked in, or it can be done under the control of LDAC. The contents of the DAC register can be read using the readback function.

Figure 44. Isolated Interface

Rev. D | Page 30 of 32

Data Sheet AD5764R

EVALUATION BOARD

The AD5764R comes with a full evaluation board to help designers evaluate the high performance of the part with a minimum of effort. All that is required to run the evaluation board is a power supply and a PC. The AD5764R evaluation kit includes a populated, tested AD5764R PCB. The evaluation board interfaces to

the USB interface of the PC. Software that allows easy programming of the AD5764R is available with the evaluation board. The software runs on any PC that has Microsoft® Windows® 2000/XP installed.

Rev. D | Page 31 of 32

AD5764R Data Sheet

COMPLIANT TO JEDEC STANDARDS MS-026-AB A

0.45

0.37

0.30

0.80 BSC

LEAD PITCH

7.00

BSC SQ

9.00 BSC SQ

1.20

MAX

0.75

0.60

0.45

1.05

1.00

0.95

0.20

0.09

0.08 MAX COPLANARITY

SEATING PLANE

0° MIN

7°

3.5° 0°

0.15

0.05

VIEW A

ROTATED 90° CCW

VIEW A

PIN 1

TOP VIEW

(PINS DO W N)

020607-A

AD5764RBSUZ

Quad 16-Bit DAC

±2 LSB Max

−40°C to +85°C

+5 V

32-Lead TQFP

SU-32-2

OUTLINE DIMENSIONS

Figure 45. 32-Lead Thin Plastic Quad Flat Package [TQFP]

(SU-32-2)

Dimensions shown in millimeters

ORDERING GUIDE

Temperature

Model1 Function INL

Range

AD5764RBSUZ-REEL7 Quad 16-Bit DAC ±2 LSB Max −40°C to +85°C +5 V 32-Lead TQFP SU-32-2 AD5764RCSUZ Quad 16-Bit DAC ±1 LSB Max −40°C to +85°C +5 V 32-Lead TQFP SU-32-2 AD5764RCSUZ-REEL7 Quad 16-Bit DAC ±1 LSB Max −40°C to +85°C +5 V 32-Lead TQFP SU-32-2 EVAL-AD5764REBZ Evaluation Board

Z = RoHS Compliant Part.

Internal Reference

Package Description

Package Option

registered trademarks are the property of their respective owners. D06064-0-10/11(D)

Rev. D | Page 32 of 32

ANALOG DEVICES AD5764R Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

REVISION HISTORY

FUNCTIONAL BLOCK DIAGRAM

SPECIFICATIONS

AC PERFORMANCE CHARACTERISTICS

TIMING CHARACTERISTICS

Timing Diagrams

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

TERMINOLOGY

THEORY OF OPERATION

DAC ARCHITECTURE

REFERENCE BUFFERS

SERIAL INTERFACE

Input Shift Register

Standalone Operation

Daisy-Chain Operation

Readback Operation

Individual DAC Updating

Simultaneous Updating of All DACs

TRANSFER FUNCTION

REGISTERS

FUNCTION REGISTER

DATA REGISTER

COARSE GAIN REGISTER

FINE GAIN REGISTER

OFFSET REGISTER

OFFSET AND GAIN ADJUSTMENT WORKED EXAMPLE

Removing Offset Error

Removing Gain Error

DESIGN FEATURES

ANALOG OUTPUT CONTROL

DIGITAL OFFSET AND GAIN CONTROL

PROGRAMMABLE SHORT-CIRCUIT PROTECTION

DIGITAL I/O PORT

DIE TEMPERATURE SENSOR

LOCAL GROUND OFFSET ADJUST

APPLICATIONS INFORMATION

TYPICAL OPERATING CIRCUIT

Precision Voltage Reference Selection

LAYOUT GUIDELINES

GALVANICALLY ISOLATED INTERFACE

MICROPROCESSOR INTERFACING

EVALUATION BOARD

OUTLINE DIMENSIONS

ORDERING GUIDE