ANALOG DEVICES AD5764R Service Manual

Complete Quad, 16-Bit, High Accuracy,

Serial Input, Bipolar Voltage Output DAC

Data Sheet

FEATURES

Complete quad, 16-bit digital-to-analog converter (DAC)
Programmable output range: ±10 V, ±10.2564 V, or ±10.5263 V
±1 LSB maximum INL error, ±1 LSB maximum DNL error
Low noise: 60 nV/√Hz
Settling time: 10 μs maximum
Integrated reference buffers
Internal reference: 10 ppm/°C maximum
On-chip die temperature sensor
Output control during power-up/brownout
Programmable short-circuit protection
Simultaneous updating via
Asynchronous
Digital offset and gain adjust
Logic output control pins
DSP-/microcontroller-compatible serial interface
Temperature range: −40°C to +85°C
iCMOS process technology

to zero code

CLR

APPLICATIONS

Industrial automation
Open-loop/closed-loop servo control
Process control
Data acquisition systems
Automatic test equipment
Automotive test and measurement
High accuracy instrumentation

LDAC

AD5764R

GENERAL DESCRIPTION

The AD5764R is a quad, 16-bit, serial input, bipolar voltage output
DAC that operates from supply voltages of ±11.4 V to ±16.5 V.
Nominal full-scale output range is ±10 V. The AD5764R provides
integrated output amplifiers, reference buffers, and proprietary
power-up/power-down control circuitry. The part also features
a digital I/O port, programmed via the serial interface, and an
analog temperature sensor. The part incorporates digital offset
and gain adjust registers per channel.

The AD5764R is a high performance converter that provides
guaranteed monotonicity, integral nonlinearity (INL) of ±1 LSB,
low noise, and 10 μs settling time. The AD5764R includes an
on-chip 5 V reference with a reference temperature coefficient
of 10 ppm/°C maximum. During power-up when the supply
voltages are changing, VOUTx is clamped to 0 V via a low
impedance path.

The AD5764R is based on the iCMOS® technology platform,
which is designed for analog systems designers within industrial/
instrumentation equipment OEMs who need high performance
ICs at higher voltage levels. iCMOS enables the development of
analog ICs capable of 30 V and operation at ±15 V supplies, while
allowing reductions in power consumption and package size,
coupled with increased ac and dc performance.

The AD5764R uses a serial interface that operates at clock rates
of up to 30 MHz and is compatible with DSP and microcontroller
interface standards. Double buffering allows the simultaneous
updating of all DACs. The input coding is programmable to either
twos complement or offset binary formats. The asynchronous clear
function clears all data registers to either bipolar zero or zero scale,
depending on the coding used. The AD5764R is ideal for both
closed-loop servo control and open-loop control applications.
The AD5764R is available in a 32-lead TQFP and offers
guaranteed specifications over the −40°C to +85°C industrial
temperature range (see Figure 1 for the functional block
diagram).

Rev. D

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

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Tel: [phone] www.analog.com
Fax: [phone] ©2008–2011 Analog Devices, Inc. All rights reserved.

AD5764R Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Functional Block Diagram .............................................................. 3

Specifications ..................................................................................... 4

AC Performance Characteristics ................................................ 6

Timing Characteristics ................................................................ 7

Absolute Maximum Ratings .......................................................... 10

Thermal Resistance .................................................................... 10

ESD Caution ................................................................................ 10

Pin Configuration and Function Descriptions ........................... 11

Typical Performance Characteristics ........................................... 13

Terminology .................................................................................... 19

Theory of Operation ...................................................................... 21

DAC Architecture ....................................................................... 21

Reference Buffers ........................................................................ 21

Serial Interface ............................................................................ 21

Simultaneous Updating via

Transfer Function ....................................................................... 23

Asynchronous Clear (

Registers ........................................................................................... 24

LDAC

........................................... 22

CLR

) ....................................................... 23

Function Register ....................................................................... 24

Data Register ............................................................................... 25

Coarse Gain Register ................................................................. 25

Fine Gain Register ...................................................................... 25

Offset Register ............................................................................ 26

Offset and Gain Adjustment Worked Example ...................... 26

Design Features ............................................................................... 27

Analog Output Control ............................................................. 27

Digital Offset and Gain Control ............................................... 27

Programmable Short-Circuit Protection ................................ 27

Digital I/O Port ........................................................................... 27

Die Temperature Sensor ............................................................ 27

Local Ground Offset Adjust ...................................................... 27

Applications Information .............................................................. 28

Typical Operating Circuit ......................................................... 28

Layout Guidelines ........................................................................... 30

Galvanically Isolated Interface ................................................. 30

Microprocessor Interfacing ....................................................... 30

Evaluation Board ........................................................................ 31

Outline Dimensions ....................................................................... 32

Ordering Guide .......................................................................... 32

REVISION HISTORY

10/11—Rev. C to Re v. D

Changed 50 MHz to 30 MHz ....................................... Throughout

Changes to t

7/11—Rev. B t o R e v. C

Changed 30 MHz to 50 MHz Throughout.................................... 1

Changes to t

8/09—Rev. A to Re v. B

Deleted Endnote 1 in Table 1 .......................................................... 4

Deleted Endnote 1 in Table 2 .......................................................... 6

Deleted Endnote 1 and Changes t

Changes to Ordering Guide .......................................................... 32

, t2, and t3 Parameters, Table 3 .................................. 7

1

, t2, and t3 Parameters, Table 3 .................................. 7

1

Parameter i n Tab l e 3 ............ 7

6

Rev. D | Page 2 of 32

2/09—Rev. 0 to R e v. A

Changes to Table 1 Tes t Conditions/Comments and

Added Endnote to Ta ble 1 ................................................................ 4

Added Endnote to Table 2 ................................................................ 6

Added Endnote to Table 3 ................................................................ 7

10/08—Revision 0: Initial Version

Data Sheet AD5764R

INPUT
REG C

GAIN REG C

OFFSET REG C

DATA

REG C

16

DAC C

INPUT
REG D

GAIN REG D

OFFSET REG D

DATA

REG D

16

DAC D

G1

G2

INPUT
REG B

GAIN REG B

OFFSET REG B

DATA

REG B

16

DAC B

INPUT
REG A

GAIN REG A

OFFSET REG A

DATA

5V

REFERENCE

REG A

16

16

DAC A

LDAC REFCD

RSTINRSTOUT

REFABREFGND

AGNDD

VOUTD

AGNDC

VOUTC

AGNDB

VOUTB

AGNDA

VOUTA

ISCC

REFERENCE

BUFFERS

SDIN
SCLK
SYNC

SDO

D0

D1

BIN/2sCOMP

CLR

PGND

DV

CC

DGND

G1

G2

G1

G2

G1

G2

AV

DD

AVSSAV

DD

INPUT
SHIFT

REGISTER

AND

CONTROL

LOGIC

VOLTAGE
MONITOR

AND

CONTROL

REFERENCE

BUFFERS

TEMP

SENSOR

TEMP

AV

SS

REFOUT

AD5764R

06064-001

FUNCTIONAL BLOCK DIAGRAM

Figure 1.

Rev. D | Page 3 of 32

AD5764R Data Sheet

ACCURACY

Outputs unloaded

Zero-Scale Tempco2

±2

±2

ppm FSR/°C max

Power Supply Sensitivity2

300

300

µV/V typ

Load Current

±1

±1

mA max

For specified performance

SPECIFICATIONS

AVDD = 11.4 V to 16.5 V, AVSS = −11.4 V to −16.5 V, AGND = DGND = REFGND = PGND = 0 V; REFAB = REFCD = 5 V external;
DV

= 2.7 V to 5.25 V, R

CC

Table 1.

Parameter B Grade1 C Grade1 Unit Test Conditions/Comments

Resolution 16 16 Bits
Relative Accuracy (INL) ±2 ±1 LSB max
Differential Nonlinearity (DNL) ±1 ±1 LSB max Guaranteed monotonic
Bipolar Zero Error ±2 ±2 mV max

±3 ±3 mV max
Bipolar Zero Tempco2 ±2 ±2 ppm FSR/°C max
Zero-Scale Error ±2 ±2 mV max

±2.5 ±2.5 mV max

Gain Error ±0.02 ±0.02 % FSR max
Gain Tempco2 ±2 ±2 ppm FSR/°C max
DC Crosstalk2 0.5 0.5 LSB max

REFERENCE INPUT/OUTPUT

Reference Input2

Reference Input Voltage 5 5 V nominal ±1% for specified performance
DC Input Impedance 1 1 MΩ min Typically 100 MΩ
Input Current ±10 ±10 µA max Typically ±30 nA
Reference Range 1/7 1/7 V min/V max

Reference Output

Output Voltage 4.995/5.005 4.995/5.005 V min/V max At 25°C, AVDD/AVSS = ±13.5 V
Reference Tempco2 ±10 ±10 ppm/°C max Typically 1.7ppm/°C

2

R

1 1 MΩ min

LOAD

= 10 kΩ, CL = 200 pF. All specifications T

LOAD

MIN

to T

, unless otherwise noted.

MAX

25°C; error at other temperatures obtained
using bipolar zero tempco

25°C; error at other temperatures obtained
using zero-scale tempco

Output Noise2 18 18 µV p-p typ 0.1 Hz to 10 Hz
Noise Spectral Density2 75 75 nV/√Hz typ At 10 kHz
Output Voltage Drift vs. Time2 ±40 ±40 ppm/500 hr typ
±50 ±50 ppm/1000 hr typ
Thermal Hysteresis2 70 70 ppm typ First temperature cycle
30 30 ppm typ Subsequent temperature cycles

OUTPUT CHARACTERISTICS2

Output Voltage Range3 ±10.5263 ±10.5263 V min/V max AVDD/AVSS = ±11.4 V, V
±14 ±14 V min/V max AVDD/AVSS = ±16.5 V, V
Output Voltage Drift vs. Time ±13 ±13 ppm FSR/500 hr typ
±15 ±15

ppm FSR/1000 hr

typ

Short-Circuit Current 10 10 mA typ R

= 6 kΩ, see Figure 31

ISCC

Capacitive Load Stability

R

= ∞ 200 200 pF max

LOAD

R

= 10 kΩ 1000 1000 pF max

LOAD

DC Output Impedance 0.3 0.3 Ω max

Rev. D | Page 4 of 32

REFIN

REFIN

= 5 V
= 7 V

Data Sheet AD5764R

Pin Capacitance

10

10

pF max

Per pin

Output High Voltage

DVCC − 1

DVCC − 1

V min

DVCC = 5 V ± 5%, sourcing 200 µA

High Impedance Output Capacitance

5

5

pF typ

SDO only

∆V

/∆ΑVDD

−85

−85

dB typ

Parameter B Grade1 C Grade1 Unit Test Conditions/Comments

DIGITAL INPUTS2 DVCC = 2.7 V to 5.25 V

Input High Voltage, VIH 2.4 2.4 V min
Input Low Voltage, VIL 0.8 0.8 V max
Input Current ±1.2 ±1.2 µA max Per pin

DIGITAL OUTPUTS (D0, D1, SDO)2

Output Low Voltage 0.4 0.4 V max DVCC = 5 V ± 5%, sinking 200 µA

Output Low Voltage 0.4 0.4 V max

= 2.7 V to 3.6 V,

DV

CC

sinking 200 µA

Output High Voltage DVCC − 0.5 DVCC − 0.5 V min

= 2.7 V to 3.6 V,

DV

CC

sourcing 200 µA

High Impedance Leakage Current ±1 ±1 µA max SDO only

DIE TEMPERATURE SENSOR2

Output Voltage at 25°C 1.47 1.47 V typ Die temperature
Output Voltage Scale Factor 5 5 mV/°C typ
Output Voltage Range 1.175/1.9 1.175/1.9 V min/V max −40°C to +105°C
Output Load Current 200 200 µA max Current source only
Power-On Time 10 10 ms typ

POWER REQUIREMENTS

AVDD/AVSS 11.4/16.5 11.4/16.5 V min/V max
DVCC 2.7/5.25 2.7/5.25 V min/V max
Power Supply Sensitivity

OUT

2

AIDD 3.55 3.55 mA/channel max Outputs unloaded

AISS 2.8 2.8 mA/channel max Outputs unloaded
DICC 1.2 1.2 mA max VIH = DVCC, VIL = DGND, 750 µA typ
Power Dissipation 275 275 mW typ ±12 V operation output unloaded

1

Temperature range: −40°C to +85°C; typical at +25°C. Device functionality is guaranteed to +105°C with degraded performance.

2

Guaranteed by design and characterization; not production tested.

3

Output amplifier headroom requirement is 1.4 V minimum.

Rev. D | Page 5 of 32

AD5764R Data Sheet

Slew Rate

5

5

V/µs typ

Digital Feedthrough

2

2

nV-sec typ

Effect of input bus activity on DAC outputs

AC PERFORMANCE CHARACTERISTICS

AVDD = 11.4 V to 16.5 V, AVSS = −11.4 V to −16.5 V, AGND = DGND = REFGND = PGND = 0 V; REFAB = REFCD = 5 V external;
DV

= 2.7 V to 5.25 V, R

CC

Table 2.

Parameter B Grade C Grade Unit Test Conditions/Comments

DYNAMIC PERFORMANCE1

Output Voltage Settling Time 8 8 µs typ Full-scale step to ±1 LSB
10 10 µs max
2 2 µs typ 512 LSB step settling

Digital-to-Analog Glitch Energy 8 8 nV-sec typ

Glitch Impulse Peak Amplitude 25 25 mV max

Channel-to-Channel Isolation 80 80 dB typ

DAC-to-DAC Crosstalk 8 8 nV-sec typ

Digital Crosstalk 2 2 nV-sec typ

Output Noise (0.1 Hz to 10 Hz) 0.1 0.1 LSB p-p typ

Output Noise (0.1 Hz to 100 kHz) 45 45 µV rms max

1/f Corner Frequency 1 1 kHz typ

Output Noise Spectral Density 60 60 nV/√Hz typ Measured at 10 kHz

Complete System Output Noise Spectral Density2 80 80 nV/√Hz typ Measured at 10 kHz

1

Guaranteed by design and characterization; not production tested.

2

Includes noise contributions from integrated reference buffers, a 16-bit DAC, and an output amplifier.

= 10 kΩ, CL = 200 pF. All specifications T

LOAD

MIN

to T

, unless otherwise noted.

MAX

Rev. D | Page 6 of 32

Data Sheet AD5764R

t10

10

ns min

TIMING CHARACTERISTICS

AVDD = 11.4 V to 16.5 V, AVSS = −11.4 V to −16.5 V, AGND = DGND = REFGND = PGND = 0 V; REFAB = REFCD = 5 V external;
DV

= 2.7 V to 5.25 V, R

CC

= 10 kΩ, CL = 200 pF. All specifications T

LOAD

MIN

to T

, unless otherwise noted.

MAX

Table 3.

Parameter

1, 2, 3

Limit at T

MIN

, T

Unit Description

MAX

t1 33 ns min SCLK cycle time
t2 13 ns min SCLK high time
t3 13 ns min SCLK low time
t4 13 ns min

4

t

13 ns min

5

t6 90 ns min

SYNC falling edge to SCLK falling edge setup time

th

SCLK falling edge to SYNC rising edge

24
Minimum

SYNC high time
t7 2 ns min Data setup time
t8 5 ns min Data hold time
t9 1.7 µs min
480 ns min

SYNC rising edge to LDAC falling edge (all DACs updated)
SYNC rising edge to LDAC falling edge (single DAC updated)
LDAC pulse width low

t11 500 ns max

LDAC falling edge to DAC output response time
t12 10 µs max DAC output settling time
t13 10 ns min
t14 2 µs max

5, 6

t

25 ns max SCLK rising edge to SDO valid

15

t16 13 ns min
t17 2 µs max
t18 170 ns min

1

Guaranteed by design and characterization; not production tested.

2

All input signals are specified with tR = tF = 5 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V.

3

See Figure 2, Figure 3, and Figure 4.

4

Standalone mode only.

5

Measured with the load circuit of Figure 5.

6

Daisy-chain mode only.

CLR pulse width low

CLR pulse activation time

SYNC rising edge to SCLK falling edge

SYNC rising edge to DAC output response time (LDAC = 0)

LDAC falling edge to SYNC rising edge

Rev. D | Page 7 of 32

AD5764R Data Sheet

DB23

SCLK

SYNC

SDIN

LDAC

LDAC = 0

CLR

1 2 24

DB0

t

1

VOUTx

VOUTx

VOUTx

t

4

t

6

t

3

t

2

t

5

t

8

t

7

t

10

t

9

t

10

t

11

t

12

t

12

t

17

t

18

t

13

t

14

06064-002

LDAC

SDO

SDIN

SYNC

SCLK

24 48

DB23 DB0 DB23 DB0

DB23

INPUT WORD FOR DAC NUNDEFINED

INPUT WORD FOR DAC N – 1INPUT WORD FOR DAC N

DB0

t

1

t

2

t

3

t

4

t

6

t

7

t

8

t

15

t

16

t

5

t

10

t

9

06064-003

Timing Diagrams

Figure 2. Serial Interface Timing Diagram

Figure 3. Daisy-Chain Timing Diagram

Rev. D | Page 8 of 32

Data Sheet AD5764R

SDO

SDIN

SYNC

SCLK

24 48

DB23 DB0 DB23 DB0

DB23

UNDEFINED

NOP CONDITION

DB0

INPUT WORD SPECIFIES

REGIST E R TO BE READ

SELECTED REGISTER DATA

CLOCKED OUT

06064-004

200µA I

OL

200µA I

OH

V

OH

(MIN) OR

V

OL

(MAX)

TO OUTPUT

PIN

C

L

50pF

06064-005

Figure 4. Readback Timing Diagram

Figure 5. Load Circuit for SDO Timing Diagram

Rev. D | Page 9 of 32

AD5764R Data Sheet

AVDD to AGND, DGND

−0.3 V to +17 V

Operating Temperature Range

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted. Transient currents of up to
100 mA do not cause SCR latch-up.

Table 4.

Parameter Rating

AVSS to AGND, DGND +0.3 V to −17 V
DVCC to DGND −0.3 V to +7 V
Digital Inputs to DGND

Digital Outputs to DGND −0.3 V to DVCC + 0.3 V
REFAB, REFCD to AGND, PGND −0.3 V to AVDD + 0.3 V
REFOUT to AGND AVSS to AVDD
TEMP AVSS to AVDD
VOUTx to AGND AVSS to AVDD
AGND to DGND −0.3 V to +0.3 V

Industrial −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Junction Temperature (TJ max) 150°C
Lead Temperature (Soldering) JEDEC industry standard
J-STD-020

−0.3 V to (DV
whichever is less

+ 0.3 V) or +7 V,

CC

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.

Table 5. Thermal Resistance

Package Type θJA θJC Unit

32-Lead TQFP 65 12 °C/W

ESD CAUTION

Rev. D | Page 10 of 32