ANALOG DEVICES AD5757 Service Manual
Quad Channel, 16-Bit,
A
Serial Input, 4 mA to 20 mA Output DAC,
Dynamic Power Control, HART Connectivity
Data Sheet
FEATURES
16-bit resolution and monotonicity
Dynamic power control for thermal management
or external PMOS mode
Current output ranges: 0 mA to 20 mA, 4 mA to 20 mA,
or 0 mA to 24 mA
±0.05% total unadjusted error (TUE) maximum
User programmable offset and gain
On-chip diagnostics
On-chip reference (±10 ppm/°C maximum)
−40°C to +105°C temperature range
APPLICATIONS
Process control
Actuator control
PLCs
HART network connectivity
GENERAL DESCRIPTION
The AD5757 is a quad, current output DAC that operates with a
power supply range from 10.8 V to 33 V. On-chip dynamic
power control minimizes package power dissipation by regulating the voltage on the output driver from 7.4 V to 29.5 V using
AD5757
a dc-to-dc boost converter optimized for minimum on-chip
power dissipation.
Each channel has a corresponding CHART pin so that HART
signals can be coupled onto the current output of the AD5757.
The part uses a versatile 3-wire serial interface that operates at
clock rates of up to 30 MHz and is compatible with standard
SPI, QSPI™, MICROWIRE™, DSP, and microcontroller interface
standards. The interface also features optional CRC-8 packet
error checking, as well as a watchdog timer that monitors
activity on the interface.
PRODUCT HIGHLIGHTS
1. Dynamic power control for thermal management.
2. 16-bit performance.
3. Multichannel.
4. HART compliant.
COMPANION PRODUCTS
Product Family: AD5755-1, AD5755
External References: ADR445, ADR02
Digital Isolators: ADuM1410, ADuM1411
Power: ADP2302, ADP2303
Additional companion products on the AD5757 product page
FUNCTIONAL BLOCK DIAGRAM
AV
DD
+15V
AGND
DV
DD
DGND
LDAC
SCLK
SDIN
SYNC
SDO
CLEAR
FAULT
ALERT
AD1
AD0
REFOUT
REFIN
NOTES
1. x = A, B, C, AND D.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
DIGIT AL
INTERFACE
REFERENCE
AD5757
GAIN REG A
OFFSET REG A
DAC CHANNEL A
DAC CHANNEL B
DAC CHANNEL C
DAC CHANNEL D
V
CC
5.0V
SW
DC-TO-DC
CONVERTER
+
DAC A
V
x
CURRENT AND
OUTPUT RANGE
BOOST_x
7.4V TO 29.5V
VOLTAGE
SCALING
I
OUT_x
R
SET_x
CHARTx
09225-101
Figure 1.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2011 Analog Devices, Inc. All rights reserved.
AD5757 Data Sheet
TABLE OF CONTENTS
Features.............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Companion Products....................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 3
Detailed Functional Block Diagram .............................................. 4
Specifications..................................................................................... 5
AC Performance Characteristics ................................................ 7
Timing Characteristics ................................................................ 7
Absolute Maximum Ratings.......................................................... 10
ESD Caution................................................................................ 10
Pin Configuration and Function Descriptions........................... 11
Typical Performance Characteristics ........................................... 14
Current Outputs ......................................................................... 14
DC-to-DC Block......................................................................... 19
Reference ..................................................................................... 20
General......................................................................................... 21
Terminology .................................................................................... 22
Theory of Operation ...................................................................... 23
DAC Architecture....................................................................... 23
Power-On State of the AD5757 ................................................23
Serial Interface ............................................................................ 23
Transfer Function....................................................................... 24
Registers........................................................................................... 25
Programming Sequence to Write/Enable the Output
Correctly ...................................................................................... 26
Changing and Reprogramming the Range ............................. 26
Data Registers ............................................................................. 27
Control Registers........................................................................ 29
Readback Operation .................................................................. 32
Device Features............................................................................... 34
Output Fault................................................................................ 34
Digital Offset and Gain Control............................................... 34
Status Readback During a Write .............................................. 34
Asynchronous Clear................................................................... 34
Packet Error Checking............................................................... 34
Watchdog Timer......................................................................... 35
Output Alert................................................................................ 35
Internal Reference...................................................................... 35
External Current Setting Resistor ............................................ 35
HART........................................................................................... 35
Digital Slew Rate Control.......................................................... 36
Power Dissipation Control........................................................ 36
DC-to-DC Converters............................................................... 36
AICC Supply Requirements—Static .......................................... 38
AICC Supply Requirements—Slewing ...................................... 38
External PMOS Mode................................................................ 39
Applications Information.............................................................. 40
Current Output Mode with Internal R
Precision Voltage Reference Selection..................................... 40
Driving Inductive Loads............................................................ 40
Transient Voltage Protection .................................................... 41
Microprocessor Interfacing....................................................... 41
Layout Guidelines....................................................................... 41
Galvanically Isolated Interface ................................................. 42
Outline Dimensions....................................................................... 43
Ordering Guide .......................................................................... 43
................................ 40
SET
Rev. B | Page 2 of 44
Data Sheet AD5757
REVISION HISTORY
11/11—Rev. A to Rev. B
Change to Test Conditions/Comments of Accuracy (External
R
) Parameter, Table 1....................................................................5
SET
Changes to Figure 4...........................................................................8
Changes to Figure 5...........................................................................9
Change to Pin 8 Description, Table 5 ...........................................11
Change to Figure 13........................................................................14
Change to Figure 20........................................................................16
Changes to Figure 48 and Power-On State of the AD5757
Section ..............................................................................................23
Change to Table 16 ..........................................................................29
Changes to Readback Operation Section, Readback Example
Section, and Table 25 ......................................................................32
Change to Figure 54........................................................................35
Change to Figure 58 Caption.........................................................38
Changes to Figure 59, Figure 60, and Figure 61 Captions.........39
Changes to Transient Voltage Protection Section and
Figure 63...........................................................................................41
Changes to Galvanically Isolated Interface Section....................42
5/11—Rev. 0 to Rev. A
Changes Features Section.................................................................1
Changes to Figure 2 ..........................................................................3
Changed AV
Min Parameter from 10.8 V to 9 V......................5
DD
Changes to Pin 22, Pin31, Pin 49 Descriptions...........................11
Changes to Pin 58 Descriptions....................................................12
Changes to Figure 8, Figure 9, and Figure 10.............................. 13
Added Figure 23, Renumbered Sequentially...............................15
Added Figure 29..............................................................................16
Added External PMOS Mode Section and Figure 62.................38
4/11—Revision 0: Initial Version
Rev. B | Page 3 of 44
AD5757 Data Sheet
DETAILED FUNCTIONAL BLOCK DIAGRAM
AV
CC
5.0V
AV
+15V
DD
SW
V
A
BOOST_ A
AGND
DV
DGND
LDAC
CLEAR
SCLK
SYNC
FAULT
ALERT
REFOUT
REFIN
SDIN
SDO
AD1
AD0
DD
POWER-ON
RESET
INPUT
SHIFT
REGISTER
AND
CONTROL
STATUS
REGISTER
WATCHDOG
TIMER
(SPI ACTIVITY)
VREF
REFERENCE
BUFFERS
AD5757
16
INPUT
REG A
GAIN REG A
OFFSET REG A
DAC CHANNEL A
DAC CHANNEL B
DAC CHANNEL C
DAC CHANNEL D
DC-TO- DC
CONVERTER
V
POWER
CONTRO L
16
DAC
+
REG A
DAC A
SWB, SWC, SW
7.4V TO 29. 5V
R2 R3
R1
V
D
SEN1VSEN2
REG
BOOST_ B,VBOOST_C,VBOOST_ D
I
OUT_A
R
SET_A
CHARTA
I
, I
SET_B
OUT_C
, R
SET_C
, I
OUT_D
, R
SET_D
OUT_B
R
CHARTB, CHARTC, CHARTD
09225-001
Figure 2.
Rev. B | Page 4 of 44
Data Sheet AD5757
SPECIFICATIONS
AVDD = V
REFIN = 5 V; R
Table 1.
Parameter1 Min Typ Max Unit Test Conditions/Comments
CURRENT OUTPUT
Output Current Ranges 0 24 mA
0 20 mA
4 20 mA
Resolution 16 Bits
ACCURACY (EXTERNAL R
Total Unadjusted Error (TUE)
−0.05 ±0.009 +0.05 % FSR
TUE Long-Term Stability 100 ppm FSR Drift after 1000 hours, TJ = 150°C
Relative Accuracy (INL) −0.006 +0.006 % FSR
Differential Nonlinearity (DNL) −1 +1 LSB Guaranteed monotonic
Offset Error −0.05 ±0.005 +0.05 % FSR
Offset Error Drift2 ±4 ppm FSR/°C
Gain Error −0.05 ±0.004 +0.05 % FSR
Gain TC2 ±3 ppm FSR/°C
Full-Scale Error −0.05 ±0.008 +0.05 % FSR
Full-Scale TC2 ±5 ppm FSR/°C
DC Crosstalk 0.0005 % FSR External R
ACCURACY (INTERNAL R
Total Unadjusted Error (TUE)
−0.11 ±0.009 +0.11 % FSR TA = 25°C
TUE Long-Term Stability 180 ppm FSR Drift after 1000 hours, TJ = 150°C
Relative Accuracy (INL) −0.006 +0.006 % FSR
−0.004 +0.004 % FSR TA = 25°C
Differential Nonlinearity (DNL) −1 +1 LSB Guaranteed monotonic
Offset Error
−0.04 ±0.007 +0.04 % FSR TA = 25°C
Offset Error Drift2 ±6 ppm FSR/°C
Gain Error −0.12 +0.12 % FSR
−0.06 ±0.002 +0.06 % FSR TA = 25°C
Gain TC2 ±9 ppm FSR/°C
Full-Scale Error
−0.1 ±0.007 +0.1 % FSR TA = 25°C
Full-Scale TC2 ±14 ppm FSR/°C
DC Crosstalk4 −0.011 % FSR Internal R
OUTPUT CHARACTERISTICS2
Current Loop Compliance Voltage V
Output Current Drift vs. Time Drift after 1000 hours, ¾ scale output, TJ = 150°C
90 ppm FSR External R
140 ppm FSR Internal R
Resistive Load 1000 Ω The dc-to-dc converter has been characterized
Output Impedance 100 MΩ
DC PSRR 0.02 1 μA/V
REFERENCE INPUT/OUTPUT
Reference Input2
Reference Input Voltage 4.95 5 5.05 V For specified performance
DC Input Impedance 45 150 MΩ
= 15 V; DVDD = 2.7 V to 5.5 V; AVCC = 4.5 V to 5.5 V; dc-to-dc converter disabled; AGND = DGND = GNDSWx = 0 V;
BOOST_x
= 300 Ω; all specifications T
L
)
SET
MIN
to T
, unless otherwise noted.
MAX
Assumes ideal resistor; see the External Current
Setting Resistor section for more information
SET
)
SET
3, 4
−0.14 +0.14 % FSR
3, 4
−0.05 +0.05 % FSR
3, 4
−0.14 +0.14 % FSR
SET
−
V
−
BOOST_x
2.4
BOOST_x
2.7
V
SET
SET
with a maximum load of 1 kΩ, chosen such that
compliance is not exceeded; see Figure 31
DC-DC MaxV
bits in Table 24
and
Rev. B | Page 5 of 44
AD5757 Data Sheet
Parameter1 Min Typ Max Unit Test Conditions/Comments
Reference Output
Output Voltage 4.995 5 5.005 V TA = 25°C
Reference TC2 −10 ±5 +10 ppm/°C
Output Noise (0.1 Hz to 10 Hz)2 7 μV p-p
Noise Spectral Density2 100 nV/√Hz At 10 kHz
Output Voltage Drift vs. Time2 180 ppm Drift after 1000 hours, TJ = 150°C
Capacitive Load2 1000 nF
Load Current 9 mA
Short-Circuit Current 10 mA
Line Regulation2 3 ppm/V
Load Regulation2 95 ppm/mA
Thermal Hysteresis2 160 ppm First temperature cycle
5 ppm Second temperature cycle
DC-TO-DC
Switch
Switch On Resistance 0.425 Ω
Switch Leakage Current 10 nA
Peak Current Limit 0.8 A
Oscillator
Oscillator Frequency 11.5 13 14.5 MHz This oscillator is divided down to give the dc-to-dc
Maximum Duty Cycle 89.6 % At 410 kHz dc-to-dc switching frequency
DIGITAL INPUTS2 JEDEC compliant
VIH, Input High Voltage 2 V
VIL, Input Low Voltage 0.8 V
Input Current −1 +1 μA Per pin
Pin Capacitance 2.6 pF Per pin
DIGITAL OUTPUTS2
SDO, ALERT
VOL, Output Low Voltage 0.4 V Sinking 200 μA
VOH, Output High Voltage DVDD − 0.5 V Sourcing 200 μA
High Impedance Leakage Current −1 +1 μA
High Impedance Output
2.5 pF
Capacitance
FAULT
VOL, Output Low Voltage 0.4 V 10 kΩ pull-up resistor to DVDD
VOL, Output Low Voltage 0.6 V At 2.5 mA
VOH, Output High Voltage 3.6 V 10 kΩ pull-up resistor to DVDD
POWER REQUIREMENTS
AVDD 9 33 V
DVDD 2.7 5.5 V
AVCC 4.5 5.5 V
AIDD 7 7.5 mA
DICC 9.2 11 mA VIH = DVDD, VIL = DGND, internal oscillator running,
AICC 1 mA Over supplies
5
I
1 mA Per channel, current output mode, 0 mA output
BOOST
Power Dissipation 155 mW AVDD = 15 V, DVCC = 5 V, dc-to-dc converter enable,
1
Temperature range: −40°C to +105°C; typical at +25°C.
2
Guaranteed by design and characterization; not production tested.
3
For current outputs with internal R
loaded with the same code.
4
See the Current Output Mode with Internal R
5
Efficiency plots in Figure 33, Figure 34, Figure 35, and Figure 36 include the I
, the offset, full-scale, and TUE measurements exclude dc crosstalk. The measurements are made with all four channels enabled
SET
section for more explanation of the dc crosstalk.
SET
quiescent current.
BOOST
See Figure 42
See Figures 43
See Figure 42
converter switching frequency
over supplies
current output mode, outputs disabled
Rev. B | Page 6 of 44
Data Sheet AD5757
AC PERFORMANCE CHARACTERISTICS
AVDD = V
REFIN = 5 V; R
Table 2.
Parameter1 Min Typ Max Unit Test Conditions/Comments
DYNAMIC PERFORMANCE
Current Output
Output Current Settling Time 15 μs To 0.1% FSR (0 mA to 24 mA)
Output Noise (0.1 Hz to 10 Hz
Bandwidth)
Output Noise Spectral Density 0.5 nA/√Hz
1
Guaranteed by design and characterization; not production tested.
TIMING CHARACTERISTICS
AVDD = V
REFIN = 5 V; R
= 15 V; DVDD = 2.7 V to 5.5 V; AVCC = 4.5 V to 5.5 V; dc-to-dc converter disabled; AGND = DGND = GNDSWx = 0 V;
BOOST_x
= 300 Ω; all specifications T
L
MIN
to T
, unless otherwise noted.
MAX
See test conditions/
ms See Figure 26, Figure 27, and Figure 28
comments
0.15 LSB p-p 16-bit LSB, 0 mA to 24 mA range
Measured at 10 kHz, midscale output, 0
mA to 24 mA range
= 15 V; DVDD = 2.7 V to 5.5 V; AVCC = 4.5 V to 5.5 V; dc-to-dc converter disabled; AGND = DGND = GNDSWx = 0 V;
BOOST_x
= 300 Ω; all specifications T
L
MIN
to T
, unless otherwise noted.
MAX
Table 3.
Parameter
1, 2, 3
Limit at T
, T
Unit Description
MIN
MAX
t1 33 ns min SCLK cycle time
t2 13 ns min SCLK high time
t3 13 ns min SCLK low time
t4 13 ns min
t5 13 ns min
t6 198 ns min
falling edge to SCLK falling edge setup time
SYNC
th
/32nd SCLK falling edge to SYNC rising edge (see ) Figure 54
24
high time
SYNC
t7 5 ns min Data setup time
t8 5 ns min Data hold time
t9 20 μs min
rising edge to LDAC falling edge (all DACs updated or any channel has
SYNC
digital slew rate control enabled)
5 μs min
t10 10 ns min
t11 500 ns max
t12
See the AC Performance
μs max DAC output settling time
rising edge to LDAC falling edge (single DAC updated)
SYNC
pulse width low
LDAC
falling edge to DAC output response time
LDAC
Characteristics section
t13 10 ns min CLEAR high time
t14 5 μs max CLEAR activation time
t15 40 ns max SCLK rising edge to SDO valid
t16 21 μs min
5 μs min
t17 500 ns min
t18 800 ns min
4
t
20 μs min
19
5 μs min
rising edge to DAC output response time (LDAC = 0) (all DACs updated)
SYNC
rising edge to DAC output response time (LDAC = 0) (single DAC updated)
SYNC
falling edge to SYNC rising edge
LDAC
pulse width
RESET
high to next SYNC low (digital slew rate control enabled) (all DACs updated)
SYNC
high to next SYNC low (digital slew rate control disabled) (single DAC
SYNC
updated)
1
Guaranteed by design and characterization; not production tested.
2
All input signals are specified with t
3
See Figure 3, Figure 4, Figure 5, and Figure 6.
4
This specification applies if
LDAC
= t
= 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.2 V.
RISE
FALL
is held low during the write cycle; otherwise, see t9.
Rev. B | Page 7 of 44
AD5757 Data Sheet
Timing Diagrams
t
1
SCLK
SYNC
SDIN
LDAC
I
OUT_x
LDAC = 0
I
OUT_x
CLEAR
I
OUT_x
12 24
t
6
t
4
t
7
MSB
t
13
t
t
3
t
8
14
t
2
t
10
t
5
t
19
LSB
t
t
9
t
17
t
16
10
t
t
11
t
12
12
t
RESET
18
09225-002
Figure 3. Serial Interface Timing Diagram
SCLK
SYNC
SDIN
SDO
1 1
MSB MSBLSB LSB
INPUT WORD SPECIFIES
REGISTER TO BE READ
UNDEFINED SELECTED REGISTER DATA
24 24
t
6
NOP CONDITI ON
MSB LSB
t
15
CLOCKED OUT
Figure 4. Readback Timing Diagram
09225-003
Rev. B | Page 8 of 44
Data Sheet AD5757
SCLK
SYNC
SDIN
SDO
LSB MSB
12 16
DUT_
R/W
DUT_
AD1
SDO DISABLED
XXXD15D14 D1D0
AD0
SDO_
ENAB
STATUSSTATUSSTATUSSTATUS
09225-004
Figure 5. Status Readback During Write
TO OUTPUT
PIN
50pF
C
200µA I
L
200µA I
OL
OH
VOH (MIN) OR
(MAX)
V
OL
09225-005
Figure 6. Load Circuit for SDO Timing Diagram
Rev. B | Page 9 of 44
AD5757 Data Sheet
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted. Transient currents of up to
100 mA do not cause SCR latch-up.
Table 4.
Parameter Rating
AVDD, V
to AGND, DGND −0.3 V to +33 V
BOOST_x
AVCC to AGND −0.3 V to +7 V
DVDD to DGND −0.3 V to +7 V
Digital Inputs to DGND
−0.3 V to DV
+ 0.3 V or +7 V
DD
(whichever is less)
Digital Outputs to DGND
−0.3 V to DV
+ 0.3 V or +7 V
DD
(whichever is less)
REFIN, REFOUT to AGND
−0.3 V to AV
+ 0.3 V or +7 V
DD
(whichever is less)
I
OUT_x
to AGND
AGND to V
or 33 V if using
BOOST_x
the dc-to-dc circuitry
SWx to AGND −0.3 V to +33 V
AGND, GNDSWx to DGND −0.3 V to +0.3 V
Operating Temperature Range ( TA)
Industrial1 −40°C to +105°C
Storage Temperature Range −65°C to +150°C
Junction Temperature (TJ max) 125°C
64-Lead LFCSP
θJA Thermal Impedance2 20°C/W
Power Dissipation (TJ max – TA)/θJA
Lead Temperature JEDEC industry standard
Soldering J-STD-020
1
Power dissipated on chip must be derated to keep the junction temperature
below 125°C.
2
Based on a JEDEC 4-layer test board.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. B | Page 10 of 44
Data Sheet AD5757
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
DCDC_D
PIN 1
INDICATO R
SET_CRSET_D
R
REFOUT
REFINNCCHARTD
646362616059585756555453525150
BOOST_D
OUT_D
IGATED
COMP
V
NC
I
AGNDNCCHARTCNCIGATEC
49
R
1
SET_B
R
2
SET_A
REFGND
REFGND
NOTES
1. NC = NO CONNECT. DO NOT CONNECT TO T HIS PIN.
2. THE EXPOSED PAD SHOULD BE CONNECTED TO AGND, OR ALTERNATIVELY,
IT CAN BE LE FT EL ECTRICALLY UNCONNECT ED. IT IS RECOMMENDED THAT
THE PAD BE THE RMALLY CO NNECTED TO A COPPER PLANE FO R ENHANCED
THERMAL PE RFORMANCE.
AD0
AD1
SYNC
SCLK
SDIN
SDO
DV
DGND
LDAC
CLEAR
ALERT
FAULT
3
4
5
6
7
8
9
10
11
DD
12
13
14
15
16
171819202122232425262728293031
DGND
RESET
AV
DD
NC
AD5757
TOP VIEW
(Not to Scale)
NC
DCDC_A
IGATEA
BOOST_A
CHARTA
V
COMP
32
NC
NC
OUT_A
AGND
I
DCDC_B
IGATEB
CHARTB
COMP
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
COMP
I
OUT_C
V
BOOST_C
AV
CC
SW
C
GNDSW
GNDSW
SW
D
AGND
SW
A
GNDSW
GNDSW
SW
B
AGND
V
BOOST_B
I
OUT_B
DCDC_C
C
D
A
B
09225-006
Figure 7. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
1 R
SET_B
An external, precision, low drift 15 kΩ current setting resistor can be connected to this pin to improve the I
temperature drift performance. See the Device Features section.
2 R
SET_A
An external, precision, low drift 15 kΩ current setting resistor can be connected to this pin to improve the I
temperature drift performance. See the Device Features section.
3, 4 REFGND Ground Reference Point for Internal Reference.
5 AD0 Address Decode for the Device Under Test (DUT) on the Board.
6 AD1 Address Decode for the DUT on the Board.
7
Active Low Input. This is the frame synchronization signal for the serial interface. While SYNC is low, data is
SYNC
transferred in on the falling edge of SCLK.
8 SCLK
Serial Clock Input. Data is clocked into the input shift register on the falling edge of SCLK. This pin operates at
clock speeds of up to 30 MHz.
9 SDIN Serial Data Input. Data must be valid on the falling edge of SCLK.
10 SDO Serial Data Output. Used to clock data from the serial register in readback mode. See Figure 4 and Figure 5.
11 DVDD Digital Supply. The voltage range is from 2.7 V to 5.5 V.
12, 17 DGND Digital Ground.
13
Load DAC, Active Low Input. This is used to update the DAC register and consequently the DAC outputs. When
LDAC
tied permanently low, the addressed DAC data register is updated on the rising edge of SYNC. If LDAC is held
high during the write cycle, the DAC input register is updated, but the DAC output update only takes place at
14 CLEAR
the falling edge of LDAC
LDAC
pin must not be left unconnected.
Active High, Edge Sensitive Input. Asserting this pin sets the output current and voltage to the preprogrammed
(see ). Using this mode, all analog outputs can be updated simultaneously. The Figure 3
clear code bit setting. Only channels enabled to be cleared are cleared. See the Device Features section for more
information. When CLEAR is active, the DAC output register cannot be written to.
OUT_B
OUT_A
Rev. B | Page 11 of 44
AD5757 Data Sheet
Pin No. Mnemonic Description
15 ALERT
16
18
FAU LT
RESET
19 AVDD Positive Analog Supply. The voltage range is from 10.8 V to 33 V.
20, 25,
NC No Connect. Do not connect to this pin.
28, 30,
50, 52,
55, 60
21 CHARTA HART Input Connection for DAC Channel A.
22 IGATEA
23 COMP
24 V
26 I
DCDC_A
BOOST_A
Current Output Pin for DAC Channel A.
OUT_A
27, 40, 53 AGND Ground Reference Point for Analog Circuitry. This must be connected to 0 V.
29 CHARTB HART Input Connection for DAC Channel B.
31 IGATEB
32 COMP
33 I
34 V
DCDC_B
Current Output Pin for DAC Channel B.
OUT_B
BOOST_B
35 AGND Ground Reference Point for Analog Circuitry. This pin must be connected to 0 V.
36 SWB
37 GNDSWB Ground Connection for DC-to-DC Switching Circuit. This pin should always be connected to ground.
38 GNDSWA Ground Connection for DC-to-DC Switching Circuit. This pin should always be connected to ground.
39 SWA
41 SWD
42 GNDSWD Ground Connections for DC-to-DC Switching Circuit. This pin should always be connected to ground.
43 GNDSWC Ground Connections for DC-to-DC Switching Circuit. This pin should always be connected to ground.
44 SWC
45 AVCC Supply for DC-to-DC Circuitry.
46 V
47 I
48 COMP
BOOST_C
Current Output Pin for DAC Channel C.
OUT_C
DCDC_C
49 IGATEC
Active High Output. This pin is asserted when there has been no SPI activity on the interface pins for a
predetermined time. See the Device Features section for more information.
Active Low Output. This pin is asserted low when an open circuit in current mode is detected, a short circuit in
voltage mode is detected, a PEC error is detected, or an overtemperature is detected (see the Device Features
section). Open-drain output.
Hardware Reset. Active Low Input.
Optional Connection for External Pass Transistor. Should be left unconnected when using the dc-to-dc converter. See
the External PMOS Mode section for more information.
DC-to-DC Compensation Capacitor. Connect a 10 nF capacitor from this pin to ground. Used to regulate the
feedback loop of the Channel A dc-to-dc converter. Alternatively, if using an external compensation resistor,
place a resistor in series with a capacitor to ground from this pin (see the DC-to-DC Converter Compensation
Capacitors and the AICC Supply Requirements—Slewing sections in the Device Features section for more
information).
Supply for Channel A Current Output Stage (see Figure 49). To use the dc-to-dc feature of the device, connect as
shown in Figure 56.
Optional Connection for External Pass Transistor. Should be left unconnected when using the dc-to-dc converter.
See the External PMOS Mode section for more information.
DC-to-DC Compensation Capacitor. Connect a 10 nF capacitor from this pin to ground. Used to regulate the
feedback loop of the Channel B dc-to-dc converter. Alternatively, if using an external compensation resistor,
place a resistor in series with a capacitor to ground from this pin (see the DC-to-DC Converter Compensation
Capacitors and AI
Supply Requirements—Slewing sections in the Device Features section for more
CC
information).
Supply for Channel B Current Output Stage (see Figure 49). To use the dc-to-dc feature of the device, connect as
shown in Figure 56.
Switching Output for Channel B DC-to-DC Circuitry. To use the dc-to-dc feature of the device, connect as shown
in Figure 56.
Switching Output for Channel A DC-to-DC Circuitry. To use the dc-to-dc feature of the device, connect as shown
in Figure 56.
Switching Output for Channel D DC-to-DC Circuitry. To use the dc-to-dc feature of the device, connect as shown
in Figure 56.
Switching Output for Channel C DC-to-DC Circuitry. To use the dc-to-dc feature of the device, connect as shown
in Figure 56.
Supply for Channel C Current Output Stage (see Figure 49). To use the dc-to-dc feature of the device, connect as
shown in Figure 56.
DC-to-DC Compensation Capacitor. Connect a 10 nF capacitor from this pin to ground. Used to regulate the
feedback loop of the Channel C dc-to-dc converter. Alternatively, if using an external compensation resistor,
place a resistor in series with a capacitor to ground from this pin (see the DC-to-DC Converter Compensation
Capacitors and AICC Supply Requirements—Slewing sections in the Device Features section for more
information).
Optional Connection for External Pass Transistor. Should be left unconnected when using the dc-to-dc converter. See
the External PMOS Mode section for more information.
Rev. B | Page 12 of 44
Data Sheet AD5757
Pin No. Mnemonic Description
51 CHARTC HART Input Connection for DAC Channel C.
54 I
56 V
57 COMP
58 IGATED
59 CHARTD HART Input Connection for DAC Channel D.
61 REFIN External Reference Voltage Input.
62 REFOUT
63 R
64 R
EPAD
Current Output Pin for DAC Channel D.
OUT_D
BOOST_D
Supply for Channel D Current Output Stage (see Figure 49). To use the dc-to-dc feature of the device, connect as
shown in Figure 56.
DCDC_D
DC-to-DC Compensation Capacitor. Connect a 10 nF capacitor from this pin to ground. Used to regulate the
feedback loop of the Channel D dc-to-dc converter. Alternatively, if using an external compensation resistor,
place a resistor in series with a capacitor to ground from this pin (see the DC-to-DC Converter Compensation
Capacitors and AICC Supply Requirements—Slewing sections in the Device Features section for more
information).
Optional Connection for External Pass Transistor. Should be left unconnected when using the dc-to-dc converter.
See the External PMOS Mode section for more information.
Internal Reference Voltage Output. It is recommended to place a 0.1 μF capacitor between REFOUT and
REFGND.
SET_D
An external, precision, low drift 15 kΩ current setting resistor can be connected to this pin to improve the I
temperature drift performance. See the Device Features section.
SET_C
An external, precision, low drift 15 kΩ current setting resistor can be connected to this pin to improve the I
temperature drift performance. See the Device Features section.
Exposed Pad. This exposed pad should be connected to AGND, or, alternatively, it can be left electrically
unconnected. It is recommended that the pad be thermally connected to a copper plane for enhanced thermal
performance.
OUT_D
OUT_C
Rev. B | Page 13 of 44
AD5757 Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
CURRENT OUTPUTS
–0.0005
INL ERROR (%FSR)
–0.0010
–0.0015
–0.0020
–0.0025
0.0025
0.0020
0.0015
0.0010
0.0005
AVDD = 15V
T
= 25°C
A
0
4mA TO 20mA, EXTERNAL R
4mA TO 20mA, EXTERNAL R
4mA TO 20mA, INTERNAL R
4mA TO 20mA, INTERNAL R
4mA TO 20mA, EXTERNAL R
0 10000 20000 30000 40000 50000 60000
SET
, WIT H DC-TO-DC CO NVERTER
SET
SET
, WIT H DC-TO-DC CO NVERTER
SET
, EXTERNAL PM OS MODE
SET
CODE
Figure 8. Integral Nonlinearity vs. Code
09225-149
0.0010
0.0008
0.0006
0.0004
0.0002
–0.0002
INL ERROR (%FSR)
–0.0004
4mA TO 20mA RANGE MAX INL
0mA TO 24mA RANGE MAX INL
0mA TO 20mA RANGE MIN INL
0
0mA TO 20mA RANGE MAX INL
4mA TO 20mA RANGE MAX INL
0mA TO 24mA RANGE MIN INL
AVDD = 15V
–0.0006
–0.0008
–0.0010
–40 –20 0 20 40 60 80 100
TEMPERATURE (°C)
Figure 11. Integral Nonlinearity vs. Temperature, Internal R
09225-152
SET
1.0
4mA TO 20mA, EXTERNA L R
4mA TO 20mA, EXTERNA L R
0.8
4mA TO 20mA, INTERNAL R
4mA TO 20mA, INTERNAL R
0.6
4mA TO 20mA, EXTERNA L R
0.4
0.2
0
–0.2
DNL ERROR (LSB)
–0.4
–0.6
AVDD = 15V
–0.8
T
= 25°C
A
–1.0
0 10000 20000 30000 40000 50000 60000
SET
, WIT H DC-TO-DC CO NVERTER
SET
SET
, WIT H DC-TO-DC CO NVERTER
SET
, EXTERNAL PM OS MODE
SET
CODE
Figure 9. Differential Nonlinearity vs. Code
0.035
AVDD = 15V
T
= 25°C
0.030
A
ALL CHANNELS ENABLED
0.025
–0.005
TOTAL UNADJUSTED ERROR (%FSR)
–0.010
–0.015
0.020
0.015
0.010
0.005
4mA TO 20mA, EXTERNAL R
4mA TO 20mA, EXTERNAL R
4mA TO 20mA, INTERNAL R
4mA TO 20mA, INTERNAL R
4mA TO 20mA, EXTERNAL R
0
0 10000 20000 30000 40000 50000 60000
SET
, WIT H DC-TO-DC CO NVERTER
SET
SET
, WITH DC-TO-DC CO NVERTER
SET
, EXTERNAL PM OS MO DE
SET
CODE
Figure 10. Total Unadjusted Error vs. Code
0.0020
4mA TO 20mA RANGE MAX INL
0.0015
0.0010
0.0005
0
–0.0005
INL ERROR (%FSR)
–0.0010
–0.0015
–0.0020
–40 –20 0 20 40 60 80 100
09225-150
Figure 12. Integral Nonlinearity vs. Temperature, External R
1.0
AVDD = 15V
ALL RANGE S
0.8
INTERNAL AND EXTERNAL R
0.6
0mA TO 24mA RANGE MAX INL
0mA TO 20mA RANGE MI N INL
0mA TO 20mA RANGE MAX INL
4mA TO 20mA RANGE MI N INL
0mA TO 24mA RANGE MI N INL
AVDD = 15V
TEMPERATURE (°C)
SET
09225-153
SET
0.4
0.2
0
DNL ERROR M AX
DNL ERROR M IN
–0.2
DNL ERROR (LSB)
–0.4
–0.6
–0.8
–1.0
–40 –20 0 20 40 60 80 100
09225-151
TEMPERATURE (°C)
09225-154
Figure 13. Differential Nonlinearity vs. Temperature
Rev. B | Page 14 of 44
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