ANALOG DEVICES AD5755 Service Manual

Quad Channel, 16-Bit, Serial Input,

A

4 mA to 20 mA and Voltage Output DAC,

Dynamic Power Control

Data Sheet

FEATURES

16-bit resolution and monotonicity Dynamic power control for thermal management Current and voltage output pins connectable to a single

terminal

Current output ranges: 0 mA to 20 mA, 4 mA to 20 mA,

or 0 mA to 24 mA ±0.05% total unadjusted error (TUE) maximum

Voltage output ranges (with 20% overrange): 0 V to 5 V, 0 V

to 10 V, ±5 V, and ±10 V

±0.04% total unadjusted error (TUE) maximum User programmable offset and gain On-chip diagnostics On-chip reference (±10 ppm/°C maximum)

−40°C to +105°C temperature range

APPLICATIONS

Process control Actuator control PLCs

GENERAL DESCRIPTION

The AD5755 is a quad, voltage and current output DAC that operates with a power supply range from −26.4 V to +33 V.

AD5755

On-chip dynamic power control minimizes package power dissipation in current mode. This is achieved by regulating the voltage on the output driver from 7.4 V to 29.5 V using a dc-todc boost converter optimized for minimum on chip power dissipation.

The part uses a versatile 3-wire serial interface that operates at clock rates of up to 30 MHz and is compatible with standard SPI, QSPI™, MICROWIRE™, DSP, and microcontroller interface standards. The interface also features optional CRC-8 packet error checking, as well as a watchdog timer that monitors activity on the interface.

PRODUCT HIGHLIGHTS

1. Dynamic power control for thermal management.

2. 16-bit performance.

3. Multichannel.

COMPANION PRODUCTS

Product Family: AD5755-1, AD5757 External References: ADR445, ADR02 Digital Isolators: ADuM1410, ADuM1411 Power: ADP2302, ADP2303

Additional companion products on the AD5755 product page

FUNCTIONAL BLOCK DIAGRAM

AV

SS

–15V AG ND

DV

DD

DGND

LDAC

SCLK

SDIN

SYNC

SDO

CLEAR

FAU LT

ALERT

AD1

AD0

REFOUT

REFIN

DIGITAL

INTERFACE

REFERENCE

AD5755

NOTES

1. x = A, B, C, AND D.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

AV

+15V

DD

GAIN REG A

OFFSET REG A

DAC CHANNEL A

DAC CHANNEL B

DAC CHANNEL C

DAC CHANNEL D

V

CC

5.0V

SW

DC-TO-DC

CONVERTER

+

DAC A

V

x

CURRENT AND

OUTPUT RANGE

BOOST_x

7.4V TO 29.5V

VOLTAGE

SCALING

I

OUT_x

R

SET_x

+V

V

OUT_x

–V

SENSE_x

07304-100

Figure 1.

AD5755 Data Sheet

REVISION HISTORY

11/11—Rev. 0 to Rev. A

Changes to Figure 2...........................................................................4

Changes to Table 1 ............................................................................5

Added Timing Diagram heading and changes to Figure 5........10

Changes to Figure 6.........................................................................11

Changes to Table 5 ..........................................................................13

Changes to Figure 13 ......................................................................16

Changes to Figure 21 ......................................................................18

Changes to Figure 37 ......................................................................20

Changes to Figure 44 ......................................................................22

Changes to Figure 56 and Figure 58 .............................................24

Changes to Figure 71 ......................................................................29

Changes to Power-On State of AD5575 Section.........................29

Changes to Table 17........................................................................35

Changes to Readback Operation Section and changes to

Table 26.............................................................................................38

Changes to Voltage Output Short-Circuit Protection Section..40

Changes to Figure 78 ......................................................................41

Changes to Figure 81 through Figure 84 Captions.....................44

Changes to Transient Voltage Protection Section and changes to

Figure 85...........................................................................................47

Changes to Galvanically Isolated Interface Section....................48

5/11—Revision 0: Initial Version

Rev. A | Page 3 of 52

AD5755 Data Sheet

DETAILED FUNCTIONAL BLOCK DIAGRAM

AV

CC

5.0V

AV

SS

–15V AGND

AV

+15V

DD

SW

V

A

BOOST_A

DV

DGND

LDAC

CLEAR

SCLK

SDIN

SYNC

SDO

FAULT

ALERT

REFOUT

REFIN

AD1

AD0

DD

POWER-ON

RESET

INPUT SHIFT

REGISTER

AND

CONTROL

STATUS

REGISTER

WATCHDOG

TIMER

(SPI ACTIVITY)

VREF

REFERENCE

BUFFERS

AD5755

16

INPUT REG A

GAIN REG A

OFFSET REG A

DAC CHANNEL A

DAC CHANNEL B

DAC CHANNEL C

DAC CHANNEL D

DC-TO-DC

CONVERTER

V

POWER

CONTROL

16

DAC

+

REG A

DAC A

7.4V TO 29.5V

R2 R3

R1

VOUT

RANGE

SCALING

SWB, SWC, SW

V

D

SEN1VSEN2

REG

BOOST_B,VBOOST_C,VBOOST_D

I

OUT_A

R

SET_A

+V

V

OUT_A

–V

I

OUT_B

R

SET_B

+V

SENSE_B

V

OUT_B

SENSE_A

, I

OUT_C

, R

,

V

SET_C

, +V

OUT_C

, I

OUT_D

, R

SENSE_

,

SET_D

V

OUT_D

, +V

C

SENSE_

D

07304-001

Figure 2.

Rev. A | Page 4 of 52

Data Sheet AD5755

SPECIFICATIONS

AVDD = V GNDSW otherwise noted.

Table 1.

Parameter1 Min Typ Max Unit Test Conditions/Comments

VOLTAGE OUTPUT

Output Voltage Ranges 0 5 V

0 10 V

−5 +5 V

−10 +10 V 0 6 V 0 12 V

−6 +6 V

−12 +12 V

Resolution 16 Bits

ACCURACY AVSS = −15 V, loaded and unloaded

Total Unadjusted Error (TUE)

B Version −0.04 +0.04 % FSR

−0.03 ±0.0032 +0.03 % FSR TA = 25°C A Version −0.25 +0.25 % FSR

−0.075 ±0.02 +0.075 % FSR TA = 25°C TUE Long-Term Stability 35 ppm FSR Drift after 1000 hours, TJ = 150°C Relative Accuracy (INL) −0.006 ±0.0012 +0.006 % FSR 0 V to 5 V, 0 V to 10 V, ±5 V, ±10 V ranges

−0.008 ±0.0012 +0.008 % FSR On overranges Differential Nonlinearity (DNL) −1 +1 LSB Guaranteed monotonic Zero-Scale Error −0.03 ±0.002 +0.03 % FSR Zero-Scale TC2 ±2

Bipolar Zero Error −0.03 ±0.002 +0.03 % FSR Bipolar Zero TC

Offset Error −0.03 ±0.002 +0.03 % FSR Offset TC2 ±2

Gain Error −0.03 ±0.004 +0.03 % FSR Gain TC2 ±3

Full-Scale Error −0.03 ±0.002 +0.03 % FSR Full-Scale TC2 ±2

OUTPUT CHARACTERISTICS2

Headroom 1 2.2 V With respect to V Footroom 1 1.4 V With respect to the AVSS supply Output Voltage Drift vs. Time 20 ppm FSR

Short-Circuit Current 12/6 16/8 mA

Load 1 kΩ For specified performance Capacitive Load Stability 10 nF

2 μF

DC Output Impedance 0.06 Ω DC PSRR 50 μV/V

= 15 V; AVSS = −15 V; DVDD = 2.7 V to 5.5 V; AVCC = 4.5 V to 5.5 V; dc-to-dc converter disabled; AGND = DGND =

BOOST_x

= 0 V; REFIN = 5 V; voltage outputs: RL = 1 kΩ, CL = 220 pF; current outputs: RL = 300 Ω; all specifications T

x

ppm FSR/°C

2

±1

ppm FSR/°C

supply

BOOST

Drift after 1000 hours, ¾ scale output, T

= −15 V

AV

SS

Programmable by user, defaults to 16 mA typical level

External compensation capacitor of 220 pF connected

Rev. A | Page 5 of 52

MIN

to T

, unless

MAX

= 150°C,

J

AD5755 Data Sheet

Parameter1 Min Typ Max Unit Test Conditions/Comments

DC Crosstalk 24 μV

CURRENT OUTPUT

Output Current Ranges 0 24 mA

0 20 mA 4 20 mA

Resolution 16 Bits

ACCURACY (EXTERNAL R

Total Unadjusted Error (TUE)

B Version −0.05 ±0.009 +0.05 % FSR

A Version −0.2 ±0.04 +0.2 % FSR TUE Long-Term Stability 100 ppm FSR Drift after 1000 hours, TJ = 150°C Relative Accuracy (INL) −0.006 +0.006 % FSR Differential Nonlinearity (DNL) −1 +1 LSB Guaranteed monotonic Offset Error −0.05 ±0.005 +0.05 % FSR Offset Error Drift2 ±4

Gain Error −0.05 ±0.004 +0.05 % FSR Gain TC2 ±3

Full-Scale Error −0.05 ±0.008 +0.05 % FSR Full-Scale TC2 ±5

DC Crosstalk 0.0005 % FSR External R

ACCURACY (INTERNAL R

Total Unadjusted Error (TUE)

B Version −0.14 +0.14 % FSR

−0.11 ±0.009 +0.11 % FSR TA = 25°C

A Version −0.35 +0.35 % FSR

−0.2 +0.04 +0.2 % FSR TA = 25°C TUE Long-Term Stability 180 ppm FSR Drift after 1000 hours, TJ = 150°C Relative Accuracy (INL) −0.006 +0.006 % FSR

Relative Accuracy (INL) −0.004 +0.004 % FSR TA = 25°C Differential Nonlinearity (DNL) −1 +1 LSB Guaranteed monotonic Offset Error

3, 4

−0.05 +0.05 % FSR

−0.04 ±0.007 +0.04 % FSR TA = 25°C Offset Error Drift2 ±6

Gain Error −0.12 +0.12 % FSR

−0.06 ±0.002 +0.06 % FSR TA = 25°C Gain TC2 ±9

Full-Scale Error

3, 4

−0.1 ±0.007 +0.1 % FSR TA = 25°C Full-Scale TC2 ±14

DC Crosstalk4 −0.011 % FSR Internal R

OUTPUT CHARACTERISTICS2

Current Loop Compliance Voltage

Output Current Drift vs. Time Drift after 1000 hours, ¾ scale output, TJ = 150°C 90 ppm FSR External R 140 ppm FSR Internal R

)

SET

Assumes ideal resistor; see the External Current Setting Resistor section for more information.

ppm FSR/°C

SET

)

SET

3, 4

ppm FSR/°C

−0.14 +0.14 % FSR

ppm FSR/°C

SET

V

BOOST_x

− 2.4

V

BOOST_x

2.7

V

−

SET

Rev. A | Page 6 of 52

Data Sheet AD5755

Parameter1 Min Typ Max Unit Test Conditions/Comments

Resistive Load 1000 Ω

Output Impedance 100 MΩ DC PSRR 0.02 1 μA/V

REFERENCE INPUT/OUTPUT

Reference Input2

Reference Input Voltage 4.95 5 5.05 V For specified performance DC Input Impedance 45 150 MΩ

Reference Output

Output Voltage 4.995 5 5.005 V TA = 25°C Reference TC2 −10 ±5 +10 ppm/°C Output Noise (0.1 Hz to 10 Hz)2 7 μV p-p Noise Spectral Density2 100 nV/√Hz At 10 kHz

Output Voltage Drift vs. Time2 180 ppm Drift after 1000 hours, TJ = 150°C Capacitive Load2 1000 nF Load Current 9 mA See Figure 63 Short-Circuit Current 10 mA Line Regulation2 3 ppm/V See Figure 64 Load Regulation2 95 ppm/mA See Figure 63 Thermal Hysteresis2 160 ppm First temperature cycle 5 ppm Second temperature cycle

DC-TO-DC

Switch

Switch On Resistance 0.425 Ω Switch Leakage Current 10 nA Peak Current Limit 0.8 A

Oscillator

Oscillator Frequency 11.5 13 14.5 MHz

Maximum Duty Cycle 89.6 % At 410 kHz dc-to-dc switching frequency

DIGITAL INPUTS2 JEDEC compliant

VIH, Input High Voltage 2 V VIL, Input Low Voltage 0.8 V Input Current −1 +1 μA Per pin Pin Capacitance 2.6 pF Per pin

DIGITAL OUTPUTS2

SDO, ALERT

VOL, Output Low Voltage 0.4 V Sinking 200 μA VOH, Output High Voltage

High Impedance Leakage

Current

High Impedance Output

Capacitance

FAU LT

VOL, Output Low Voltage 0.4 V 10 kΩ pull-up resistor to DVDD VOL, Output Low Voltage 0.6 V At 2.5 mA VOH, Output High Voltage 3.6 V 10 kΩ pull-up resistor to DVDD

POWER REQUIREMENTS

AVDD 9 33 V AVSS −26.4 −10.8 V DVDD 2.7 5.5 V

DVDD −

0.5

−1 +1 μA

2.5 pF

V Sourcing 200 μA

The dc-to-dc converter has been characterized with a maximum load of 1 kΩ, chosen such that compliance is not exceeded; see Figure 52 and DC-DC MaxV bits in Table 25

This oscillator is divided down to give the dc-to-dc converter switching frequency

Rev. A | Page 7 of 52

AD5755 Data Sheet

Parameter1 Min Typ Max Unit Test Conditions/Comments

AVCC 4.5 5.5 V AIDD 8.6 10.5 mA

7 7.5 mA Current output mode on all channels, AISS −11 −8.8 mA

−1.7 mA Current output mode on all channels DICC 9.2 11 mA

AICC 1 mA Output unloaded, over supplies

5

I

2.7 mA

BOOST

1 mA Per channel, current output mode Power Dissipation 173 mW

1

Temperature range: −40°C to +105°C; typical at +25°C.

2

Guaranteed by design and characterization; not production tested.

3

For current outputs with internal R

loaded with the same code.

4

See the Current Output Mode with Internal R

5

Efficiency plots in Figure 54, Figure 55, Figure 56, and Figure 57 include the I

, the offset, full-scale, and TUE measurements exclude dc crosstalk. The measurements are made with all four channels enabled

SET

section for more explanation of the dc crosstalk.

SET

quiescent current.

BOOST

AC PERFORMANCE CHARACTERISTICS

AVDD = V GNDSW otherwise noted.

= 15 V; AVSS = −15 V; DVDD = 2.7 V to 5.5 V; AVCC = 4.5 V to 5.5 V; dc-to-dc converter disabled; AGND = DGND =

BOOST_x

= 0 V; REFIN = 5 V; voltage outputs: RL = 2 kΩ, CL = 220 pF; current outputs: RL = 300 Ω; all specifications T

x

Voltage output mode on all channels, output unloaded, over supplies

= DVDD, VIL = DGND, internal oscillator running,

V

IH

over supplies

Per channel, voltage output mode, output unloaded, over supplies

= 15 V, AVSS = −15 V, dc-to-dc converter

AV

DD

enable, current output mode, outputs disabled

MIN

to T

MAX

, unless

Table 2.

Parameter1 Min Typ Max Unit Test Conditions/Comments

DYNAMIC PERFORMANCE

Voltage Output

Output Voltage Settling Time 11 μs 5 V step to ±0.03% FSR, 0 V to 5 V range 18 μs 10 V step to ±0.03% FSR, 0 V to 10 V range 13 μs

100 mV step to 1 LSB (16-bit LSB), 0 V to 10 V

range Slew Rate 1.9 V/μs 0 V to 10 V range Power-On Glitch Energy 150 nV-sec Digital-to-Analog Glitch Energy 6 nV-sec Glitch Impulse Peak Amplitude 25 mV Digital Feedthrough 1 nV-sec DAC to DAC Crosstalk 2 nV-sec 0 V to 10 V range Output Noise (0.1 Hz to 10 Hz

0.15 LSB p-p 16-bit LSB, 0 V to 10 V range

Bandwidth)

Output Noise Spectral Density 150 nV/√Hz

Measured at 10 kHz, midscale output, 0 V to 10 V

range AC PSRR 83 dB

200 mV 50 Hz/60 Hz sine wave superimposed on

power supply voltage

Current Output

Output Current Settling Time 15 μs To 0.1% FSR (0 mA to 24 mA)

See test conditions/

ms See Figure 48, Figure 49, and Figure 50

comments

Output Noise (0.1 Hz to 10 Hz

0.15 LSB p-p 16-bit LSB, 0 mA to 24 mA range

Bandwidth)

Output Noise Spectral Density 0.5 nA/√Hz

Measured at 10 kHz, midscale output, 0 mA to

24 mA range

1

Guaranteed by design and characterization; not production tested.

Rev. A | Page 8 of 52

Data Sheet AD5755

TIMING CHARACTERISTICS

AVDD = V GNDSW otherwise noted.

= 15 V; AVSS = −15 V; DVDD = 2.7 V to 5.5 V; AVCC = 4.5 V to 5.5 V; dc-to-dc converter disabled; AGND = DGND =

BOOST_x

= 0 V; REFIN = 5 V; voltage outputs: RL = 1 kΩ, CL = 220 pF; current outputs: RL = 300 Ω; all specifications T

x

MIN

to T

MAX

, unless

Table 3.

Parameter

1, 2, 3

Limit at T

MIN

, T

Unit Description

MAX

t1 33 ns min SCLK cycle time t2 13 ns min SCLK high time t3 13 ns min SCLK low time t4 13 ns min t5 13 ns min

t6 198 ns min

falling edge to SCLK falling edge setup time

SYNC

th

/32nd SCLK falling edge to SYNC rising edge (see ) Figure 77

24

high time

SYNC t7 5 ns min Data setup time t8 5 ns min Data hold time t9 20 μs min

rising edge to LDAC falling edge (all DACs updated or any channel has

SYNC

digital slew rate control enabled) 5 μs min

t10 10 ns min t11 500 ns max t12

See the AC Performance

μs max DAC output settling time

rising edge to LDAC falling edge (single DAC updated)

SYNC

pulse width low

LDAC

falling edge to DAC output response time

LDAC

Characteristics section t13 10 ns min CLEAR high time t14 5 μs max CLEAR activation time t15 40 ns max SCLK rising edge to SDO valid t16 21 μs min 5 μs min

t17 500 ns min t18 800 ns min

4

t

20 μs min

19

5 μs min

rising edge to DAC output response time (LDAC = 0) (all DACs updated)

SYNC

rising edge to DAC output response time (LDAC = 0) (single DAC updated)

SYNC

falling edge to SYNC rising edge

LDAC

pulse width

RESET

high to next SYNC low (digital slew rate control enabled) (all DACs updated)

SYNC

high to next SYNC low (digital slew rate control disabled) (single DAC

SYNC updated)

1

Guaranteed by design and characterization; not production tested.

2

All input signals are specified with t

3

See Figure 3, Figure 4, Figure 5, and Figure 6.

4

This specification applies if

LDAC

= t

= 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.2 V.

RISE

FALL

is held low during the write cycle; otherwise, see t9.

Rev. A | Page 9 of 52

AD5755 Data Sheet

Timing Diagrams

t

1

SCLK

SYNC

SDIN

LDAC

V

OUT_x

LDAC = 0

V

OUT_x

CLEAR

V

OUT_x

12 24

t

6

t

4

t

7

MSB

t

13

t

3

t

8

14

t

2

t

10

t

5

t

19

LSB

t

9

t

17

t

16

10

t

11

t

12

t

RESET

18

07304-002

Figure 3. Serial Interface Timing Diagram

SCLK

SYNC

SDIN

SDO

1 1

MSB MSBLSB LSB

INPUT WORD SPECIFIES REGISTER TO BE READ

UNDEFINED SELECTED REGISTER DATA

24 24

t

6

NOP CONDIT ION

MSB LSB

t

15

CLOCKED OUT

Figure 4. Readback Timing Diagram

07304-203

Rev. A | Page 10 of 52

Data Sheet AD5755

SCLK

SYNC

SDIN

SDO

LSB MSB

12 16

DUT_

R/W

DUT_

AD1

SDO DISABLED

XXXD15D14 D1D0

AD0

SDO_ ENAB

STATUSSTATUSSTATUSSTATUS

07304-204

Figure 5. Status Readback During Write

TO OUTPUT

50pF

C

200µA I

L

200µA I

OL

OH

VOH (MIN) OR

(MAX)

V

OL

07304-005

Figure 6. Load Circuit for SDO Timing Diagram

Rev. A | Page 11 of 52

AD5755 Data Sheet

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted. Transient currents of up to 100 mA do not cause SCR latch-up.

Table 4.

Parameter Rating

AVDD, V

to AGND, DGND −0.3 V to +33 V

BOOST_x

AVSS to AGND, DGND +0.3 V to −28 V AVDD to AVSS −0.3 V to +60 V AVCC to AGND −0.3 V to +7 V DVDD to DGND −0.3 V to +7 V Digital Inputs to DGND

−0.3 V to DV

+ 0.3 V or +7 V

DD

(whichever is less)

Digital Outputs to DGND

−0.3 V to DV

+ 0.3 V or +7 V

DD

(whichever is less)

REFIN, REFOUT to AGND

−0.3 V to AV

+ 0.3 V or +7 V

DD

(whichever is less)

V

OUT_x

to AGND

AV

SS

to V

or 33 V if using

BOOST_x

the dc-to-dc circuitry

+V

SENSE_x

, −V

SENSE_x

to AGND

AV

SS

to V

or 33 V if using

BOOST_x

the dc-to-dc circuitry

I

OUT_x

to AGND

AV

SS

to V

or 33 V if using

BOOST_x

the dc-to-dc circuitry SWx to AGND −0.3 to +33 V AGND, GNDSWx to DGND −0.3 V to +0.3 V Operating Temperature Range ( TA)

Industrial1 −40°C to +105°C Storage Temperature Range −65°C to +150°C Junction Temperature (TJ max) 125°C 64-Lead LFCSP

θJA Thermal Impedance2 20°C/W Power Dissipation (TJ max − TA)/θJA Lead Temperature JEDEC industry standard

Soldering J-STD-020

1

Power dissipated on chip must be derated to keep the junction temperature

below 125°C.

2

Based on a JEDEC 4-layer test board.

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

Rev. A | Page 12 of 52

Data Sheet AD5755

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

LV_D

PIN 1

INDICATO R

DCDC_D

SENSE_D

SET_CRSET_D

R

646362616059585756555453525150

SENSE_D

REFOUT

REFIN

COMP

–V

+V

COMP

V

BOOST_DVOUT_D

LV_C

SENSE_C

AVSSCOMP

OUT_C

–V

+V

V

49

OUT_D

I

R

1

SET_B

2

R

SET_A

REFGND REFGND

NOTES

1. THIS EXPOSED PADDLE SHOULD BE CO NNECTED TO THE PO TENTIALOF T HE AV IT IS RE COMMENDED T HAT THE P ADDLE BE THERMALLY CO NNECTED TO A COPPER PLANE FOR ENHANCED THERMAL PE RFORMANCE.

3 4 5

AD0

6

AD1

7

SYNC

8

SCLK

9

SDIN

10

SDO

DV

11

DD

12

DGND

13

LDAC

14

CLEAR

15

ALERT

16

FAULT

171819202122232425262728293031

POC

PIN, OR, ALTERNAT IVELY, IT CAN BE LEFT ELECTRI CALLY UNCO NNECTED.

SS

AV

RESET

DD

LV_A

–V

COMP

AD5755

TOP VIEW

(Not to Scale)

OUT_AIOUT_A

DCDC_A

V

SENSE_A+VSENSE_A

BOOST_A

V

COMP

AV

SS

32

LV_B

OUT_B

DCDC_B

V

SENSE_B+VSENSE_B

–V

COMP

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

COMP I

OUT_C

V

BOOST_C

AV

CC

SW

C

GNDSW GNDSW

SW

D

AV

SS

SW

A

GNDSW GNDSW

SW

B

AGND V

BOOST_B

I

OUT_B

DCDC_C

C

D

A

B

07304-006

Figure 7. Pin Configuration

Table 5. Pin Function Descriptions

Pin No. Mnemonic Description

1 R

SET_B

An external, precision, low drift 15 kΩ current setting resistor can be connected to this pin to improve the I temperature drift performance. See the Device Features section.

2 R

SET_A

An external, precision, low drift 15 kΩ current setting resistor can be connected to this pin to improve the I

temperature drift performance. See the Device Features section. 3 REFGND Ground Reference Point for Internal Reference. 4 REFGND Ground Reference Point for Internal Reference. 5 AD0 Address Decode for the Device Under Test (DUT) on the Board. 6 AD1 Address Decode for the DUT on the Board. 7

Active Low Input. This is the frame synchronization signal for the serial interface. While SYNC is low, data is

SYNC

transferred in on the falling edge of SCLK. 8 SCLK

Serial Clock Input. Data is clocked into the input shift register on the falling edge of SCLK. This operates at clock

speeds of up to 30 MHz. 9 SDIN Serial Data Input. Data must be valid on the falling edge of SCLK. 10 SDO Serial Data Output. Used to clock data from the serial register in readback mode. See Figure 4 and Figure 5. 11 DVDD Digital Supply. The voltage range is from 2.7 V to 5.5 V. 12 DGND Digital Ground. 13

Load DAC, Active Low Input. This is used to update the DAC register and consequently the DAC outputs. When

LDAC

tied permanently low, the addressed DAC data register is updated on the rising edge of SYNC. If LDAC is held

high during the write cycle, the DAC input register is updated, but the DAC output update only takes place at

14 CLEAR

the falling edge of LDAC

LDAC

pin must not be left unconnected.

Active High, Edge Sensitive Input. Asserting this pin sets the output current and voltage to the preprogrammed

(see ). Using this mode, all analog outputs can be updated simultaneously. The Figure 3

clear code bit setting. Only channels enabled to be cleared are cleared. See the Device Features section for more

information. When CLEAR is active, the DAC output register cannot be written to.

OUT_B

OUT_A

Rev. A | Page 13 of 52

AD5755 Data Sheet

Pin No. Mnemonic Description

15 ALERT

16

FAU LT

17 POC

18

RESET 19 AVDD Positive Analog Supply. The voltage range is from 9 V to 33 V. 20 COMP

21 −V

22 +V 23 COMP

24 V

25 V 26 I

LV_A

SENSE_A

DCDC_A

BOOST_A

Buffered Analog Output Voltage for DAC Channel A.

OUT_A

Current Output Pin for DAC Channel A.

OUT_A

27 AVSS Negative Analog Supply Pin. Voltage range is from −10.8 V to −26.4 V. 28 COMP

29 −V

30 +V 31 V 32 COMP

33 I 34 V

LV_B

SENSE_B

Buffered Analog Output Voltage for DAC Channel B.

OUT_B

DCDC_B

Current Output Pin for DAC Channel B.

OUT_B

BOOST_B

35 AGND Ground Reference Point for Analog Circuitry. This must be connected to 0 V. 36 SWB

37 GNDSWB Ground Connection for DC-to-DC Switching Circuit. This pin should always be connected to ground. 38 GNDSWA Ground Connection for DC-to-DC Switching Circuit. This pin should always be connected to ground. 39 SWA

40 AVSS Negative Analog Supply Pin. The voltage range is from −10.8 V to −26.4 V. 41 SWD

42 GNDSWD Ground Connections for DC-to-DC Switching Circuit. This pin should always be connected to ground. 43 GNDSWC Ground Connections for DC-to-DC Switching Circuit. This pin should always be connected to ground.

Active High Output. This pin is asserted when there has been no SPI activity on the interface pins for a predetermined time. See the Device Features section for more information.

Active Low Output. This pin is asserted low when an open circuit in current mode is detected, a short circuit in voltage mode is detected, a PEC error is detected, or an overtemperature is detected (see the Device Features section). Open-drain output.

Power-On Condition. This pin determines the power-on condition and is read during power-on or, alternatively, after a device reset. If POC = 0, the device is powered up with the voltage and current channels in tristate mode. If POC = 1, the device is powered up with a 30 kΩ pull-down resistor to ground on the voltage output channel, and the current channel is in tristate mode.

Hardware Reset, Active Low Input.

Optional Compensation Capacitor Connection for V this pin and the V

pin allows the voltage output to drive up to 2 μF. Note that the addition of this capacitor

OUT_A

Output Buffer. Connecting a 220 pF capacitor between

OUT_A

reduces the bandwidth of the output amplifier, increasing the settling time. Sense Connection for the Negative Voltage Output Load Connection for V

. This pin must stay within ±3.0 V

OUT_A

of AGND for specified operation.

Sense Connection for the Positive Voltage Output Load Connection for V

DC-to-DC Compensation Capacitor. Connect a 10 nF capacitor from this pin to ground. Used to regulate the

OUT_A

.

feedback loop of the Channel A dc-to-dc converter. Alternatively, if using an external compensation resistor, place a resistor in series with a capacitor to ground from this pin (see the DC-to-DC Converter Compensation Capacitors and the AICC Supply Requirements—Slewing sections in the Device Features section for more information).

Supply for Channel A Current Output Stage (see Figure 72). This is also the supply for the V

stage, which is

OUT_x

regulated to 15 V by the dc-to-dc converter. To use the dc-to-dc feature of the device, connect as shown in Figure 78.

Optional Compensation Capacitor Connection for V this pin and the V

pin allows the voltage output to drive up to 2 μF. Note that the addition of this capacitor

OUT_B

Output Buffer. Connecting a 220 pF capacitor between

OUT_B

reduces the bandwidth of the output amplifier, increasing the settling time. Sense Connection for the Negative Voltage Output Load Connection for V

. This pin must stay within ±3.0 V

OUT_B

of AGND for specified operation.

Sense Connection for the Positive Voltage Output Load Connection for V

DC-to-DC Compensation Capacitor. Connect a 10 nF capacitor from this pin to ground. Used to regulate the

OUT_B

.

feedback loop of the Channel B dc-to-dc converter. Alternatively, if using an external compensation resistor, place a resistor in series with a capacitor to ground from this pin (see the DC-to-DC Converter Compensation Capacitors and the AICC Supply Requirements—Slewing sections in the Device Features section for more information).

Supply for Channel B Current Output Stage (see Figure 72). This is also the supply for the V

stage, which is

OUT_x

regulated to 15 V by the dc-to-dc converter. To use the dc-to-dc feature of the device, connect as shown in Figure 78.

Switching Output for Channel B DC-to-DC Circuitry. To use the dc-to-dc feature of the device, connect as shown in Figure 78.

Switching Output for Channel A DC-to-DC Circuitry. To use the dc-to-dc feature of the device, connect as shown in Figure 78.

Switching Output for Channel D DC-to-DC Circuitry. To use the dc-to-dc feature of the device, connect as shown in Figure 78.

Rev. A | Page 14 of 52

Data Sheet AD5755

Pin No. Mnemonic Description

44 SWC

45 AVCC Supply for DC-to-DC Circuitry. 46 V

47 I 48 COMP

49 V 50 +V 51 −V

52 COMP

BOOST_C

Current Output Pin for DAC Channel C.

OUT_C

DCDC_C

Buffered Analog Output Voltage for DAC Channel C.

OUT_C

SENSE_C

LV_C

53 AVSS Negative Analog Supply Pin. 54 I 55 V 56 V

57 COMP

58 +V 59 −V

60 COMP

Current Output Pin for DAC Channel D.

OUT_D

Buffered Analog Output Voltage for DAC Channel D.

OUT_D

BOOST_D

DCDC_D

SENSE_D

LV_D

61 REFIN External Reference Voltage Input. 62 REFOUT

63 R

64 R

SET_D

SET_C

EPAD

Switching Output for Channel C DC-to-DC Circuitry. To use the dc-to-dc feature of the device, connect as shown in Figure 78.

Supply for Channel C Current Output Stage (see Figure 72). This is also the supply for the V

stage, which is

OUT_x

regulated to 15 V by the dc-to-dc converter. To use the dc-to-dc feature of the device, connect as shown in Figure 78.

DC-to-DC Compensation Capacitor. Connect a 10 nF capacitor from this pin to ground. Used to regulate the feedback loop of the Channel C dc-to-dc converter. Alternatively, if using an external compensation resistor, place a resistor in series with a capacitor to ground from this pin (see the DC-to-DC Converter Compensation Capacitors and AICC Supply Requirements—Slewing sections in the Device Features section for more information).

Sense Connection for the Positive Voltage Output Load Connection for V

Sense Connection for the Negative Voltage Output Load Connection for V

.

OUT_C

. This pin must stay within ±3.0 V

OUT_C

of AGND for specified operation. Optional Compensation Capacitor Connection for V

this pin and the V

pin allows the voltage output to drive up to 2 μF. Note that the addition of this capacitor

OUT_C

Output Buffer. Connecting a 220 pF capacitor between

OUT_C

reduces the bandwidth of the output amplifier, increasing the settling time.

Supply for Channel D Current Output Stage (see Figure 72). This is also the supply for the V

OUT_x

regulated to 15 V by the dc-to-dc converter. To use the dc-to-dc feature of the device, connect as shown in Figure 78.

DC-to-DC Compensation Capacitor. Connect a 10 nF capacitor from this pin to ground. Used to regulate the feedback loop of Channel D dc-to-dc converter. Alternatively, if using an external compensation resistor, place a resistor in series with a capacitor to ground from this pin (see the DC-to-DC Converter Compensation Capacitors and AICC Supply Requirements—Slewing sections in the Device Features section for more information).

Sense Connection for the Positive Voltage Output Load Connection for V

Sense Connection for the Negative Voltage Output Load Connection for V

.

OUT_D

. This pin must stay within ±3.0 V

OUT_D

of AGND for specified operation. Optional Compensation Capacitor Connection for V

this pin and the V

pin allows the voltage output to drive up to 2 μF. Note that the addition of this capacitor

OUT_D

Output Buffer. Connecting a 220 pF capacitor between

OUT_D

reduces the bandwidth of the output amplifier, increasing the settling time.

Internal Reference Voltage Output. It is recommended to place a 0.1 μF capacitor between REFOUT and REFGND.

An external, precision, low drift 15 kΩ current setting resistor can be connected to this pin to improve the I temperature drift performance. See the Device Features section.

Exposed Pad. This exposed pad should be connected to the potential of the AV

pin, or, alternatively, it can be

SS

left electrically unconnected. It is recommended that the pad be thermally connected to a copper plane for enhanced thermal performance.

stage, which is

OUT_D

OUT_C

Rev. A | Page 15 of 52

AD5755 Data Sheet

TYPICAL PERFORMANCE CHARACTERISTICS

VOLTAGE OUTPUTS

0.0015

0.0010

0.0005

INL ERRO R (%FSR)

–0.0005

±10V RANGE ±5V RANGE +10V RANGE +5V RANGE +10V RANGE W ITH DCDC

0

AVDD = +15V AVSS = –15V

= 25°C

T

A

0.0015

0.0010

0.0005

INL (%FSR)

–0.0005

–0.0010

+5V RANGE MAX INL +10V RANG E MAX INL ±5V RANGE MAX INL ±10V RANGE MAX IN L +5V RANGE MIN INL + 10V RANGE MIN INL ±5V RANGE MIN INL ±10V RANGE M IN INL

0

AV

= +15V

DD

AV

= –15V

SS

OUTPUT UNLOADED

–0.0010

0 10k 20k 30k 40k 50k 60k

CODE

Figure 8. Integral Nonlinearity Error vs. DAC Code

1.0

0.8

0.6

0.4

0.2

–0.2

DNL ERROR (LSB)

–0.4

–0.6

–0.8

–1.0

±10V RANGE ±5V RANGE +10V RANGE +5V RANGE +10V RANGE W ITH DCDC

0

0 10k 20k 30k 40k 50k 60k

CODE

AVDD = +15V

= –15V

AV

SS

= 25°C

T

A

Figure 9. Differential Nonlinearity Error vs. DAC Code

–0.002

–0.004

–0.006

TOTAL UNADJUSTED ERROR (%F SR)

–0.008

–0.010

0.006

0.004

0.002

0

10k 20k 30k 40k 50k 60k

±10V RANGE ±5V RANGE +10V RANGE +5V RANGE +10V RANGE WITH DCDC

CODE

Figure 10. Total Unadjusted Error vs. DAC Code

AVDD = +15V

= –15V

AV

SS

= 25°C

T

A

–0.0015

–40 –20 0 20 40 60 80 100

07304-023

TEMPERATURE (°C)

07304-127

Figure 11. Integral Nonlinearity Error vs. Temperature

1.0

0.8

0.6

0.4

0.2

–0.2

DNL ERROR (LSB)

–0.4

–0.6

–0.8

–1.0

07304-024

AVDD = +15V

= –15V

AV

SS

ALL RANGES

0

–40 –20 0 20 40 60 80 100

DNL ERROR MAX DNL ERROR MIN

TEMPERATURE (°C)

07304-128

Figure 12. Differential Nonlinearity Error vs. Temperature

0.012

0.010

0.008

0.006

0.004

0.002

0

–0.002

TOTAL UNADJUSTED ERROR (%F SR)

–0.004

–0.006

–40 –20 0 20 40 60 80 100

07304-025

+5V RANGE +10V RANGE ±5V RANGE ±10V RANGE

AVDD = +15V AV

= –15V

SS

OUTPUT UNLOADED

TEMPERATURE (°C)

07304-129

Figure 13. Total Unadjusted Error vs. Temperature

Rev. A | Page 16 of 52

ANALOG DEVICES AD5755 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

PRODUCT HIGHLIGHTS

COMPANION PRODUCTS

FUNCTIONAL BLOCK DIAGRAM

TABLE OF CONTENTS

REVISION HISTORY

DETAILED FUNCTIONAL BLOCK DIAGRAM

SPECIFICATIONS

AC PERFORMANCE CHARACTERISTICS

TIMING CHARACTERISTICS

Timing Diagrams

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

VOLTAGE OUTPUTS