ANALOG DEVICES AD5750-1 Service Manual

Industrial Current/Voltage

www.BDTIC.com/ADI

Output Driver,

Programmable Ranges

Preliminary Technical Data

FEATURES

Current Output Ranges: 4–20mA, 0–20mA or 0–24mA,
±20ma, ±24ma

B Grade - 0.1% Total Unadjusted Error (TUE)
A Grade - 0.3% Total Unadjusted Error (TUE)

5ppm/°C Output Drift
Voltage Output Ranges: 0-5V, 0-10V, ±5V, ±10V,
20% over-range

B Grade - 0.1% Total Unadjusted Error (TUE)

A Grade - 0.3% Total Unadjusted Error (TUE)
Flexible Serial Digital Interface
On-Chip Output Fault Detection
PEC Error Checking
Asynchronous CLEAR Function
Power Supply Range

AV

: = +12V to +24V (+/-10%)

DD

AV

: = -12V to -24V (+/-10%)

SS

Output Loop Compliance to AV
Temperature Range: -40°C to +105°C
LFCSP Packages

APPLICATIONS

Process Control
Actuator Control
PLC

GENERAL DESCRIPTION

The AD5750 is a single channel, low-cost, precision,
voltage/current output driver with hardware or software
programmable output ranges. The software ranges are
configured via an SPI/Microwire compatible serial interface.
The AD5750 targets applications in PLC and industrial process
control. The analog input to the AD5750 is provided from a
low voltage, single supply digital-to-analog converter and is
internally conditioned to provide the desired output
current/voltage range.
The output current range is programmable across five current
ranges - 4–20mA, 0–20mA or 0–24mA, ±20ma and ±24ma.

– 2.5 V

DD

AD5750

Voltage output is provided from a separate pin that can be
configured to provide 0V to 5V, 0V to 10V, ±5V or ±10V
output ranges. An over-range of 20% is available on the voltage
ranges.

Analog outputs are short and open circuit protected and can
drive capacitive loads of 1uF and inductive loads of 0.1H.
The device is specified to operate with a power supply range
from ±12 V to ±24 V. Output loop compliance is 0 V to AV
– 2.5 V.

The flexible serial interface is SPI
compatible and can be operated in 3-wire mode to minimize the
digital isolation required in isolated applications. The interface
also features an optional PEC error checking feature using
CRC-8 error checking, useful in industrial environments where
data communication corruption can occur.

The device also includes a power-on-reset function ensuring
that the device powers up in a known state and an
asynchronous CLEAR pin which sets the outputs to zero-scale /
mid-scale voltage output or the low end of the selected current
range.

A HW SELECT pin is used to configure the part for hardware
or software mode on power up.

The total output error is typically ±0.1% in both current mode
and voltage mode.

Table 1. Related Devices

Part Number Description
AD5422

and MICROWIRE

Single Channel, 16-Bit, Serial
Input Current Source and
Voltage Output DAC

DD

Rev. PrC

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rights of third parties that may result from its use. Specifications subject to change without notice. No
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Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2008 Analog Devices, Inc. All rights reserved.

AD5750 Preliminary Technical Data

www.BDTIC.com/ADI

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Functional Block Diagram .............................................................. 3

Specifications ..................................................................................... 4

Timing Characteristics ................................................................ 8

Absolute Maximum Ratings .......................................................... 10

ESD Caution ................................................................................ 10

Pin Configuration and Function Descriptions ........................... 11

Typical Performance Characteristics ........................................... 13

Terminology .................................................................................... 14

Theory of Operation ...................................................................... 15

CURRENT OUTPUT Architecture ......................................... 17

OUTEN ........................................................................................ 17

Software control: ......................................................................... 18

HARDWARE CONTROL: ........................................................ 20

Transfer Function ....................................................................... 21

Features ............................................................................................ 22

output fault alert – SOFTWARE MODE ................................ 22

output fault alert – HARDWARE MODE ............................... 22

voltage output short circuit protection .................................... 22

Asynchronous Clear (CLEAR) ................................................. 22

External current setting resistor ............................................... 22

Applications Information .............................................................. 24

Transient voltage protection ..................................................... 24

Layout Guidelines....................................................................... 24

Galvanically Isolated Interface ................................................. 24

Microprocessor Interfacing ....................................................... 24

Outline Dimensions ....................................................................... 25

Ordering Guide .......................................................................... 25

REVISION HISTORY

PrC – Preliminary Version. May 6, 2008

Rev. PrC | Page 2 of 25

Preliminary Technical Data AD5750

www.BDTIC.com/ADI

FUNCTIONAL BLOCK DIAGRAM

CLEAR

CLRSEL

SCLK/OUTEN*

SDIN/R0*

SYNC/RSEL*

SDO/VFAULT*

HW SELECT

VIN

VREF

RESET

FAULT/TEMP*

NC/IFAULT*

INPUT SHIFT

REGISTER

AND

CONTROL

LOGIC

STATUS REG

OVERTEMP

VOUT SHORT F A ULT

IOUT OPEN FAULT

OUTPUT RANG E ERROR

AD5750

DVCC

VOUT RANGE
SCALING

IOUT RANGE
SCALING

POWER

RESET

ON

GND

AVDD

GND

VOUT SHORT FAULT

V

DD

R2

RSET

V

SS

IOUT OPEN FAULT

COMP2COMP1

VSENSE+

VOUT

VSENSE-

R3

REXT1

Vx

REXT2

IOUT

AD2/R1*

AD1/R2*

AD0/R3*

Figure 1. Functional Block Diagram

AVSS

* Denotes shared pin. Software mode denoted by regular text, hardware mode denoted by bold

text. E.G. for FAULT/TEMP pin, in software mode this pin will take on FAULT function. In
Hardware mode, this pin will take on TEMP function.

Rev. PrC | Page 3 of 25

AD5750 Preliminary Technical Data

www.BDTIC.com/ADI

SPECIFICATIONS

AVDD/AVSS=±12V (+/-10%) to ±24V (+/-10%) , DVCC =2.7 V to 5.5 V, GND = 0 V. RL = 2 kΩ, CL = 200 pF, IOUT : RL = 300Ω, HL =
50mH; All specifications T

Table 2.

Parameter B grade

INPUT VOLTAGE RANGE

Input Leakage Current 1 1 uA max

VOLTAGE OUTPUT

Output Voltage Ranges 0 to 5 0 to 5 V

0 to 10 0 to 10 V

-5 to +5 -5 to +5 V

-10 to +10 -10 to +10 V

ACCURACY Output unloaded

Bipolar Output

Total Unadjusted Error
(TUE)

Relative Accuracy (INL) ±0.02 ±0.02 % FSR max
Bipolar Zero Error 0.01 0.01 % FSR typ Error at analog input = mid scale
Bipolar Zero TC TBD TBD ppm % FSR max
Offset Error 0.015 0.015 % FSR typ Error at analog input = 10mv
Zero Scale Error 0.015 0.015 % FSR typ Error at analog input = 0.0v
Zero Scale TC TBD TBD ppm % FSR max
Gain Error 0.005 0.005 % FSR typ (Ideal Span – Measured Span)/Ideal Span
Gain Error TC TBD TBD ppm % FSR max
Full Scale Error 0.015 0.015 % FSR typ Error at analog input = 4.096v (FS)
Full Scale Error TC TBD TBD ppm % FSR max

Unipolar Output

Total Unadjusted Error
(TUE)

Relative Accuracy (INL) ±0.02 ±0.02 % FSR max
Offset Error 0.01 0.01 % FSR typ Error at analog input = 10mv
Zero Scale Error 0.015 0.015 % FSR typ Error at analog input = 0.0v
Zero Scale TC TBD TBD ppm % FSR max
Gain Error 0.003 0.003 % FSR typ (Ideal Span – Measured Span)/Ideal Span
Gain Error TC TBD TBD ppm % FSR max
Full Scale Error 0.01 0.01 % FSR typ Error at analog input = 4.096v (FS)
Full Scale Error TC TBD TBD ppm % FSR max

Output Voltage Over-Ranges 0 to 6 0 to 6 V Programmable Over-Ranges.

0 to 12

-6 to +6

-12 to +12
Overrange
Relative Accuracy (INL)

OUTPUT CHARACTERISTICS

MIN

to T

, unless otherwise noted.

MAX

1

A grade2 Unit Test Conditions/Comments

0 to 4.096 0 to 4.096 V

AVDD needs to have minimum 1.1v headroom, or

> +11.1v.

AVDD/AVSS needs to have minimum 1.1v

headroom, or > +/-11.1v.

0.1 0.3 % FSR max Over temperature and supplies.

0.1 0.1 % FSR max Over temperature and supplies.

See Features Section.

0 to 12

-6 to +6

-12 to +12

±0.02 ±0.02 % FSR max

V
V
V

Rev. PrC | Page 4 of 25

Preliminary Technical Data AD5750

www.BDTIC.com/ADI

Parameter B grade1 A grade2 Unit Test Conditions/Comments

Short-Circuit Current 15 15 mA max
Load Conditions

Resistance 1 1 K Ohm min For Specified Performance
Capacitance Load Stability
RL = ∞ 20 20 nF max
RL = 2 kΩ TBD TBD nF max
RL = ∞ 1 1 μF max

0.1% Settling Time

Slew Rate 1 1 V/μs typ
Output Noise TBD

Output Noise Spectral

Density
DC Output Impedance 0.3 0.3 Ω typ
DC PSRR 10 10 μV/V

AC PSRR TBD TBD dB

Power-On Glitch Energy 10 10 nV-sec typ

CURRENT OUTPUT

Output Current Ranges 0 to 24 0 to 24 mA

0 to 20 0 to 20 mA
4 to 20 4 to 20 mA
±20 ±20 mA
±24 ±24 mA

ACCURACY

Total Unadjusted Error (TUE) ±0.1 ±0.3 % FSR max With External Precision Resistor

TUE TC ±5 ±5 ppm max With External Precision Resistor

10 10 Us Specified with 200pF load

TBD
80
100 100 nV/√Hz typ Measured at 10KHz

80

μV rms max
μV rms max

External compensation capacitor of 4nF

connected.

0.1 Hz to 10 Hz Bandwidth
100 kHz Bandwidth

200mV 50/60Hz Sinewavesuperimposed on

power supply voltage.

Bipolar Output

Relative Accuracy (INL) ±0.02 ±0.02 % FSR max
Bipolar Zero Error 0.0325 0.0325 % FSR typ Error at analog input = mid scale
Bipolar Zero TC TBD TBD ppm % FSR max
Offset Error 0.0175 0.0175 % FSR typ Error at analog input = 10mv
Zero Scale Error 0.0175 0.0175 % FSR typ Error at analog input = 0.0v
Zero Scale TC TBD TBD ppm % FSR max
Gain Error 0.01 0.01 % FSR typ (Ideal Span – Measured Span)/Ideal Span
Gain Error TC TBD TBD ppm % FSR max
Full Scale Error 0.0125 0.0125 % FSR typ Error at analog input = 4.096v (FS)
Full Scale Error TC TBD TBD ppm % FSR max

Unipolar Output

Relative Accuracy (INL) ±0.02 ±0.02 % FSR max
Offset Error 0.01 0.01 % FSR typ Error at analog input = 10mv
Zero Scale Error 0.01 0.01 % FSR typ Error at analog input = 0.0v
Zero Scale TC TBD TBD ppm % FSR max
Gain Error 0.15 0.15 % FSR typ (Ideal Span – Measured Span)/Ideal Span
Gain Error TC TBD TBD ppm % FSR max
Full Scale Error 0.01 0.01 % FSR typ Error at analog input = 4.096v (FS)
Full Scale Error TC TBD TBD ppm % FSR max

Rev. PrC | Page 5 of 25

AD5750 Preliminary Technical Data

www.BDTIC.com/ADI

Parameter B grade1 A grade2 Unit Test Conditions/Comments

Total Unadjusted Error (TUE) ±0.3 ±0.3 % FSR max With Internal Resistor

TUE TC ±20

±50

Bipolar Output

Relative Accuracy (INL) ±0.02 ±0.02 % FSR max
Bipolar Zero Error 0.0325 0.0325 % FSR typ Error at analog input = mid scale
Bipolar Zero TC TBD TBD ppm % FSR max
Offset Error 0.01 0.01 % FSR typ Error at analog input = 10mv
Zero Scale Error 0.01 0.01 % FSR typ Error at analog input = 0.0v
Zero Scale TC TBD TBD ppm % FSR max
Gain Error 0.003 0.003 % FSR typ (Ideal Span – Measured Span)/Ideal Span
Gain Error TC TBD TBD ppm % FSR max
Full Scale Error 0.01 0.01 % FSR typ Error at analog input = 4.096v (FS)
Full Scale Error TC TBD TBD ppm % FSR max

Unipolar Output

Relative Accuracy (INL) ±0.02 ±0.02 % FSR max
Offset Error 0.01 0.01 % FSR typ Error at analog input = 10mv
Zero Scale Error 0.01 0.01 % FSR typ Error at analog input = 0.0v
Zero Scale TC TBD TBD ppm % FSR max
Gain Error 0.005 0.005 % FSR typ (Ideal Span – Measured Span)/Ideal Span
Gain Error TC TBD TBD ppm % FSR max
Full Scale Error 0.01 0.01 % FSR typ Error at analog input = 4.096v (FS)
Full Scale Error TC TBD TBD ppm % FSR max

CURRENT MODE
OVERRANGES

0 to 20.4 0 to 20.4 mA SEE FEATURES SECTION
4 to 20.4 4 to 20.4 mA SEE FEATURES SECTION

OUTPUT CHARACTERISTICS

Current Loop Compliance

Voltage

Resistive Load

Inductive Load 0.1 0.1 H max

0.1% Settling Time

DC PSRR 1 1 μA/V max
Output Impedance 25 25 MΩ typ

REFERENCE INPUT

Reference Input

Reference Input Voltage 4.096 4.096 V nom ±1% for specified performance
Input Leakage Current 1 1 uA max

DIGITAL INPUTS

VIH, Input High Voltage 2 2 V min
VIL, Input Low Voltage 0.8 0.8 V max
Input Current ±1 ±1 μA max Per pin
Pin Capacitance 10 10 pF typ Per pin

0 to 24.5 0 to 24.5 mA SEE FEATURES SECTION

AVDD – 2.5 AVDD – 2.5 V max

See

Comment

10 10 us

DV

±20
±50

See

Comment

ppm typ
ppm max

kΩ max Chosen such that compliance is not exceeded.

Rev. PrC | Page 6 of 25

With Internal Resistor

= 2.7 V to 5.5 V, JEDEC compliant

CC

Preliminary Technical Data AD5750

www.BDTIC.com/ADI

Parameter B grade1 A grade2 Unit Test Conditions/Comments
DIGITAL OUTPUTS

FAULT, IFAULT, TEMP, VFAULT

VOL, Output Low Voltage 0.4 0.4 V max
VOL, Output Low Voltage 0.6 0.6 V typ @ 2.5 Ma

VOH, Output High Voltage 3.6 3.6 V min

SDO

VOL, Output Low Voltage 0.5 0.5 V max Sinking 200ua
VOH, Output High Voltage DVCC-0.5 DVCC-0.5 V min Sourcing 200ua
High Impedance Leakage

current

High Impedance Output

Capacitance

POWER REQUIREMENTS

AVDD 12 to 24 12 to 24 V min to V max +/-10%
AVSS -12 to 24 -12 to 24 V min to V max +/-10%
DVCC

Input Voltage 2.7 to 5.5 2.7 to 5.5 V min to V max Internal supply disabled
AVDD TBD TBD mA Output unloaded
AVSS TBD TBD mA Output unloaded
DICC TBD TBD mA max VIH = DVCC, VIL = GND, TBD mA typ
Power Dissipation TBD TBD mW typ

1

Temperature range: -40°C to +105°C; typical at +25°C.

2

Temperature range: -40°C to +105°C; typical at +25°C.

10kΩ pull-up resistor to DV

10kΩ pull-up resistor to DV

±TBD ±TBD ua max

20 20 pF max

CC

CC

Rev. PrC | Page 7 of 25

AD5750 Preliminary Technical Data

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TIMING CHARACTERISTICS

AVDD/AVSS=±12V (+/-10%) to ±24V (+/-10%) , DVCC =2.7 V to 5.5 V, GND = 0 V. RL = 2 kΩ, CL = 200 pF, IOUT : RL = 300Ω, HL =
50mH; All specifications T

Table 3.

Parameter

1, 2

Limit at T

t1 33 ns min SCLK cycle time
t2 13 ns min SCLK high time
t3 13 ns min SCLK low time
t4 13 ns min
t5 13 ns min

t6 13 ns min
t7 6 ns min Data setup time

t8 0 ns min Data hold time
t10 , t9 1 μs max CLEAR pulse high/low activation time
t11 25 ns min

t

25 ns max SCLK rising edge to SDO valid (SDO CL=20pf)

12

1 Guaranteed by characterization. Not production tested.
2 All input signals are specified with tR = tF = 5 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V.

MIN

to T

, unless otherwise noted.

MAX

, T

Unit Description

MIN

MAX

falling edge to SCLK falling edge setup time

SYNC

th

SCLK falling edge to SYNC rising edge

16
Minimum SYNC

Minimum SYNC

high time (WRITE MODE)

high time (READ MODE)

TO OUTPUT

PIN

C

15pF

200µA I

L

200µA I

SDO Load Timing.

OL

VOH(min)-VOL(max)

2

OH

Rev. PrC | Page 8 of 25