ANALOG DEVICES AD5735 Service Manual

Quad-Channel, 12-Bit, Serial Input, 4 mA to 20 mA

and Voltage Output DAC with Dynamic Power Control

Data Sheet

FEATURES

12-bit resolution and monotonicity Dynamic power control for thermal management Current and voltage output pins connectable to a single

terminal

Current output ranges: 0 mA to 20 mA, 4 mA to 20 mA,

and 0 mA to 24 mA ±0.1% total unadjusted error (TUE) maximum

Voltage output ranges (with 20% overrange): 0 V to 5 V,

0 V to 10 V, ±5 V, and ±10 V

±0.09% total unadjusted error (TUE) maximum User-programmable offset and gain On-chip diagnostics On-chip reference: ±10 ppm/°C maximum

−40°C to +105°C temperature range

APPLICATIONS

Process control Actuator control PLCs

GENERAL DESCRIPTION

The AD5735 is a quad-channel voltage and current output DAC that operates with a power supply range from −26.4 V to +33 V.

FUNCTIONAL BLOCK DIAGRAM

–15V AGND

AV +15V

AD5735

On-chip dynamic power control minimizes package power dissipation in current mode. This reduced power dissipation is achieved by regulating the voltage on the output driver from

7.4 V to 29.5 V using a dc-to-dc boost converter optimized for minimum on-chip power dissipation.

The AD5735 uses a versatile 3-wire serial interface that operates at clock rates of up to 30 MHz and is compatible with standard SPI, QSPI™, MICROWIRE®, DSP, and microcontroller interface standards. The serial interface also features optional CRC-8 packet error checking, as well as a watchdog timer that monitors activity on the interface.

PRODUCT HIGHLIGHTS

1. Dynamic power control for thermal management.

2. 12-bit performance.

3. Quad channel.

COMPANION PRODUCTS

Product Family: AD5755, AD5755-1, AD5757, AD5737 External References: ADR445, ADR02 Digital Isolators: ADuM1410, ADuM1411 Power: ADP2302, ADP2303

Additional companion products on the AD5735 product page

5.0V

BOOST_x

DGND

LDAC

SCLK

SDIN

SYNC

SDO

CLEAR

FAU LT

ALERT

AD1

AD0

REFOUT

REFIN

NOTES

1. x = A, B, C, OR D.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

DIGITAL

INTERFACE

REFERENCE

AD5735

GAIN REG A

OFFSET REG A

DAC CHANNEL A

DAC CHANNEL B

DAC CHANNEL C

DAC CHANNEL D

Figure 1.

DC-TO- DC

CONVERTER

DAC A

7.4V TO 29. 5V

CURRENT AND

VO LTAGE

OUTPUT RANGE

SCALING

OUT_x

SET_x

OUT_x

–V

SENSE_x

09961-100

AD5735 Data Sheet

Features.............................................................................................. 1

Applications....................................................................................... 1

General Description ......................................................................... 1

Product Highlights ........................................................................... 1

Companion Products....................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Detailed Functional Block Diagram .............................................. 3

Specifications..................................................................................... 4

AC Performance Characteristics ................................................ 7

Timing Characteristics ................................................................ 8

Absolute Maximum Ratings.......................................................... 11

Thermal Resistance .................................................................... 11

ESD Caution................................................................................ 11

Pin Configuration and Function Descriptions........................... 12

Typical Performance Characteristics ........................................... 15

Voltage Outputs .......................................................................... 15

Current Outputs ......................................................................... 19

DC-to-DC Converter................................................................. 23

Reference ..................................................................................... 24

General......................................................................................... 25

Terminology .................................................................................... 26

Theory of Operation ...................................................................... 28

DAC Architecture....................................................................... 28

Power-On State of the AD5735 ................................................29

Serial Interface ............................................................................ 29

Transfer Function .......................................................................29

Registers........................................................................................... 30

Enabling the Output................................................................... 31

Reprogramming the Output Range ......................................... 31

Data Registers ............................................................................. 32

Control Registers........................................................................ 34

Readback Operation .................................................................. 37

Device Features............................................................................... 39

Fault Output ................................................................................ 39

Voltage Output Short-Circuit Protection................................ 39

Digital Offset and Gain Control............................................... 39

Status Readback During a Write .............................................. 39

Asynchronous Clear................................................................... 40

Packet Error Checking............................................................... 40

Watchdog Timer......................................................................... 40

Alert Output................................................................................ 40

Internal Reference...................................................................... 40

External Current Setting Resistor ............................................ 40

Digital Slew Rate Control.......................................................... 41

Dynamic Power Control............................................................ 41

DC-to-DC Converters............................................................... 42

AICC Supply Requirements—Static .......................................... 43

AICC Supply Requirements—Slewing ...................................... 43

Applications Information.............................................................. 45

Voltage and Current Output Pins on the Same Terminal..... 45

Current Output Mode with Internal R

Precision Voltage Reference Selection..................................... 45

Driving Inductive Loads............................................................ 46

Transient Voltage Protection .................................................... 46

Microprocessor Interfacing....................................................... 46

Layout Guidelines....................................................................... 46

Galvanically Isolated Interface ................................................. 47

Outline Dimensions....................................................................... 48

Ordering Guide .......................................................................... 48

................................ 45

SET

REVISION HISTORY

11/11—Rev. 0 to Rev. A

Added Comments to OUTPUT CHARACTERISTICS and ACCURACY, CURRENT OUTPUT Parameters in

Table 1 ................................................................................................ 4

Changes to Power-On State of the AD5735 Section.................. 29

Changes to Readback Operation Section .................................... 37

7/11—Revision 0: Initial Version

Rev. A | Page 2 of 48

Data Sheet AD5735

DETAILED FUNCTIONAL BLOCK DIAGRAM

5.0V

–15V AGND

+15V

BOOST_A

DGND

LDAC

CLEAR

SCLK

SDIN

SYNC

SDO

FAULT

ALERT

REFOUT

REFIN

AD1

AD0

POWER-ON

RESET

INPUT SHIFT

AND

CONTROL

STATUS

WATCHDOG

TIMER

(SPI ACTIVIT Y)

REF

REFERENCE

BUFFERS

AD5735

DAC

REG A

GAIN REG A

OFFSET REG A

DAC CHANNEL A

DAC CHANNEL B

DAC CHANNEL C

DAC CHANNEL D

DC-TO-DC

CONVERT ER

DYNAMIC

POWER

CONTRO L

DAC

INPUTDATA REG A

DAC A

7.4V TO 29.5V

R2 R3

OUT

RANGE

SCALING

SWB, SWC, SW

SEN1VSEN2

BOOST_B,VBOOST_ C,VBOOST_D

OUT_A

SET_A

SENSE_A

OUT_A

–V

SENSE_A

OUT_B

SET_B

±V

SENSE_B

OUT_B

, I

OUT_C

, R

SET_C

, ±V

OUT_C

, I

OUT_D

, R

SENSE_

SET_D

OUT_D

, ±V

SENSE_

09961-001

Figure 2.

Rev. A | Page 3 of 48

AD5735 Data Sheet

SPECIFICATIONS

AVDD = V GNDSW unless otherwise noted.

Table 1.

Parameter1 Min Typ Max Unit Test Conditions/Comments

VOLTAGE OUTPUT

Output Voltage Ranges 0 5 V

0 10 V

−5 +5 V

−10 +10 V 0 6 V 0 12 V

−6 +6 V

−12 +12 V Resolution 12 Bits

ACCURACY, VOLTAGE OUTPUT

Total Unadjusted Error (TUE) −0.09 ±0.012 +0.09 % FSR 0 V to 5 V, 0 V to 10 V, ±5 V, ±10 V ranges

−0.13 ±0.05 +0.13 % FSR On overranges (0 V to 6 V, 0 V to 12 V, ±6 V, ±12 V) TUE Long-Term Stability 35 ppm FSR Drift after 1000 hours, TJ = 150°C Relative Accuracy (INL) −0.032 ±0.006 +0.032 % FSR Differential Nonlinearity (DNL) −1 +1 LSB Guaranteed monotonic Zero-Scale Error −0.05 ±0.004 +0.05 % FSR 0 V to 5 V, 0 V to 10 V ranges

−0.08 ±0.004 +0.08 % FSR On overranges (0 V to 6 V, 0 V to 12 V) Zero-Scale TC2 Bipolar Zero Error −0.05 ±0.003 +0.05 % FSR ±5 V, ±10 V ranges

−0.08 ±0.03 +0.08 % FSR On overranges (±6 V, ±12 V) Bipolar Zero TC2 ±2 ppm FSR/°C Offset Error −0.065 ±0.005 +0.065 % FSR 0 V to 5 V, 0 V to 10 V, ±5 V, ±10 V ranges

−0.09 ±0.03 +0.09 % FSR On overranges (0 V to 6 V, 0 V to 12 V, ±6 V, ±12 V) Offset TC2 ±2 ppm FSR/°C Gain Error −0.08 ±0.004 +0.08 % FSR 0 V to 5 V, 0 V to 10 V, ±5 V, ±10 V ranges

−0.15 ±0.004 +0.15 % FSR On overranges (0 V to 6 V, 0 V to 12 V, ±6 V, ±12 V) Gain TC2 ±3 ppm FSR/°C Full-Scale Error −0.09 ±0.01 +0.09 % FSR 0 V to 5 V, 0 V to 10 V, ±5 V, ±10 V ranges

−0.13 ±0.05 +0.13 % FSR On overranges (0 V to 6 V, 0 V to 12 V, ±6 V, ±12 V) Full-Scale TC2 ±2 ppm FSR/°C

OUTPUT CHARACTERISTICS,

VOLTAGE OUTPUT Headroom 1 2.2 V Footroom 1 1.4 V Output Voltage Drift vs. Time 20 ppm FSR Drift after 1000 hours, ¾ scale output, TJ = 150°C,

Short-Circuit Current 12/6 16/8 mA Programmable by user; defaults to 16 mA typical Resistive Load 1 kΩ For specified performance Capacitive Load Stability 10 nF

2 μF External 220 pF compensation capacitor connected

DC Output Impedance 0.06 Ω DC PSRR 50 μV/V DC Crosstalk 24 μV

CURRENT OUTPUT

Output Current Ranges 0 24 mA

0 20 mA 4 20 mA

Resolution 12 Bits

= 15 V; AVSS = −15 V; DVDD = 2.7 V to 5.5 V; AVCC = 4.5 V to 5.5 V; dc-to-dc converter disabled; AGND = DGND =

BOOST_x

= 0 V; REFIN = 5 V; voltage outputs: RL = 1 kΩ, CL = 220 pF; current outputs: RL = 300 Ω; all specifications T

±2 ppm FSR/°C

With respect to V

BOOST

supply

With respect to the AVSS supply

= −15 V

Rev. A | Page 4 of 48

MIN

to T

MAX

Data Sheet AD5735

Parameter1 Min Typ Max Unit Test Conditions/Comments

ACCURACY, CURRENT OUTPUT

(EXTERNAL R

)

SET

Total Unadjusted Error (TUE) −0.1 ±0.019 +0.1 % FSR TUE Long-Term Stability 100 ppm FSR Drift after 1000 hours, TJ = 150°C Relative Accuracy (INL) −0.032 ±0.006 +0.032 % FSR Differential Nonlinearity (DNL) −1 +1 LSB Guaranteed monotonic Offset Error −0.1 ±0.012 +0.1 % FSR Offset Error Drift2 ±4 ppm FSR/°C Gain Error −0.1 ±0.004 +0.1 % FSR Gain TC2 ±3 ppm FSR/°C Full-Scale Error −0.1 ±0.014 +0.1 % FSR Full-Scale TC2 ±5 ppm FSR/°C DC Crosstalk 0.0005 % FSR External R

ACCURACY, CURRENT OUTPUT

(INTERNAL R Total Unadjusted Error (TUE)

)

SET

3, 4

−0.14 ±0.022 +0.14 % FSR TUE Long-Term Stability 180 ppm FSR Drift after 1000 hours, TJ = 150°C Relative Accuracy (INL) −0.032 ±0.006 +0.032 % FSR Differential Nonlinearity (DNL) −1 +1 LSB Guaranteed monotonic Offset Error

3, 4

−0.1 ±0.017 +0.1 % FSR Offset Error Drift2 ±6 ppm FSR/°C Gain Error −0.12 ±0.004 +0.12 % FSR Gain TC2 ±9 ppm FSR/°C Full-Scale Error

3, 4

−0.14 ±0.02 +0.14 % FSR Full-Scale TC2 ±14 ppm FSR/°C DC Crosstalk4 −0.011 % FSR Internal R

OUTPUT CHARACTERISTICS,

CURRENT OUTPUT

Current Loop Compliance Voltage V

Output Current Drift vs. Time Drift after 1000 hours, ¾ scale output, TJ = 150°C

90 ppm FSR External R 140 ppm FSR Internal R

Resistive Load 1000 Ω The dc-to-dc converter has been characterized

DC Output Impedance 100 MΩ DC PSRR 0.02 1 μA/V

REFERENCE INPUT/OUTPUT

Reference Input2

Reference Input Voltage 4.95 5 5.05 V For specified performance DC Input Impedance 45 150 MΩ

Reference Output

Output Voltage 4.995 5 5.005 V TA = 25°C Reference TC2 −10 ±5 +10 ppm/°C Output Noise (0.1 Hz to 10 Hz)2 7 μV p-p Noise Spectral Density2 100 nV/√Hz At 10 kHz Output Voltage Drift vs. Time2 180 ppm Drift after 1000 hours, TJ = 150°C Capacitive Load2 1000 nF Load Current 9 mA See Figure 62 Short-Circuit Current 10 mA Line Regulation2 3 ppm/V See Figure 63 Load Regulation2 95 ppm/mA See Figure 62 Thermal Hysteresis2 160 ppm First temperature cycle

5 ppm Second temperature cycle

Assumes ideal resistor, see External Current

Setting Resistor section for more information.

SET

−

BOOST_x

2.4

BOOST_x

2.7

SET

with a maximum load of 1 kΩ, chosen such that compliance is not exceeded; see Figure 51 and the DC-DC MaxV bits in Table 28

Rev. A | Page 5 of 48

AD5735 Data Sheet

Parameter1 Min Typ Max Unit Test Conditions/Comments

DC-TO-DC CONVERTER

Switch

Switch On Resistance 0.425 Ω Switch Leakage Current 10 nA Peak Current Limit 0.8 A

Oscillator

Oscillator Frequency 11.5 13 14.5 MHz This oscillator is divided down to provide the

Maximum Duty Cycle 89.6 % At 410 kHz dc-to-dc switching frequency

DIGITAL INPUTS2 JEDEC compliant

Input High Voltage, VIH 2 V Input Low Voltage, VIL 0.8 V Input Current −1 +1 μA Per pin Pin Capacitance 2.6 pF Per pin

DIGITAL OUTPUTS2

SDO, ALERT Pins

Output Low Voltage, VOL 0.4 V Sinking 200 μA Output High Voltage, VOH DVDD − 0.5 V Sourcing 200 μA High Impedance Leakage Current −1 +1 μA High Impedance Output

2.5 pF

Capacitance

FAULT

Output Low Voltage, VOL 0.4 V 10 kΩ pull-up resistor to DVDD

0.6 V At 2.5 mA Output High Voltage, VOH 3.6 V 10 kΩ pull-up resistor to DVDD

POWER REQUIREMENTS

AVDD 9 33 V AVSS −26.4 −10.8 V DVDD 2.7 5.5 V AVCC 4.5 5.5 V AIDD 8.6 10.5 mA Voltage output mode on all channels, outputs

7 7.5 mA Current output mode on all channels

AISS −11 −8.8 mA Voltage output mode on all channels, outputs

−1.7 mA Current output mode on all channels

DICC 9.2 11 mA VIH = DVDD, VIL = DGND, internal oscillator running,

AICC 1 mA Outputs unloaded, over supplies

2.7 mA Per channel, voltage output mode, outputs

BOOST

1 mA Per channel, current output mode

Power Dissipation 173 mW AVDD = 15 V, AVSS = −15 V, dc-to-dc converter

Temperature range: −40°C to +105°C; typical at +25°C.

Guaranteed by design and characterization; not production tested.

For current outputs with internal R

and loaded with the same code.

See the Current Output Mode with Internal R

Efficiency plots in Figure 53 through Figure 56 include the I

, the offset, full-scale, and TUE measurements exclude dc crosstalk. The measurements are made with all four channels enabled

SET

section for more information about dc crosstalk.

SET

quiescent current.

BOOST

dc-to-dc converter switching frequency

unloaded, over supplies

over supplies

unloaded, over supplies

enabled, current output mode, outputs disabled

Rev. A | Page 6 of 48

Data Sheet AD5735

AC PERFORMANCE CHARACTERISTICS

AVDD = V GNDSW unless otherwise noted.

Table 2.

Parameter1 Min Typ Max Unit Test Conditions/Comments

DYNAMIC PERFORMANCE, VOLTAGE

OUTPUT Output Voltage Settling Time 11 μs 5 V step to ±0.03% FSR, 0 V to 5 V range 18 μs 10 V step to ±0.03% FSR, 0 V to 10 V range Slew Rate 1.9 V/μs 0 V to 10 V range Power-On Glitch Energy 150 nV-sec Digital-to-Analog Glitch Energy 6 nV-sec Glitch Impulse Peak Amplitude 25 mV Digital Feedthrough 1 nV-sec DAC-to-DAC Crosstalk 2 nV-sec 0 V to 10 V range Output Noise (0.1 Hz to 10 Hz

Bandwidth)

Output Noise Spectral Density 150 nV/√Hz

AC PSRR 83 dB

DYNAMIC PERFORMANCE, CURRENT

OUTPUT Output Current Settling Time 15 μs To 0.1% FSR, 0 mA to 24 mA range See Test Conditions/Comments ms

Output Noise (0.1 Hz to 10 Hz

Bandwidth)

Output Noise Spectral Density 0.5 nA/√Hz

Guaranteed by design and characterization; not production tested.

= 15 V; AVSS = −15 V; DVDD = 2.7 V to 5.5 V; AVCC = 4.5 V to 5.5 V; dc-to-dc converter disabled; AGND = DGND =

BOOST_x

= 0 V; REFIN = 5 V; voltage outputs: RL = 2 kΩ, CL = 220 pF; current outputs: RL = 300 Ω; all specifications T

0.01 LSB p-p 12-bit LSB, 0 V to 10 V range

Measured at 10 kHz, midscale output, 0 V to 10 V range

200 mV, 50 Hz/60 Hz sine wave superimposed on power supply voltage

For settling times when using the dc-to-dc converter, see Figure 47, Figure 48, and Figure 49

0.01 LSB p-p 12-bit LSB, 0 mA to 24 mA range

Measured at 10 kHz, midscale output, 0 mA to 24 mA range

MIN

to T

MAX

Rev. A | Page 7 of 48

AD5735 Data Sheet

TIMING CHARACTERISTICS

AVDD = V GNDSW unless otherwise noted.

= 15 V; AVSS = −15 V; DVDD = 2.7 V to 5.5 V; AVCC = 4.5 V to 5.5 V; dc-to-dc converter disabled; AGND = DGND =

BOOST_x

= 0 V; REFIN = 5 V; voltage outputs: RL = 1 kΩ, CL = 220 pF; current outputs: RL = 300 Ω; all specifications T

MIN

to T

MAX

Table 3.

Parameter

1, 2, 3

Limit at T

MIN

, T

Unit Description

MAX

t1 33 ns min SCLK cycle time t2 13 ns min SCLK high time t3 13 ns min SCLK low time t4 13 ns min t5 13 ns min

t6 198 ns min

falling edge to SCLK falling edge setup time

SYNC 24th/32nd SCLK falling edge to SYNC

high time

SYNC t7 5 ns min Data setup time t8 5 ns min Data hold time t9 20 μs min

rising edge to LDAC falling edge (all DACs updated or any channel has

SYNC

digital slew rate control enabled) 5 μs min

t10 10 ns min t11 500 ns max

rising edge to LDAC falling edge (single DAC updated)

SYNC

pulse width low

LDAC

falling edge to DAC output response time

LDAC t12 See Table 2 μs max DAC output settling time t13 10 ns min CLEAR high time t14 5 μs max CLEAR activation time t15 40 ns max SCLK rising edge to SDO valid t16

rising edge to DAC output response time (LDAC = 0)

SYNC 21 μs min All DACs updated 5 μs min Single DAC updated t17 500 ns min t18 800 ns min

falling edge to SYNC rising edge

LDAC

pulse width

RESET

high to next SYNC low (digital slew rate control enabled)

SYNC 20 μs min All DACs updated 5 μs min Single DAC updated

Guaranteed by design and characterization; not production tested.

All input signals are specified with t

See Figure 3, Figure 4, Figure 5, and Figure 6.

This specification applies if

LDAC

= t

= 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.2 V.

RISE

FALL

is held low during the write cycle; otherwise, see t9.

rising edge (see ) Figure 76

Rev. A | Page 8 of 48

Data Sheet AD5735

Timing Diagrams

SCLK

SYNC

SDIN

LDAC

OUT_x

LDAC = 0

OUT_x

CLEAR

OUT_x

12 24

MSB

LSB

RESET

09961-002

Figure 3. Serial Interface Timing Diagram

SCLK

SYNC

SDIN

SDO

1 1

MSB MSBLSB LSB

INPUT WORD SPECIFIES REGISTER TO BE RE AD

UNDEFINED SELECTED REGISTER DATA

24 24

NOP CONDITI ON

MSB LSB

CLOCKED OUT

Figure 4. Readback Timing Diagram

09961-003

Rev. A | Page 9 of 48

AD5735 Data Sheet

SCLK

SYN

SDIN

SDO

LSB MSB

12 16

DUT_

R/W

DUT_

AD1

SDO DISABLED

XXXD15D14 D1D0

AD0

SDO_ ENAB

STATUSSTATUSSTATUSSTATUS

09961-004

Figure 5. Status Readback During Write, Timing Diagram

200µA I

TO OUTPUT

50pF

200µA I

Figure 6. Load Circuit for SDO Timing Diagrams

VOH (MIN) OR V

(MAX)

09961-005

Rev. A | Page 10 of 48

Data Sheet AD5735

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted. Transient currents of up to 100 mA do not cause SCR latch-up.

Table 4.

Parameter Rating

AVDD, V

to AGND, DGND −0.3 V to +33 V

BOOST_x

AVSS to AGND, DGND +0.3 V to −28 V AVDD to AVSS −0.3 V to +60 V AVCC to AGND −0.3 V to +7 V DVDD to DGND −0.3 V to +7 V Digital Inputs to DGND

−0.3 V to DV

+ 0.3 V or +7 V

(whichever is less)

Digital Outputs to DGND

−0.3 V to DV

+ 0.3 V or +7 V

(whichever is less)

REFIN, REFOUT to AGND

−0.3 V to AV

+ 0.3 V or +7 V

(whichever is less)

OUT_x

to AGND

to V

or 33 V if using

BOOST_x

the dc-to-dc converter

SENSE_x

, −V

SENSE_x

to AGND

to V

or 33 V if using

BOOST_x

the dc-to-dc converter

OUT_x

to AGND

to V

or 33 V if using

BOOST_x

the dc-to-dc converter SWx to AGND −0.3 V to +33 V AGND, GNDSWx to DGND −0.3 V to +0.3 V Operating Temperature Range ( TA)

Industrial1 −40°C to +105°C Storage Temperature Range −65°C to +150°C Junction Temperature (TJ max) 125°C Power Dissipation (TJ max − TA)/θJA Lead Temperature JEDEC industry standard

Soldering J-STD-020

Power dissipated on chip must be derated to keep the junction temperature

below 125°C.

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL RESISTANCE

Junction-to-air thermal resistance (θJA) is specified for a JEDEC 4-layer test board.

Table 5. Thermal Resistance

Package Type θJA Unit

64-Lead LFCSP (CP-64-3) 20 °C/W

ESD CAUTION

Rev. A | Page 11 of 48

AD5735 Data Sheet

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

LV_D

INDI

PIN 1

ATO R

DCDC_D

SENSE_D

SET_CRSET_D

646362616059585756555453525150

SENSE_D

REFOUT

REFIN

COMP

–V

COMP

BOOST_ DVOUT_D

LV_C

SENSE_C

AVSSCOMP

OUT_C

–V

OUT_D

SET_B

SET_A

REFGND REFGND

NOTES

1.THE EXPO SED PADDLE SHOULD BE CONNECTED TO THE P OTENTI AL OF THE AV

IT IS RECOMMENDED THAT THE PADDLE BE THERMALLY CONNECTED TO A COPPER PLANE F OR ENHANCED THERMA L PERFORMANCE.

3 4 5

AD0

AD1

SYNC

SCLK

SDIN

SDO

DGND

LDAC

CLEAR

ALERT

FAULT

171819202122232425262728293031

POC

PIN, OR, ALTERNATIVELY, IT CAN BE LEFT ELECTRI CALLY UNCONNECT ED.

RESET

LV_ A

COMP

AD5735

TOP VIEW

(Not to Scale)

DCDC_A

SENSE_A+VSENSE_A

BOOST_A

–V

COMP

OUT_AIOUT_A

LV_B

OUT_B

DCDC_B

SENSE_B+VSENSE_B

–V

COMP

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

COMP I

OUT_C

BOOST_ C

GNDSW GNDSW

AGND V

BOOST_ B

OUT_B

DCDC_C

9961-006

Figure 7. Pin Configuration

Table 6. Pin Function Descriptions

Pin No. Mnemonic Description

1 R

2 R

SET_B

SET_A

An external, precision, low drift, 15 kΩ current setting resistor can be connected to this pin to improve the

temperature drift performance. For more information, see the External Current Setting Resistor section.

OUT_B

An external, precision, low drift, 15 kΩ current setting resistor can be connected to this pin to improve the

temperature drift performance. For more information, see the External Current Setting Resistor section.

OUT_A

3 REFGND Ground Reference Point for Internal Reference. 4 REFGND Ground Reference Point for Internal Reference. 5 AD0 Address Decode for the Device Under Test (DUT) on the Board. 6 AD1 Address Decode for the DUT on the Board. 7

Frame Synchronization Signal for the Serial Interface. Active low input. When SYNC is low, data is clocked

SYNC

into the input shift register on the falling edge of SCLK.

8 SCLK

Serial Clock Input. Data is clocked into the input shift register on the falling edge of SCLK. The serial interface

operates at clock speeds of up to 30 MHz. 9 SDIN Serial Data Input. Data must be valid on the falling edge of SCLK. 10 SDO Serial Data Output. Used to clock data from the serial register in readback mode (see Figure 4 and Figure 5). 11 DVDD Digital Supply Pin. The voltage range is from 2.7 V to 5.5 V. 12 DGND Digital Ground. 13

Load DAC. This active low input is used to update the DAC register and, consequently, the DAC outputs.

LDAC

When LDAC

is tied permanently low, the addressed DAC data register is updated on the rising edge of

SYNC. If LDAC is held high during the write cycle, the DAC input register is updated, but the DAC output

14 CLEAR

is updated only on the falling edge of LDAC (see ). Using this mode, all analog outputs can be

updated simultaneously. The

LDAC

pin must not be left unconnected.

Active High, Edge Sensitive Input. When this pin is asserted, the output current and voltage are set to the

Figure 3

programmed clear code bit setting. Only channels enabled to be cleared are cleared. For more information,

see the Asynchronous Clear section. When CLEAR is active, the DAC output register cannot be written to.

Rev. A | Page 12 of 48

Data Sheet AD5735

Pin No. Mnemonic Description

15 ALERT

FAU LT

17 POC

RESET 19 AVDD Positive Analog Supply Pin. The voltage range is from 9 V to 33 V. 20 COMP

21 −V

22 +V

23 COMP

24 V

25 V 26 I

BOOST_A

OUT_A

LV_A

SENSE_A

DCDC_A

Current Output Pin for DAC Channel A. 27 AVSS Negative Analog Supply Pin. The voltage range is from −10.8 V to −26.4 V. 28 COMP

29 −V

30 +V

31 V 32 COMP

33 I

OUT_B

34 V

LV_B

SENSE_B

Buffered Analog Output Voltage for DAC Channel B.

OUT_B

DCDC_B

Current Output Pin for DAC Channel B.

BOOST_B

35 AGND Ground Reference Point for Analog Circuitry. This pin must be connected to 0 V. 36 SWB

37 GNDSWB Ground Connection for DC-to-DC Switching Circuit. This pin should always be connected to ground. 38 GNDSWA Ground Connection for DC-to-DC Switching Circuit. This pin should always be connected to ground. 39 SWA

40 AVSS Negative Analog Supply Pin. The voltage range is from −10.8 V to −26.4 V. 41 SWD

42 GNDSWD Ground Connection for DC-to-DC Switching Circuit. This pin should always be connected to ground. 43 GNDSWC Ground Connection for DC-to-DC Switching Circuit. This pin should always be connected to ground. 44 SWC

Active High Output. This pin is asserted when there is no SPI activity on the interface pins for a preset time. For more information, see the Alert Output section.

Active Low, Open-Drain Output. This pin is asserted low when any of the following conditions is detected: open circuit in current mode; short circuit in voltage mode; PEC error; or an overtemperature condition (see the Fault Output section).

Power-On Condition. This pin determines the power-on condition and is read during power-on and after a device reset. If POC = 0, the device is powered up with the voltage and current channels in tristate mode. If POC = 1, the device is powered up with a 30 kΩ pull-down resistor to ground on the voltage output channel, and the current channel is in tristate mode.

Hardware Reset, Active Low Input.

Optional Compensation Capacitor Connection for V between this pin and the V

pin allows the voltage output to drive up to 2 μF. Note that the addition

OUT_A

Output Buffer. Connecting a 220 pF capacitor

OUT_A

of this capacitor reduces the bandwidth of the output amplifier, increasing the settling time. Sense Connection for the Negative Voltage Output Load Connection for V

. This pin must stay within

OUT_A

±3.0 V of AGND for specified operation. Sense Connection for the Positive Voltage Output Load Connection for V

between this pin and the V DC-to-DC Compensation Capacitor. Connect a 10 nF capacitor from this pin to ground. Used to regulate the

pin is added directly to the headroom requirement.

OUT_A

. The difference in voltage

OUT_A

feedback loop of the Channel A dc-to-dc converter. Alternatively, if using an external compensation resistor, place a resistor in series with a capacitor to ground from this pin. For more information, see the DC-to-DC Converter Compensation Capacitors section and the AI

Supply Requirements—Slewing section.

Supply for Channel A Current Output Stage (see Figure 71). This pin is also the supply for the V which is regulated to 15 V by the dc-to-dc converter. To use the dc-to-dc converter, connect this pin as shown in Figure 77.

Buffered Analog Output Voltage for DAC Channel A.

Optional Compensation Capacitor Connection for V between this pin and the V

pin allows the voltage output to drive up to 2 μF. Note that the addition

OUT_B

Output Buffer. Connecting a 220 pF capacitor

OUT_B

of this capacitor reduces the bandwidth of the output amplifier, increasing the settling time. Sense Connection for the Negative Voltage Output Load Connection for V

. This pin must stay within

OUT_B

±3.0 V of AGND for specified operation. Sense Connection for the Positive Voltage Output Load Connection for V

between this pin and the V

DC-to-DC Compensation Capacitor. Connect a 10 nF capacitor from this pin to ground. Used to regulate the

pin is added directly to the headroom requirement.

OUT_B

. The difference in voltage

OUT_B

feedback loop of the Channel B dc-to-dc converter. Alternatively, if using an external compensation resistor, place a resistor in series with a capacitor to ground from this pin. For more information, see the DC-to-DC Converter Compensation Capacitors section and the AI

Supply Requirements—Slewing section.

Supply for Channel B Current Output Stage (see Figure 71). This pin is also the supply for the V which is regulated to 15 V by the dc-to-dc converter. To use the dc-to-dc converter, connect this pin as shown in Figure 77.

Switching Output for Channel B DC-to-DC Circuitry. To use the dc-to-dc converter, connect this pin as shown in Figure 77.

Switching Output for Channel A DC-to-DC Circuitry. To use the dc-to-dc converter, connect this pin as shown in Figure 77.

Switching Output for Channel D DC-to-DC Circuitry. To use the dc-to-dc converter, connect this pin as shown in Figure 77.

Switching Output for Channel C DC-to-DC Circuitry. To use the dc-to-dc converter, connect this pin as shown in Figure 77.

Rev. A | Page 13 of 48

OUT_A

OUT_B

stage,

AD5735 Data Sheet

Pin No. Mnemonic Description

45 AVCC Supply for DC-to-DC Circuitry. The voltage range is from 4.5 V to 5.5 V. 46 V

47 I 48 COMP

49 V 50 +V

51 −V

52 COMP

53 AVSS Negative Analog Supply Pin. The voltage range is from −10.8 V to −26.4 V. 54 I 55 V 56 V

57 COMP

58 +V

59 −V

60 COMP

61 REFIN External Reference Voltage Input. 62 REFOUT

63 R

64 R

EPAD

BOOST_C

Supply for Channel C Current Output Stage (see Figure 71). This pin is also the supply for the V which is regulated to 15 V by the dc-to-dc converter. To use the dc-to-dc converter, connect this pin as shown in Figure 77.

Current Output Pin for DAC Channel C.

OUT_C

DCDC_C

DC-to-DC Compensation Capacitor. Connect a 10 nF capacitor from this pin to ground. Used to regulate the feedback loop of the Channel C dc-to-dc converter. Alternatively, if using an external compensation resistor, place a resistor in series with a capacitor to ground from this pin. For more information, see the DC-to-DC Converter Compensation Capacitors section and the AICC Supply Requirements—Slewing section.

Buffered Analog Output Voltage for DAC Channel C.

OUT_C

SENSE_C

Sense Connection for the Positive Voltage Output Load Connection for V between this pin and the V

pin is added directly to the headroom requirement.

OUT_C

Sense Connection for the Negative Voltage Output Load Connection for V ±3.0 V of AGND for specified operation.

LV_C

Optional Compensation Capacitor Connection for V between this pin and the V

pin allows the voltage output to drive up to 2 μF. Note that the addition

OUT_C

of this capacitor reduces the bandwidth of the output amplifier, increasing the settling time.

Current Output Pin for DAC Channel D.

OUT_D

Buffered Analog Output Voltage for DAC Channel D.

OUT_D

BOOST_D

Supply for Channel D Current Output Stage (see Figure 71). This pin is also the supply for the V which is regulated to 15 V by the dc-to-dc converter. To use the dc-to-dc converter, connect this pin as shown in Figure 77.

DCDC_D

DC-to-DC Compensation Capacitor. Connect a 10 nF capacitor from this pin to ground. Used to regulate the feedback loop of the Channel D dc-to-dc converter. Alternatively, if using an external compensation resistor, place a resistor in series with a capacitor to ground from this pin. For more information, see the DC-to-DC Converter Compensation Capacitors section and the AI

SENSE_D

Sense Connection for the Positive Voltage Output Load Connection for V between this pin and the V

pin is added directly to the headroom requirement.

OUT_D

Sense Connection for the Negative Voltage Output Load Connection for V ±3.0 V of AGND for specified operation.

LV_D

Optional Compensation Capacitor Connection for V between this pin and the V

pin allows the voltage output to drive up to 2 μF. Note that the addition

OUT_D

of this capacitor reduces the bandwidth of the output amplifier, increasing the settling time.

Internal Reference Voltage Output. It is recommended that a 0.1 μF capacitor be placed between REFOUT and REFGND.

SET_D

SET_C

An external, precision, low drift, 15 kΩ current setting resistor can be connected to this pin to improve the

temperature drift performance. For more information, see the External Current Setting Resistor section.

OUT_D

An external, precision, low drift, 15 kΩ current setting resistor can be connected to this pin to improve the

temperature drift performance. For more information, see the External Current Setting Resistor section.

OUT_C

Exposed Pad. The exposed paddle should be connected to the potential of the AV it can be left electrically unconnected. It is recommended that the paddle be thermally connected to a copper plane for enhanced thermal performance.

. The difference in voltage

OUT_C

. This pin must stay within

OUT_C

Output Buffer. Connecting a 220 pF capacitor

OUT_C

Supply Requirements—Slewing section.

. The difference in voltage

OUT_D

. This pin must stay within

OUT_D

Output Buffer. Connecting a 220 pF capacitor

OUT_D

pin, or, alternatively,

OUT_C

OUT_D

stage,

Rev. A | Page 14 of 48

Data Sheet AD5735

TYPICAL PERFORMANCE CHARACTERISTICS

VOLTAGE OUTPUTS

0.008 AVDD = +15V

= –15V

= 25°C

±10V RANGE

±12V RANGE

±10V RANGE WITH DC-TO-DC CONVERTER

0 1000 2000 3000 4000

CODE

09961-208

INL ERRO R (%FSR)

–0.002

–0.004

–0.006

0.006

0.004

0.002

Figure 8. Integral Nonlinearity Error vs. DAC Code Figure 11. Integral Nonlinearity Error vs. Temperature

0.008

0.006

0.004

–0.002

INL ERROR (%FSR)

–0.004

–0.006

–0.008

0.002

+5V RANGE MAX INL ±10V RANGE MAX INL ±12V RANGE MAX INL

+5V RANGE MIN INL ±10V RANGE MIN INL ±12V RANGE MIN INL

–40 –20 0 20 40 60

TEMPERATURE (°C)

AVDD=+15V

= –15V

OUTPUT UNLOADED

100

09961-211

1.0

AVDD = +15V AV

= –15V

= 25°C

±10V RANGE

±12V RANGE

±10V RANGE WITH DC-TO-DC CONVERTER

0 1000 2000 3000 4000

AVDD = +15V AV

= –15V

= 25°C

±10V RANGE

±12V RANGE

±10V RANGE WITH DC-TO-DC CONVERTER

0 1000 2000 3000 4000

CODE

DNL ERROR (LSB)

TOTAL UNADJUSTED ERROR (%FSR)

0.8

0.6

0.4

0.2

–0.2

–0.4

–0.6

–0.8

–1.0

0.02

0.01

–0.01

–0.02

–0.03

–0.04

1.0

AVDD = +15V

= –15V

0.8

0.6

0.4

0.2

–0.2

DNL ERRO R (LSB)

–0.4

–0.6

–0.8

–1.0

–40 –20 0 20 40 60 80 100

09961-209

ALL RANGES

MAX DNL

MIN DNL

TEMPERATURE (°C)

09961-212

Figure 12. Differential Nonlinearity Error vs. Temperature Figure 9. Differential Nonlinearity Error vs. DAC Code

0.06

0.05

+5V RANGE

0.04

0.03

0.02

0.01

TOTAL UNADJUSTED ERROR (%FSR)

–0.01

–40 –20 0 20 40 60 80 100

09961–210

±10V RANGE ±12V RANGE

AVDD = +15V AV

= –15V

OUTPUT UNLOADED

TEMPERATURE (°C)

09961-129

Figure 13. Total Unadjusted Error vs. Temperature Figure 10. Total Unadjusted Error vs. DAC Code

Rev. A | Page 15 of 48

+ 33 hidden pages

ANALOG DEVICES AD5735 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

PRODUCT HIGHLIGHTS

COMPANION PRODUCTS

TABLE OF CONTENTS

REVISION HISTORY

DETAILED FUNCTIONAL BLOCK DIAGRAM

SPECIFICATIONS

AC PERFORMANCE CHARACTERISTICS

TIMING CHARACTERISTICS

Timing Diagrams

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

VOLTAGE OUTPUTS