Datasheet AD5725 Datasheet (ANALOG DEVICES)

Quad, 12-Bit, Parallel Input,

A

V

A

A

Unipolar/Bipolar, Voltage Output DAC

AD5725

FEATURES

+5 V to ±15 V operation
Unipolar or bipolar operation
±0.5 LSB max INL error, ±1 LSB max DNL error
Settling time: 10 μs max (10 V step)
Double-buffered inputs
Simultaneous updating via
Asynchronous

CLR

to zero/mid scale

LDAC

Readback
Operating temperature range: −40°C to +85°C

®

iCMOS

process technology

APPLICATIONS

Industrial automation
Closed-loop servo control, process control

R/W

CS

DB0

TO

DB11

V

L

A0

A1

FUNCTIONAL BLOCK DIAGRAM

V

V

DD

SS

I/O

REGISTER

AND

CONTROL

LOGIC

12

AD5725

DGND

12

INPUT
REG A

INPUT
REG B

INPUT
REG C

INPUT
REG D

Figure 1.

DAC

REG A

DAC

REG B

DAC

REG C

DAC

REG D

12

12

12

12

V

DAC A

DAC B

DAC C

DAC D

REFNLDACCLR

REFP

V

V

V

V

Automotive test and measurement
Programmable logic controllers

GENERAL DESCRIPTION

The AD5725 is a quad, 12-bit, parallel input, voltage output
digital-to-analog converter that offers guaranteed monotonicity,
integral nonlinearity (INL) of ±0.5 LSB maximum and 10 μs
maximum settling time.

Output voltage swing is set by two reference inputs, V
V

. By setting the V

REFN

input to 0 V and the V

REFN

REFP

REFP

to a

and

positive voltage, the DAC provides a unipolar positive output
range. A similar configuration with V

at 0 V and V

REFP

REFN

at a
negative voltage provides a unipolar negative output range.
Bipolar outputs are configured by connecting both V
V

to nonzero voltages. This method of setting output voltage

REFN

REFP

and

ranges has advantages over the bipolar offsetting methods
because it is not dependent on internal and external resistors
with different temperature coefficients.

iCMOS® Process Technology
For analog systems designers within industrial/instrumentation equipment OEMs who need high performance ICs at higher-voltage levels, iCMOS is a technology
platform that enables the development of analog ICs capable of 30 V and operating at ±15 V supplies while allowing dramatic reductions in power consumption and
package size, and increased ac and dc performance.

Digital controls allow the user to load or read back data from
any DAC, load any DAC, and transfer data to all DACs at
one time.

The AD5725 is available in a 28-lead SSOP package. It can be
operated from a wide variety of supply and reference voltages,
with supplies ranging from single +5 V to ±15 V, and references
from +2.5 V to ±10 V. Power dissipation is less than 270 mW
with ±15 V supplies and only 40 mW with a +5 V supply.
Operation is specified over the temperature range of −40°C
to +85°C.

OUT

OUTB

OUTC

OUTD

06442-001

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2007–2008 Analog Devices, Inc. All rights reserved.

AD5725

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1 

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

AC Performance Characteristics ................................................ 5

Timing Characteristics, ............................................................... 6

Absolute Maximum Ratings ............................................................ 8

ESD Caution .................................................................................. 8

Pin Configuration and Function Descriptions ............................. 9

Typical Performance Characteristics ........................................... 10

Terminology .................................................................................... 14

REVISION HISTORY

12/08—Rev. 0 to Rev. A

Changes to Figure 26 ...................................................................... 13

7/07—Revision 0: Initial Version

Theory of Operation ...................................................................... 15

DAC Architecture ....................................................................... 15

Output Amplifiers ...................................................................... 15

Reference Inputs ......................................................................... 15

Parallel Interface ......................................................................... 15

Data Coding ................................................................................ 15

CLR

.............................................................................................. 15

Power Supplies ............................................................................ 17

Reference Configuration ........................................................... 17

Single +5 V Supply Operation .................................................. 18

Outline Dimensions ....................................................................... 19

Ordering Guide .......................................................................... 19

Rev. A | Page 2 of 20

AD5725

SPECIFICATIONS

AVDD = +15 V, AVSS = −15 V, DGND = 0 V; V

Table 1.

Parameter Value Unit Test Conditions/Comments

ACCURACY Outputs unloaded

Resolution 12 Bits
Relative Accuracy (INL) ±0.5 LSB max B grade
±1 LSB max A grade
Differential Nonlinearity (DNL) ±1 LSB max Guaranteed monotonic
Zero-Scale Error ±2 LSB max RL = 2 kΩ
Zero-Scale TC2 ±15 ppm FSR/°C typ RL = 2 kΩ
Full-Scale Error ±2 LSB max RL = 2 kΩ
Full-Scale TC2 ±20 ppm FSR/°C typ RL = 2 kΩ

REFERENCE INPUT

V

REFP

Reference Input Range3 V
AVDD − 2.5 V max
Input Current ±2.75 mA max Typically 1.5 mA

V

REFN

Reference Input Range3 −10 V min
V
Input Current2 2.75 mA max Typically 2 mA

Large Signal Bandwidth2 160 kHz typ −3 dB, V

OUTPUT CHARACTERISTICS2

Output Current ±5 mA max RL = 2 kΩ, CL = 100 pF

DIGITAL INPUTS VL = 2.7 V to 5.5 V, JEDEC compliant

VIH, Input High Voltage 2.4 V min TA = 25°C
VIL, Input Low Voltage 0.8 V max TA = 25°C
Input Current2 1 μA max
Input Capacitance2 8 pF typ

DIGITAL OUTPUTS (SDO)

VOH, Output High Voltage 4 V min IOH = 0.4 mA
VOL, Output Low Voltage 0.4 V max IOL = −1.6 mA

POWER SUPPLY CHARACTERISTICS

Power Supply Sensitivity

2

30 ppm FSR/V max 14.25 V ≤ AV

AIDD 3 mA/channel max Outputs unloaded, V
AISS 2.5 mA/channel max Outputs unloaded, typically 1.625 mA
Power Dissipation 270 mW max

1

All supplies can be varied ±5%, and operation is guaranteed. Device is tested with nominal supplies.

2

Guaranteed by design and characterization, not production tested.

3

Operation is guaranteed over this reference range, but linearity is neither tested nor guaranteed.

= +10 V; V

REFP

+ 2.5 V min

REFN

− 2.5 V max

REFP

= −10 V, VL = 5 V. All specifications T

REFN

MIN

= 0 V to 10 V p-p

REFP

≤ 15.75 V

DD

to T

, unless otherwise noted.1

MAX

= 2.5 V, typically 2.125 mA

REFP

Rev. A | Page 3 of 20

AD5725

AVDD = +5 V, AVSS = −5 V/0 V, DGND = 0 V; V
otherwise noted.

Table 2.

Parameter Value Unit Test Conditions/Comments

ACCURACY Outputs unloaded

Resolution 12 Bits
Relative Accuracy (INL) ±0.5 LSB max B grade

±1 LSB max A grade
±1 LSB max B grade, AVSS = 0 V1

±2 LSB max A grade, AVSS = 0 V1
Differential Nonlinearity (DNL) ±1 LSB max Guaranteed monotonic
Zero-Scale Error ±5 LSB max AVSS = −5 V

±10 LSB max AVSS = 0 V
Zero-Scale TC2 100 ppm FSR/°C typ
Full-Scale Error ±5 LSB max AVSS = −5 V

±10 LSB max AVSS = 0 V
Full-Scale TC2 100 ppm FSR/°C typ

REFERENCE INPUT

V

REFP

Reference Input Range3 V
AVDD − 2.5 V max
Input Current2 ±0.5 mA max Code 0x0000

V

REFN

Reference Input Range3 −2.5 V min AVSS = −5 V
0 V min AVSS = 0 V
V

Large Signal Bandwidth2 450 kHz typ −3 dB, V

OUTPUT CHARACTERISTICS2

Output Current ±1.25 mA max RL = 2 kΩ, CL = 100 pF

DIGITAL INPUTS VL = 2.7 V to 5.5 V, JEDEC compliant

VIH, Input High Voltage 2.4 V min TA = 25°C
VIL, Input Low Voltage 0.8 V max TA = 25°C
Input Current2 1 μA max
Input Capacitance2 8 pF typ

DIGITAL OUTPUTS (SDO)

VOH, Output High Voltage 4 V min IOH = 0.4 mA
VOL, Output Low Voltage 0.4 V max IOL = −1.6 mA

POWER SUPPLY CHARACTERISTICS

Power Supply Sensitivity

2

100 ppm FSR/V typ

AIDD 2 mA/channel max Outputs unloaded.
AISS 1.5 mA/channel max Outputs unloaded, A
Power Dissipation 70 mW max AVSS = −5 V
40 mW max AVSS = 0 V

1

For single supply operation only (V

2

Guaranteed by design and characterization, not production tested.

3

Operation is guaranteed over this reference range, but linearity is neither tested nor guaranteed.

= 0 V, AVSS = 0 V): Due to internal offset errors, INL and DNL are measured beginning at code 0x005.

REFN

= +2.5 V; V

REFP

+ 2.5 V min

REFN

− 2.5 V max

REFP

= −2.5 V/0 V, VL = 5 V. All specifications T

REFN

to T

MIN

= 0 V to 2.5 V p-p

REFP

MAX

= −5 V

VSS

, unless

Rev. A | Page 4 of 20

AD5725

AC PERFORMANCE CHARACTERISTICS1

AVDD = +15 V/+5 V, AVSS = −15 V/−5 V/0 V, DGND = 0 V; V
T

to T

MIN

, unless otherwise noted.

MAX

Table 3.

Parameter A Grade B Grade Unit Test Conditions/Comments

DYNAMIC PERFORMANCE

Output Voltage Settling Time 10 10 μs typ To 0.01%, 10 V step, RL = 1 kΩ

7 7 μs typ To 0.01%, 2.5 V step, RL = 1 kΩ

Slew Rate 2.2 2.2 V/μs typ 10% to 90%
Analog Crosstalk 72 72 dB typ
Digital Feedthrough 5 5 nV-s typ

1

Guaranteed by design and characterization, not production tested.

= +10 V/+2.5 V; V

REFP

= −10 V/−2.5 V/0 V, VL = 5 V. All specifications

REFN

Rev. A | Page 5 of 20

AD5725

TIMING CHARACTERISTICS

AVDD = +5 V/+15 V, AVSS = −5 V/0 V/−15 V, DGND = 0 V; V
T

to T

MIN

Table 4.

Parameter Limit at T

t

10 ns min Chip Select Write Pulse Width

WCS

tWS 0 ns min Write Setup, t
tWH 0 ns min Write Hold, t
tAS 0 ns min Address Setup
tAH 0 ns min Address Hold
tLS 5 ns min Load Setup
tLH 5 ns min Load Hold
t

5 ns min Write Data Setup, t

WDS

t

0 ns min Write Data Hold, t

WDH

t

10 ns min Load Data Pulse Width

LDW

t

10 ns min Reset Pulse Width

RESET

t

30 ns min Chip Select Read Pulse Width

RCS

t

0 ns min Read Data Hold, t

RDH

t

0 ns min Read Data Setup, t

RDS

tDZ 15 ns max Data to High-Z, CL = 10 pF
t

35 ns max Chip Select to Data, CL = 100 pF

CSD

1

All input control signals are specified with tr = tf = 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V.

2

Guaranteed by design and characterization, not production tested.

, unless otherwise noted.

MAX

1, 2

= +2.5 V/+10 V; V

REFP

, T

Unit Description

MIN

MAX

= −2.5 V/0 V/−10 V, VL = 5 V. All specifications

REFN

= 10 ns

WCS

= 10 ns

WCS

= 10 ns

WCS

= 10 ns

WCS

= 30 ns

RCS

= 30 ns

RCS

Rev. A | Page 6 of 20

AD5725

Timing Diagrams

10ns

R/W

ADDRESS

LDAC

DATA IN

CS

t

WS

t

AS

ADDRESS

ONE

t

LS

t

WDS

DATA1

VALID

ADDRESS

TWO

DATA2

VALID

ADDRESS

THREE

DATA3

VALID

ADDRESS

FOUR

DATA4

VALID

t

WH

t

LH

t

WDH

Figure 4. Single Buffer Mode Timing

CS

R/W

A0/A1

DATA

OUT

t

RCS

t

RDS

t

AS

HIGH-Z HIGH-Z

t

CSD

DATA VALID

t

RDH

t

AH

t

DZ

Figure 2. Data Read Timing

6442-002

06442-004

10ns

t

WS

t

AS

ADDRESS

ONE

t

WDS

DATA1

VALID

ADDRESS

TWO

DATA2

VALID

ADDRESS

THREE

DATA3

VALID

Figure 5. Double Buffer Mode Timing

ADDRESS

FOUR

t

LS

DATA4

VALID

t

t

LDW

t

WH

LH

t

WDH

06442-005

CS

R/W

A0/A1

LDAC

DATA IN

RESET

t

t

WS

t

AS

t

LS

t

WDS

t

RESET

Figure 3. Data Write Timing

WCS

t

WH

t

AH

t

WDH

t

LDW

06442-003

t

LH

CS

R/W

ADDRESS

LDAC

DATA IN

Rev. A | Page 7 of 20

AD5725

ABSOLUTE MAXIMUM RATINGS

TA = 25°C unless otherwise noted. Transient currents of up to
100 mA do not cause SCR latch-up.

Table 5.

Parameter Rating

AVSS to DGND +0.3 V to −16.5 V
AVDD to DGND −0.3 V to +16.5 V
AV

to AVDD +0.3 V to −33 V

SS

VL to DGND −0.3 V to +7 V
Current into Any Pin ±15 mA
Digital Pin Voltage to DGND −0.3 V to +7 V
Operating Temperature Range

Industrial −40°C to +85°C

Storage Temperature Range −65°C to +150°C
Junction Temperature (TJ max) 105°C
28-Lead SSOP Package

θJA Thermal Impedance 100°C/W
θJC Thermal Impedance 39°C/W
Power Dissipation Package

(Derate 10 mW/°C Above 70°C)

Reflow Soldering

Time at Peak Temperature 10 sec to 40 sec
Lead Temperature (Soldering, 60 sec) 300°C

900 mW

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

Rev. A | Page 8 of 20

AD5725

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

V

Table 6. Pin Function Descriptions

Pin No. Mnemonic Description

1 V

REFP

Positive DAC Reference Input. The voltage applied to this pin defines the full-scale output voltage.

Allowable range is AV
2 V
3 V
4 AV
5 DGND
6

Buffered Analog Output Voltage of DAC B.

OUTB

Buffered Analog Output Voltage of DAC A.

OUTA

Negative Analog Supply Pin. Voltage ranges from 0 V to −15 V.

SS

Digital Ground Pin.

CLR Active Low Input. Sets input registers and DAC registers to zero scale (0x000) for the AD5725-1 or midscale

(0x800) for the AD5725.
7

LDAC
8 DB0
9 DB1
10 DB2
11 DB3
12 DB4
13 DB5
14 DB6
15 DB7
16 DB8
17 DB9

18 DB10
19 DB11
20

R/W

21 A1
22 A0
23

24 V
25 AV
26 V
27 V
28 V

CS

Voltage Supply for Readback Function. Can be left open circuit if not used.

L

DD

OUTD

OUTC

REFN

Read/Write Pin. Active low to write data to DAC; Active high to read back previous data at data bit pins with

Positive Analog Supply Pin. Voltage ranges from +5 V to +15 V.

Buffered Analog Output Voltage of DAC D.

Buffered Analog Output Voltage of DAC C.

Active Low Load DAC Input.
Data Bit 0 (LSB).

Data Bit 1.
Data Bit 2.
Data Bit 3.
Data Bit 4.
Data Bit 5.
Data Bit 6.
Data Bit 7.
Data Bit 8.
Data Bit 9.
Data Bit 10.
Data Bit 11 (MSB).

V

connected to +5 V.

L

Address Bit 1.
Address Bit 0.
Active Low Chip Select Pin.

Negative DAC Reference Input. The voltage applied to this pin defines the zero-scale output voltage.
Allowable range is AV

1

REFP

V

2

OUTB

V

3

OUTA

4

AV

SS

DGND

5

6

7

8

9

10

11

12

13

14

AD5725

TOP VIEW

(Not to Scale)

CLR

LDAC

DB0 (LSB)

DB1

DB2

DB3

DB4

DB5

DB6

Figure 6. Pin Configuration Diagram

− 2.5 V to V

DD

to V

SS

REFP

REFN

− 2.5 V.

+ 2.5 V.

V

28

REFN

27

V

OUTC

V

26

OUTD

AV

25

24

V

L

CS

23

A0

22

21

A1

20

R/W

DB11 (MSB)

19

DB10

18

17

DB9

DB8

16

DB7

15

DD

6442-006

Rev. A | Page 9 of 20

AD5725

TYPICAL PERFORMANCE CHARACTERISTICS

1.0
AVDD = +15V

AV

= –15V

SS

0.8
V

= –10V

REFN

T

= 25°C

A

0.6

0.4

0.2

0

–0.2

–0.4

MAX DNL ERROR (LSB)

–0.6

–0.8

–1.0

612

7891011

V

(V)

Figure 7. DNL vs. V

REFP

REFP

(V

SUPPLY

= ±15 V)

06442-017

0.5
AVDD = 5V
AV

= 0V

SS

0.4
V

= 0V

REFN

T

= 25°C

A

0.3

0.2

0.1

0

–0.1

MAX INL ERROR (LSB)

–0.2

–0.3

–0.4

1.0 3.0

1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8

V

(V)

REFP

Figure 10. INL vs. V

REFP

(V

SUPPLY

= +5 V)

06442-020

0.05

0

–0.05

–0.10

–0.15

MAX DNL ERROR (LSB)

AVDD = 5V

–0.20

AV

= 0V

SS

V

= 0V

REFN

T

= 25°C

A

–0.25

1.0 3.0

1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8

V

(V)

REFP

Figure 8. DNL vs. V

1.0
AVDD = +15V
AV

0.8

0.6

0.4

0.2

–0.2

–0.4

MAX INL ERROR (LSB)

–0.6

–0.8

–1.0

= –15V

SS

V

= –10V

REFN

T

= 25°C

A

0

612

7 8 9 10 11

Figure 9. INL vs. V

V

REFP

REFP

REFP

(V

(V

(V)

SUPPLY

SUPPLY

= +5 V)

= ±15 V)

06442-018

06442-019

0

AVDD = +15V
AV

= –15V

SS

= +10V

V

–0.1

REFP

V

= –10V

REFN

2k LOAD

–0.2

–0.3

–0.4

–0.5

FULL-SCAL E ERROR (LSB)

–0.6

–0.7

DAC B

–40 80

–20 0 20 40 60

Figure 11. Full-Scale Error vs. Temperature

0.3
AVDD = +15V

= –15V

AV

SS

= +10V

V

REFP

0.2

0.1

–0.1

ZERO-SCALE ERROR (LSB)

–0.2

–0.3

= –10V

V

REFN

2k LOAD

0

DAC D

DAC B

–40 80

–20 0 20 40 60

Figure 12. Zero-Scale Error vs. Temperature

DAC A

DAC C

DAC A

TEMPERATURE ( °C)

TEMPERATURE ( °C)

DAC D

DAC C

06442-023

06442-024

Rev. A | Page 10 of 20

AD5725

0.3

0.4

0.2

0.1

0

INL ERROR (L SB)

–0.1

AVDD = +15V
AV

= –15V

SS

–0.2

–0.3

= +10V

V

REFP

= –10V

V

REFN

T

= 25°C

A

0 500 1000 1500 2000 2500 3000 3500 4000

DAC (Code)

Figure 13. Channel-to-Channel Matching (V

SUPPLY

0.3

0.2

0.1

0

–0.1

INL ERROR (L SB)

–0.2

AVDD = 5V

= 0V

AV

SS

= 2.5V

V

–0.3

REFP

= 0V

V

REFN

= 25°C

T

A

–0.4

0 500 1000 1500 2000 2500 3000 3500 4000

DAC (Code)

Figure 14. Channel-to-Channel Matching (V

SUPPLY

DAC A
DAC B
DAC C
DAC D

= ±15 V)

DAC A
DAC B
DAC C
DAC D

= +5 V)

0.3

+85°C

0.2

+25°C
–40°C

0.1

0

–0.1

INL ERROR (L SB)

–0.2

AVDD = +15V
AV

= –15V

SS

–0.3

–0.4

06442-025

= +10V

V

REFP

= –10V

V

REFN

0 500 1000 1500 2000 2500 3000 3500 4000

DAC (Code)

06442-028

Figure 16. INL vs. DAC Code

0.20

0.15

0.10

0.05

0

–0.05

DNL ERRO R (LSB)

–0.10

AVDD = +15V

= –15V

AV

SS

–0.15

–0.20

06442-026

= +10V

V

REFP

= –10V

V

REFN

0 500 1000 1500 2000 2500 3000 3500 4000

DAC (Code)

+85°C
+25°C
–40°C

06442-042

Figure 17. DNL vs. DAC Code

16

14

12

10

8

(mA)

DD

I

6

4

AVDD = +15V

= –15V

AV

SS

= –10V

V

REFN

2

DIGITAL INPUTS HIGH

= 25°C

T

A

0

–7 13

–5–3–11357911

V

(V)

REFP

Figure 15. IDD vs. V

REFP

06442-027

Rev. A | Page 11 of 20

1.7995

1.5995

AV

SS

= –15V

V

REFP

= +10V V

REFN

= –10V TA = 25°CAVDD = +15V

1.3995

1.1995

0.9995

(mA)

0.7995

REFP

IV

0.5995

0.3995

0.1995

–0.0005

0 4000

500 1000 1500 2000 2500 3000 3500

DAC (Code)

Figure 18. IV

vs. DAC Code

REFP

06442-029

AD5725

12

AVDD = +15V
AV

= –15V

SS

= +10V

V

REFP

10

V
T

REFN
A

= –10V

= 25°C

8

6

4

FULL-SCALE VOLTAGE (V)

2

0

0.01 100

0.1 1 10

LOAD RESISTANCE (k)

Figure 19. Output Voltage Swing vs. Resistive Load

06442-035

1.0

0.9

0.8

0.7

AVDD = +15V
AV
V

REFP

V

REFN

T

A

0.6

0.5

0.4

0.3

NOISE DENSI TY (mV)

0.2

0.1

0

–0.1

1 100k

10 100 1k 10k

NOISE FREQ UENCY (Hz)

Figure 22. Output Noise Spectral Density vs. Frequency

= –15V

SS

= +10V
= –10V

= 25°C

06442-044

2

0

–2

–4

–6

–8

GAIN (dB)

–10

AVDD = +15V

= –15V

AV

SS

–12

V

= 0V ± 100mV

REFP

= –10V

V

REFN

–14

DATA BITS = +5V

= 25°C

T

A

–16

10 10M

100 1k 10k 100k 1M

FREQUENCY (Hz)

Figure 20. Small Signal Response

8

I

DD

I

SS

POWER SUPPL Y CURRENT (mA)

6

AVDD = +15V

4

AV

2

0

–2

–4

–6

SS

= –15V

20

AVDD = +15V
AV

= –15V

SS

15

10

= +10V

V

REFP

= –10V

V

REFN

T

= 25°C

A

DATA = 0x000

5

(µA)

0

OUT

I

–5

–10

–15

–20

–15 15

06442-036

25

20

15

–10 –5 0 5 10

V

(V)

OUT

Figure 23. I

AVDD = 15V

= 0V

AV

SS

= 10V

V

REFP

V

= 0V

REFN

= 25°C

T

A

DATA = 0x800

OUT

vs. V

OUT

(V

SUPPLY

= ±15 V)

06442-040

10

(µA)

OUT

5

I

0

–5

–8

–35 85

–15 5 25 45 65

TEMPERATURE ( °C)

Figure 21. Power Supply Current vs. Temperature

06442-045

Rev. A | Page 12 of 20

–10

01

123456789

V

(V)

OUT

Figure 24. I

OUT

vs. V

OUT

(V

SUPPLY

= +15 V)

0

06442-041

AD5725

AVDD = +15V
AV

= –15V

SS

1

CH1 50µV M 2s A CH1 0V

V
V

REFP
REFN

= +10V
= –10V

= 25°C

T

A

BW = 100kHz

Figure 25. Broadband Noise

1.0

0.8

0.6

0.4

0.2

0

GLITCH AMP LITUDE (V)

–0.2

–0.4

06442-046

0 1000900800700600500400300200100

Figure 26. Output Glitch

0x800  0x7FF ( ±15V SUPPLY )
0x7FF  0x800 ( ±15V SUPPLY )
0x800  0x7FF ( ±5V SUPPLY )
0x7FF  0x800 ( ±5V SUPPLY )

TIME (ns)

06442-043

Rev. A | Page 13 of 20

AD5725

TERMINOLOGY

Relative Accuracy or Integral Nonlinearity (INL)

For the DAC, relative accuracy or integral nonlinearity is a
measure of the maximum deviation, in LSBs, from a straight
line passing through the endpoints of the DAC transfer
function. A typical INL vs. code plot can be seen in Figure 16.

Differential Nonlinearity (DNL)

Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ±1 LSB maximum
ensures monotonicity. This DAC is guaranteed monotonic by
design. A typical DNL vs. code plot can be seen in Figure 17.

Monotonicity

A DAC is monotonic if the output either increases or remains
constant for increasing digital input code. The AD5725 is
monotonic over its full operating temperature range.

Full-Scale Error

Full-scale error is a measure of the output error when full-scale
code is loaded to the DAC register. Ideally, the output should be
V

− 1 LSB. Full-scale error is expressed in LSBs. A plot of

REFP

full-scale error vs. temperature can be seen in Figure 11.

Full-Scale Error TC

Full-scale error TC is a measure of the change in full-scale error
with a change in temperature. Full-scale error TC is expressed
in ppm FSR/°C.

Zero-Scale Error

Zero-scale error is the error in the DAC output voltage when
0x0000 (straight binary coding) is loaded to the DAC register.
Ideally, the output voltage should be V
error vs. temperature can be seen in Figure 12.

. A plot of zero-scale

REFN

Zero-Scale Error TC

Zero-scale error TC is a measure of the change in zero-scale
error with a change in temperature. Zero-scale error TC is
expressed in ppm FSR/°C.

Output Voltage Settling Time

Output voltage settling time is the amount of time it takes for
the output to settle to a specified level for a full-scale input
change.

Slew Rate

The slew rate of a device is a limitation in the rate of change of
the output voltage. The output slewing speed of a voltage­output DAC is usually limited by the slew rate of the amplifier
used at its output. Slew rate is measured from 10% to 90% of the
output signal and is given in V/μs.

Digital Feedthrough

Digital feedthrough is a measure of the impulse injected into
the analog output of the DAC from the digital inputs of the
DAC, but it is measured when the DAC output is not updated.
It is specified in nV-sec and measured with a full-scale code
change on the data bus.

Power Supply Sensitivity

Power supply sensitivity indicates how the output of the DAC is
affected by changes in the power supply voltage.

Analog Crosstalk

Analog crosstalk is the dc change in the output level of one
DAC in response to a change in the output of another DAC. It is
measured with a full-scale output change on one DAC while
monitoring another DAC. It is expressed in dB.

Rev. A | Page 14 of 20

AD5725

(

THEORY OF OPERATION

The AD5725 is a quad voltage output, 12-bit parallel input DAC
featuring a 12-bit data bus with readback capability. The AD5725
operates from single or dual supplies ranging from +5 V up to
±15 V. The output voltage range is set by the reference voltages
applied at the V

REFP

and V

REFN

pins.

DAC ARCHITECTURE

Each of the four DACs is a voltage switched, high impedance
(50 kΩ), R-2R ladder configuration. Each 2R resistor is driven
by a pair of switches that connect the resistor to either V
or V

.

REFL

REFH

OUTPUT AMPLIFIERS

The output amplifiers are capable of generating both unipolar
and bipolar output voltages. They are capable of driving a load
of 2 kΩ in parallel with 500 pF to DGND. The source and sink
capabilities of the output amplifiers can be seen in Figure 23
and Figure 24. The slew rate is 2.2 V/μs with a full-scale settling
time of 10 μs. The amplifiers are short-circuit protected.

Careful attention to grounding is important for accurate
operation of the AD5725. With four outputs and two references
there is potential for ground loops. Since the AD5725 has no
analog ground, the ground must be specified with respect to the
reference.

REFERENCE INPUTS

All four DACs share common positive reference (V
negative reference (V

) inputs. The voltages applied to these

REFN

reference inputs set the output high and low voltage limits on all
four of the DACs. Each reference input has voltage restrictions
with respect to the other reference and to the power supplies.
V

can be any voltage between AVSS and V

REFN

V

can be any value between AVDD – 2.5 V and

REFP

V

+ 2.5 V. Note that because of these restrictions, the

REFN

AD5725 references cannot be inverted (V
greater than V

REFP

).

It is important to note that the AD5725 V

REFP

cannot be

REFN

input both sinks

REFP

and sources current. Also, the input current of both V
V

are code dependent. Many references have limited current

REFN

sinking capability and must be buffered with an amplifier to
drive V

REFP

. The V

reference input has no such special

REFN

requirements.

It is recommended that the reference inputs be bypassed with

0.2 μF capacitors when operating with ±10 V references. This
limits the reference bandwidth.

) and

REFP

− 2.5 V and

and

REFP

PARALLEL INTERFACE

See Tab le 7 for the digital control logic truth table. The parallel
interface consists of a 12-bit bidirectional data bus, two register
select inputs, A0 and A1, a R/
load DAC (

LDAC

) input. Control of the DACs and bus

direction is determined by these inputs as shown in .

W

input, a chip select (CS), and a

Tabl e 7
Digital data bits are labeled with the MSB defined as Data Bit 11
and the LSB as Data Bit 0. All digital pins are TTL/CMOS
compatible.

The register select inputs A0 and A1 select individual DAC
Register A (Binary Code 00) through Register D (Binary Code 11).
Decoding of the registers is enabled by the

CS

input. When CS
is high, no decoding takes place, and neither the writing nor the
reading of the input registers is enabled. The loading of the
second bank of registers is controlled by the asynchronous
LDAC

input. By taking

registers can be updated simultaneously. Note that the t

LDAC

low while CS is high, all output

LDW

required pulse width for updating all DACs is a minimum of
10 ns. The R/

W

input, when enabled by CS, controls the writing

to and reading from the input register.

DATA CODING

The AD5725 uses binary coding. The output voltage can be
calculated as follows:

)

DVV

×−

VV

+=

OUT

D is the digital code in decimal.

where

REFN

REFNREFP

4096

CLR

CLR

The
during the DACs operation. The
of
midscale code (0x800) for the AD5725 or zero code (0x000) for
the AD5725-1. The
the DAC is configured for bipolar references and an output of

0 V is desired.

function can be used either at power-up or at any time

CLR

function is independent

CS

. This pin is active low and sets the DAC registers to either

CLR

to midscale code is most useful when

Rev. A | Page 15 of 20

AD5725

Table 7. AD5725 Logic Truth Table

A1 A0 R/W

Low Low Low Low High Low Write Write Transparent A
Low High Low Low High Low Write Write Transparent B
High Low Low Low High Low Write Write Transparent C
High High Low Low High Low Write Write Transparent D
Low Low Low Low High High Write Hold Write Input A
Low High Low Low High High Write Hold Write Input B
High Low Low Low High High Write Hold Write Input C
High High Low Low High High Write Hold Write Input D
Low Low High Low High High Read Hold Read Input A
Low High High Low High High Read Hold Read Input B
High Low High Low High High Read Hold Read Input C
High High High Low High High Read Hold Read Input D
X X X High High Low Hold Update all DAC registers All
X X X High High High Hold Hold Hold All
X X X X Low X All Registers set to mid/zero scale All
X X X High

CS

CLR

LDAC

X All Registers latched to mid/zero scale All

INPUT REG DAC REG MODE DAC

Rev. A | Page 16 of 20

AD5725

V

V

POWER SUPPLIES

Power supplies required are AVSS, AVDD, and VL. The AVSS
supply can be set between −15 V and 0 V. AV

is the positive

DD

supply; its operating range is between +5 V and +15 V.

is the digital output supply voltage for the readback function.

V

L

It is normally connected to +5 V. This pin is a logic reference
input only. It does not supply current to the device. If the readback
function is not used, V

can be left open-circuit. While VL does

L

not supply current to the AD5725, it does supply current to the
digital outputs when the readback function is used.

REFERENCE CONFIGURATION

Output voltage ranges can be configured as either unipolar or
bipolar, and within these choices, a wide variety of options
exists. The unipolar configuration can be either a positive or a
negative voltage output, and the bipolar configuration can be
either symmetrical or nonsymmetrical.

+15

INPUT

ADR01

BALANCE

100k

GAIN
100k

+

V

OUTPUT

TRIM

OP1177

10k

+10V OPERATION

0.2µF

V

REFP

REFN

Figure 27. Unipolar +10 V Operation

+15

39k

46

12

AD688 FOR ±10V
AD588 FOR ±5V

5

138

3

6.2

1

0.2µF

14

6.2

15

0.2µF

7

1µF

±5 OR ±10V OPERATION

Figure 28. Symmetrical Bipolar Operation

+15V

AV

DD

AD5725

AV

SS

–15V

+15V

AV

V

REFP

AD5725

V

REFN

AV

–15V

0.1µF

10µF

06442-007

DD

0.1µF

10µF

SS

06442-008

Figure 28 (Symmetrical Bipolar Operation) shows the AD5725
configured for ±10 V operation. See the AD688 data sheet for a
full explanation of reference operation. Adjustments may not be
required for many applications since the AD688 is a very high
accuracy reference. However, if additional adjustments are
required, adjust the AD5725 full scale first. Begin by loading the
digital full-scale code (0xFFF). Then, adjust the gain adjust
potentiometer to attain a DAC output voltage of 9.9976 V.
Then, adjust the balance adjust to set the mid-scale output
voltage to 0.000 V.

The 0.2 μF bypass capacitors shown at the reference inputs in
Figure 28 should be used whenever ±10 V references are used.
Applications with single references or references to ±5 V may
not require the 0.2 μF bypassing. The 6.2 Ω resistor in series
with the output of the reference amplifier is to keep the amplifier
from oscillating with the capacitive load. We have found that
this is large enough to stabilize this circuit. Larger resistor
values are acceptable, provided that the drop across the resistor
does not exceed a V

. Assuming a minimum VBE of 0.6 V and a

BE

maximum current of 2.75 mA, the resistor should be under
200 Ω for the loading of a single AD5725.

Using two separate references is not recommended. Having two
references can cause different drifts with time and temperature,
whereas with a single reference, most drifts will track.

Unipolar positive full-scale operation can usually be set with a
reference with the correct output voltage. This is preferable to
using a reference and dividing down to the required value. For a
10 V full-scale output, the circuit can be configured as shown in
Figure 29. In this configuration, the full-scale value is set first by
adjusting the 10 kΩ resistor for a full-scale output of 9.9976 V.

Rev. A | Page 17 of 20

AD5725

V

V

Figure 29 shows the AD5725 configured for −10 V to 0 V
operation. An ADR01 and OP1177 are configured to produce a

−10 V output, which is connected directly to V

REFP

for the

reference voltage.

0.1µF

10µF

+15

+15V

AV

DD

V

REFP

AD5725

V

REFN

AV

SS

–15V

0V TO –10V O PERATIO N

Figure 29. Unipolar −10 V Operation

V

TEMP

0.2µF

IN

ADR01

U1

GND

V

OUT

TRIM

+15V

U2

V+

OP1177

V–

–15V

6442-009

SINGLE +5 V SUPPLY OPERATION

For operation with a +5 V supply, the reference voltage should
be set between +1.0 V and +2.5 V for optimum linearity. Figure 30
shows an ADR03 used to supply a +2.5 V reference voltage. The
headroom of the reference and DAC are both sufficient to support
a +5 V supply with ±5 V tolerance. AV
connected to the same supply. Separate bypassing to each pin
should be used.

5

10µF 0.01µF

INPUT

ADR03

GND

OUTPUT

TRIM

0V TO 2.5V OPERATI ON
SINGLE 5V SUPPLY

10k

Figure 30. +5 V Single-Supply Operation

V

0.2µF

V

REFP

REFN

and VL should be

DD

AV

DD

0.1µF

AD5725

AV

SS

10µF

06442-010

Rev. A | Page 18 of 20

AD5725

OUTLINE DIMENSIONS

10.50

10.20

9.90

0.38

0.22

15

5.60

5.30

8.20

5.00

7.80

1.85

1.75

1.65

SEATING
PLANE

7.40

0.25

0.09

8°
4°
0°

0.95

0.75

0.55

060106-A

14

2.00 MAX

0.05 MIN

COPLANARITY

0.10

28

1

0.65 BSC

COMPLIANT TO JEDEC STANDARDS MO-150-AH

Figure 31. 28-Lead Shrink Small Outline Package [SSOP]

(RS-28)

Dimensions shown in millimeters

ORDERING GUIDE

INL

Model Temperature Range

(LSB)

Clear Action Package Description

AD5725ARSZ-1500RL71 −40°C to +85°C 1 Clear to zero scale 28-Lead Shrink Small Outline Package [SSOP] RS-28
AD5725ARSZ-1REEL1 −40°C to +85°C 1 Clear to zero scale 28-Lead Shrink Small Outline Package [SSOP] RS-28
AD5725ARSZ-500RL71 −40°C to +85°C 1 Clear to midscale 28-Lead Shrink Small Outline Package [SSOP] RS-28
AD5725ARSZ-REEL1 −40°C to +85°C 1 Clear to midscale 28-Lead Shrink Small Outline Package [SSOP] RS-28
AD5725BRSZ-1500RL71 −40°C to +85°C 0.5 Clear to zero scale 28-Lead Shrink Small Outline Package [SSOP] RS-28
AD5725BRSZ-1REEL1 −40°C to +85°C 0.5 Clear to zero scale 28-Lead Shrink Small Outline Package [SSOP] RS-28
AD5725BRSZ-500RL71 −40°C to +85°C 0.5 Clear to midscale 28-Lead Shrink Small Outline Package [SSOP] RS-28
AD5725BRSZ-REEL1 −40°C to +85°C 0.5 Clear to midscale 28-Lead Shrink Small Outline Package [SSOP] RS-28

1

Z = RoHS Compliant Part.

Package
Option

Rev. A | Page 19 of 20

AD5725

NOTES

©2007–2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06442-0-12/08(A)

Rev. A | Page 20 of 20