ANALOG DEVICES AD5725 Service Manual

Quad, 12-Bit, Parallel Input,

A

V

A

A

Unipolar/Bipolar, Voltage Output DAC

AD5725

FEATURES

+5 V to ±15 V operation
Unipolar or bipolar operation
±0.5 LSB max INL error, ±1 LSB max DNL error
Settling time: 10 μs max (10 V step)
Double-buffered inputs
Simultaneous updating via
Asynchronous

CLR

to zero/mid scale

LDAC

Readback
Operating temperature range: −40°C to +85°C

®

iCMOS

process technology

APPLICATIONS

Industrial automation
Closed-loop servo control, process control

R/W

CS

DB0

TO

DB11

V

L

A0

A1

FUNCTIONAL BLOCK DIAGRAM

V

V

DD

SS

I/O

REGISTER

AND

CONTROL

LOGIC

12

AD5725

DGND

12

INPUT
REG A

INPUT
REG B

INPUT
REG C

INPUT
REG D

Figure 1.

DAC

REG A

DAC

REG B

DAC

REG C

DAC

REG D

12

12

12

12

V

DAC A

DAC B

DAC C

DAC D

REFNLDACCLR

REFP

V

V

V

V

Automotive test and measurement
Programmable logic controllers

GENERAL DESCRIPTION

The AD5725 is a quad, 12-bit, parallel input, voltage output
digital-to-analog converter that offers guaranteed monotonicity,
integral nonlinearity (INL) of ±0.5 LSB maximum and 10 μs
maximum settling time.

Output voltage swing is set by two reference inputs, V
V

. By setting the V

REFN

input to 0 V and the V

REFN

REFP

REFP

to a

and

positive voltage, the DAC provides a unipolar positive output
range. A similar configuration with V

at 0 V and V

REFP

REFN

at a
negative voltage provides a unipolar negative output range.
Bipolar outputs are configured by connecting both V
V

to nonzero voltages. This method of setting output voltage

REFN

REFP

and

ranges has advantages over the bipolar offsetting methods
because it is not dependent on internal and external resistors
with different temperature coefficients.

iCMOS® Process Technology
For analog systems designers within industrial/instrumentation equipment OEMs who need high performance ICs at higher-voltage levels, iCMOS is a technology
platform that enables the development of analog ICs capable of 30 V and operating at ±15 V supplies while allowing dramatic reductions in power consumption and
package size, and increased ac and dc performance.

Digital controls allow the user to load or read back data from
any DAC, load any DAC, and transfer data to all DACs at
one time.

The AD5725 is available in a 28-lead SSOP package. It can be
operated from a wide variety of supply and reference voltages,
with supplies ranging from single +5 V to ±15 V, and references
from +2.5 V to ±10 V. Power dissipation is less than 270 mW
with ±15 V supplies and only 40 mW with a +5 V supply.
Operation is specified over the temperature range of −40°C
to +85°C.

OUT

OUTB

OUTC

OUTD

06442-001

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2007–2008 Analog Devices, Inc. All rights reserved.

AD5725

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1 

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

AC Performance Characteristics ................................................ 5

Timing Characteristics, ............................................................... 6

Absolute Maximum Ratings ............................................................ 8

ESD Caution .................................................................................. 8

Pin Configuration and Function Descriptions ............................. 9

Typical Performance Characteristics ........................................... 10

Terminology .................................................................................... 14

REVISION HISTORY

12/08—Rev. 0 to Rev. A

Changes to Figure 26 ...................................................................... 13

7/07—Revision 0: Initial Version

Theory of Operation ...................................................................... 15

DAC Architecture ....................................................................... 15

Output Amplifiers ...................................................................... 15

Reference Inputs ......................................................................... 15

Parallel Interface ......................................................................... 15

Data Coding ................................................................................ 15

CLR

.............................................................................................. 15

Power Supplies ............................................................................ 17

Reference Configuration ........................................................... 17

Single +5 V Supply Operation .................................................. 18

Outline Dimensions ....................................................................... 19

Ordering Guide .......................................................................... 19

Rev. A | Page 2 of 20

AD5725

SPECIFICATIONS

AVDD = +15 V, AVSS = −15 V, DGND = 0 V; V

Table 1.

Parameter Value Unit Test Conditions/Comments

ACCURACY Outputs unloaded

Resolution 12 Bits
Relative Accuracy (INL) ±0.5 LSB max B grade
±1 LSB max A grade
Differential Nonlinearity (DNL) ±1 LSB max Guaranteed monotonic
Zero-Scale Error ±2 LSB max RL = 2 kΩ
Zero-Scale TC2 ±15 ppm FSR/°C typ RL = 2 kΩ
Full-Scale Error ±2 LSB max RL = 2 kΩ
Full-Scale TC2 ±20 ppm FSR/°C typ RL = 2 kΩ

REFERENCE INPUT

V

REFP

Reference Input Range3 V
AVDD − 2.5 V max
Input Current ±2.75 mA max Typically 1.5 mA

V

REFN

Reference Input Range3 −10 V min
V
Input Current2 2.75 mA max Typically 2 mA

Large Signal Bandwidth2 160 kHz typ −3 dB, V

OUTPUT CHARACTERISTICS2

Output Current ±5 mA max RL = 2 kΩ, CL = 100 pF

DIGITAL INPUTS VL = 2.7 V to 5.5 V, JEDEC compliant

VIH, Input High Voltage 2.4 V min TA = 25°C
VIL, Input Low Voltage 0.8 V max TA = 25°C
Input Current2 1 μA max
Input Capacitance2 8 pF typ

DIGITAL OUTPUTS (SDO)

VOH, Output High Voltage 4 V min IOH = 0.4 mA
VOL, Output Low Voltage 0.4 V max IOL = −1.6 mA

POWER SUPPLY CHARACTERISTICS

Power Supply Sensitivity

2

30 ppm FSR/V max 14.25 V ≤ AV

AIDD 3 mA/channel max Outputs unloaded, V
AISS 2.5 mA/channel max Outputs unloaded, typically 1.625 mA
Power Dissipation 270 mW max

1

All supplies can be varied ±5%, and operation is guaranteed. Device is tested with nominal supplies.

2

Guaranteed by design and characterization, not production tested.

3

Operation is guaranteed over this reference range, but linearity is neither tested nor guaranteed.

= +10 V; V

REFP

+ 2.5 V min

REFN

− 2.5 V max

REFP

= −10 V, VL = 5 V. All specifications T

REFN

MIN

= 0 V to 10 V p-p

REFP

≤ 15.75 V

DD

to T

, unless otherwise noted.1

MAX

= 2.5 V, typically 2.125 mA

REFP

Rev. A | Page 3 of 20

AD5725

AVDD = +5 V, AVSS = −5 V/0 V, DGND = 0 V; V
otherwise noted.

Table 2.

Parameter Value Unit Test Conditions/Comments

ACCURACY Outputs unloaded

Resolution 12 Bits
Relative Accuracy (INL) ±0.5 LSB max B grade

±1 LSB max A grade
±1 LSB max B grade, AVSS = 0 V1

±2 LSB max A grade, AVSS = 0 V1
Differential Nonlinearity (DNL) ±1 LSB max Guaranteed monotonic
Zero-Scale Error ±5 LSB max AVSS = −5 V

±10 LSB max AVSS = 0 V
Zero-Scale TC2 100 ppm FSR/°C typ
Full-Scale Error ±5 LSB max AVSS = −5 V

±10 LSB max AVSS = 0 V
Full-Scale TC2 100 ppm FSR/°C typ

REFERENCE INPUT

V

REFP

Reference Input Range3 V
AVDD − 2.5 V max
Input Current2 ±0.5 mA max Code 0x0000

V

REFN

Reference Input Range3 −2.5 V min AVSS = −5 V
0 V min AVSS = 0 V
V

Large Signal Bandwidth2 450 kHz typ −3 dB, V

OUTPUT CHARACTERISTICS2

Output Current ±1.25 mA max RL = 2 kΩ, CL = 100 pF

DIGITAL INPUTS VL = 2.7 V to 5.5 V, JEDEC compliant

VIH, Input High Voltage 2.4 V min TA = 25°C
VIL, Input Low Voltage 0.8 V max TA = 25°C
Input Current2 1 μA max
Input Capacitance2 8 pF typ

DIGITAL OUTPUTS (SDO)

VOH, Output High Voltage 4 V min IOH = 0.4 mA
VOL, Output Low Voltage 0.4 V max IOL = −1.6 mA

POWER SUPPLY CHARACTERISTICS

Power Supply Sensitivity

2

100 ppm FSR/V typ

AIDD 2 mA/channel max Outputs unloaded.
AISS 1.5 mA/channel max Outputs unloaded, A
Power Dissipation 70 mW max AVSS = −5 V
40 mW max AVSS = 0 V

1

For single supply operation only (V

2

Guaranteed by design and characterization, not production tested.

3

Operation is guaranteed over this reference range, but linearity is neither tested nor guaranteed.

= 0 V, AVSS = 0 V): Due to internal offset errors, INL and DNL are measured beginning at code 0x005.

REFN

= +2.5 V; V

REFP

+ 2.5 V min

REFN

− 2.5 V max

REFP

= −2.5 V/0 V, VL = 5 V. All specifications T

REFN

to T

MIN

= 0 V to 2.5 V p-p

REFP

MAX

= −5 V

VSS

, unless

Rev. A | Page 4 of 20

AD5725

AC PERFORMANCE CHARACTERISTICS1

AVDD = +15 V/+5 V, AVSS = −15 V/−5 V/0 V, DGND = 0 V; V
T

to T

MIN

, unless otherwise noted.

MAX

Table 3.

Parameter A Grade B Grade Unit Test Conditions/Comments

DYNAMIC PERFORMANCE

Output Voltage Settling Time 10 10 μs typ To 0.01%, 10 V step, RL = 1 kΩ

7 7 μs typ To 0.01%, 2.5 V step, RL = 1 kΩ

Slew Rate 2.2 2.2 V/μs typ 10% to 90%
Analog Crosstalk 72 72 dB typ
Digital Feedthrough 5 5 nV-s typ

1

Guaranteed by design and characterization, not production tested.

= +10 V/+2.5 V; V

REFP

= −10 V/−2.5 V/0 V, VL = 5 V. All specifications

REFN

Rev. A | Page 5 of 20

AD5725

TIMING CHARACTERISTICS

AVDD = +5 V/+15 V, AVSS = −5 V/0 V/−15 V, DGND = 0 V; V
T

to T

MIN

Table 4.

Parameter Limit at T

t

10 ns min Chip Select Write Pulse Width

WCS

tWS 0 ns min Write Setup, t
tWH 0 ns min Write Hold, t
tAS 0 ns min Address Setup
tAH 0 ns min Address Hold
tLS 5 ns min Load Setup
tLH 5 ns min Load Hold
t

5 ns min Write Data Setup, t

WDS

t

0 ns min Write Data Hold, t

WDH

t

10 ns min Load Data Pulse Width

LDW

t

10 ns min Reset Pulse Width

RESET

t

30 ns min Chip Select Read Pulse Width

RCS

t

0 ns min Read Data Hold, t

RDH

t

0 ns min Read Data Setup, t

RDS

tDZ 15 ns max Data to High-Z, CL = 10 pF
t

35 ns max Chip Select to Data, CL = 100 pF

CSD

1

All input control signals are specified with tr = tf = 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V.

2

Guaranteed by design and characterization, not production tested.

, unless otherwise noted.

MAX

1, 2

= +2.5 V/+10 V; V

REFP

, T

Unit Description

MIN

MAX

= −2.5 V/0 V/−10 V, VL = 5 V. All specifications

REFN

= 10 ns

WCS

= 10 ns

WCS

= 10 ns

WCS

= 10 ns

WCS

= 30 ns

RCS

= 30 ns

RCS

Rev. A | Page 6 of 20