Quad, 16-/12-Bit nanoDAC+
V
V
Data Sheet
FEATURES
High relative accuracy (INL): ±2 LSB maximum @ 16 bits
Tiny package: 3 mm × 3 mm, 16-lead LFCSP
Total unadjusted error (TUE): ±0.1% of FSR maximum
Offset error: ±1.5 mV maximum
Gain error: ±0.1% of FSR maximum
High drive capability: 20 mA, 0.5 V from supply rails
User selectable gain of 1 or 2 (GAIN pin)
Reset to zero scale or midscale (RSTSEL pin)
1.8 V logic compatibility
50 MHz SPI with readback or daisy chain
Low glitch: 0.5 nV-sec
Robust 4 kV HBM and 1.5 kV FICDM ESD rating
Low power: 1.8 mW at 3 V
2.7 V to 5.5 V power supply
−40°C to +105°C temperature range
APPLICATIONS
Digital gain and offset adjustment
Programmable attenuators
Process control (PLC I/O cards)
Industrial automation
Data acquisition systems
V
LOGIC
SCLK
SYNC
SDIN
SDO
with SPI Interface
AD5686/AD5684
FUNCTIONAL BLOCK DIAGRAM
DD
AD5686/AD5684
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
INTERF AC E LOGIC
INPUT
REGISTER
GND
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
POWER-ON
RESET
RSTSEL GAINLDAC RESET
Figure 1.
REF
STRING
DAC A
STRING
DAC B
STRING
DAC C
STRING
DAC D
GAIN
×1/×2
BUFFER
BUFFER
BUFFER
BUFFER
POWER-
DOWN
LOGIC
V
A
OUT
V
B
OUT
V
C
OUT
V
D
OUT
10797-001
GENERAL DESCRIPTION
The AD5686/AD5684, members of the nanoDAC+™ family, are
low power, quad, 16-/12-bit buffered voltage output DACs.
The devices include a gain select pin giving a full-scale output
of 2.5 V (gain = 1) or 5 V (gain = 2). All devices operate from
a single 2.7 V to 5.5 V supply, are guaranteed monotonic by
design, and exhibit less than 0.1% FSR gain error and 1.5 mV
offset error performance. The devices are available in a 3 mm
× 3 mm LFCSP and a TSSOP package.
The AD5686/AD5684 also incorporate a power-on reset circuit
and a RSTSEL pin that ensures that the DAC outputs power up
to zero scale or midscale and remain at that level until a valid
write takes place. Each part contains a per-channel power-down
feature that reduces the current consumption of the device to
4 μA at 3 V while in power-down mode.
The AD5686/AD5684 employ a versatile SPI interface that
operates at clock rates up to 50 MHz, and all devices contain
a V
pin intended for 1.8 V/3 V/5 V logic.
LOGIC
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
Table 1. Quad nanoDAC+ Devices
Interface Reference 16-Bit 14-Bit 12-Bit
SPI Internal AD5686R AD5685R AD5684R
SPI External AD5686 AD5684
I2C Internal AD5696R AD5695R AD5694R
I2C External AD5696 AD5694
PRODUCT HIGHLIGHTS
1. High Relative Accuracy (INL).
AD5686 (16-bit): ±2 LSB maximum
AD5684 (12-bit): ±1 LSB maximum
2. Excellent DC Performance.
Tota l u n adj u ste d e r ror : ±0 . 1% o f FS R ma x imu m
Offset error: ±1.5 mV maximum
Gain error: ±0.1% of FSR maximum
3. Two Pa ckage Options.
3 mm × 3 mm, 16-lead LFCSP
16-lead TSSOP
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2012 Analog Devices, Inc. All rights reserved.
AD5686/AD5684 Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
AC Characteristics ........................................................................ 5
Timing Characteristics ................................................................ 6
Daisy-Chain and Readback Timing Characteristics................ 7
Absolute Maximum Ratings ............................................................ 9
ESD Caution .................................................................................. 9
Pin Configurations and Function Descriptions ......................... 10
Typical Performance Characteristics ........................................... 11
Terminology .................................................................................... 16
Theory of Operation ...................................................................... 18
Digital-to-Analog Converter .................................................... 18
Transfer Function ....................................................................... 18
DAC Architecture ....................................................................... 18
Serial Interface ............................................................................ 19
Standalone Operation ................................................................ 20
Write and Update Commands .................................................. 20
Daisy-Chain Operation ............................................................. 20
Readback Operation .................................................................. 21
Power-Down Operation ............................................................ 21
Load DAC (Hardware
LDAC
Mask Register ................................................................. 22
Hardware Reset (
Reset Select Pin (RSTSEL) ........................................................ 23
Applications Information .............................................................. 24
Microprocessor Interfacing ....................................................... 24
AD5686/AD5684 to ADSP-BF531 Interface .......................... 24
AD5686/AD5684 to SPORT Interface .................................... 24
Layout Guidelines....................................................................... 24
Galvanically Isolated Interface ................................................. 25
Outline Dimensions ....................................................................... 26
Ordering Guide .......................................................................... 27
LDAC
Pin) ........................................... 22
) .......................................................... 23
RESET
REVISION HISTORY
7/12—Revision 0: Initial Version
Rev. 0 | Page 2 of 28
Data Sheet AD5686/AD5684
1
STATIC PERFORMANCE2
AD5686
Resolution
16
16
Bits
Gain Temperature
REF
REF
REF
REF
OUT
OUT
DD
REF
LOGIC
REF
LOGIC
SPECIFICATIONS
VDD = 2.7 V to 5.5 V; V
= 2.5 V; 1.8 V ≤ V
REF
≤ 5.5 V; all specifications T
LOGIC
MIN
to T
, unless otherwise noted. RL = 2 kΩ; CL = 200 pF.
MAX
Table 2.
A Grade1
B Grade
Parameter Min Typ Max Min Typ Max Unit Test Conditions/Comments
Relative Accuracy ±2 ±8 ±1 ±2 LSB Gain = 2
±2 ±8 ±1 ±3 LSB Gain = 1
Differential Nonlinearity ±1 ±1 LSB Guaranteed monotonic by design
AD5684
Resolution 12 12 Bits
Relative Accuracy ±0.12 ±2 ±0.12 ±1 LSB
Differential Nonlinearity ±1 ±1 LSB Guaranteed monotonic by design
Zero-Code Error 0.4 4 0.4 1.5 mV All 0s loaded to DAC register
Offset Error +0.1 ±4 +0.1 ±1.5 mV
Full-Scale Error +0.01 ±0.2 +0.01 ±0.1
Gain Error ±0.02 ±0.2 ±0.02 ±0.1
Total Unadjusted Error ±0.01 ±0.25 ±0.01 ±0.1
±0.25 ±0.2
Offset Error Drift
±1 ±1 µV/°C
3
±1 ±1 ppm Of FSR/°C
Coefficient3
DC Power Supply Rejection
3
Ratio
DC Crosstalk3
0.15 0.15 mV/V DAC code = midscale; V
±2 ±2 µV
±3 ±3 µV/mA Due to load current change
±2 ±2 µV Due to powering down (per channel)
OUTPUT CHARACTERISTICS3
Output Voltage Range 0 V
0 2 × V
0 V
0 2 × V
Capacitive Load Stability 2 2 nF RL = ∞
10 10 nF RL = 1 kΩ
Resistive Load4 1 1 kΩ
Load Regulation 80 80 µV/mA
80 80 µV/mA
Short-Circuit Current5 40 40 mA
Load Impedance at Rails6 25 25 Ω See Figure 23
Power-Up Time 2.5 2.5 µs
REFERENCE INPUT
Reference Current 90 90 µA V
180 180 µA V
Reference Input Range 1 VDD 1 VDD V Gain = 1
1 VDD/2 1 VDD/2 V Gain = 2
Reference Input Impedance 16 16 kΩ Gain = 2
32 32 kΩ Gain = 1
% of
FSR
% of
FSR
% of
FSR
% of
FSR
V Gain = 1
V Gain = 2, see Figure 23
All 1s loaded to DAC register
Gain = 2
Gain = 1
= 5 V ± 10%
DD
Due to single channel, full-scale
output change
5 V ± 10%, DAC code = midscale;
−30 mA ≤ I
≤ +30 mA
3 V ± 10%, DAC code = midscale;
−20 mA ≤ I
≤ +20 mA
Coming out of power-down mode;
V
= 5 V
= VDD = V
= VDD = V
=5.5 V, gain = 1
=5.5 V, gain = 2
Rev. 0 | Page 3 of 28
AD5686/AD5684 Data Sheet
1
INL
LOGIC
LOGIC
INH
LOGIC
LOGIC
SINK
LOGIC
LOGIC
SOUR CE
POWER REQUIREMENTS
REF
REF
A Grade1
B Grade
Parameter Min Typ Max Min Typ Max Unit Test Conditions/Comments
LOGIC INPUTS3
Input Current ±2 ±2 µA Per pin
Input Low Voltage (V
Input High Voltage (V
) 0.3 × V
) 0.7 × V
0.7 × V
0.3 × V
V
V
Pin Capacitance 2 2 pF
LOGIC OUTPUTS (SDO)3
Output Low Voltage, VOL 0.4 0.4 V I
Output High Voltage, VOH V
Floating State Output
− 0.4 V
− 0.4 V I
4 4 pF
= 200 μA
= 200 μA
Capacitance
V
I
LOGIC
LOGIC
1.8 5.5 1.8 5.5 V
3 3 µA
VDD 2.7 5.5 2.7 5.5 V Gain = 1
V
+ 1.5 5.5 V
+ 1.5 5.5 V Gain = 2
IDD VIH = VDD, VIL = GND, VDD = 2.7 V to 5.5 V
Normal Mode7 0.59 0.7 0.59 0.7 mA
All Power-Down Modes8 1 4 1 4 µA −40°C to +85°C
6 6 µA −40°C to +105°C
1
Temperature range, A and B grade: −40°C to +105°C.
2
DC specifications tested with the outputs unloaded, unless otherwise noted. Upper dead band = 10 mV and exists only when V
with gain = 2. Linearity calculated using a reduced code range of 256 to 65,280 (AD5686) or 12 to 4080 (AD5684).
V
DD
3
Guaranteed by design and characterization; not production tested.
4
Channel A and Channel B can have a combined output current of up to 30 mA. Similarly, Channel C and Channel D can have a combined output current of up to
30 mA up to a junction temperature of 110°C.
5
VDD = 5 V. The device includes current limiting that is intended to protect the device during temporary overload conditions. Junction temperature can be exceeded
during current limit. Operation above the specified maximum operation junction temperature may impair device reliability.
6
When drawing a load current at either rail, the output voltage headroom with respect to that rail is limited by the 25 Ω typical channel resistance of the output
devices. For example, when sinking 1 mA, the minimum output voltage = 25 Ω × 1 mA = 25 mV (see Figure 23).
7
Interface inactive. All DACs active. DAC outputs unloaded.
8
All DACs powered down.
= VDD with gain = 1 or when V
REF
REF
/2 =
Rev. 0 | Page 4 of 28
Data Sheet AD5686/AD5684
Total Harmonic Distortion4
−80 dB
At ambient, BW = 20 kHz, VDD = 5 V, f
OUT
= 1 kHz
OUT
OUT
OUT
AC CHARACTERISTICS
VDD = 2.7 V to 5.5 V; V
otherwise noted.
1
Table 3.
Parameter2 Min Typ Max Unit Test Conditions/Comments3
Output Voltage Settling Time
AD5686 5 8 µs ¼ to ¾ scale settling to ±2 LSB
AD5684 5 7 µs ¼ to ¾ scale settling to ±2 LSB
Slew Rate 0.8 V/µs
Digital-to-Analog Glitch Impulse 0.5 nV-sec 1 LSB change around major carry
Digital Feedthrough 0.13 nV-sec
Multiplying Bandwidth 500 kHz
Digital Crosstalk 0.1 nV-sec
Analog Crosstalk 0.2 nV-sec
DAC-to-DAC Crosstalk 0.3 nV-sec
Output Noise Spectral Density 100 nV/√Hz DAC code = midscale, 10 kHz; gain = 2
Output Noise 6 µV p-p 0.1 Hz to 10 Hz
SNR 90 dB At ambient, BW = 20 kHz, VDD = 5 V, f
SFDR 83 dB At ambient, BW = 20 kHz, VDD = 5 V, f
SINAD 80 dB At ambient, BW = 20 kHz, VDD = 5 V, f
1
Guaranteed by design and characterization; not production tested.
2
See the Terminology section.
3
Temperature range is −40°C to +105°C, typical @ 25°C.
4
Digitally generated sine wave @ 1 kHz.
= 2.5 V; 1.8 V ≤ V
REF
≤ 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications T
LOGIC
to T
MIN
= 1 kHz
= 1 kHz
= 1 kHz
MAX
, unless
Rev. 0 | Page 5 of 28
AD5686/AD5684 Data Sheet
LOGIC
LOGIC
Data Setup Time
t5 8 5
ns
t
4
t
3
SCLK
SYNC
SDIN
t
1
t
2
t
5
t
6
t
7
t
8
DB23
t
9
t
10
t
11
LDAC
1
LDAC
2
t
12
1
ASYNCHRONOUS LDAC UPDATE MODE .
2
SYNCHRONOUS LDAC UPDATE MODE .
RESET
t
13
t
14
V
OUT
DB0
10797-002
TIMING CHARACTERISTICS
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 2.
V
= 2.7 V to 5.5 V, 1.8 V ≤ V
DD
Table 4.
1.8 V ≤ V
Parameter1 Symbol Min Max Min Max Unit
SCLK Cycle Time t1 33 20 ns
SCLK High Time t2 16 10 ns
SCLK Low Time t3 16 10 ns
to SCLK Falling Edge Setup Time t4 15 10 ns
SYNC
Data Hold Time t6 8 5 ns
SCLK Falling Edge to
Minimum
Falling Edge to SCLK Fall Ignore t9 16 10 ns
SYNC
Pulse Width Low t10 25 15 ns
LDAC
High Time t8 20 20 ns
SYNC
SCLK Falling Edge to
SCLK Falling Edge to
Minimum Pulse Width Low t13 30 30 ns
RESET
Pulse Activation Time t14 30 30 ns
RESET
Rising Edge t7 15 10 ns
SYNC
Rising Edge t11 30 20 ns
LDAC
Falling Edge t12 20 20 ns
LDAC
Power-Up Time2 4.5 4.5 µs
1
Maximum SCLK frequency is 50 MHz at VDD = 2.7 V to 5.5 V, 1.8 V ≤ V
2
Time to exit power-down to normal mode of AD5686/AD5684 operation, 32nd clock edge to 90% of DAC midscale value, with output unloaded.
LOGIC
≤ 5.5 V; V
= 2.5 V. All specifications T
REF
≤ VDD. Guaranteed by design and characterization; not production tested.
LOGIC
MIN
to T
, unless otherwise noted.
MAX
< 2.7 V 2.7 V ≤ V
≤ 5.5 V
Figure 2. Serial Write Operation
Rev. 0 | Page 6 of 28
Data Sheet AD5686/AD5684
LOGIC
LOGIC
200µA I
OL
200µA I
OH
V
OH
(MIN)
TO OUTPUT
PIN
C
L
20pF
10797-003
t
4
t
5
t
6
t
8
SDO
SDIN
SYNC
SCLK
4824
DB23 DB0 DB23 DB0
DB23
INPUT WORD FOR DAC NUNDEFINED
INPUT WORD FOR DAC N + 1INPUT WORD FOR DAC N
DB0
t
11
t
12
t
10
10797-004
DAISY-CHAIN AND READBACK TIMING CHARACTERISTICS
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 4
and Figure 5. V
Table 5.
1.8 V ≤ V
Parameter1 Symbol Min Max Min Max Unit
SCLK Cycle Time t1 66 40 ns
SCLK High Time t2 33 20 ns
SCLK Low Time t3 33 20 ns
to SCLK Falling Edge t4 33 20 ns
SYNC
Data Setup Time t5 5 5 ns
Data Hold Time t6 5 5 ns
SCLK Falling Edge to
Minimum
Minimum
SDO Data Valid from SCLK Rising Edge t10 36 25 ns
SCLK Falling Edge to
Rising Edge to SCLK Rising Edge t12 15 10 ns
SYNC
1
Maximum SCLK frequency is 25 MHz or 15 MHz at VDD = 2.7 V to 5.5 V, 1.8 V ≤ V
Circuit and Timing Diagrams
= 2.7 V to 5.5 V, 1.8 V ≤ V
DD
Rising Edge t7 15 10 ns
SYNC
High Time t8 60 30 ns
SYNC
High Time t9 60 30 ns
SYNC
Rising Edge t11 15 10 ns
SYNC
LOG IC
≤ 5.5 V; V
= 2.5 V. All specifications T
REF
< 2.7 V 2.7 V ≤ V
≤ VDD. Guaranteed by design and characterization; not production tested.
LOGIC
MIN
to T
, unless otherwise noted.
MAX
≤ 5.5 V
Figure 3. Load Circuit for Digital Output (SDO) Timing Specifications
Figure 4. Daisy-Chain Timing Diagram
Rev. 0 | Page 7 of 28
AD5686/AD5684 Data Sheet
SYNC
t
8
t
6
SCLK
24
1
24
1
t
9
t
4
t
2
t
7
t
3
t
1
DB23 DB0 DB23 DB0
SDIN
NOP CONDITIONINPUT WORD SPECIFIES
REGIST E R TO BE READ
t
5
DB23 DB0 DB23 DB0
SDO
SELECTED REGISTER DATA
CLOCKED OUT
UNDEFINED
t
10
10797-005
Figure 5. Readback Timing Diagram
Rev. 0 | Page 8 of 28
Data Sheet AD5686/AD5684
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 6.
Parameter Rating
VDD to GND −0.3 V to +7 V
V
to GND −0.3 V to +7 V
LOGI C
V
to GND −0.3 V to VDD + 0.3 V
OUT
V
to GND −0.3 V to VDD + 0.3 V
REF
Digital Input Voltage to GND −0.3 V to V
Operating Temperature Range −40°C to +105°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 125°C
16-Lead TSSOP, θJA Thermal
Impedance, 0 Airflow (4-Layer Board)
16-Lead LFCSP, θJA Thermal
Impedance, 0 Airflow (4-Layer Board)
Reflow Soldering Peak
Temperature, Pb Free (J-STD-020)
ESD
HBM1 4 kV
FICDM 1.5 kV
1
Human body model (HBM) classification.
112.6°C/W
70°C/W
260°C
LOGI C
+ 0.3 V
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. 0 | Page 9 of 28
AD5686/AD5684 Data Sheet
Pin No.
OUT
OUT
OUT
DD
REF
LOGIC
12
14
SDIN
Serial Data Input. These devices have a 24-bit input shift register. Data is clocked into the register on
Power-On Reset Pin. Tying this pin to GND powers up all four DACs to zero scale. Tying this pin to
VDD powers up all four DACs to midscale.
REF
OUT
12
11
10
1
3
4
SDIN
SYNC
SCLK
9
V
LOGIC
V
OUT
A
V
DD
2
GND
V
OUT
C
6
SDO
5
V
OUT
D
7
LDAC
8
GAIN
16
V
OUT
B
15
V
REF
14
RSTSEL
13
RESET
AD5686/AD5684
NOTES
1. THE EXPOSED PAD MUST BE TIED TO GND.
TOP VIEW
(Not to S cale)
10797-006
1
2
3
4
5
6
7
8
V
OUT
B
V
OUT
A
GND
V
OUT
D
V
OUT
C
V
DD
V
REF
SDO
16
15
14
13
12
11
10
9
RESET
SDIN
SYNC
GAIN
LDAC
V
LOGIC
SCLK
RSTSEL
TOP VIEW
(Not to S cale)
AD5686/
AD5684
10797-007
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Figure 6. 16-Lead LFCSP Pin Configuration
Table 7. Pin Function Descriptions
Mnemonic Description LFCSP TSSOP
1 3 V
A Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
2 4 GND Ground Reference Point for All Circuitry on the Part.
3 5 VDD Power Supply Input. These parts can be operated from 2.7 V to 5.5 V, and the supply should be
decoupled with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND.
4 6 V
5 7 V
C Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.
D Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.
6 8 SDO Serial Data Output. Can be used to daisy-chain a number of AD5686/AD5684 devices together or
can be used for readback. The serial data is transferred on the rising edge of SCLK and is valid on
the falling edge of the clock.
7 9
LDAC
can be operated in two modes, asynchronously and synchronously. Pulsing this pin low allows
LDAC
any or all DAC registers to be updated if the input registers have new data. This allows all DAC outputs
to be simultaneously updated. This pin can also be tied permanently low.
8 10 GAIN Span Set Pin. When this pin is tied to GND, all four DAC outputs have a span from 0 V to V
9 11 V
this pin is tied to V
Digital Power Supply. Voltage ranges from 1.8 V to 5.5 V.
, all four DAC outputs have a span from 0 V to 2 × V
10 12 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock
input. Data can be transferred at rates of up to 50 MHz.
11 13
Active Low Control Input. This is the frame synchronization signal for the input data. When
SYNC
goes low, data is transferred in on the falling edges of the next 24 clocks.
the falling edge of the serial clock input.
13 15
Asynchronous Reset Input. The
RESET
pulses are ignored. When
input is falling edge sensitive. When
RESET
is activated, the input register and the DAC register are updated with
RESET
zero scale or midscale, depending on the state of the RSTSEL pin.
14 16 RSTSEL
15 1 V
16 2 V
17 N/A EPAD Exposed Pad. The exposed pad must be tied to GND.
Reference Input Voltage.
B Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
Rev. 0 | Page 10 of 28
Figure 7. 16-Lead TSSOP Pin Configuration
.
is low, all
RESET
. When
REF
SYNC
LDAC
Data Sheet AD5686/AD5684
10
–10
–8
–6
–4
–2
0
2
4
8
6
0 10000 20000 30000 40000 50000 60000
INL (LSB)
CODE
VDD = 5V
T
A
= 25°C
REFERENCE = 2.5V
10797-118
10
–10
–8
–6
–4
–2
0
2
4
8
6
0 625 1250 1875 2500 3125 3750 4096
INL (LSB)
CODE
VDD = 5V
T
A
= 25°C
REFERENCE = 2.5V
10797-120
1.0
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.8
0.6
0 10000 20000 30000 40000 50000 60000
DNL (LSB)
CODE
VDD = 5V
T
A
= 25°C
REFERENCE = 2.5V
10797-121
1.0
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.8
0.6
0 625 1250 1875 2500 3125 3750 4096
DNL (LSB)
CODE
VDD = 5V
T
A
= 25°C
REFERENCE = 2. 5V
10797-123
10
–10
–8
–6
–4
–2
0
2
4
6
8
–40 1106010
ERROR (LSB)
TEMPERATURE (°C)
INL
DNL
VDD = 5V
T
A
= 25°C
REFERENCE = 2.5V
10797-124
10
–10
–8
–6
–4
–2
0
2
4
6
8
0 5.04.54.03.53.02.52.01.51.00.5
ERROR (LSB)
V
REF
(V)
INL
DNL
VDD = 5V
T
A
= 25°C
REFERENCE = 2.5V
10797-125
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 8. AD5686 INL
Figure 9. AD5684 INL
Figure 11. AD5684 DNL
Figure 12. INL Error and DNL Error vs. Temperature
Figure 10. AD5686 DNL
Figure 13. INL Error and DNL Error vs. V
REF
Rev. 0 | Page 11 of 28
AD5686/AD5684 Data Sheet
10
–10
–8
–6
–4
–2
0
2
4
6
8
2.7 5.24.74.23.73.2
ERROR (LSB)
SUPPLY VOLTAGE (V)
INL
DNL
VDD = 5V
T
A
= 25°C
REFERENCE = 2.5V
10797-126
0.10
–0.10
–0.08
–0.06
–0.04
–0.02
0
0.02
0.04
0.06
0.08
–40 –20 0 20 40 60 80 100 120
ERROR (% of FSR)
TEMPERATURE (°C)
GAIN ERROR
FULL-S CALE ERROR
VDD = 5V
T
A
= 25°C
REFERENCE = 2.5V
10797-127
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
–40 –20 0 20 40 60 80 100 120
ERROR (mV)
TEMPERATURE (°C)
OFFSET ERROR
ZERO-CO DE E RROR
VDD = 5V
T
A
= 25°C
REFERENCE = 2.5V
10797-128
0.10
–0.10
–0.08
–0.06
–0.04
–0.02
0
0.02
0.04
0.06
0.08
2.7 5.24.74.23.73.2
ERROR (% of FSR)
SUPPLY VOLTAGE (V)
GAIN ERROR
FULL-S CALE ERROR
V
DD
= 5V
T
A
= 25°C
REFERENCE = 2.5V
10797-129
1.5
–1.5
–1.0
–0.5
0
0.5
1.0
2.7 5.24.74.23.73.2
ERROR (mV)
SUPPLY VOLTAGE (V)
ZERO-CO DE E RROR
OFFSET ERROR
V
DD
= 5V
T
A
= 25°C
REFERENCE = 2.5V
10797-130
0.10
TOTAL UNADJUS TED ERROR (% o f FSR)
Figure 14. INL Error and DNL Error vs. Supply Voltage
Figure 15. Gain Error and Full-Scale Error vs. Temperature
Figure 16. Zero-Code Error and Offset Error vs. Temperature
Figure 17. Gain Error and Full-Scale Error vs. Supply Voltage
Figure 18. Zero-Code Error and Offset Error vs. Supply Voltage
VDD = 5V
= 25°C
T
0.09
A
REFERENCE = 2.5V
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0
–40 –20 0 20 40 60 80 100 120
TEMPERATURE (°C)
10797-131
Figure 19. TUE vs. Temperature
Rev. 0 | Page 12 of 28
Data Sheet AD5686/AD5684
0.10
TOTAL UNADJUS TED ERROR (% o f FSR)
0
–0.01
–0.02
–0.03
–0.04
–0.05
–0.06
–0.07
–0.08
–0.09
–0.10
0 10000 20000 30000 40000 50000 60000 65535
TOTAL UNADJUS TED ERROR (% of FSR)
CODE
VDD = 5V
T
A
= 25°C
REFERENCE = 2.5V
10797-133
25
20
15
10
5
0
540 560 580 600 620 640
HITS
IDD (mA)
V
DD
= 5V
T
A
= 25°C
REFERENCE = 2. 5V
10797-135
1.0
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
0 5 10 15 20 25 30
ΔV
OUT
(V)
LOAD CURRENT ( mA)
SOURCING 2.7V
SOURCING 5V
SINKING 2.7V
SINKING 5V
10797-200
7
–2
–1
0
1
2
3
4
5
6
–0.06 –0.04 –0.02 0 0.02 0.04 0.06
V
OUT
(V)
LOAD CURRENT ( A)
0xFFFF
0x4000
0x8000
0xC000
0x0000
V
DD
= 5V
T
A
= 25°C
GAIN = 2
REFERENCE = 2.5V
10797-138
5
–2
–1
0
1
2
3
4
–0.06 –0.04
–0.02 0 0.02 0.04 0.06
V
OUT
(V)
LOAD CURRENT ( A)
0xFFFF
0x4000
0x8000
0xC000
0x0000
VDD = 3V
T
A
= 25°C
REFERENCE = 2. 5V
GAIN = 1
10797-139
0.08
0.06
0.04
0.02
0
–0.02
–0.04
–0.06
VDD = 5V
–0.08
= 25°C
T
A
REFERENCE = 2.5V
–0.10
2.7 5.24.74.23.73.2
Figure 20. TUE vs. Supply Voltage, Gain = 1
SUPPLY VOLTAGE (V)
10797-132
Figure 23. Headroom/Footroom vs. Load Current
Figure 21. TUE vs. Code
Figure 22. IDD Histogram
Figure 24. Source and Sink Capability at 5 V
Figure 25. Source and Sink Capability at 3 V
Rev. 0 | Page 13 of 28
AD5686/AD5684 Data Sheet
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
–40 1106010
CURRENT (mA)
TEMPERATURE (°C)
FULL-SCALE
10797-140
0
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
10 32016040 8020
V
OUT
(V)
TIME (µs)
DAC A
DAC B
DAC C
DAC D
V
DD
= 5V
T
A
= 25°C
REFERENCE = 2.5V
¼ TO ¾ SCALE
10797-141
–0.01
0
0.06
0.01
0.02
0.03
0.04
0.05
–1
0
6
1
2
3
4
5
–10 15100 5–5
V
OUT
(V)
V
DD
(V)
TIME (µs)
CH D
V
DD
CH A
CH B
CH C
TA = 25°C
REFERENCE = 2.5V
10797-142
0
1
3
2
–5 100 5
V
OUT
(V)
TIME (µs)
CH D
SYNC
CH A
CH B
CH C
VDD = 5V
T
A
= 25°C
REFERENCE = 2.5V
GAIN = 1
GAIN = 2
10797-143
2.4988
2.5008
2.5003
2.4998
2.4993
0 128 104 62
V
OUT
(V)
TIME (µs)
CHANNEL B
T
A
= 25°C
V
DD
= 5.25V
REFERENCE = 2.5V
CODE = 7FF F TO 8000
ENERGY = 0. 227206nV-sec
10797-144
–0.002
–0.001
0
0.001
0.002
0.003
0 252010 155
V
OUT
AC-COUPLED ( V )
TIME (µs)
CH B
CH C
CH D
10797-145
Figure 26. Supply Current vs. Temperature
Figure 27. Settling Time, 5 V
Figure 29. Exiting Power-Down to Midscale
Figure 30. Digital-to-Analog Glitch Impulse
Figure 28. Power-On Reset to 0 V
Figure 31. Analog Crosstalk, Channel A
Rev. 0 | Page 14 of 28
Data Sheet AD5686/AD5684
CH1 10µV M1.0s A CH1 802mV
1
T
V
DD
= 5V
T
A
= 25°C
REFERENCE = 2. 5V
10797-146
20
THD (dBV)
4.0
V
(V)
–60
–50
–40
–30
–20
–10
0
10k 10M1M100k
BANDWIDTH (dB)
FREQUENCY ( Hz )
V
DD
= 5V
T
A
= 25°C
REFERENCE = 2. 5V , ±0.1V p- p
10797-151
Figure 32. 0.1 Hz to 10 Hz Output Noise Plot
0
–20
–40
–60
–80
–100
–120
–140
–160
–180
0 20000160008000 1200040002000 1800010000 140006000
FREQUENCY ( Hz )
Figure 33. Total Harmonic Distortion @ 1 kHz
VDD = 5V
= 25°C
T
A
REFERENCE = 2.5V
0nF
3.9
3.8
3.7
3.6
3.5
OUT
3.4
3.3
3.2
3.1
3.0
0.1nF
10nF
0.22nF
4.7nF
1.590 1.6301.6201.600 1.610 1.6251.605 1.6151.595
Figure 34. Settling Time vs. Capacitive Load
10797-149
Figure 35. Multiplying Bandwidth, Reference = 2.5 V, ±0.1 V p-p, 10 kHz to
VDD = 5V
= 25°C
T
A
REFERENCE = 2.5V
TIME (ms)
10797-150
10 MHz
Rev. 0 | Page 15 of 28
AD5686/AD5684 Data Sheet
TERMINOLOGY
Relative Accuracy or Integral Nonlinearity (INL)
For the DAC, relative accuracy or integral nonlinearity is a
measurement of the maximum deviation, in LSBs, from a
straight line passing through the endpoints of the DAC transfer
function. A typical INL vs. code plot is shown in Figure 8.
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ±1 LSB maximum
ensures monotonicity. These DACs are guaranteed monotonic
by design. A typical DNL vs. code plot can be seen in Figure 10.
Zero-Code Error
Zero-code error is a measurement of the output error when
zero code (0x0000) is loaded to the DAC register. Ideally, the
output should be 0 V. The zero-code error is always positive in
the AD5686/AD5684 because the output of the DAC cannot go
below 0 V due to a combination of the offset errors in the DAC
and the output amplifier. Zero-code error is expressed in mV. A
plot of zero-code error vs. temperature can be seen in Figure 16.
Full-Scale Error
Full-scale error is a measurement of the output error when fullscale code (0xFFFF) is loaded to the DAC register. Ideally, the
output should be V
− 1 LSB. Full-scale error is expressed in
DD
percent of full-scale range (% of FSR). A plot of full-scale error
vs. temperature can be seen in Figure 15.
Gain Error
Gain error is a measurement of the span error of the DAC. It is
the deviation in slope of the DAC transfer characteristic from
the ideal expressed as % of FSR.
Offset Error Drift
Offset error drift is a measurement of the change in offset error
with a change in temperature. It is expressed in µV/°C.
Gain Temperature Coefficient
Gain temperature coefficient is a measurement of the change in
gain error with changes in temperature. It is expressed in ppm
of FSR/°C.
Offset Error
Offset error is a measurement of the difference between V
(actual) and V
(ideal) expressed in mV in the linear region of
OUT
OUT
the transfer function. It can be negative or positive.
DC Power Supply Rejection Ratio (PSRR)
DC PSRR indicates how the output of the DAC is affected by
changes in the supply voltage. PSRR is the ratio of the change in
V
to a change in VDD for full-scale output of the DAC. It is
OUT
measured in mV/V. V
is held at 2.5 V, and VDD is varied by
REF
±10%.
Output Voltage Settling Time
The output voltage setting time is the amount of time it takes
for the output of a DAC to settle to a specified level for a ¼ to ¾
full-scale input change and is measured from the rising edge
SYNC
of
.
Digital-to-Analog Glitch Impulse
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nV-sec,
and is measured when the digital input code is changed by
1 LSB at the major carry transition (0x7FFF to 0x8000) (see
Figure 30).
Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into the
analog output of the DAC from the digital inputs of the DAC,
but is measured when the DAC output is not updated. It is
specified in nV-sec and measured with a full-scale code change
on the data bus, that is, from all 0s to all 1s and vice versa.
Noise Spectral Density
Noise spectral density is a measurement of the internally
generated random noise. Random noise is characterized as a
spectral density (nV/√Hz). It is measured by loading the DAC
to midscale and measuring noise at the output. It is measured in
nV/√Hz.
DC Crosstalk
DC crosstalk is the dc change in the output level of one DAC
in response to a change in the output of another DAC. It is
measured with a full-scale output change on one DAC (or soft
power-down and power-up) while monitoring another DAC
kept at midscale. It is expressed in μV.
DC crosstalk due to load current change is a measurment of
the impact that a change in load current on one DAC has to
another DAC kept at midscale. It is expressed in μV/mA.
Digital Crosstalk
Digital crosstalk is the glitch impulse transferred to the output
of one DAC at midscale in response to a full-scale code change
(all 0s to all 1s and vice versa) in the input register of another
DAC. It is measured in standalone mode and is expressed in
nV-sec.
Rev. 0 | Page 16 of 28
Data Sheet AD5686/AD5684
Analog Crosstalk
Analog crosstalk is the glitch impulse transferred to the output
of one DAC due to a change in the output of another DAC. It is
measured by loading one of the input registers with a full-scale
code change (all 0s to all 1s and vice versa). Then execute a
software LDAC and monitor the output of the DAC whose
digital code was not changed. The area of the glitch is expressed
in nV-sec.
DAC-to-DAC Crosstalk
DAC-to-DAC crosstalk is the glitch impulse transferred to
the output of one DAC in response to a digital code change
and subsequent analog output change of another DAC. It is
measured by loading the attack channel with a full-scale code
change (all 0s to all 1s and vice versa) using the write to and
update commands while monitoring the output of another
channel that is at midscale. The energy of the glitch is
expressed in nV-sec.
Multiplying Bandwidth
The amplifiers within the DAC have a finite bandwidth. The
multiplying bandwidth is a measure of this. A sine wave on the
reference (with full-scale code loaded to the DAC) appears on
the output.
Total Harmonic Distortion (THD)
THD is the difference between an ideal sine wave and its
attenuated version using the DAC. The sine wave is used as the
reference for the DAC, and the THD is a measurement of the
harmonics present on the DAC output. It is measured in dB.
Rev. 0 | Page 17 of 28
AD5686/AD5684 Data Sheet
×=
N
REF
OUT
D
GainVV
2
INPUT
REGISTER
DAC
REGISTER
RESISTOR
STRING
REF (+)
V
REF
GND
REF (–)
V
OUT
X
GAIN
(GAIN = 1 O R 2)
10797-052
R
R
R
R
R
TO OUTPUT
AMPLIFIER
V
REF
10797-053
THEORY OF OPERATION
DIGITAL-TO-ANALOG CONVERTER
The AD5686/AD5684 are quad, 16-/12-bit, serial input, voltage
output DACs. The parts operate from supply voltages of 2.7 V to
5.5 V. Data is written to the AD5686/AD5684 in a 24-bit word
format via a 3-wire serial interface. The AD5686/AD5684
incorporate a power-on reset circuit to ensure that the DAC
output powers up to a known output state. The devices also
have a software power-down mode that reduces the typical
current consumption to typically 4 µA.
TRANSFER FUNCTION
Because the input coding to the DAC is straight binary, the ideal
output voltage when using an external reference is given by
where:
D is the decimal equivalent of the binary code that is loaded to
the DAC register as follows:
0 to 4095 for the 12-bit device.
0 to 65,535 for the 16-bit device.
N is the DAC resolution.
V
is the value of the external reference.
REF
Gain is the gain of the output amplifier and is set to 1 by default.
The gain can be set to ×1 or ×2 using the gain select pin. When
this pin is tied to GND, all four DAC outputs have a span of 0 V
to V
. When this pin is tied to VDD, all four DAC outputs have
REF
a span of 0 V to 2 × V
REF
.
DAC ARCHITECTURE
The DAC architecture consists of a string DAC followed by an
output amplifier. Figure 36 shows a block diagram of the DAC
architecture.
Figure 36. Single DAC Channel Architecture Block Diagram
The resistor string structure is shown in Figure 37. It is a string
of resistors, each of Value R. The code loaded to the DAC register
determines the node on the string where the voltage is to be
tapped off and fed into the output amplifier. The voltage is
tapped off by closing one of the switches connecting the
string to the amplifier. Because the DAC is a string of resistors,
it is guaranteed monotonic.
Figure 37. Resistor String Structure
Output Amplifiers
The output buffer amplifier can generate rail-to-rail voltages on
its output, which gives an output range of 0 V to V
range depends on the value of V
, the GAIN pin, offset error,
REF
. The actual
DD
and gain error. The GAIN pin selects the gain of the output.
• If this pin is tied to GND, all four outputs have a gain of 1,
and the output range is 0 V to V
• If this pin is tied to V
, all four outputs have a gain of 2,
DD
and the output range is 0 V to 2 × V
REF
.
.
REF
These amplifiers are capable of driving a load of 1 kΩ in parallel
with 2 nF to GND. The slew rate is 0.8 V/µs with a ¼ to ¾ scale
settling time of 5 µs.
Rev. 0 | Page 18 of 28
Data Sheet AD5686/AD5684
0 0 0 0 No operation
0 0 0
1
DAC D
DAC C
DAC B
DAC A
1 0 0 0 DAC D
ADDRESS BITSCOMMAND BIT S
DACDDACCDACBDAC
A
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
C3 C2 C1 C0
DB23 (MSB) DB0 (LSB)
DATA BITS
10797-054
ADDRESS BITSCOMMAND BITS
DACDDACCDACBDAC
A
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X
C3 C2 C1 C0
DB23 (MSB) DB0 (LSB)
DATA BITS
10797-056
SERIAL INTERFACE
The AD5686/AD5684 have a 3-wire serial interface (
SCLK, and SDIN) that is compatible with SPI, QSPI™, and
MICROWIRE® interface standards as well as most DSPs. See
Figure 2 for a timing diagram of a typical write sequence. The
AD5686/AD5684 contain an SDO pin to allow the user to daisy-
chain multiple devices together (see the Daisy-Chain Operation
section) or for readback.
Input Shift Register
The input shift register of the AD5686/AD5684 is 24 bits wide.
Data is loaded MSB first (DB23). The first four bits are the
command bits, C3 to C0 (see Table 8), followed by the 4-bit
DAC address bits, DAC A, DAC B, DAC C, andDAC D (see
Table 9), and finally the bit data-word.
For the AD5686, the data-word comprises 16-bit input code(see
Figure 38). For the AD5684, the data-word comprises 12-bit input
code, followed by zero or four don’t care bits (see Figure 39).
These data bits are transferred to the input register on the 24
falling edges of SCLK and are updated on the rising edge
SYNC
of
.
Commands can be executed on individual DAC channels,
combined DAC channels, or on all DACs, depending on the
address bits selected (see Table 9).
SYNC
,
Table 8. Command Bit Definitions
Command Bits
C3 C2 C1 C0 Description
Write to Input Register n (dependent on
0 0 1 0
0 0 1 1 Write to and update DAC Channel n
0 1 0 0 Power down/power up DAC
0 1 0 1
0 1 1 0 Software reset (power-on reset)
0 1 1 1 Reserved
1 0 0 0 Set up DCEN register (daisy-chain enable)
1 0 0 1 Set up readback register (readback enable)
1 0 1 0 Reserved
… … … … Reserved
1 1 1 1 Reserved
Update DAC Register n with contents of Input
Register n
LDAC
Hardware
mask register
LDAC
Table 9. Address Bits and Selected DACs
Address Bits
Selected DAC Channel
0 0 0 1 DAC A
0 0 1 0 DAC B
0 1 0 0 DAC C
0 0 1 1 DAC A and DAC B
1 1 1 1 All DACs
1
Any combination of DAC channels can be selected using the address bits.
)
1
Figure 38. AD5686 Input Shift Register Conten ts
Figure 39. AD5684 Input Shift Register Conten ts
Rev. 0 | Page 19 of 28
AD5686/AD5684 Data Sheet
68HC11*
MISO
SDIN
SCLK
MOSI
SCK
PC7
PC6
SDO
SCLK
SDO
SCLK
SDO
SDIN
SDIN
SYNC
SYNC
SYNC
LDAC
LDAC
LDAC
AD5686/
AD5684
AD5686/
AD5684
AD5686/
AD5684
*ADDITIONAL PINS OMITTED FOR CLARITY.
10797-057
STANDALONE OPERATION
The write sequence begins by bringing the
from the SDIN line is clocked into the 24-bit input shift register
on the falling edge of SCLK. After the last of 24 data bits is
clocked in,
SYNC
should be brought high. The programmed
function is then executed, that is, an
in DAC register contents and/or a change in the mode of
SYNC
operation. If
is taken high at a clock before the 24th
clock, it is considered a valid frame and invalid data may be
loaded to the DAC.
of 20 ns (single channel, see t
sequence so that a falling edge of
write sequence.
SYNC
must be brought high for a minimum
in Figure 2) before the next write
8
SYNC
SYNC
should be idle at rails between write
sequences for even lower power operation of the part.
SYNC
The
line is kept low for 24 falling edges of SCLK, and the
DAC is updated on the rising edge of
After data is transferred into the input register of the addressed
DAC, all DAC registers and outputs can be updated by
taking
LDAC
low while the
SYNC
line is high.
WRITE AND UPDATE COMMANDS
Write to Input Register n (Dependent on
Command 0001 allows the user to write to each DAC’s
dedicated input register individually. When
the input register is transparent (if not controlled by the
LDAC
mask register).
Update DAC Register n with Contents of Input Register n
Command 0010 loads the DAC registers/outputs with the
contents of the selected input registers and updates the DAC
outputs directly.
Write to and Update DAC Channel n (Independent of
)
LDAC
Command 0011 allows the user to write to the DAC registers
and update the DAC outputs directly.
DAISY-CHAIN OPERATION
For systems that contain several DACs, the SDO pin can be
used to daisy-chain several devices together. This function
is enabled through a software executable daisy-chain enable
(DCEN) command. Command 1000 is reserved for this DCEN
function (see Table 8). The daisy-chain mode is enabled by
setting Bit DB0 in the DCEN register. The default setting is
standalone mode, where DB0 = 0. Table 10 shows how the state
of the bit corresponds to the mode of operation of the device.
Table 10. Daisy-Chain Enable (DCEN) Register
DB0 Description
0 Standalone mode (default)
1 DCEN mode
SYNC
line low. Data
LDAC
-dependent change
can initiate the next
SYNC
.
)
LDAC
LDAC
is low,
The SCLK pin is continuously applied to the input shift register
when
data ripples out of the input shift register and appears on the
SDO line. This data is clocked out on the rising edge of SCLK
and is valid on the falling edge. By connecting the SDO line to
the SDIN input on the next DAC in the chain, a daisy-chain
interface is constructed. Each DAC in the system requires 24
clock pulses. Therefore, the total number of clock cycles must
equal 24 × N, where N is the total number of devices that are
updated. If
of 24, it is considered a valid frame and invalid data may be
loaded to the DAC. When the serial transfer to all devices is
complete,
each device in the daisy chain and prevents any further data
from being clocked into the input shift register. The serial clock
can be continuous or a gated clock. A continuous SCLK source
can be used only if
number of clock cycles. In gated clock mode, a burst clock
containing the exact number of clock cycles must be used,
and
Rev. 0 | Page 20 of 28
Figure 40. Daisy-Chaining the AD5686/AD5684
SYNC
is low. If more than 24 clock pulses are applied, the
SYNC
is taken high at a clock that is not a multiple
SYNC
is taken high. This latches the input data in
SYNC
can be held low for the correct
SYNC
must be taken high after the final clock to latch the data.
Data Sheet AD5686/AD5684
RESISTOR
NETWORK
V
OUT
X
DAC
POWER-DOWN
CIRCUITRY
AMPLIFIER
10797-058
READBACK OPERATION
Readback mode is invoked through a software executable
readback command. If the SDO output is disabled via the daisychain mode disable bit in the control register, it is automatically
enabled for the duration of the read operation, after which it is
disabled again. Command 1001 is reserved for the readback
function. This command, in association with selecting one
of the address bits, DAC A to DAC D, selects the register to
read. Note that only one DAC register can be selected during
readback. The remaining three address bits must be set to
Logic 0. The remaining data bits in the write sequence are
don’t care bits. If more than one or no bits are selected, DAC
Channel A is read back by default. During the next SPI write,
the data appearing on the SDO output contains the data from
the previously addressed register.
For example, to read back the DAC register for Channel A, the
following sequence should be implemented:
1. Write 0x900000 to the AD5686/AD5684 input register.
This configures the part for read mode with the DAC
register of Channel A selected. Note that all data bits,
DB15 to DB0, are don’t care bits.
2. Follow this with a second write, a NOP condition,
0x000000. During this write, the data from the register
is clocked out on the SDO line. DB23 to DB20 contain
undefined data, and the last 16 bits contain the DB19 to
DB4 DAC register contents.
Table 11. Modes of Operation
Operating Mode PDx1 PDx0
Normal Operation 0 0
Power-Down Modes
1 kΩ to GND 0 1
100 kΩ to GND 1 0
Three-State 1 1
Any or all DACs (DAC A to DAC D) can be powered down
to the selected mode by setting the corresponding bits. See
Table 12 for the contents of the input shift register during the
power-down/power-up operation.
When both Bit PDx1 and Bit PDx0 (where x is the channel
selected) in the input shift register are set to 0, the parts work
normally with their normal power consumption of 0.59 mA at
5 V. However, for the three power-down modes, the supply
current falls to 4 μA at 5 V. Not only does the supply current
fall, but the output stage is also internally switched from the
output of the amplifier to a resistor network of known values.
This has the advantage that the output impedance of the part is
known while the part is in power-down mode. There are three
different power-down options (see Table 11). The output is
connected internally to GND through either a 1 kΩ or a 100 kΩ
resistor, or it is left open-circuited (three-state). The output stage
is illustrated in Figure 41.
POWER-DOWN OPERATION
The AD5686/AD5684 provide three separate power-down
modes (see Table 11). Command 0100 is designated for the powerdown function (see Table 8). These power-down modes are
software programmable by setting eight bits, Bit DB7 to Bit DB0,
in the input shift register. Two bits are associated with each DAC
channel. Tabl e 11 shows how the state of the two bits corresponds
to the mode of operation of the device.
The bias generator, output amplifier, resistor string, and other
associated linear circuitry are shut down when the power-down
mode is activated. However, the contents of the DAC registers
are unaffected when in power-down. The DAC registers can be
updated while the device is in power-down mode. The time
required to exit power-down is typically 4.5 µs for V
Table 12. 24-Bit Input Shift Register Contents for Power-Down/Power-Up Operation
Figure 41. Output Stage During Power-Down
1
DD
DB15
to
DB23 DB22 DB21 DB20 DB19 to DB16
DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1
0 1 0 0 X X PDD1 PDD0 PDC1 PDC0 PDB1 PDB0 PDA1 PDA0
Command bits (C3 to C0) Address bits
(don’t care)
1
X = don’t care.
Power-Down
Select DAC D
Power-Down
Select DAC C
Power-Down
Select DAC B
Power-Down
Select DAC A
= 5 V.
DB0
(LSB)
Rev. 0 | Page 21 of 28
AD5686/AD5684 Data Sheet
1
X1
DAC channels are updated and
LOGIC
LOGIC
SYNC
SCLK
V
OUT
X
DAC
REGISTER
INTERFACE
LOGIC
OUTPUT
AMPLIFIER
LDAC
SDO
SDIN
V
REF
INPUT
REGISTER
16-/12-BIT
DAC
10797-059
LOAD DAC (HARDWARE
The AD5686/AD5684 DACs have double buffered interfaces
consisting of two banks of registers: input registers and DAC
registers. The user can write to any combination of the input
registers. Updates to the DAC register are controlled by
LDAC
the
pin.
LDAC
PIN)
MASK REGISTER
LDAC
Command 0101 is reserved for the software
LDAC
function.
Address bits are ignored. Writing to the DAC using Command
LDAC
0101 loads the 4-bit
for each channel is 0; that is, the
register (DB3 to DB0). The default
LDAC
pin works normally.
Setting the bits to 1 forces this DAC channel to ignore transitions
on the
LDAC
pin, regardless of the state of the hardware
LDAC
pin. This flexibility is useful in applications where the user
LDAC
wishes to select which channels respond to the
LDAC
The
over the hardware
register gives the user extra flexibility and control
LDAC
pin (see Table 13). Setting the
pin.
LDAC
bits (DB3 to DB0) to 0 for a DAC channel means that this
channel’s update is controlled by the hardware
LDAC
pin.
Figure 42. Simplified Diagram of Input Loading Circuitry for a Single DAC
Instantaneous DAC Updating (
LDAC
is held low while data is clocked into the input register
LDAC
Held Low)
using Command 0001. Both the addressed input register and
SYNC
the DAC register are updated on the rising edge of
the output begins to change (see
Deferred DAC Updating (
LDAC
is held high while data is clocked into the input register
Table 14).
LDAC
Is Pulsed Low)
and
using Command 0001. All DAC outputs are asynchronously
LDAC
updated by taking
low after
high. The update now occurs on the falling edge of
Table 14. Write Commands and
Command Description
0001
0010 Update DAC Register n with contents of Input
0011 Write to and update DAC Channel n V
1
A high to low hardware
(blocked) by the
2
When LDAC is permanently tied low, the LDAC mask bits are ignored.
Write to Input Register n (dependent on
Register n
LDAC
LDAC
pin transition always updates the contents of the DAC register with the contents of the input register on channels that are not masked
mask register.
SYNC
has been taken
LDAC
Pin Truth Table1
LDAC
LDAC
.
)
Load
Bits
LDAC
LDAC
Overwrite Definition
Register
LDAC
Pin
LDAC
override the
channels see
Operation
LDAC
LDAC
pin.
LDAC
pin. DAC
as 1.
Table 13.
LDAC
(DB3 to DB0)
0 1 or 0 Determined by the
1
X = don’t care.
Hardware
Pin State
V
GND2 Data update Data update
V
LOGIC
GND No change Updated with input register contents
GND Data update Data update
LDAC
Input Register
Contents DAC Register Contents
Data update No change (no update)
No change Updated with input register contents
Data update Data update
Rev. 0 | Page 22 of 28
Data Sheet AD5686/AD5684
HARDWARE RESET (
RESET
is an active low reset that allows the outputs to be
cleared to either zero scale or midscale. The clear code value is
user selectable via the
RESET
keep
operation (see Figure 2). When the
high, the output remains at the cleared value until a new value
is programmed. The outputs cannot be updated with a new
value while the
executable reset function that resets the DAC to the poweron reset code. Command 0110 is designated for this software
reset function (see
during power-on reset are ignored.
low for a minimum of 30 ns to complete the
RESET
RESET
RESET
pin is low. There is also a software
Table 8). Any events on
)
select pin. It is necessary to
RESET
signal is returned
LDAC
or
RESET
RESET SELECT PIN (RSTSEL)
The AD5686/AD5684 contain a power-on reset circuit that
controls the output voltage during power-up. By connecting
the RSTSEL pin low, the output powers up to zero scale. Note
that this is outside the linear region of the DAC. By connecting
the RSTSEL pin high, V
remains powered up at this level until a valid write sequence
is made to the DAC.
powers up to midscale. The output
OUT
Rev. 0 | Page 23 of 28
AD5686/AD5684 Data Sheet
ADSP-BF531
SYNCSPISELx
SCLK
SCK
SDINMOSI
LDACPF9
RESETPF8
AD5686/
AD5684
10797-164
ADSP-BF527
SYNCSPORT_TFS
SCLKSPORT_TSCK
SDINSPORT_DTO
LDACGPIO0
RESETGPIO1
AD5686/
AD5684
10797-165
AD5686/
AD5684
GND
PLANE
BOARD
10797-166
APPLICATIONS INFORMATION
MICROPROCESSOR INTERFACING
Microprocessor interfacing to the AD5686/AD5684 is via a
serial bus that uses a standard protocol that is compatible with
DSP processors and microcontrollers. The communications
channel requires a 3- or 4-wire interface consisting of a clock
signal, a data signal, and a synchronization signal. The devices
require a 24-bit data-word with data valid on the rising edge
SYNC
of
.
AD5686/AD5684 TO ADSP-BF531 INTERFACE
The SPI interface of the AD5686/AD5684 is designed to be
easily connected to industry-standard DSPs and microcontrollers. Figure 43 shows the AD5686/AD5684 connected
to the Analog Devices, Inc., Blackfin® DSP. The Blackfin has an
integrated SPI port that can be connected directly to the SPI
pins of the AD5686/AD5684.
Figure 43. ADSP-BF531 Interface
AD5686/AD5684 TO SPORT INTERFACE
The Analog Devices ADSP-BF527 has one SPORT serial
port. Figure 44 shows how one SPORT interface can be used
to control the AD5686/AD5684.
LAYOUT GUIDELINES
In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to
ensure the rated performance. The PCB on which the AD5686/
AD5684 are mounted should be designed so that the AD5686/
AD5684 lie on the analog plane.
The AD5686/AD5684 should have ample supply bypassing
of 10 µF in parallel with 0.1 µF on each supply, located as close
to the package as possible, ideally right up against the device.
The 10 µF capacitors are the tantalum bead type. The 0.1 µF
capacitor should have low effective series resistance (ESR)
and low effective series inductance (ESI), such as the common
ceramic types, which provide a low impedance path to ground
at high frequencies to handle transient currents due to internal
logic switching.
In systems where there are many devices on one board, it is
often useful to provide some heat sinking capability to allow
the power to dissipate easily.
The AD5686/AD5684 LFCSP models have an exposed pad
beneath the device. Connect this pad to the GND supply for the
part. For optimum performance, use special considerations to
design the motherboard and to mount the package. For
enhanced thermal, electrical, and board level performance,
solder the exposed pad on the bottom of the package to the
corresponding thermal land pad on the PCB. Design thermal
vias into the PCB land pad area to further improve heat
dissipation.
The GND plane on the device can be increased (as shown in
Figure 45) to provide a natural heat sinking effect.
Figure 44. SPORT Interface
Figure 45. Pad Connection to Board
Rev. 0 | Page 24 of 28
Data Sheet AD5686/AD5684
ENCODE
SERIAL
CLOCK IN
CONTROLLER
ADuM1400
1
SERIAL
DATA OUT
SYNC OUT
LOAD DAC
OUT
DECODE
TO
SCLK
TO
SDIN
TO
SYNC
TO
LDAC
V
IA
V
OA
ENCODE
DECODE
V
IB
V
OB
ENCODE DECODE
V
IC
V
OC
ENCODE
DECODE
V
ID
V
OD
1
ADDITIONAL PINS OMITTED FOR CLARITY.
10797-167
GALVANICALLY ISOLATED INTERFACE
In many process control applications, it is necessary to
provide an isolation barrier between the controller and
the unit being controlled to protect and isolate the controlling
circuitry from any hazardous common-mode voltages that may
occur. iCoupler® products from Analog Devices provide voltage
isolation in excess of 2.5 kV. The serial loading structure of the
AD5686/AD5684 makes the part ideal for isolated interfaces
because the number of interface lines is kept to a minimum.
Figure 46 shows a 4-channel isolated interface to the AD5686/
AD5684 using an ADuM1400. For more information, visit
http://www.analog.com/icouplers.
Figure 46. Isolated Interface
Rev. 0 | Page 25 of 28
AD5686/AD5684 Data Sheet
3.10
3.00 SQ
2.90
0.30
0.23
0.18
1.75
1.60 SQ
1.45
08-16-2010-E
1
0.50
BSC
BOTTOM VIEWTOP VIEW
16
5
8
9
12
13
4
EXPOSED
PAD
PIN 1
INDICATOR
0.50
0.40
0.30
SEATING
PLANE
0.05 MAX
0.02 NOM
0.20 REF
0.25 MIN
COPLANARITY
0.08
PIN 1
INDICATOR
FOR PROP E R CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CO NFIGURATI ON AND
FUNCTIO N DE S CRIPTIONS
SECTION OF THIS DATA SHEET.
0.80
0.75
0.70
COMPLIANT
TO
JEDEC STANDARDS MO-220-WEED-6.
16
9
81
PIN 1
SEATING
PLANE
8°
0°
4.50
4.40
4.30
6.40
BSC
5.10
5.00
4.90
0.65
BSC
0.15
0.05
1.20
MAX
0.20
0.09
0.75
0.60
0.45
0.30
0.19
COPLANARITY
0.10
COMPLI ANT TO JEDEC S TANDARDS MO-153-AB
OUTLINE DIMENSIONS
Figure 47. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
3 mm × 3 mm Body, Very Very Thin Quad
(CP-16-22)
Dimensions shown in millimeters
Figure 48. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
Rev. 0 | Page 26 of 28
Data Sheet AD5686/AD5684
Package
Package
ORDERING GUIDE
Model1 Resolution Temperature Range Accuracy
AD5686ACPZ-RL7 16 Bits −40°C to +105°C ±8 LSB INL 16-Lead LFCSP_WQ CP-16-22 DJH
AD5686BCPZ-RL7 16 Bits −40°C to +105°C ±2 LSB INL 16-Lead LFCSP_WQ CP-16-22 DJJ
AD5686ARUZ 16 Bits −40°C to +105°C ±8 LSB INL 16-Lead TSSOP RU-16
AD5686ARUZ-RL7 16 Bits −40°C to +105°C ±8 LSB INL 16-Lead TSSOP RU-16
AD5686BRUZ 16 Bits −40°C to +105°C ±2 LSB INL 16-Lead TSSOP RU-16
AD5686BRUZ-RL7 16 Bits −40°C to +105°C ±2 LSB INL 16-Lead TSSOP RU-16
AD5684BCPZ-RL7 12 Bits −40°C to +105°C ±1 LSB INL 16-Lead LFCSP_WQ CP-16-22 DJP
AD5684ARUZ 12 Bits −40°C to +105°C ±2 LSB INL 16-Lead TSSOP RU-16
AD5684ARUZ-RL7 12 Bits −40°C to +105°C ±2 LSB INL 16-Lead TSSOP RU-16
AD5684BRUZ 12 Bits −40°C to +105°C ±1 LSB INL 16-Lead TSSOP RU-16
AD5684BRUZ-RL7 12 Bits −40°C to +105°C ±1 LSB INL 16-Lead TSSOP RU-16
EVAL-AD5686RSDZ 16-Bit Evaluation Board
EVAL-AD5684RSDZ 12-Bit Evaluation Board
1
Z = RoHS Compliant Part.
Description
Option
Branding
Rev. 0 | Page 27 of 28
AD5686/AD5684 Data Sheet
NOTES
©2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D10797-0-7/12(0)
Rev. 0 | Page 28 of 28
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