ANALOG DEVICES AD5684R Service Manual

Quad, 16-/14-/12-Bit nanoDAC+

V

with 2 ppm/°C Reference, SPI Interface

Data Sheet

FEATURES

High relative accuracy (INL): ±2 LSB maximum @ 16 bits Low drift 2.5 V reference: 2 ppm/°C typical Tiny package: 3 mm × 3 mm, 16-lead LFCSP

Total unadjusted error (TUE): ±0.1% of FSR maximum Offset error: ±1.5 mV maximum Gain error: ±0.1% of FSR maximum High drive capability: 20 mA, 0.5 V from supply rails User selectable gain of 1 or 2 (GAIN pin) Reset to zero scale or midscale (RSTSEL pin)

1.8 V logic compatibility 50 MHz SPI with readback or daisy chain Low glitch: 0.5 nV-sec Robust 4 kV HBM and 1.5 kV FICDM ESD rating Low power: 3.3 mW at 3 V

2.7 V to 5.5 V power supply

−40°C to +105°C temperature range

APPLICATIONS

Optical transceivers Base-station power amplifiers Process control (PLC I/O cards) Industrial automation Data acquisition systems

AD5686R/AD5685R/AD5684R

FUNCTIONAL BLOCK DIAGRAM

V

LOGIC

SCLK

SYNC

DD

AD5686R/AD5685R/AD5684R

SDIN

INTERFACE LOGIC

SDO

INPUT

REGISTER

INPUT

REGISTER

INPUT

REGISTER

INPUT

REGISTER

GND

DAC

REGISTER

DAC

REGISTER

DAC

REGISTER

DAC

REGISTER

POWER-ON

RESET

RSTSEL GAINLDAC RESET

Figure 1.

REF

STRING

DAC A

STRING

DAC B

STRING

DAC C

STRING

DAC D

GAIN ×1/×2

2.5V

REFERENCE

BUFFER

POWER-

DOWN LOGIC

V

A

OUT

V

B

OUT

V

C

OUT

V

D

OUT

10485-001

GENERAL DESCRIPTION

The AD5686R/AD5685R/AD5684R, members of the nanoDAC+® family, are low power, quad, 16-/14-/12-bit buffered voltage output DACs. The devices include a 2.5 V, 2 ppm/°C internal reference (enabled by default) and a gain select pin giving a full-scale output of 2.5 V (gain = 1) or 5 V (gain = 2). All devices operate from a single 2.7 V to 5.5 V supply, are guaranteed monotonic by design, and exhibit less than 0.1% FSR gain error and 1.5 mV offset error performance. The devices are available in a 3 mm × 3 mm LFCSP and a TSSOP package.

The AD5686R/AD5685R/AD5684R also incorporate a poweron reset circuit and a RSTSEL pin that ensures that the DAC outputs power up to zero scale or midscale and remains there until a valid write takes place. Each part contains a per-channel power-down feature that reduces the current consumption of the device to 4 μA at 3 V while in power-down mode.

The AD5686R/AD5685R/AD5684R employ a versatile SPI interface that operates at clock rates up to 50 MHz, and all devices contain a V

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

pin intended for 1.8 V/3 V/5 V logic.

LOGIC

Table 1. Quad nanoDAC+ Devices

Interface Reference 16-Bit 14-Bit 12-Bit

SPI Internal AD5686R AD5685R AD5684R I2C Internal AD5696R AD5695R AD5694R

PRODUCT HIGHLIGHTS

1. High Relative Accuracy (INL).

AD5686R (16-bit): ±2 LSB maximum AD5685R (14-bit): ±1 LSB maximum AD5684R (12-bit): ±1 LSB maximum

2. Low Drift 2.5 V On-Chip Reference.

2 ppm/°C typical temperature coefficient 5 ppm/°C maximum temperature coefficient

3. Two Pa ckage Opti ons .

3 mm × 3 mm, 16-lead LFCSP 16-lead TSSOP

AD5686R/AD5685R/AD5684R Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

AC Characteristics ........................................................................ 5

Timing Characteristics ................................................................ 6

Daisy-Chain and Readback Timing Characteristics ............... 7

Absolute Maximum Ratings ............................................................ 9

ESD Caution .................................................................................. 9

Pin Configuration and Function Descriptions ........................... 10

Typical Performance Characteristics ........................................... 11

Terminology .................................................................................... 18

Theory of Operation ...................................................................... 20

Digital-to-Analog Converter .................................................... 20

Transfer Function ....................................................................... 20

DAC Architecture ....................................................................... 20

Serial Interface ............................................................................ 21

Standalone Operation ................................................................ 22

Write and Update Commands .................................................. 22

Daisy-Chain Operation ............................................................. 23

Readback Operation .................................................................. 23

Power-Down Operation ............................................................ 24

Load DAC (Hardware

LDAC

Mask Register ................................................................. 25

Hardware Reset (

Reset Select Pin (RSTSEL) ........................................................ 26

Internal Reference Setup ........................................................... 26

Solder Heat Reflow ..................................................................... 26

Long-Term Temperature Drift ................................................. 26

Thermal Hysteresis .................................................................... 27

Applications Information .............................................................. 28

Microprocessor Interfacing ....................................................... 28

AD5686R/AD5685R/AD5684R to ADSP-BF531 Interface .. 28

AD5686R/AD5685R/AD5684R to SPORT Interface ............ 28

Layout Guidelines....................................................................... 28

Galvanically Isolated Interface ................................................. 29

Outline Dimensions ....................................................................... 30

Ordering Guide .......................................................................... 31

LDAC

Pin) ........................................... 25

) .......................................................... 26

RESET

REVISION HISTORY

4/12—Revision 0: Initial Version

Rev. 0 | Page 2 of 32

Data Sheet AD5686R/AD5685R/AD5684R

STATIC PERFORMANCE2

AD5686R

Resolution

16

Bits

% of

±3

±3 µV/mA

Due to load current change

Load Impedance at Rails6

25

25 Ω

See Figure 34

Power-Up Time

2.5

2.5 µs

Coming out of power-down mode;

SPECIFICATIONS

VDD = 2.7 V to 5.5 V; 1.8 V ≤ V

≤ 5.5 V; all specifications T

LOGIC

MIN

to T

, unless otherwise noted. RL = 2 kΩ; CL = 200 pF.

MAX

Table 2.

1

A Grade1 Parameter Min Typ Max Min Typ Max Unit Test Conditions/Comments

Relative Accuracy ±2 ±8 ±1 ±2 LSB Gain = 2 ±2 ±8 ±1 ±3 Gain = 1 Differential Nonlinearity ±1 ±1 LSB Guaranteed monotonic by design

AD5685R

Resolution 14 14 Bits Relative Accuracy ±0.5 ±4 ±0.5 ±1 LSB Differential Nonlinearity ±1 ±1 LSB Guaranteed monotonic by design

AD5684R

Resolution 12 12 Bits Relative Accuracy ±0.12 ±2 ±0.12 ±1 LSB

Differential Nonlinearity ±1 ±1 LSB Guaranteed monotonic by design Zero-Code Error 0.4 4 0.4 1.5 mV All zeros loaded to DAC register Offset Error +0.1 ±4 +0.1 ±1.5 mV Full-Scale Error +0.01 ±0.2 +0.01 ±0.1

Gain Error ±0.02 ±0.2 ±0.02 ±0.1

Total Unadjusted Error ±0.01 ±0.25 ±0.01 ±0.1

±0.25 ±0.2

Offset Error Drift Gain Temperature

Coefficient DC Power Supply Rejection

Ratio

3

DC Crosstalk3

±1 ±1 µV/°C ±1 ±1 ppm Of FSR/°C

0.15 0.15 mV/V DAC code = midscale; V

±2 ±2 µV

B Grade

% of FSR

FSR

All ones loaded to DAC register

External reference; gain = 2; TSSOP

Internal reference; gain = 1; TSSOP

= 5 V ± 10%

DD

Due to single channel, full-scale output change

±2 ±2 µV Due to powering do wn (per channel)

OUTPUT CHARACTERISTICS3

Output Voltage Range 0 V 0 2 × V Capacitive Load Stability 2 2 nF RL = ∞ 10 10 nF RL = 1 kΩ Resistive Load4 1 1 kΩ Load Regulation 80 80 µV/mA

80 80 µV/mA

Short-Circuit Current5 40 40 mA

0 V

REF

0 2 × V

REF

Rev. 0 | Page 3 of 32

V Gain = 1

REF

V Gain = 2, see Figure 34

REF

5 V ± 10%, DAC code = midscale;

−30 mA ≤ I 3 V ± 10%, DAC code = midscale;

−20 mA ≤ I

VDD = 5 V

≤ 30 mA

OUT

≤ 20 mA

OUT

AD5686R/AD5685R/AD5684R Data Sheet

8, 9

20

µ

At ambient

125

125 ppm

First cycle

Pin Capacitance

2 2 pF

I

3

µ

1

A Grade1

B Grade

Parameter Min Typ Max Min Typ Max Unit Test Conditions/Comments

REFERENCE OUTPUT

Output Voltage7 2.4975 2.5025 2.4975 2.5025 V At ambient Reference TC Output Impedance3

Output Voltage Noise3 Output Voltage Noise

Density Load Regulation Sourcing3 Load Regulation Sinking3 Output Current Load

Capability Line Regulation3 Long-Term Stability/Drift3

5 20 2 5 ppm/°C See the Terminology section

0.04 0.04 Ω 12 12

3

240 240 nV/√Hz

40 ±5

40

mA VDD ≥ 3 V

±5

µV p-p

V/mA

µV/mA

0.1 Hz to 10 Hz At ambient; f = 10 kHz, C

At ambient

100 100 µV/V At ambient 12 12 ppm After 1000 hours at 125°C

= 10 nF

L

Thermal Hysteresis3 25 25 ppm Additional cycles

LOGIC INPUTS3

Input Current ±2 ±2 µA Per pin V

, Input Low Voltage 0.3 × V

INL

V

, Input High Voltage 0.7 × V

INH

LOGIC OUTPUTS (SDO)3

0.7 × V

LOGIC

Output Low Voltage, VOL 0.4 0.4 V Output High Voltage, VOH V Floating State Output

− 0.4 V

LOGIC

4 4 pF

0.3 × V

LOGIC

V

LOGIC

− 0.4 V

LOGIC

V

LOGIC

= 200 μA

I

SINK

I

SOUR CE

= 200 μA

Capacitance

POWER REQUIREMENTS

V

LOGIC

1.8 5.5 1.8 5.5 V A

VDD 2.7 5.5 2.7 5.5 V Gain = 1 VDD V

+ 1.5 5.5 V

REF

+ 1.5 5.5 V Gain = 2

REF

IDD VIH = VDD, VIL = GND, VDD = 2.7 V to 5.5 V

Normal Mode10 0.59 0.7 0.59 0.7 mA Internal reference off

1.1 1.3 1.1 1.3 mA Internal reference on, at full scale All Power-Down

11

Modes

1 4 1 4 µA −40°C to +85°C

6 6 µA −40°C to +105°C

1

Temperature range: A and B grade: −40°C to +105°C.

2

DC specifications tested with the outputs unloaded, unless otherwise noted. Upper dead band = 10 mV and exists only when V

with gain = 2. Linearity calculated using a reduced code range of 256 to 65,280 (AD5686R), 64 to 16,320 (AD5685R), and 12 to 4080 (AD5684R).

V

DD

3

Guaranteed by design and characterization; not production tested.

4

Channel A and Channel B can have a combined output current of up to 30 mA. Similarly, Channel C and Channel D can have a combined output current of up to

30 mA up to a junction temperature of 110°C.

5

VDD = 5 V. The device includes current limiting that is intended to protect the device during temporary overload conditions. Junction temperature can be exceeded

during current limit. Operation above the specified maximum operation junction temperature may impair device reliability.

6

When drawing a load current at either rail, the output voltage headroom with respect to that rail is limited by the 25 Ω typical channel resistance of the output

devices. For example, when sinking 1 mA, the minimum output voltage = 25 Ω × 1 mA = 25 mV (see

7

Initial accuracy presolder reflow is ±750 µV; output voltage includes the effects of preconditioning drift. See the Internal Reference Setup section.

8

Reference is trimmed and tested at two temperatures and is characterized from −40°C to +105°C.

9

Reference temperature coefficient calculated as per the box method. See the Terminology section for further information.

10

Interface inactive. All DACs active. DAC outputs unloaded.

11

All DACs powered down.

Figure 34).

= VDD with gain = 1 or when V

REF

/2 =

Rev. 0 | Page 4 of 32

Data Sheet AD5686R/AD5685R/AD5684R

Total Harmonic Distortion4

−80 dB

At ambient, BW = 20 kHz, VDD = 5 V, f

= 1 kHz

AC CHARACTERISTICS

VDD = 2.7 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; 1.8 V ≤ V

1

noted.

Table 3.

Parameter2 Min Typ Max Unit Test Conditions/Comments3

Output Voltage Settling Time

AD5686R 5 8 µs ¼ to ¾ scale settling to ±2 LSB AD5685R 5 8 µs ¼ to ¾ scale settling to ±2 LSB

AD5684R 5 7 µs ¼ to ¾ scale settling to ±2 LSB

Slew Rate 0.8 V/µs Digital-to-Analog Glitch Impulse 0.5 nV-sec 1 LSB change around major carry Digital Feedthrough 0.13 nV-sec Digital Crosstalk 0.1 nV-sec Analog Crosstalk 0.2 nV-sec DAC-to-DAC Crosstalk 0.3 nV-sec

Output Noise Spectral Density 300 nV/√Hz DAC code = midscale, 10 kHz; gain = 2 Output Noise 6 µV p-p 0.1 Hz to 10 Hz SNR 90 dB At ambient, BW = 20 kHz, VDD = 5 V, f SFDR 83 dB At ambient, BW = 20 kHz, VDD = 5 V, f SINAD 80 dB At ambient, BW = 20 kHz, VDD = 5 V, f

1

Guaranteed by design and characterization, not production tested.

2

See the Terminology section.

3

Temperature range is −40°C to +105°C, typical @ 25°C.

4

Digitally generated sine wave @ 1 kHz.

≤ 5.5 V; all specifications T

LOGIC

MIN

to T

, unless otherwise

MAX

OUT

= 1 kHz

OUT

= 1 kHz

OUT

= 1 kHz

OUT

Rev. 0 | Page 5 of 32

AD5686R/AD5685R/AD5684R Data Sheet

Minimum

High Time (Single, Combined or All Channel Update)

t8

20 20 ns

t

4

t

3

SCLK

SYNC

SDIN

t

1

t

2

t

5

t

6

t

7

t

8

DB23

t

9

t

10

t

11

LDAC

1

LDAC

2

t

12

1

ASYNCHRONOUS LDAC UPDATE MODE .

2

SYNCHRONOUS LDAC UPDATE MODE .

RESET

t

13

t

14

V

OUT

DB0

10485-002

TIMING CHARACTERISTICS

All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 2. V

= 2.7 V to 5.5 V, 1.8 V ≤ V

DD

Table 4.

Parameter1 Symbol Min Max Min Max Unit SCLK Cycle Time t1 33 20 ns SCLK High Time t2 16 10 ns SCLK Low Time t3 16 10 ns

to SCLK Falling Edge Setup Time t4 15 10 ns

SYNC Data Setup Time t5 5 5 ns Data Hold Time t6 5 5 ns SCLK Falling Edge to

Rising Edge t7 15 10 ns

SYNC

Falling Edge to SCLK Fall Ignore t9 16 10 ns

SYNC

Pulse Width Low t10 25 15 ns

LDAC SCLK Falling Edge to SCLK Falling Edge to

Minimum Pulse Width Low t13 30 30 ns

RESET

Pulse Activation Time t14 30 30 ns

RESET

Rising Edge t11 30 20 ns

LDAC

Falling Edge t12 20 20 ns

LDAC

Power-Up Time2 4.5 4.5 µs

1

Maximum SCLK frequency is 50 MHz at VDD = 2.7 V to 5.5 V, 1.8 V ≤ V

2

Time to exit power-down to normal mode of AD5686R/AD5685R/AD5684R operation, 32nd clock edge to 90% of DAC midscale value, with output unloaded.

LOGIC

≤ 5.5 V; V

= 2.5 V. All specifications T

REFIN

≤ VDD. Guaranteed by design and characterization; not production tested.

LOGIC

MIN

to T

1.8 V ≤ V

, unless otherwise noted.

MAX

< 2.7 V 2.7 V ≤ V

LOGIC

≤ 5.5 V

Figure 2. Serial Write Operation

Rev. 0 | Page 6 of 32

Data Sheet AD5686R/AD5685R/AD5684R

SCLK High Time

t2

33 20 ns

10485-003

200µA I

OL

200µA I

OH

V

OH

(MIN)

TO OUTPUT

C

L

20pF

t

4

t

5

t

6

t

8

SDO

SDIN

SYNC

SCLK

4824

DB23 DB0 DB23 DB0

DB23

INPUT WORD FOR DAC NUNDEFINED

INPUT WORD FOR DAC N + 1INPUT WORD FOR DAC N

DB0

t

11

t

12

t

10

10485-004

DAISY-CHAIN AND READBACK TIMING CHARACTERISTICS

All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 4 and Figure 5. V

2.7 V to 5.5 V.

Table 5.

1.8 V ≤ V Parameter1 Symbol Min Max Min Max Unit

SCLK Cycle Time t1 66 40 ns

SCLK Low Time t3 33 20 ns

to SCLK Falling Edge t4 33 20 ns

SYNC Data Setup Time t5 5 5 ns

Data Hold Time t6 5 5 ns SCLK Falling Edge to Minimum Minimum

SDO Data Valid from SCLK Rising Edge t10 36 25 ns SCLK Falling Edge to

Rising Edge to SCLK Rising Edge t

SYNC

1

Maximum SCLK frequency is 25 MHz or 15 MHz at VDD = 2.7 V to 5.5 V, 1.8 V ≤ V

Circuit and Timing Diagrams

= 2.7 V to 5.5 V, 1.8 V ≤ V

DD

Rising Edge t7 15 10 ns

SYNC

High Time t8 60 30 ns

SYNC

High Time t9 60 30 ns

SYNC

Rising Edge t

SYNC

≤ 5.5 V; V

LOG IC

5

15 10 ns

11

5

15 10 ns

12

= 2.5 V. All specifications T

REF

< 2.7 V 2.7 V ≤ V

LOGIC

≤ VDD. Guaranteed by design and characterization; not production tested.

LOGIC

MIN

to T

, unless otherwise noted. VDD =

MAX

≤ 5.5 V

LOGIC

Figure 3. Load Circuit for Digital Output (SDO) Timing Specifications

Figure 4. Daisy-Chain Timing Diagram

Rev. 0 | Page 7 of 32

AD5686R/AD5685R/AD5684R Data Sheet

10485-005

SYNC

t

8

t

6

SCLK

24

1

24

1

t

9

t

4

t

2

t

7

t

3

t

1

DB23 DB0 DB23 DB0

SDIN

NOP CONDITIONINPUT WORD SPECIFIES

REGIST E R TO BE READ

t

5

DB23 DB0 DB23 DB0

SDO

SELECTED REGISTER DATA

CLOCKED OUT

UNDEFINED

t

10

Figure 5. Readback Timing Diagram

Rev. 0 | Page 8 of 32

Data Sheet AD5686R/AD5685R/AD5684R

Storage Temperature Range

−65°C to +150°C

Reflow Soldering Peak

260°C

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 5.

Parameter Rating

VDD to GND −0.3 V to +7 V V

to GND −0.3 V to +7 V

LOGIC

V

to GND −0.3 V to VDD + 0.3 V

OUT

V

to GND −0.3 V to VDD + 0.3 V

REF

Digital Input Voltage to GND −0.3 V to V Operating Temperature Range −40°C to +105°C

Junction Temperature 125°C 16-Lead TSSOP, θJA Thermal

Impedance, 0 Airflow (4-Layer Board) 16-Lead LFCSP, θJA Thermal

Impedance, 0 Airflow (4-Layer Board)

112.6°C/W

70°C/W

LOGIC

+ 0.3 V

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

Temperature, Pb Free (J-STD-020) ESD1 4 kV FICDM 1.5 kV

1

Human body model (HBM) classification.

Rev. 0 | Page 9 of 32

AD5686R/AD5685R/AD5684R Data Sheet

Pin No.

12

14

SDIN

Serial Data Input. This device has a 24-bit input shift register. Data is clocked into the register on the

Power-On Reset Pin. Tying this pin to GND powers up all four DACs to zero scale. Tying this pin to VDD powers up all four DACs to midscale.

12 11 10

1

3 4

SDIN SYNC SCLK

9

V

LOGIC

V

OUT

A

V

DD

2

GND

V

OUT

C

6

SDO

5

V

OUT

D

7

LDAC

8

GAIN

16

V

OUT

B

15

V

REF

14

RSTSEL

13

RESET

AD5686R/AD5685R/AD5684R

NOTES

1. THE EXPOSED PAD MUST BE TIED TO GND.

TOP VIEW

(Not to S cale)

10485-006

1

2

3

4

5

6

7

8

V

OUT

B

V

OUT

A

GND

V

OUT

D

V

OUT

C

V

DD

V

REF

SDO

16

15

14

13

12

11

10

9

RESET SDIN SYNC

GAIN LDAC

V

LOGIC

SCLK

RSTSEL

TOP VIEW

(Not to S cale)

AD5686R/ AD5685R/

AD5684R

10485-007

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Figure 6. 16-Lead LFCSP Pin Configuration

Table 6. Pin Function Descriptions

Mnemonic Description LFCSP TSSOP

1 3 V

A Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.

OUT

2 4 GND Ground Reference Point for All Circuitry on the Part. 3 5 VDD Power Supply Input. These parts can be operated from 2.7 V to 5.5 V, and the supply should be

decoupled with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND. 4 6 V 5 7 V

C Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.

OUT

D Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.

OUT

6 8 SDO Serial Data Output. Can be used to daisy-chain a number of AD5686R/AD5685R/AD5684R devices

together or can be used for readback. The serial data is transferred on the rising edge of SCLK and is

valid on the falling edge of the clock. 7 9

LDAC

can be operated in two modes, asynchronously and synchronously. Pulsing this pin low allows

LDAC

any or all DAC registers to be updated if the input registers have new data. This allows all DAC outputs

to simultaneously update. This pin can also be tied permanently low. 8 10 GAIN Span Set Pin. When this pin is tied to GND, all four DAC outputs have a span from 0 V to V

9 11 V

pin is tied to V

Digital Power Supply. Voltage ranges from 1.8 V to 5.5 V.

LOGIC

, all four DACs output a span of 0 V to 2 × V

DD

10 12 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock

input. Data can be transferred at rates of up to 50 MHz. 11 13

Active Low Control Input. This is the frame synchronization signal for the input data. When

SYNC

goes low, data is transferred in on the falling edges of the next 24 clocks.

falling edge of the serial clock input. 13 15

Asynchronous Reset Input. The

RESET

pulses are ignored. When

input is falling edge sensitive. When

RESET

is activated, the input register and the DAC register are updated with

RESET

zero scale or midscale, depending on the state of the RSTSEL pin. 14 16 RSTSEL

15 1 V

16 2 V 17 N/A EPAD Exposed Pad. The exposed pad must be tied to GND.

Reference Voltage. The AD5686R/AD5685R/AD5684R have a common reference pin. When using

REF

the internal reference, this is the reference output pin. When using an external reference, this is the

reference input pin. The default for this pin is as a reference output.

B Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.

OUT

Rev. 0 | Page 10 of 32

Figure 7. 16-Lead TSSOP Pin Configuration

.

REF

is low, all

RESET

. If this

REF

SYNC

LDAC

ANALOG DEVICES AD5684R Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

FUNCTIONAL BLOCK DIAGRAM

GENERAL DESCRIPTION

PRODUCT HIGHLIGHTS

REVISION HISTORY

SPECIFICATIONS

AC CHARACTERISTICS

TIMING CHARACTERISTICS

DAISY-CHAIN AND READBACK TIMING CHARACTERISTICS

Circuit and Timing Diagrams

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS