Analog Devices AD5678 prb Datasheet

4 x12-Bit and 4 x16-Bit Octal DAC with

On-Chip Reference in 14 Lead TSSOP

Preliminary Technical Data

FEATURES

Low Power Octal DAC with
4 DACs x 16 Bits

4 DACs x 12 Bits
14/16-Lead TSSOP Package
On-chip 1.25/2.5V, 10ppm/°C Reference
Power-Down to 200 nA @ 5V, 50 nA @ 3V
3V/5V Power Supply
Guaranteed Monotonic by Design
Power-On-Reset to Zero
Three Power-Down Functions
Hardware /LDAC and /CLR functions
Rail-to-Rail Operation
Temperature Range -40°C to +125°C

APPLICATIONS

ProcessControl
Data Acquisition Systems
Portable Battery Powered Instruments
Digital Gain and Offset Adjustment
Programmable Voltage and Current Sources

GENERAL DESCRIPTION

The AD5678 is a low power, octal buffered voltage-out DAC; 4
DACs with 12-bits of resolution and 4 DACs with16-bits of
resolution, in a single package. All devices operate from a
single +2.7V to +5.5V, and are guaranteed monotonic by
design.

The AD5678 has an on-chip reference with an internal gain of
two. The AD5678-1 has a 1.25V 10ppm/°C max reference and
the AD5678-2, has a 2.5V 10ppm/°C max reference. The on­board reference is off at power-up allowing the use of an
external reference. The internal reference is turned on by
writing to the DAC. The part incorporates a power-on-reset
circuit that ensures that the DAC output powers up to zero
volts and remains there until a valid write takes place. The part
contains a power-down feature that reduces the current
consumption of the device to 200nA at 5V and provides
software selectable output loads while in power-down mode for
any or all DACs channels.

AD5678

Programmable Attenuators

V

I

NPUT

REGISTER

I

NPUT

REGISTER

I

NPUT

REGISTER

I

NPUT

REGISTER

I

NPUT

REGIS-

TER

I

NPUT

REGISTER

I

NPUT

REGISTER

I

NPUT

REGISTER

POWER-ON

DD

REGISTER

REGISTER

REGISTER

REGISTER

REGISTER

REGISTER

REGISTER

RESET

SCLK

SYNC

DIN

*RU-16 PACKAGE ONLY

AD5678

LDAC

INTERFACE

LOGIC

LDAC*

CLR*

Figure 1. Functional Block Diagram

The outputs of all DACs may be updated simultaneously using
the /LDAC function, with the added functionality of selecting
through software any number of DAC channels to synchronize.
There is also an asynchronous active low /CLR that clears all
DACs to a software selectable code - 0 V, midscale or fullscale .

The AD5678 utilizes a versatile three-wire serial interface that
operates at clock rates up to 50 MHz and is compatible with
standard SPI™, QSPI™, MICROWIRE™ and DSP interface
standards. Its on-chip precision output amplifier allows rail-to­rail output swing to be achieved.

PRODUCT HIGHLIGHTS

1. Octal – 4x12-/4x16-Bit DAC; 12-Bit Accuracy

Guaranteed.

2. On-chip 1.25/2.5V, 10ppm/°C max Reference.

3. Available in 14/16-lead TSSOP package.

4. Power-On-Reset to Zero volts.

5. Power-down capability. When powered down, the

DAC typically consumes 50nA at 3V and 200nA at 5V.

DAC

DAC

DAC

D

AC

REGISTER

D

AC

D

AC

D

AC

D

AC

V

STRING

DAC A

STRING

DAC B

STRING

DAC C

STRING
DAC D

STRING
DAC E

STRING

DAC F

STRING
DAC G

STRING

DAC H

REF

1.25/2.5V
Ref

BUFFER

BUFFER

BUFFER

BUFFER

BUFFER

BUFFER

BUFFER

BUFFER

POWER-DOWN

GND

LOGIC

V

A

OUT

V

B

OUT

V

C

OUT

V

D

OUT

V

E

OUT

V

F

OUT

V

G

OUT

V

H

OUT

Rev. PrB

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2005 Analog Devices, Inc. All rights reserved.

AD5678

TABLE OF CONTENTS

Features.......................................................................................... 1

Preliminary Technical Data

Terminology................................................................................ 10

Applications................................................................................... 1

General Description..................................................................... 1

Product Highlights....................................................................... 1

AD5678–Specifications.................................................................... 3

Timing Characteristics..................................................................... 8

Pin Configuration and Function Descriptions............................. 9

Absolute Maximum Ratings.......................................................... 10

ESD Caution................................................................................ 10

REVISION HISTORY

Revision 0: Initial Version

AD5678–Typical Performance Characteristics .......................... 12

General Description................................................................... 15

Serial Interface............................................................................ 15

Microprocessor Interfacing............................................................

Applications .....................................................................................

Outline Dimensions....................................................................... 22

Ordering Guide ...............................................................................

Rev.PrB | Page 2 of 22

Preliminary Technical Data

AD5678

AD5678–SPECIFICATIONS

(VDD = +4.5 V to +5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; External REFIN = VDD; all specifications T
noted)

Table 1.

A Grade

B Version

Parameter Min Typ Max Unit

STATIC PERFORMANCE

3,4

Conditions/Comments

1,2

AD5678 (DAC C, D, E, F)
Resolution 12 Bits
Relative Accuracy ±0.5 ±6 LSB See Figure 4
Differential Nonlinearity ±1 LSB Guaranteed Monotonic by Design. See Figure 5.
AD5678 (DAC A, B, G, H)
Resolution 16 Bits
Relative Accuracy ±32 LSB See Figure 4
Differential Nonlinearity ±1 LSB Guaranteed Monotonic by Design. See Figure 5.
Load Regulation 2 LSB/mA

VDD=Vref=5V, Midscale

sourcing/sinking
Zero Code Error +1 +9 mV All Zeroes Loaded to DAC Register. See Figure 8.
Zero Code Error Drift3 ±20 µV/°C
Full-Scale Error -0.15 -1.25 % of FSR All Ones Loaded to DAC Register. See Figure 8.
Gain Error ±0.7 % of FSR
Gain Temperature Coefficient ±5 ppm of FSR/°C
Offset Error ±1 ±9 mV
Offset Temperature Coefficient 1.7 µV/°C

DC Power Supply Rejection Ratio6

DC Crosstalk6 (Ext Ref)

DC Crosstalk6 (Int Ref)

10

4.5

10

20

4.5

20

–80

dB VDD ±10%

µV
µV/mA
µV
µV
µV/mA
µV

RL = 2 k. to GND or VDD

Due to Load current change

Due to Powering Down (per channel)

RL = 2 k. to GND or VDD

Due to Load current change

Due to Powering Down (per channel)

OUTPUT CHARACTERISTICS6
Output Voltage Range 0 VDD V
Capacitive Load Stability 2 pF RL=∞
10 pF RL=2 kΩ
DC Output Impedance 0.5 Ω
Short Circuit Current 30 mA VDD=+5V
Power-Up Time 4 µs Coming out of Power-Down Mode. VDD=+5V

REFERENCE INPUTS3

Reference Input voltage

Reference Current 35 45 µ A V

VDD

V ±1% for specified performance

= VDD = +5.5V (per DAC channel)

REF

1

Temperature ranges are as follows: B Version: -40°C to +125°C, typical at 25°C.

2

Linearity calculated using a reduced code range of 485 to 64714. Output unloaded.

3

DC specifications tested with the outputs unloaded unless stated otherwise.

4

Linearity is tested using a reduced code range: AD5628 (Code 48 to Code 4047), AD5648 (Code / to Code /), and AD5678 (Code 485 to 64714).

6

Guaranteed by design and characterization; not production tested.

8

Interface inactive. All DACs active. DAC outputs unloaded.

9

All eight DACs powered down.

Specifications subject to change without notice.

MIN

to T

unless otherwise

MAX

Iout=0mA to 15mA

Rev. PrB| Page 3 of 22

AD5678

A Grade

Parameter Min Typ Max Unit

Reference Input Range 0 VDD

Reference Input Impedance 14.6

REFERENCE OUTPUT
Output Voltage
AD5678x-2/3 2.495 2.5 2.505 V
Reference TC ±10 ppm/°C
Reference Output Impedance 2

LOGIC INPUTS3
Input Current ±1 µA
V

, Input Low Voltage 0.8 V VDD=+5 V

INL

V

, Input High Voltage 2 V VDD=+5 V

INH

Pin Capacitance 3 pF
POWER REQUIREMENTS
VDD 4.5 5.5 V All Digital Inputs at 0 or VDD
IDD (Normal Mode)8 DAC Active and Excluding Load Current
VDD=4.5 V to +5.5 V 2 4 mA VIH=VDD and VIL=GND
IDD (All Power-Down Modes)9
VDD=4.5 V to +5.5 V 0.2 1 µA VIH=VDD and VIL=GND
POWER EFFICIENCY
I

89 % I

OUT/IDD

kΩ

kΩ

Preliminary Technical Data

B Version
Conditions/Comments

Per DAC channel

LOAD

1,2

=2 mA, VDD=+5 V

Rev.PrB | Page 4 of 22

Preliminary Technical Data

1

AC CHARACTERISTICS

specifications T

MIN

to T

unless otherwise noted)

MAX

(VDD = +4.5 V to +5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; External REFIN = VDD; all

AD5678

Parameter2 Min Typ Max Unit

Output Voltage Settling Time
AD5678 (DAC C, D, E, F) 6 8 µs ¼ to ¾ scale settling to ±2LSB
AD5678 (DAC A, B, G, H) 8 10 µs ¼ to ¾ scale settling to ±2LSB
Settling Time for 1LSB Step
Slew Rate 1.5 V/µs
Digital-to-Analog Glitch Impulse 5 nV-s 1 LSB Change Around Major Carry. See Figure 21.
Channel –to-Channel Isolation 100 dB
Digital Feedthrough 0.1 nV-s
Digital Crosstalk 0.5 nV-s
Analog Crosstalk 1 nV-s
DAC-to-DAC Crosstalk 3 nV-s
Multiplying Bandwidth 200 kHz VREF = 2V ± 0.1 V p-p.
Total Harmonic Distortion -80 dB VREF = 2V ± 0.1 V p-p. Frequency = 10kHz
Output Noise Spectral Density 120 nV/√Hz DAC code=8400H, 1kHz
100 nV/√Hz DAC code=8400H, 10kHz
Output Noise 15

1

µVp-p

B Version
Conditions/Comments

0.1Hz to 10Hz;

NOTES

1Guaranteed by design and characterization; not production tested.
2See the Terminology section.
3Temperature range (Y Version): –40°C to +125°C; typical at +25°C.

Specifications subject to change without notice.

Rev. PrB| Page 5 of 22

AD5678

Preliminary Technical Data

AD5678–SPECIFICATIONS

(VDD = +2.7 V to +3.6 V; RL = 2 kΩ to GND; CL = 200 pF to GND; External REFIN = VDD; all specifications T
noted)

Table 2

A Grade

B Version

Parameter Min Typ Max Unit

STATIC PERFORMANCE
AD5678 (DAC C, D, E, F)
Resolution 12 Bits
Relative Accuracy ±0.5 ±6 LSB See Figure 4
Differential Nonlinearity ±1 LSB Guaranteed Monotonic by Design. See Figure 5.
AD5678 (DAC A, B, G, H)
Resolution 16 Bits
Relative Accuracy ±32 LSB See Figure 4
Differential Nonlinearity ±1 LSB Guaranteed Monotonic by Design. See Figure 5.
Load Regulation 4 LSB/mA

Zero Code Error +1 +9 mV All Zeroes Loaded to DAC Register. See Figure 8.
Zero Code Error Drift1 ±20 µV/°C
Full-Scale Error -0.15 -1.25 % of FSR All Ones Loaded to DAC Register. See Figure 8.
Gain Error ±0.7 % of FSR
Gain Temperature Coefficient ±5 ppm of FSR/°C
Offset Error ±1 ±9 mV
Offset Temperature Coefficient 1.7 µV/°C

DC Power Supply Rejection Ratio6

DC Crosstalk6 (Ext Ref)

DC Crosstalk6 (Int Ref)

OUTPUT CHARACTERISTICS6
Output Voltage Range 0 VDD V
Capacitive Load Stability 2 pF RL=∞
10 pF RL=2 kΩ
DC Output Impedance 0.5 Ω
Short Circuit Current 30 mA VDD=+3V
Power-Up Time 5 µs Coming Out of Power-Down Mode. VDD=+3V

REFERENCE INPUTS3

Reference Input voltage VDD V ±1% for specified performance

Reference Current 20 20 µ A V

Reference Input Range 0 VDD

Reference Input Impedance 14.6

REFERENCE OUTPUT
Output Voltage
AD5678x-1 1.248 1.25 1.252 V
Reference TC ±10 ppm/°C

3,4

–80

10

4.5

10

20

4.5

20

dB VDD = ±10%

µV
µV/mA
µV
µV
µV/mA
µV

kΩ

Conditions/Comments

VDD=Vref=3V, Midscale

sourcing/sinking

RL = 2 k. to GND or VDD

Due to Load current change

Due to Powering Down (per channel)

RL = 2 k. to GND or VDD

Due to Load current change

Due to Powering Down (per channel)

REF

Per DAC channel

1,1

= VDD = +3.6V (per DAC channel)

MIN

to T

unless otherwise

MAX

Iout=0mA to 7.5mA

Rev.PrB | Page 6 of 22

Preliminary Technical Data

AD5678

Reference Output Impedance 2

kΩ

LOGIC INPUTS3
Input Current ±1 µA
V

, Input Low Voltage 0.8 V VDD=+3 V

INL

V

, Input High Voltage 2 V VDD=+3 V

INH

Pin Capacitance 3 pF
POWER REQUIREMENTS
VDD 2.7 3.6 V All Digital Inputs at 0 or VDD
IDD (Normal Mode)8 DAC Active and Excluding Load Current
VDD=2.7 V to +3.6 V 2 4 mA VIH=VDD and VIL=GND
IDD (All Power-Down Modes)9
VDD=2.7 V to +3.6 V 0.2 1 µA VIH=VDD and VIL=GND
POWER EFFICIENCY
I

89 % I

OUT/IDD

=2 mA, VDD=+5 V

LOAD

AC CHARACTERISTICS1

(VDD = +2.7 V to +3.6 V; RL = 2 kΩ to GND; CL = 200 pF to GND; External REFIN = VDD; all specifications T
noted)

B Version

Parameter2 Min Typ Max Unit

Conditions/Comments

1

Output Voltage Settling Time
AD5678 (DAC C, D, E, F) 6 8 µs ¼ to ¾ scale settling to ±2LSB
AD5678 (DAC A, B, G, H) 8 10 µs ¼ to ¾ scale settling to ±2LSB
Settling Time for 1LSB Step
Slew Rate 1.5 V/µs
Digital-to-Analog Glitch Impulse 10 nV-s 1 LSB Change Around Major Carry. See Figure 21.
Channel –to-Channel Isolation 100 dB
Digital Feedthrough 0.5 nV-s
Digital Crosstalk 0.5 nV-s
Analog Crosstalk 1 nV-s
DAC-to-DAC Crosstalk 3 nV-s
Multiplying Bandwidth 200 kHz VREF = 2V ± 0.1 V p-p.
Total Harmonic Distortion -80 dB VREF = 2V ± 0.1 V p-p. Frequency = 10kHz
Output Noise Spectral Density 120 nV/√Hz DAC code=8400H, 1kHz
100 nV/√Hz DAC code=8400H, 10kHz
Output Noise 15

NOTES

1Guaranteed by design and characterization; not production tested.
2See the Terminology section.
3Temperature range (Y Version): –40°C to +125°C; typical at +25°C.

Specifications subject to change without notice.

µVp-p

0.1Hz to 10Hz;

MIN

to T

unless otherwise

MAX

Rev. PrB| Page 7 of 22