ANALOG DEVICES AD5678 Service Manual

4 × 12-Bit and 4 × 16-Bit Octal DAC with

V

/

V

FEATURES

Low power octal DAC with

Four 16-bit DACs

Four 12-bit DACs
14-lead/16-lead TSSOP
On-chip 1.25 V/2.5 V, 5 ppm/°C reference
Power down to 400 nA @ 5 V, 200 nA @ 3 V

2.7 V to 5.5 V power supply
Guaranteed monotonic by design
Power-on reset to zero scale
3 power-down functions
Hardware

function to programmable code

CLR

LDAC

and

Rail-to-rail operation

APPLICATIONS

Process control
Data acquisition systems
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage current sources
Programmable attenuators

GENERAL DESCRIPTION

override function

LDAC

On-Chip Reference in 14-Lead TSSOP

AD5678

FUNCTIONAL BLOCK DIAGRAM

AD5678

SCLK

SYNC

DIN

1

RU-16 PACKAGE ONLY

LDAC

INTERFACE

LOGIC

1

LDAC

CLR

V

DD

INPUT

REGISTER

INPUT

REGISTER

INPUT

REGISTER

INPUT

REGISTER

INPUT

REGISTER

INPUT

REGISTER

INPUT

REGISTER

INPUT

REGISTER

POWER-ON

RESET

1

DAC

REGISTER

DAC

REGISTER

DAC

REGISTER

DAC

REGISTER

DAC

REGISTER

DAC

REGISTER

DAC

REGISTER

DAC

REGISTER

Figure 1.

REFIN

STRING

DAC A

STRING

DAC B

STRING

DAC C

STRING

DAC D

STRING

DAC E

STRING

DAC F

STRING

DAC G

STRING

DAC H

REFOUT

1.25V/2.5V
REF

BUFFER

BUFFER

BUFFER

BUFFER

BUFFER

BUFFER

BUFFER

BUFFER

POWER-DOWN

LOGIC

GND

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

A

B

C

D

E

F

G

H

05299-001

The AD5678 is a low power, octal, buffered voltage-output
DAC with four 12-bit DACs and four 16-bit DACs in a single
package. All devices operate from a single 2.7 V to 5.5 V supply
and are guaranteed monotonic by design.

The AD5678 has an on-chip reference with an internal gain of 2.
The AD5678-1 has a 1.25 V 5 ppm/°C reference, giving a full­scale output of 2.5 V; the AD5678-2 has a 2.5 V 5 ppm/°C
reference, giving a full-scale output of 5 V. The on-board
reference is off at power-up, allowing the use of an external
reference. The internal reference is enabled via a software write.

The part incorporates a power-on reset circuit that ensures that
the DAC output powers up to 0 V and remains powered up at
this level until a valid write takes place. The part contains a
power-down feature that reduces the current consumption of
the device to 400 nA at 5 V and provides software-selectable
output loads while in power-down mode for any or all DAC
channels.

Rev. C

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

The outputs of all DACs can be updated simultaneously using
the

function, with the added functionality of user-

LDAC

selectable DAC channels to simultaneously update. There is
also an asynchronous

that clears all DACs to a software-

CLR

selectable code—0 V, midscale, or full scale.

The AD5678 utilizes a versatile 3-wire serial interface that
operates at clock rates of up to 50 MHz and is compatible with
standard SPI®, QSPI™, MICROWIRE™, and DSP interface
standards. The on-chip precision output amplifier enables rail­to-rail output swing.

PRODUCT HIGHLIGHTS

1. Octal DAC (four 12-bit DACs and four 16-bit DACs).

2. On-chip 1.25 V/2.5 V, 5 ppm/°C reference.

3. Available in 14-lead/16-lead TSSOP.

4. Power-on reset to 0 V.

5. Power-down capability. When powered down, the DAC

typically consumes 200 nA at 3 V and 400 nA at 5 V.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2005–2011 Analog Devices, Inc. All rights reserved.

AD5678

TABLE OF CONTENTS

Features.............................................................................................. 1

D/A Section................................................................................. 20

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

AC Characteristics........................................................................ 7

Timing Characteristics ................................................................ 8

Absolute Maximum Ratings............................................................ 9

ESD Caution.................................................................................. 9

Pin Configuration and Function Descriptions........................... 10

Typical Performance Characteristics ........................................... 11

Terminology .................................................................................... 18

Theory of Operation ...................................................................... 20

Resistor String............................................................................. 20

Internal Reference...................................................................... 20

Output Amplifier........................................................................ 21

Serial Interface............................................................................ 21

Input Shift Register .................................................................... 22

Interrupt .......................................................................... 22

SYNC

Internal Reference Register....................................................... 23

Power-On Reset.......................................................................... 23

Power-Down Modes .................................................................. 23

Clear Code Register ................................................................... 23

Function .......................................................................... 25

LDAC

Power Supply Bypassing and Grounding................................ 25

Outline Dimensions....................................................................... 26

Ordering Guide .......................................................................... 26

REVISION HISTORY

2/11—Rev. B to Rev. C

Changes to Zero-Code Error Parameter and Offset Error

Parameter, Table 1............................................................................. 3

Changes to Zero-Code Error Parameter and Offset Error

Parameter, Table 2............................................................................. 5

2/09—Rev. A to Rev. B

Changes to Reference Current Parameter, Table 1....................... 3

Change to I

Changes to Reference Current Parameter, Table 2....................... 5

Change to I

11/05—Rev. 0 to Rev. A

Change to General Description...................................................... 1

Change to Specifications.................................................................. 3

Replaced Figure 48 .........................................................................22

Change to the Power-Down Modes Section ............................... 23

10/05—Revision 0: Initial Version

(Normal Mode) Parameter, Table 1 ...................... 4

DD

(Normal Mode) Parameter, Table 2 ...................... 6

DD

Rev. C | Page 2 of 28

AD5678

SPECIFICATIONS

VDD = 4.5 V to 5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, V

Table 1.

A Grade1 B Grade1
Parameter Min Typ Max Min Typ Max Unit Conditions/Comments

STATIC PERFORMANCE

2

AD5678 (DAC C, D, E, F)

Resolution 12 12 Bits
Relative Accuracy ±0.5 ±2 ±0.5 ±1 LSB See Figure 11
Differential Nonlinearity ±0.25 ±0.25 LSB

AD5678 (DAC A, B, G, H)

Resolution 16 16 Bits
Relative Accuracy ±8 ±32 ±8 ±16 LSB See Figure 5

Differential Nonlinearity ±1 ±1 LSB Guaranteed monotonic by design (see Figure 6)
Zero-Code Error 6 19 6 19 mV All 0s loaded to DAC register (see Figure 17)
Zero-Code Error Drift ±2 ±2 µV/°C
Full-Scale Error −0.2 −1 −0.2 −1 % FSR All 1s loaded to DAC register (see Figure 18)
Gain Error ±1 ±1 % FSR
Gain Temperature

±2.5 ±2.5 ppm Of FSR/°C

Coefficient
Offset Error ±6 ±19 ±6 ±19 mV
DC Power Supply Rejection

–80 –80 dB V

Ratio
DC Crosstalk

10 10 µV

(External Reference)
5 5 µV/mA Due to load current change
10 10 µV Due to powering down (per channel)
DC Crosstalk

25 25 µV

(Internal Reference)
10 10 µV/mA Due to load current change

OUTPUT CHARACTERISTICS3

Output Voltage Range 0 VDD 0 VDD V
Capacitive Load Stability 2 2 nF RL = ∞
10 10 nF RL = 2 kΩ
DC Output Impedance 0.5 0.5 Ω
Short-Circuit Current 30 30 mA VDD = 5 V
Power-Up Time 4 4 µs Coming out of power-down mode; VDD = 5 V

REFERENCE INPUTS

Reference Input Voltage VDD VDD V ±1% for specified performance
Reference Current 35 55 35 55 µA V
Reference Input Range 0 VDD 0 VDD V
Reference Input Impedance 14.6 14.6 kΩ Per DAC channel

REFERENCE OUTPUT

Output Voltage

AD5678-2 2.495 2.505 2.495 2.505 V At ambient
Reference TC3 ±5 ±10 ±5 ±10 ppm/°C
Reference Output Impedance 7.5 7.5 kΩ

LOGIC INPUTS3

Input Current ±3 ±3 µA All digital inputs
Input Low Voltage, V
Input High Voltage, V

0.8 0.8 V VDD = 5 V

INL

2 2 V VDD = 5 V

INH

Pin Capacitance 3 3 pF

= VDD. All specifications T

REFIN

MIN

to T

, unless otherwise noted.

MAX

Guaranteed monotonic by design
(see Figure 12)

± 10%

DD

Due to full-scale output change,

= 2 kΩ to GND or VDD

R

L

Due to full-scale output change,
R

= 2 kΩ to GND or VDD

L

= VDD = 5.5 V (per DAC channel)

REF

Rev. C | Page 3 of 28

AD5678

A Grade1 B Grade1
Parameter Min Typ Max Min Typ Max Unit Conditions/Comments

POWER REQUIREMENTS

VDD 4.5 5.5 4.5 5.5 V

All digital inputs at 0 or V
DAC active, excludes load current

IDD (Normal Mode)4 V

= VDD and VIL = GND

IH

VDD = 4.5 V to 5.5 V 1.3 1.8 1.3 1.8 mA Internal reference off
VDD = 4.5 V to 5.5 V 2 2.6 2 2.6 mA Internal reference on

IDD (All Power-Down Modes)5

VDD = 4.5 V to 5.5 V 0.4 1 0.4 1 µA VIH = VDD and VIL = GND

1

Temperature range is −40°C to +105°C, typical at 25°C.

2

Linearity calculated using a reduced code range of AD5678 12-bit DACs (Code 32 to Code 4,064) and AD5678 16-bit DACs (Code 512 to Code 65,024). Output

unloaded.

3

Guaranteed by design and characterization; not production tested.

4

Interface inactive. All DACs active. DAC outputs unloaded.

5

All eight DACs powered down.

,

DD

Rev. C | Page 4 of 28

AD5678

VDD = 2.7 V to 3.6 V, RL = 2 kΩ to GND, CL = 200 pF to GND, V

Table 2.

A Grade1 B Grade1
Parameter Min Typ Max Min Typ Max Unit Conditions/Comments

STATIC PERFORMANCE

2

AD5678 (DAC C, D, E, F)

Resolution 12 12 Bits

Relative Accuracy ±0.5 ±2 ±0.5 ±1 LSB See Figure 11

Differential Nonlinearity ±1 ±1 LSB

AD5678 (DAC A, B, G, H)

Resolution 16 16 Bits

Relative Accuracy ±32 ±16 LSB See Figure 5

Differential Nonlinearity ±1 ±1 LSB Guaranteed monotonic by design (See Figure 6)
Zero-Code Error 6 19 6 19 mV All 0s loaded to DAC register (See Figure 17)
Zero-Code Error Drift ±2 ±2 µV/°C
Full-Scale Error −0.2 −1 −0.2 −1 % FSR All 1s loaded to DAC register (See Figure 18)
Gain Error ±1 ±1 % FSR
Gain Temperature Coefficient ±2.5 ±2.5 ppm Of FSR/°C
Offset Error ±6 ±19 ±6 ±19 mV
Offset Temperature Coefficient 1.7 1.7 µV/°C
DC Power Supply Rejection

–80 –80 dB V

Ratio
DC Crosstalk

10 10 µV

(External Reference)

4.5 4.5 µV/mA Due to load current change
10 10 µV Due to powering down (per channel)
DC Crosstalk

25 25 µV

(Internal Reference)

4.5 4.5 µV/mA Due to load current change

OUTPUT CHARACTERISTICS3

Output Voltage Range 0 VDD 0 VDD V
Capacitive Load Stability 2 2 nF RL = ∞
10 10 nF RL = 2 kΩ
DC Output Impedance 0.5 0.5 Ω
Short-Circuit Current 30 30 mA VDD = 3 V
Power-Up Time 4 4 µs Coming out of power-down mode; VDD = 3 V

REFERENCE INPUTS

Reference Input Voltage VDD V
Reference Current 20 55 20 55 µA V
Reference Input Range 0 VDD 0 VDD V
Reference Input Impedance 14.6 14.6 kΩ Per DAC channel

REFERENCE OUTPUT

Output Voltage

AD5678-1 1.247 1.253 1.247 1.253 V At ambient
Reference TC3 ±5 ±15 ±5 ±15 ppm/°C
Reference Output Impedance 7.5 7.5 kΩ

= VDD. All specifications T

REFIN

MIN

to T

, unless otherwise noted.

MAX

Guaranteed monotonic by design
(see Figure 12)

± 10%

DD

Due to full-scale output change,

= 2 kΩ to GND or VDD

R

L

Due to full-scale output change,

= 2 kΩ to GND or VDD

R

L

V ±1% for specified performance

DD

= VDD = 3.6 V (per DAC channel)

REF

Rev. C | Page 5 of 28

AD5678

A Grade1 B Grade1
Parameter Min Typ Max Min Typ Max Unit Conditions/Comments

LOGIC INPUTS3

Input Current ±3 ±3 µA All digital inputs
Input Low Voltage, V
Input High Voltage, V
Pin Capacitance 3 3 pF

POWER REQUIREMENTS

VDD 2.7 3.6 2.7 3.6 V

IDD (Normal Mode)4 V

VDD = 2.7 V to 3.6 V 1.2 1.7 1.2 1.7 mA Internal reference off
VDD = 2.7 V to 3.6 V 1.7 2.6 1.7 2.6 mA Internal reference on

IDD (All Power-Down Modes)5

VDD = 2.7 V to 3.6 V 0.2 1 0.2 1 µA VIH = VDD and VIL = GND

1

Temperature range is −40°C to +105°C, typical at 25°C.

2

Linearity calculated using a reduced code range of AD5678 12-bit DACs (Code 32 to Code 4,064) and AD5678 16-bit DACs (Code 512 to Code 65,024). Output

unloaded.

3

Guaranteed by design and characterization; not production tested.

4

Interface inactive. All DACs active. DAC outputs unloaded.

5

All eight DACs powered down.

0.8 0.8 V VDD = 3 V

INL

2 2 V VDD = 3 V

INH

All digital inputs at 0 or V
DAC active, excludes load current

= VDD and VIL = GND

IH

,

DD

Rev. C | Page 6 of 28

AD5678

AC CHARACTERISTICS

VDD = 2.7 V to 5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, V

Table 3.

Parameter

1, 2

Min Typ Max Unit Conditions/Comments3

Output Voltage Settling Time 6 10 µs ¼ to ¾ scale settling to ±2 LSB
Slew Rate 1.5 V/µs
Digital-to-Analog Glitch Impulse 4 nV-s 1 LSB change around major carry (see Figure 34)
Digital Feedthrough 0.1 nV-s
Reference Feedthrough −90 dB V
Digital Crosstalk 0.5 nV-s
Analog Crosstalk 2.5 nV-s
DAC-to-DAC Crosstalk 3 nV-s
Multiplying Bandwidth 340 kHz V
Total Harmonic Distortion −80 dB V
Output Noise Spectral Density 120 nV/√Hz DAC code = 0x8400, 1 kHz
100 nV/√Hz DAC code = 0x8400, 10 kHz
Output Noise 15 V p-p 0.1 Hz to 10 Hz

1

Guaranteed by design and characterization; not production tested.

2

See the Terminology section.

3

Temperature range is −40°C to +105°C, typical at 25°C.

= VDD. All specifications T

REFIN

= 2 V ± 0.1 V p-p, frequency = 10 Hz to 20 MHz

REF

= 2 V ± 0.2 V p-p

REF

= 2 V ± 0.1 V p-p, frequency = 10 kHz

REF

MIN

to T

, unless otherwise noted.

MAX

Rev. C | Page 7 of 28

AD5678

TIMING CHARACTERISTICS

All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 2.
V

= 2.7 V to 5.5 V. All specifications T

DD

Table 4.

Limit at T

MIN

, T

Parameter VDD = 2.7 V to 5.5 V Unit Conditions/Comments

t1 1 20 ns min SCLK cycle time
t2 8 ns min SCLK high time
t3 8 ns min SCLK low time
t4 13 ns min

t5 4 ns min Data set-up time
t6 4 ns min Data hold time
t7 0 ns min

t8 15 ns min
t9 13 ns min
t10 0 ns min
t11 10 ns min
t12 15 ns min
t13 5 ns min
t14 0 ns min
t15 300 ns typ

1

Maximum SCLK frequency is 50 MHz at VDD = 2.7 V to 5.5 V. Guaranteed by design and characterization; not production tested.

t

SCLK

t

8

SYNC

DIN

1

LDAC

to T

MIN

MAX

, unless otherwise noted.

MAX

to SCLK falling edge set-up time

SYNC

SCLK falling edge to SYNC
Minimum SYNC

rising edge to SCLK fall ignore

SYNC
SCLK falling edge to SYNC

pulse width low

LDAC
SCLK falling edge to LDAC

pulse width low

CLR
SCLK falling edge to LDAC

pulse activation time

CLR

10

t

4

t

6

t

5

DB31

t

1

t

t

3

2

DB0

t

9

t

7

t

11

t

14

rising edge

high time

fall ignore

rising edge

falling edge

2

LDAC

t

CLR

V

OUT

1

ASYNCHRONOUS LDAC UPDAT E MODE.

2

SYNCHRONOUS LDAC UPDAT E MODE.

13

t

12

t

15

05299-002

Figure 2. Serial Write Operation

Rev. C | Page 8 of 28

AD5678

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 5.

Parameter Rating

VDD to GND −0.3 V to +7 V
Digital Input Voltage to GND −0.3 V to VDD + 0.3 V
V

REFIN/VREFOUT

Operating Temperature Range

Industrial (B Version) −40°C to +105°C

Storage Temperature Range −65°C to +150°C
Junction Temperature (TJ
TSSOP Package

Power Dissipation (TJ
θJA Thermal Impedance 150.4°C/W

Lead Temperature, Soldering

SnPb 240°C
Pb Free 260°C

to GND −0.3 V to VDD + 0.3 V

) 150°C

MAX

− TA)/θJA

MAX

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. C | Page 9 of 28