ANALOG DEVICES AD5678 Service Manual

4 × 12-Bit and 4 × 16-Bit Octal DAC with

V

/

V

FEATURES

Low power octal DAC with

Four 16-bit DACs

Four 12-bit DACs
14-lead/16-lead TSSOP
On-chip 1.25 V/2.5 V, 5 ppm/°C reference
Power down to 400 nA @ 5 V, 200 nA @ 3 V

2.7 V to 5.5 V power supply
Guaranteed monotonic by design
Power-on reset to zero scale
3 power-down functions
Hardware

function to programmable code

CLR

LDAC

and

Rail-to-rail operation

APPLICATIONS

Process control
Data acquisition systems
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage current sources
Programmable attenuators

GENERAL DESCRIPTION

override function

LDAC

On-Chip Reference in 14-Lead TSSOP

AD5678

FUNCTIONAL BLOCK DIAGRAM

AD5678

SCLK

SYNC

DIN

1

RU-16 PACKAGE ONLY

LDAC

INTERFACE

LOGIC

1

LDAC

CLR

V

DD

INPUT

REGISTER

INPUT

REGISTER

INPUT

REGISTER

INPUT

REGISTER

INPUT

REGISTER

INPUT

REGISTER

INPUT

REGISTER

INPUT

REGISTER

POWER-ON

RESET

1

DAC

REGISTER

DAC

REGISTER

DAC

REGISTER

DAC

REGISTER

DAC

REGISTER

DAC

REGISTER

DAC

REGISTER

DAC

REGISTER

Figure 1.

REFIN

STRING

DAC A

STRING

DAC B

STRING

DAC C

STRING

DAC D

STRING

DAC E

STRING

DAC F

STRING

DAC G

STRING

DAC H

REFOUT

1.25V/2.5V
REF

BUFFER

BUFFER

BUFFER

BUFFER

BUFFER

BUFFER

BUFFER

BUFFER

POWER-DOWN

LOGIC

GND

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

A

B

C

D

E

F

G

H

05299-001

The AD5678 is a low power, octal, buffered voltage-output
DAC with four 12-bit DACs and four 16-bit DACs in a single
package. All devices operate from a single 2.7 V to 5.5 V supply
and are guaranteed monotonic by design.

The AD5678 has an on-chip reference with an internal gain of 2.
The AD5678-1 has a 1.25 V 5 ppm/°C reference, giving a full­scale output of 2.5 V; the AD5678-2 has a 2.5 V 5 ppm/°C
reference, giving a full-scale output of 5 V. The on-board
reference is off at power-up, allowing the use of an external
reference. The internal reference is enabled via a software write.

The part incorporates a power-on reset circuit that ensures that
the DAC output powers up to 0 V and remains powered up at
this level until a valid write takes place. The part contains a
power-down feature that reduces the current consumption of
the device to 400 nA at 5 V and provides software-selectable
output loads while in power-down mode for any or all DAC
channels.

Rev. C

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

The outputs of all DACs can be updated simultaneously using
the

function, with the added functionality of user-

LDAC

selectable DAC channels to simultaneously update. There is
also an asynchronous

that clears all DACs to a software-

CLR

selectable code—0 V, midscale, or full scale.

The AD5678 utilizes a versatile 3-wire serial interface that
operates at clock rates of up to 50 MHz and is compatible with
standard SPI®, QSPI™, MICROWIRE™, and DSP interface
standards. The on-chip precision output amplifier enables rail­to-rail output swing.

PRODUCT HIGHLIGHTS

1. Octal DAC (four 12-bit DACs and four 16-bit DACs).

2. On-chip 1.25 V/2.5 V, 5 ppm/°C reference.

3. Available in 14-lead/16-lead TSSOP.

4. Power-on reset to 0 V.

5. Power-down capability. When powered down, the DAC

typically consumes 200 nA at 3 V and 400 nA at 5 V.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2005–2011 Analog Devices, Inc. All rights reserved.

AD5678

TABLE OF CONTENTS

Features.............................................................................................. 1

D/A Section................................................................................. 20

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

AC Characteristics........................................................................ 7

Timing Characteristics ................................................................ 8

Absolute Maximum Ratings............................................................ 9

ESD Caution.................................................................................. 9

Pin Configuration and Function Descriptions........................... 10

Typical Performance Characteristics ........................................... 11

Terminology .................................................................................... 18

Theory of Operation ...................................................................... 20

Resistor String............................................................................. 20

Internal Reference...................................................................... 20

Output Amplifier........................................................................ 21

Serial Interface............................................................................ 21

Input Shift Register .................................................................... 22

Interrupt .......................................................................... 22

SYNC

Internal Reference Register....................................................... 23

Power-On Reset.......................................................................... 23

Power-Down Modes .................................................................. 23

Clear Code Register ................................................................... 23

Function .......................................................................... 25

LDAC

Power Supply Bypassing and Grounding................................ 25

Outline Dimensions....................................................................... 26

Ordering Guide .......................................................................... 26

REVISION HISTORY

2/11—Rev. B to Rev. C

Changes to Zero-Code Error Parameter and Offset Error

Parameter, Table 1............................................................................. 3

Changes to Zero-Code Error Parameter and Offset Error

Parameter, Table 2............................................................................. 5

2/09—Rev. A to Rev. B

Changes to Reference Current Parameter, Table 1....................... 3

Change to I

Changes to Reference Current Parameter, Table 2....................... 5

Change to I

11/05—Rev. 0 to Rev. A

Change to General Description...................................................... 1

Change to Specifications.................................................................. 3

Replaced Figure 48 .........................................................................22

Change to the Power-Down Modes Section ............................... 23

10/05—Revision 0: Initial Version

(Normal Mode) Parameter, Table 1 ...................... 4

DD

(Normal Mode) Parameter, Table 2 ...................... 6

DD

Rev. C | Page 2 of 28

AD5678

SPECIFICATIONS

VDD = 4.5 V to 5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, V

Table 1.

A Grade1 B Grade1
Parameter Min Typ Max Min Typ Max Unit Conditions/Comments

STATIC PERFORMANCE

2

AD5678 (DAC C, D, E, F)

Resolution 12 12 Bits
Relative Accuracy ±0.5 ±2 ±0.5 ±1 LSB See Figure 11
Differential Nonlinearity ±0.25 ±0.25 LSB

AD5678 (DAC A, B, G, H)

Resolution 16 16 Bits
Relative Accuracy ±8 ±32 ±8 ±16 LSB See Figure 5

Differential Nonlinearity ±1 ±1 LSB Guaranteed monotonic by design (see Figure 6)
Zero-Code Error 6 19 6 19 mV All 0s loaded to DAC register (see Figure 17)
Zero-Code Error Drift ±2 ±2 µV/°C
Full-Scale Error −0.2 −1 −0.2 −1 % FSR All 1s loaded to DAC register (see Figure 18)
Gain Error ±1 ±1 % FSR
Gain Temperature

±2.5 ±2.5 ppm Of FSR/°C

Coefficient
Offset Error ±6 ±19 ±6 ±19 mV
DC Power Supply Rejection

–80 –80 dB V

Ratio
DC Crosstalk

10 10 µV

(External Reference)
5 5 µV/mA Due to load current change
10 10 µV Due to powering down (per channel)
DC Crosstalk

25 25 µV

(Internal Reference)
10 10 µV/mA Due to load current change

OUTPUT CHARACTERISTICS3

Output Voltage Range 0 VDD 0 VDD V
Capacitive Load Stability 2 2 nF RL = ∞
10 10 nF RL = 2 kΩ
DC Output Impedance 0.5 0.5 Ω
Short-Circuit Current 30 30 mA VDD = 5 V
Power-Up Time 4 4 µs Coming out of power-down mode; VDD = 5 V

REFERENCE INPUTS

Reference Input Voltage VDD VDD V ±1% for specified performance
Reference Current 35 55 35 55 µA V
Reference Input Range 0 VDD 0 VDD V
Reference Input Impedance 14.6 14.6 kΩ Per DAC channel

REFERENCE OUTPUT

Output Voltage

AD5678-2 2.495 2.505 2.495 2.505 V At ambient
Reference TC3 ±5 ±10 ±5 ±10 ppm/°C
Reference Output Impedance 7.5 7.5 kΩ

LOGIC INPUTS3

Input Current ±3 ±3 µA All digital inputs
Input Low Voltage, V
Input High Voltage, V

0.8 0.8 V VDD = 5 V

INL

2 2 V VDD = 5 V

INH

Pin Capacitance 3 3 pF

= VDD. All specifications T

REFIN

MIN

to T

, unless otherwise noted.

MAX

Guaranteed monotonic by design
(see Figure 12)

± 10%

DD

Due to full-scale output change,

= 2 kΩ to GND or VDD

R

L

Due to full-scale output change,
R

= 2 kΩ to GND or VDD

L

= VDD = 5.5 V (per DAC channel)

REF

Rev. C | Page 3 of 28

AD5678

A Grade1 B Grade1
Parameter Min Typ Max Min Typ Max Unit Conditions/Comments

POWER REQUIREMENTS

VDD 4.5 5.5 4.5 5.5 V

All digital inputs at 0 or V
DAC active, excludes load current

IDD (Normal Mode)4 V

= VDD and VIL = GND

IH

VDD = 4.5 V to 5.5 V 1.3 1.8 1.3 1.8 mA Internal reference off
VDD = 4.5 V to 5.5 V 2 2.6 2 2.6 mA Internal reference on

IDD (All Power-Down Modes)5

VDD = 4.5 V to 5.5 V 0.4 1 0.4 1 µA VIH = VDD and VIL = GND

1

Temperature range is −40°C to +105°C, typical at 25°C.

2

Linearity calculated using a reduced code range of AD5678 12-bit DACs (Code 32 to Code 4,064) and AD5678 16-bit DACs (Code 512 to Code 65,024). Output

unloaded.

3

Guaranteed by design and characterization; not production tested.

4

Interface inactive. All DACs active. DAC outputs unloaded.

5

All eight DACs powered down.

,

DD

Rev. C | Page 4 of 28

AD5678

VDD = 2.7 V to 3.6 V, RL = 2 kΩ to GND, CL = 200 pF to GND, V

Table 2.

A Grade1 B Grade1
Parameter Min Typ Max Min Typ Max Unit Conditions/Comments

STATIC PERFORMANCE

2

AD5678 (DAC C, D, E, F)

Resolution 12 12 Bits

Relative Accuracy ±0.5 ±2 ±0.5 ±1 LSB See Figure 11

Differential Nonlinearity ±1 ±1 LSB

AD5678 (DAC A, B, G, H)

Resolution 16 16 Bits

Relative Accuracy ±32 ±16 LSB See Figure 5

Differential Nonlinearity ±1 ±1 LSB Guaranteed monotonic by design (See Figure 6)
Zero-Code Error 6 19 6 19 mV All 0s loaded to DAC register (See Figure 17)
Zero-Code Error Drift ±2 ±2 µV/°C
Full-Scale Error −0.2 −1 −0.2 −1 % FSR All 1s loaded to DAC register (See Figure 18)
Gain Error ±1 ±1 % FSR
Gain Temperature Coefficient ±2.5 ±2.5 ppm Of FSR/°C
Offset Error ±6 ±19 ±6 ±19 mV
Offset Temperature Coefficient 1.7 1.7 µV/°C
DC Power Supply Rejection

–80 –80 dB V

Ratio
DC Crosstalk

10 10 µV

(External Reference)

4.5 4.5 µV/mA Due to load current change
10 10 µV Due to powering down (per channel)
DC Crosstalk

25 25 µV

(Internal Reference)

4.5 4.5 µV/mA Due to load current change

OUTPUT CHARACTERISTICS3

Output Voltage Range 0 VDD 0 VDD V
Capacitive Load Stability 2 2 nF RL = ∞
10 10 nF RL = 2 kΩ
DC Output Impedance 0.5 0.5 Ω
Short-Circuit Current 30 30 mA VDD = 3 V
Power-Up Time 4 4 µs Coming out of power-down mode; VDD = 3 V

REFERENCE INPUTS

Reference Input Voltage VDD V
Reference Current 20 55 20 55 µA V
Reference Input Range 0 VDD 0 VDD V
Reference Input Impedance 14.6 14.6 kΩ Per DAC channel

REFERENCE OUTPUT

Output Voltage

AD5678-1 1.247 1.253 1.247 1.253 V At ambient
Reference TC3 ±5 ±15 ±5 ±15 ppm/°C
Reference Output Impedance 7.5 7.5 kΩ

= VDD. All specifications T

REFIN

MIN

to T

, unless otherwise noted.

MAX

Guaranteed monotonic by design
(see Figure 12)

± 10%

DD

Due to full-scale output change,

= 2 kΩ to GND or VDD

R

L

Due to full-scale output change,

= 2 kΩ to GND or VDD

R

L

V ±1% for specified performance

DD

= VDD = 3.6 V (per DAC channel)

REF

Rev. C | Page 5 of 28

AD5678

A Grade1 B Grade1
Parameter Min Typ Max Min Typ Max Unit Conditions/Comments

LOGIC INPUTS3

Input Current ±3 ±3 µA All digital inputs
Input Low Voltage, V
Input High Voltage, V
Pin Capacitance 3 3 pF

POWER REQUIREMENTS

VDD 2.7 3.6 2.7 3.6 V

IDD (Normal Mode)4 V

VDD = 2.7 V to 3.6 V 1.2 1.7 1.2 1.7 mA Internal reference off
VDD = 2.7 V to 3.6 V 1.7 2.6 1.7 2.6 mA Internal reference on

IDD (All Power-Down Modes)5

VDD = 2.7 V to 3.6 V 0.2 1 0.2 1 µA VIH = VDD and VIL = GND

1

Temperature range is −40°C to +105°C, typical at 25°C.

2

Linearity calculated using a reduced code range of AD5678 12-bit DACs (Code 32 to Code 4,064) and AD5678 16-bit DACs (Code 512 to Code 65,024). Output

unloaded.

3

Guaranteed by design and characterization; not production tested.

4

Interface inactive. All DACs active. DAC outputs unloaded.

5

All eight DACs powered down.

0.8 0.8 V VDD = 3 V

INL

2 2 V VDD = 3 V

INH

All digital inputs at 0 or V
DAC active, excludes load current

= VDD and VIL = GND

IH

,

DD

Rev. C | Page 6 of 28

AD5678

AC CHARACTERISTICS

VDD = 2.7 V to 5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, V

Table 3.

Parameter

1, 2

Min Typ Max Unit Conditions/Comments3

Output Voltage Settling Time 6 10 µs ¼ to ¾ scale settling to ±2 LSB
Slew Rate 1.5 V/µs
Digital-to-Analog Glitch Impulse 4 nV-s 1 LSB change around major carry (see Figure 34)
Digital Feedthrough 0.1 nV-s
Reference Feedthrough −90 dB V
Digital Crosstalk 0.5 nV-s
Analog Crosstalk 2.5 nV-s
DAC-to-DAC Crosstalk 3 nV-s
Multiplying Bandwidth 340 kHz V
Total Harmonic Distortion −80 dB V
Output Noise Spectral Density 120 nV/√Hz DAC code = 0x8400, 1 kHz
100 nV/√Hz DAC code = 0x8400, 10 kHz
Output Noise 15 V p-p 0.1 Hz to 10 Hz

1

Guaranteed by design and characterization; not production tested.

2

See the Terminology section.

3

Temperature range is −40°C to +105°C, typical at 25°C.

= VDD. All specifications T

REFIN

= 2 V ± 0.1 V p-p, frequency = 10 Hz to 20 MHz

REF

= 2 V ± 0.2 V p-p

REF

= 2 V ± 0.1 V p-p, frequency = 10 kHz

REF

MIN

to T

, unless otherwise noted.

MAX

Rev. C | Page 7 of 28

AD5678

TIMING CHARACTERISTICS

All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 2.
V

= 2.7 V to 5.5 V. All specifications T

DD

Table 4.

Limit at T

MIN

, T

Parameter VDD = 2.7 V to 5.5 V Unit Conditions/Comments

t1 1 20 ns min SCLK cycle time
t2 8 ns min SCLK high time
t3 8 ns min SCLK low time
t4 13 ns min

t5 4 ns min Data set-up time
t6 4 ns min Data hold time
t7 0 ns min

t8 15 ns min
t9 13 ns min
t10 0 ns min
t11 10 ns min
t12 15 ns min
t13 5 ns min
t14 0 ns min
t15 300 ns typ

1

Maximum SCLK frequency is 50 MHz at VDD = 2.7 V to 5.5 V. Guaranteed by design and characterization; not production tested.

t

SCLK

t

8

SYNC

DIN

1

LDAC

to T

MIN

MAX

, unless otherwise noted.

MAX

to SCLK falling edge set-up time

SYNC

SCLK falling edge to SYNC
Minimum SYNC

rising edge to SCLK fall ignore

SYNC
SCLK falling edge to SYNC

pulse width low

LDAC
SCLK falling edge to LDAC

pulse width low

CLR
SCLK falling edge to LDAC

pulse activation time

CLR

10

t

4

t

6

t

5

DB31

t

1

t

t

3

2

DB0

t

9

t

7

t

11

t

14

rising edge

high time

fall ignore

rising edge

falling edge

2

LDAC

t

CLR

V

OUT

1

ASYNCHRONOUS LDAC UPDAT E MODE.

2

SYNCHRONOUS LDAC UPDAT E MODE.

13

t

12

t

15

05299-002

Figure 2. Serial Write Operation

Rev. C | Page 8 of 28

AD5678

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 5.

Parameter Rating

VDD to GND −0.3 V to +7 V
Digital Input Voltage to GND −0.3 V to VDD + 0.3 V
V

REFIN/VREFOUT

Operating Temperature Range

Industrial (B Version) −40°C to +105°C

Storage Temperature Range −65°C to +150°C
Junction Temperature (TJ
TSSOP Package

Power Dissipation (TJ
θJA Thermal Impedance 150.4°C/W

Lead Temperature, Soldering

SnPb 240°C
Pb Free 260°C

to GND −0.3 V to VDD + 0.3 V

) 150°C

MAX

− TA)/θJA

MAX

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. C | Page 9 of 28

AD5678

V

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

1

SYNC

2

V

DD

3

V

A

OUT

V

OUT

V

OUT

V

OUT

REFIN/VREFOUT

C

E

G

AD5678

4

TOP VIEW

(Not to Scale)

5

6

7

Figure 3. 14-Lead TSSOP (RU-14)

Table 6. Pin Function Descriptions

Pin No.

14-Lead
TSSOP

N/A

1 2

2 3 V

3 4 V
11 13 V
4 5 V
10 12 V
7 8 V

N/A 9

5 6 V
9 11 V
6 7 V
8 10 V

16-Lead
TSSOP Mnemonic

1

LDAC

Active Low Control Input. This is the frame synchronization signal for the input data. When

SYNC

DD

A Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.

OUT

B Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.

OUT

C Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.

OUT

D Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.

OUT

REFIN/VREFOUT

Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is low, all LDAC

CLR

OUT

OUT

OUT

OUT

E Analog Output Voltage from DAC E. The output amplifier has rail-to-rail operation.
F Analog Output Voltage from DAC F. The output amplifier has rail-to-rail operation.
G Analog Output Voltage from DAC G. The output amplifier has rail-to-rail operation.

H Analog Output Voltage from DAC H. The output amplifier has rail-to-rail operation.
12 14 GND
13 15 DIN

14 16 SCLK

1

LDAC

14

SCLK

13

DIN

12

GND

11

V

B

OUT

10

D

V

OUT

9

F

V

OUT

8

H

V

OUT

05299-003

V

REFIN/VREFOUT

SYNC

V

OUT

V

OUT

V

OUT

V

OUT

V

DD

A

C

E

G

2

3

AD5678

4

TOP VIEW

(Not to Scale)

5

6

7

8

16

SCLK

15

DIN

14

GND

13

V

B

OUT

12

V

D

OUT

11

V

F

OUT

10

H

V

OUT

9

CLR

05299-004

Figure 4. 16-Lead TSSOP (RU-16)

Description

Pulsing this pin low allows any or all DAC registers to be updated if the input registers have
new data. This allows all DAC outputs to simultaneously update. Alternatively, this pin can be
tied permanently low.

SYNC goes low, it powers on the SCLK and DIN buffers and enables the input shift register.
Data is transferred in on the falling edges of the next 32 clocks. If SYNC is taken high before
the 32nd falling edge, the rising edge of SYNC acts as an interrupt and the write sequence is
ignored by the device.

Power Supply Input. These parts can be operated from 2.7 V to 5.5 V, and the supply should
be decoupled with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND.

The AD5678 has a common pin for reference input and reference output. When using the
internal reference, this is the reference output pin. When using an external reference, this is
the reference input pin. The default for this pin is as a reference input.

pulses are ignored. When CLR

is activated, the input register and the DAC register are
updated with the data contained in the CLR code register—zero, midscale, or full scale.
Default setting clears the output to 0 V.

Ground Reference Point for All Circuitry on the Part.
Serial Data Input. This device has a 32-bit shift register. Data is clocked into the register on

the falling edge of the serial clock input.
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial

clock input. Data can be transferred at rates of up to 50 MHz.

Rev. C | Page 10 of 28

AD5678

TYPICAL PERFORMANCE CHARACTERISTICS

10

VDD = V

8

T

6

4

2

0

–2

INL ERROR (LSB)

–4

–6

–8

–10

0 5k 10k 15k 20k 25k 30k 35k 40k 45k 50k 55k 60k 65k

= 25°C

A

REF

= 5V

CODE

Figure 5. INL—16-Bit DAC

1.0
VDD = V
T

0.8

0.6

0.4

0.2

0

–0.2

DNL ERROR (LSB)

–0.4

–0.6

–0.8

–1.0

0 10k 20k 30k 40k 50k 60k

= 25°C

A

REF

= 5V

CODE

Figure 6. DNL—16-Bit DAC

05299-011

05299-012

1.0
VDD = 5V

0.8

V

= 2.5V

REFOUT

TA = 25°C

0.6

0.4

0.2

0

–0.2

DNL ERRO R (LSB)

–0.4

–0.6

–0.8

–1.0

0

5000

20000

15000

10000

35000

30000

25000

CODE

Figure 8. DNL 16-Bit DAC, 2.5 V Internal Reference

10

VDD = 3V

8

V

= 1.25V

REFOUT

T

= 25°C

A

6

4

2

0

–2

INL ERROR (LSB)

–4

–6

–8

–10

0

5000

25000

20000

15000

10000

30000

CODE

40000

35000

Figure 9. INL—16-Bit DAC, 1.25 V Internal Reference

05299-014

65000

60000

55000

50000

45000

40000

05299-015

65000

60000

55000

50000

45000

10

VDD = 5V

8

V

= 2.5V

REFOUT

TA = 25°C

6

4

2

0

–2

INL ERROR (LSB)

–4

–6

–8

–10

0

5000

20000

15000

10000

35000

30000

25000

CODE

Figure 7. INL—16-Bit DAC, 2.5 V Internal Reference

1.0

VDD = 3V

0.8

V

= 1.25V

REFOUT

T

= 25°C

A

0.6

0.4

0.2

0

–0.2

DNL ERROR (LSB)

–0.4

–0.6

–0.8

05299-013

65000

60000

55000

50000

45000

40000

–1.0

0

5000

10000

CODE

40000

35000

30000

25000

20000

15000

55000

50000

45000

05299-016

65000

60000

Figure 10. DNL—16-Bit DAC, 1.25 V Internal Reference

Rev. C | Page 11 of 28

AD5678

1.0
VDD = V

T

0.8

0.6

0.4

0.2

0

–0.2

INL ERROR (LSB)

–0.4

–0.6

–0.8

–1.0

0 500 1000 1500 2000 2500 3000 3500 4000

0.20
V

T

0.15

0.10

0.05

0

–0.05

DNL ERROR (LSB)

–0.10

–0.15

–0.20

0 500 1000 1500 2000 2500 300

= 5V

REF

= 25°C

A

Figure 11. INL—12-Bit DAC

= V

= 5V

DD

REF

= 25°C

A

Figure 12. DNL—12-Bit DAC

CODE

CODE

0 3500 4000

0.20
VDD = 5V
V

= 2.5V

REFOUT

0.15

TA = 25°C

0.10

0.05

0

–0.05

DNL ERRO R (LSB)

–0.10

05299-045

–0.15

–0.20

0 1000500 20001500 350030002500 4000

CODE

05299-048

Figure 14. DNL 12-Bit DAC, 2.5 V Internal Reference

1.0
VDD = 3V

0.8

V

= 1.25V

REFOUT

T

= 25°C

A

0.6

0.4

0.2

0

–0.2

INL ERROR (LSB)

–0.4

–0.6

05299-046

–0.8

–1.0

0 500 1000 1500 2000 2500 3000 350 0 4000

CODE

05299-049

Figure 15. INL—12-Bit DAC, 1.25 V Internal Reference

1.0
VDD = 5V
V

REFOUT

T

= 25°C

A

= 2.5V

CODE

0.8

0.6

0.4

0.2

0

–0.2

INL ERRO R (LS B)

–0.4

–0.6

–0.8

–1.0

0 1000500 20001500 350030002500 4000

Figure 13. INL—12-Bit DAC, 2.5 V Internal Reference

05299-047

Rev. C | Page 12 of 28

0.20
VDD = 3V

V

= 1.25V

REFOUT

0.15
T

= 25°C

A

0.10

0.05

0

–0.05

DNL ERROR (LSB)

–0.10

–0.15

–0.20

0 500 1000 1500 2000 2500 3000 350 0 4000

CODE

Figure 16. DNL—12-Bit DAC, 1.25 V Internal Reference

05299-050

AD5678

0

VDD = 5V

–0.02

–0.04

–0.06

–0.08

–0.10

–0.12

ERROR (% F SR)

–0.14

–0.16

–0.18

–0.20

–40 –20 40200 1008060

GAIN ERROR

FULL-SCALE ERROR

TEMPERATURE (°C)

Figure 17. Gain Error and Full-Scale Error vs. Temperature

1.5

1.0

0.5

0

–0.5

ERROR (mV)

–1.0

–1.5

–2.0

–2.5

–40 –20 402008060 100

ZERO-SCALE ERROR

OFFSET ERROR

TEMPERATURE (°C)

Figure 18. Zero-Scale Error and Offset Error vs. Temperature

1.0

= 25°C

T

A

0.5

0

–0.5

–1.0

ERROR (mV)

–1.5

–2.0

05299-017

–2.5

2.7 3.2 4.23.7 5.24.7

ZERO-SCALE ERROR

VDD (V)

OFFSET ERROR

05299-020

Figure 20. Zero-Scale Error and Offset Error vs. Supply Voltage

20

VDD = 3.6V
V

18

16

14

12

10

FREQUENCY

05299-018

= 5.5V

DD

8

6

4

2

0

1.20 1.22 1.24 1. 26 1.28 1.30 1. 32 1.34 1. 36 1.38 1.40 1. 42

Figure 21. I

Histogram with External Reference

DD

IDD (mA)

1.44

05299-021

1.0

0.5

GAIN ERROR

0

–0.5

ERROR (% FSR)

–1.0

–1.5

–2.0

FULL-SCAL E ERROR

2.7 3.2 3.7 4.74.2 5.2
VDD (V)

Figure 19. Gain Error and Full-Scale Error vs. Supply Voltage

05299-019

Rev. C | Page 13 of 28

14

VDD = 3.6V
V

= 5.5V

DD

12

10

V

= 1.25V V

REFOUT

8

6

FREQUENCY

4

2

0

2.02

2.04 2.06 2.08 2.10 2.12 2. 14 2.16 2.18 2.20 2.22 2.24 2. 26 2.28

Figure 22. I

Histogram with Internal Reference

DD

IDD (mA)

REFOUT

= 2.5V

05299-022

AD5678

(

m

0.50
DAC LOADED WIT H
FULL-SCAL E

0.40
SOURCING CURRENT

0.30

0.20

VDD= 3V

0.10

V

= 1.25V

REFOUT

0

–0.10

ERROR VOLTAGE (V)

–0.20

–0.30

–0.40

–0.50

–10 –8 –6 –4 –2 0 2 4 861

VDD= 5V
V

REFOUT

= 2.5V

CURRENT (mA)

DAC LOADED WIT H
ZERO-SCALE
SINKING CURRENT

Figure 23. Headroom at Rails vs. Source and Sink

05299-023

0

2.0
TA = 25°C

1.8

1.6

1.4

1.2

1.0

(mA)

DD

I

0.8

0.6

0.4

0.2

0

512 10512 20512 30512 40512 50512 60512

VDD = V

VDD = V

= 3V

REF

REF

CODE

= 5V

Figure 26. Supply Current vs. Code

05299-026

6.00
VDD= 5V

V

= 2.5V

REFOUT

5.00
T

= 25°C

A

4.00

3.00

(V)

OUT

V

2.00

1.00

0

–1.00

–30 –20 –10 0 10 20 30

CURRENT (mA)

FULL SCALE

3/4 SCALE

MIDSCALE

1/4 SCALE

ZERO SCALE

Figure 24. AD5678-2 Source and Sink Capability

4.00
VDD= 3V

V

= 1.25V

REFOUT

T

= 25°C

A

3.00

FULL SCALE

1.6

1.4

1.2

1.0

0.8

(mA)

DD

I

0.6

0.4

0.2

05299-024

0

–40 –20 0 20 40 60 80 100

VDD = V

VDD = V

TEMPERATURE ( °C)

REFIN

= 3.6V

REFIN

= 5.5V

05299-027

Figure 27. Supply Current vs. Temperature

1.6

TA=25°C

1.4

1.2

2.00

(V)

OUT

V

1.00

0

–1.00

–30 –20 –10 0 10 20 30

3/4 SCALE

MIDSCALE

1/4 SCALE

ZERO SCALE

CURRENT (mA)

Figure 25. AD5678-1 Source and Sink Capability

05299-025

1.0

A)

0.8

DD

I

0.6

0.4

0.2

0

2.7

3.2 4.23.7 5.24.7

VDD(V)

05299-028

Figure 28. Supply Current vs. Supply Voltage

Rev. C | Page 14 of 28

AD5678

8

TA = 25°C

7

6

VDD = V
T

= 25°C

A

REF

= 5V

5

4

(mA)

DD

I

3

2

1

VDD = 3V

0

012345

VDD = 5V

V

LOGIC

(V)

Fi e gure 29. Supply Current vs. Logic Input Voltag

VDD = V
T
FULL-SCALE CODE CHANGE
0x0000 TO 0xFFFF
OUTPUT L OADED WIT H 2kΩ
AND 200pF TO G ND

V

= 909mV/DIV

OUT

1

= 25°C

A

REF

= 5V

05299-029

6

V

1

2

DD

V

OUT

CH1 2.0V CH2 1.0V M100 μs 125MS/s

A CH1 1.28V

Fig le ure 32. Power-On Reset to Midsca

SYNC

1

3

2

SLCK

V

OUT

8.0ns/p t

VDD = 5V

05299-032

TIME BASE = 4μs/DIV

Figure 30. Full-Scale Settling Time, 5 V

V

1

2

DD

V

OUT

CH1 2.0V CH2 500mV M100 μs 125MS/s

A CH1 1.28V

Figure 31. Power-On Reset to 0 V

VDD = V
T

= 25°C

A

= 5V

REF

MAX(C2)*

420.0mV

8.0ns/p t

05299-030

CH1 5.0V
CH3 5.0V

CH2 500mV M400ns A CH1 1.4V

05299-033

Figure 33. Exiting Power-Down to Midscale

2.505

2.504

2.503

2.502

2.501

2.500

2.499

2.498

2.497

2.496

(V)

2.495

OUT

2.494

V

2.493

2.492

2.491

2.490

2.489

2.488

2.487

05299-031

2.486

2.485
0 512

64 128 192 256 320 384 448

VDD = 5V

= 2.5V

V

REFOUT

= 25°C

T

A

4ns/SAMPL E NUMBER

GLITCH IMPULSE = 3.55nV- s
1 LSB CHANGE AROUND

MIDSCALE ( 0x8000 TO 0x7FF F)

SAMPLE

05299-034

Figure 34. Digital-to-Analog Glitch Impulse (Negative)

Rev. C | Page 15 of 28

AD5678

2.5000

2.4995

2.4990

2.4985

2.4980

(V)

2.4975

OUT

V

2.4970

2.4965

2.4960

2.4955

2.4950
0 512

64 128 192 256 320 384 448

SAMPLE

VDD = 5V
V

REFOUT

= 25°C

T

A

4ns/SAMPL E NUMBER

Figure 35. Analog Crosstalk

2.4900

2.4895

2.4890

2.4885

2.4880

(V)

OUT

2.4875

V

2.4870

2.4865

2.4860

2.4855
0 512

64 128 192 256 320 384 448

SAMPLE

VDD = 5V
V

REFO

= 2

T

A

4ns/SAMPL E NUMBER

Figure 36. DAC-to-DAC Crosstalk

UT

5°C

= 2.5V

05299-035

= 2.5V

05299-036

VDD = 5V

= 2.5V

V

REFOUT

T

= 25°C

A

DAC LOADED WITH MIDSCALE

1

10μV/DIV

5s/DIV

Figure 38. 0.1 Hz to 10 Hz Output Noise Plot, Internal Reference

VDD = 3V

= 1.25V

V

REFOUT

= 25°C

T

A

DAC LOADED WITH MIDSCALE

1

5μV/DIV

4s/DIV

Figure 39. 0.1 Hz to 10 Hz Output Noise Plot, Internal Reference

05299-038

05299-039

VDD = V
T
DAC LOADED WITH MIDSCALE

1

Y AXIS = 2μV/DIV
X AXIS = 4s/DIV

= 25°C

A

REF

= 5V

Figure 37. 0.1 Hz to 10 Hz Output Noise Plot, External Reference

05299-037

Rev. C | Page 16 of 28

800

TA=25°C
MIDSCALE L OADED

700

600

500

400

300

OUTPUT NOISE (nV/ √Hz)

200

VDD=3V

100

V = 1.25V

REFOUT

0

100 100001000 100000 1000000

VDD=5V
V

=2.5V

REFOUT

FREQUE NCY ( Hz)

Figure 40. Noise Spectral Density, Internal Reference

9-040
0529

AD5678

–

20

VDD=5V
T

=25°C

A

–30

DAC LOADED W ITH FULL SCALE
V

= 2V ± 0.3V p-p

REF

–40

–50

–60

(dB)

–70

–80

–90

–100

2k 4k 6k 8k 10k

FREQUENCY (Hz)

Figure 41. Total Harmonic Distortion

16

V

= V

REF

DD

TA = 25°C

14

V

3V

=

12

s)

μ

10

TIME (

8

6

4

012 34 567 981

CAPACITANCE (nF)

DD

V

5V

=

DD

Figure 42. Settling Time vs. Capacitive Load

05299-041

05299-042

0

3

V

F

OUT

V

B

OUT

4

4

2

CH3 5.0V CH4 1.0V

CH2 1.0V M200n s A CH3 1.10V

Figure 43. Hardware

5

0

–5

–10

–15

(dB)

–20

–25

–30

–35

–40

10k 100k 1M 10M

Figure 44. Multiplying Bandwidth

CLR

CLR

FREQUENCY (Hz)

05299-043

VDD = 5V
T

= 25°C

A

05299-044

Rev. C | Page 17 of 28

AD5678

TERMINOLOGY

Relative Accuracy

For the DAC, relative accuracy, or integral nonlinearity (INL), is
a measure of the maximum deviation in LSBs from a straight
line passing through the endpoints of the DAC transfer
function. Figure 5, Figure 7, and Figure 9 show plots of typical
INL vs. code.

Full-Scale Error

Full-scale error is a measure of the output error when full-scale
code (0xFFFF) is loaded into the DAC register. Ideally, the
output should be V

− 1 LSB. Full-scale error is expressed as a

DD

percentage of the full-scale range. Figure 17 shows a plot of
typical full-scale error vs. temperature.

Differential Nonlinearity

Differential nonlinearity (DNL) is the difference between the
measured change and the ideal 1 LSB change between any two
adjacent codes. A specified differential nonlinearity of ±1 LSB
maximum ensures monotonicity. This DAC is guaranteed mono­tonic by design. Figure 6, Figure 8, and Figure 10 show plots of
typical DNL vs. code.

Offset Error

Offset error is a measure of the difference between the actual
V

and the ideal V

OUT

, expressed in millivolts in the linear

OUT

region of the transfer function. Offset error is measured on the
AD5678 with Code 512 loaded into the DAC register. It can be
negative or positive and is expressed in millivolts.

Zero-Code Error

Zero-code error is a measure of the output error when zero
code (0x0000) is loaded into the DAC register. Ideally, the
output should be 0 V. The zero-code error is always positive in
the AD5678, because the output of the DAC cannot go below 0 V.
It is due to a combination of the offset errors in the DAC and
output amplifier. Zero-code error is expressed in millivolts.
Figure 18 shows a plot of typical zero-code error vs.
temperature.

Gain Error

Gain error is a measure of the span error of the DAC. It is the
deviation in slope of the DAC transfer characteristic from the
ideal, expressed as a percentage of the full-scale range.

Zero-Code Error Drift

Zero-code error drift is a measure of the change in zero-code
error with a change in temperature. It is expressed in V/°C.

Gain Error Drift

Gain error drift is a measure of the change in gain error with
changes in temperature. It is expressed in (ppm of full-scale
range)/°C.

Digital-to-Analog Glitch Impulse

Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nV-s
and is measured when the digital input code is changed by
1 LSB at the major carry transition (0x7FFF to 0x8000). See
Figure 34.

DC Power Supply Rejection Ratio (PSRR)

PSRR indicates how the output of the DAC is affected by changes
in the supply voltage. PSRR is the ratio of the change in V
a change in V
in decibels. V

for full-scale output of the DAC. It is measured

DD

is held at 2 V, and VDD is varied ±10%.

REF

OUT

to

DC Crosstalk

DC crosstalk is the dc change in the output level of one DAC in
response to a change in the output of another DAC. It is measured
with a full-scale output change on one DAC (or soft power-down
and power-up) while monitoring another DAC. It is expressed
in microvolts.

DC crosstalk due to load current change is a measure of the
impact that a change in load current on one DAC has to another
DAC kept at midscale. It is expressed in microvolts per milliamp.

Reference Feedthrough

Reference feedthrough is the ratio of the amplitude of the signal
at the DAC output to the reference input when the DAC output
is not being updated (that is,

is high). It is expressed in

LDAC

decibels.

Channel-to-Channel Isolation

Channel-to-channel isolation is the ratio of the amplitude of the
signal at the output of one DAC to a sine wave on the reference
input of another DAC. It is measured in decibels.

Digital Feedthrough

Digital feedthrough is a measure of the impulse injected into
the analog output of a DAC from the digital input pins of the
device, but is measured when the DAC is not being written to
(

held high). It is specified in nV-s and measured with a

SYNC

full-scale change on the digital input pins, that is, from all 0s to
all 1s or vice versa.

Rev. C | Page 18 of 28

AD5678

Digital Crosstalk

Digital crosstalk is the glitch impulse transferred to the output
of one DAC at midscale in response to a full-scale code change
(all 0s to all 1s or vice versa) in the input register of another
DAC. It is measured in standalone mode and is expressed in
nV-s.

Multiplying Bandwidth

The amplifiers within the DAC have a finite bandwidth. The
multiplying bandwidth is a measure of this. A sine wave on the
reference (with full-scale code loaded to the DAC) appears on
the output. The multiplying bandwidth is the frequency at
which the output amplitude falls to 3 dB below the input.

Analog Crosstalk

Analog crosstalk is the glitch impulse transferred to the output
of one DAC due to a change in the output of another DAC. It is
measured by loading one of the input registers with a full-scale
code change (all 0s to all 1s or vice versa) while keeping

high, and then pulsing

the DAC whose digital code has not changed. The area of the
glitch is expressed in nV-s.

DAC-to-DAC C rosst a l k

DAC-to-DAC crosstalk is the glitch impulse transferred to the
output of one DAC due to a digital code change and subsequent
output change of another DAC. This includes both digital and
analog crosstalk. It is measured by loading one of the DACs
with a full-scale code change (all 0s to all 1s or vice versa) with

low and monitoring the output of another DAC. The

LDAC
energy of the glitch is expressed in nV-s.

low and monitoring the output of

LDAC

LDAC

Total Harmonic Distortion (THD)

Total harmonic distortion is the difference between an ideal
sine wave and its attenuated version using the DAC. The sine
wave is used as the reference for the DAC, and the THD is a
measure of the harmonics present on the DAC output. It is
measured in decibels.

Rev. C | Page 19 of 28

AD5678

V

THEORY OF OPERATION

D/A SECTION

The AD5678 DAC is fabricated on a CMOS process. The archi­tecture consists of a string of DACs followed by an output buffer
amplifier. The parts include an internal 1.25 V/2.5 V, 5 ppm/°C
reference with an internal gain of 2. Figure 45 shows a block
diagram of the DAC architecture.

DD

REF (+)

DAC REGISTER

RESISTOR

STRING

REF (–)

GND

Figure 45. DAC Architecture

OUTPUT
AMPLIFIER
(GAI N = +2)

V

OUT

Because the input coding to the DAC is straight binary, the ideal
output voltage when using an external reference is given by

OUT

VV

REFIN

⎟

⎜

N

2

⎠

⎝

D

⎞

⎛

×=

the ideal output voltage when using an internal reference is
given by

D

⎞

⎛

VV

2

××=

⎟

REFOUTOUT

⎜

N

2

⎠

⎝

where:

D = decimal equivalent of the binary code that is loaded to the

DAC register.
0 to 4,095 for AD5678 DAC C, D, E, F (12 bits).
0 to 65,535 for AD5678 DAC A, B, G, H (16 bits).

N = the DAC resolution.

RESISTOR STRING

The resistor string section is shown in Figure 46. It is simply a
string of resistors, each of value R. The code loaded into the
DAC register determines at which node on the string the
voltage is tapped off to be fed into the output amplifier. The
voltage is tapped off by closing one of the switches connecting
the string to the amplifier. Because it is a string of resistors, it is
guaranteed monotonic.

05299-005

INTERNAL REFERENCE

The AD5678 has an on-chip reference with an internal gain of

2. The AD5678-1 has a 1.25 V 5 ppm/°C reference, giving a full­scale output of 2.5 V. The AD5678-2 has a 2.5 V 5 ppm/°C
reference, giving a full-scale output of 5 V. The on-board
reference is off at power-up, allowing the use of an external
reference. The internal reference is enabled via a write to a
control register. See Tabl e 7 .

The internal reference associated with each part is available at
the V

REFOUT

used to drive external loads. When using the internal reference,
it is recommended that a 100 nF capacitor be placed between
the reference output and GND for reference stability.

Individual channel power-down is not supported while using
the internal reference.

R

R

R

R

R

Figure 46. Resistor String

TO OUTP UT
AMPLIFIER

05299-006

pin. A buffer is required if the reference output is

Rev. C | Page 20 of 28

AD5678

OUTPUT AMPLIFIER

The output buffer amplifier can generate rail-to-rail voltages on
its output, which gives an output range of 0 V to V

DD

. The
amplifier is capable of driving a load of 2 kΩ in parallel with
1,000 pF to GND. The source and sink capabilities of the output
amplifier can be seen in Figure 24 and Figure 25. The slew rate
is 1.5 V/µs with a ¼ to ¾ scale settling time of 10 µs.

SERIAL INTERFACE

The AD5678 has a 3-wire serial interface (
DIN) that is compatible with SPI, QSPI, and MICROWIRE

interface standards as well as most DSPs. See for a
timing diagram of a typical write sequence.

The write sequence begins by bringing the
from the DIN line is clocked into the 32-bit shift register on the

falling edge of SCLK. The serial clock frequency can be as high
as 50 MHz, making the AD5678 compatible with high speed

nd

DSPs. On the 32

falling clock edge, the last data bit is clocked
in and the programmed function is executed, that is, a change
in DAC register contents and/or a change in the mode of
operation. At this stage, the

line can be kept low or be

SYNC

brought high. In either case, it must be brought high for a
minimum of 15 ns before the next write sequence so that a
falling edge of

Because the

SYNC

than it does when V

can initiate the next write sequence.

SYNC

buffer draws more current when VIN = 2 V

= 0.8 V,

IN

should be idled low

SYNC

between write sequences for even lower power operation of the
part. As is mentioned previously, however,

brought high again just before the next write sequence.

SYNC

Figure 2

SYNC

SYNC

, SCLK, and

line low. Data

must be

Table 7. Command Definitions

Command

C3 C2 C1 C0 Description

0 0 0 0 Write to Input Register n
0 0 0 1 Update DAC Register n
0 0 1 0

0 0 1 1 Write to and update DAC Channel n
0 1 0 0 Power down/power up DAC
0 1 0 1 Load clear code register
0 1 1 0

0 1 1 1 Reset (power-on reset)
1 0 0 0 Set up internal REF register
1 0 0 1 Reserved
– – – – Reserved
1 1 1 1 Reserved

Write to Input Register n, update all
(software LDAC

Load LDAC

)

register

Table 8. Address Commands

Address (n)

A3 A2 A1 A0

0 0 0 0 DAC A (16 bits)
0 0 0 1 DAC B (16 bits)
0 0 1 0 DAC C (12 bits)
0 0 1 1 DAC D (12 bits)
0 1 0 0 DAC E (12 bits)
0 1 0 1 DAC F (12 bits)
0 1 1 0 DAC G (16 bits)
0 1 1 1 DAC H (16 bits)
1 1 1 1 All DACs

Selected DAC
Channel

Rev. C | Page 21 of 28

AD5678

INTERRUPT

INPUT SHIFT REGISTER

The input shift register is 32 bits wide. The first four bits are
don’t cares. The next four bits are the command bits, C3 to C0
(see Table 7), followed by the 4-bit DAC address bits, A3 to A0
(see Table 8), and finally the 16-/12-bit data-word. The data­word comprises the 16-/12-bit input code followed by four or
eight don’t care bits for the AD5678 DAC A, B, G, H and
AD5678 DAC C, D, E, F, respectively (See Figure 47 and
Figure 48). These data bits are transferred to the DAC register
on the 32

DB31 (MSB) DB0 (LSB)

X

XXX

nd

falling edge of SCLK.

C3 C2 C1 C0 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X

SYNC

In a normal write sequence, the

32 falling edges of SCLK, and the DAC is updated on the 32
falling edge and rising edge of

brought high before the 32

nd

falling edge, this acts as an
interrupt to the write sequence. The shift register is reset, and
the write sequence is seen as invalid. Neither an update of the
DAC register contents nor a change in the operating mode
occurs—see Figure 49.

DATA BITS

line is kept low for

SYNC

. However, if

SYNC

SYNC

nd

is

ADDRESS BITSCOMMAND BITS

Figure 47. AD5678 Input Register Content for DAC A, B, G , H

DB31 (MSB) DB0 (LSB)

X

XXX

C3C2C1C0A3A2A1A0D11D10D9D8D7D6D5D4D3D2D1D0XXXXXXXX

DATA BITS

ADDRESS BITSCOMMAND BITS

Figure 48. AD5678 Input Register Content for DAC C, D, E, F

SCLK

SYNC

DIN

DB31 DB0

INVALID WRITE SEQUENCE:

SYNC HIGH BEFORE 32ND FALLING EDGE

Figure 49.

SYNC

Interrupt Facility

DB31 DB0

VALID WRITE SEQUENCE , OUTPUT UPDATES

ON THE 32ND FALLING EDGE

05299-007

05299-008

05299-009

Rev. C | Page 22 of 28

AD5678

INTERNAL REFERENCE REGISTER

The on-board reference is off at power-up by default. This
allows the use of an external reference if the application requires
it. The on-board reference can be turned on/off by a user­programmable internal REF register by setting Bit DB0 high or
low (see Tabl e 9). Command 1000 is reserved for this internal
REF set-up command (see Tabl e 7). Tab l e 1 1 shows the state of
the bits in the input shift register corresponds to the mode of
operation of the device.

POWER-ON RESET

The AD5678 contains a power-on reset circuit that controls the
output voltage during power-up. The AD5678 output powers up
to 0 V, and the output remains powered up at this level until a
valid write sequence is made to the DAC. This is useful in
applications where it is important to know the state of the
output of the DAC while it is in the process of powering up.
There is also a software executable reset function that resets the
DAC to the power-on reset code. Command 0111 is reserved
for this reset function—see Tabl e 7. Any events on

during power-on reset are ignored.

CLR

LDAC

or

POWER-DOWN MODES

The AD5678 contains four separate modes of operation.
Command 0100 is reserved for the power-down function. See
Tabl e 7 . These modes are software-programmable by setting
two bits, Bit DB9 and Bit DB8, in the control register.

Tabl e 1 1 shows how the state of the bits corresponds to the
mode of operation of the device. Any or all DACs (DAC H to
DAC A) can be powered down to the selected mode by setting
the corresponding eight bits (DB7 to DB0) to 1. See Tab l e 1 2 for
the contents of the input shift register during power-down/power­up operation. When using the internal reference, only all channel
power-down to the selected modes is supported.

When both bits are set to 0, the part works normally with its
normal power consumption of 1.3 mA at 5 V. However, for the
three power-down modes, the supply current falls to 400 nA at
5 V (200 nA at 3 V). Not only does the supply current fall, but
the output stage is also internally switched from the output of
the amplifier to a resistor network of known values. This has the
advantage that the output impedance of the part is known while

the part is in power-down mode. There are three different
options. The output is connected internally to GND through
either a 1 kΩ or a 100 kΩ resistor, or it is left open-circuited
(three-state). The output stage is illustrated in Figure 50.

The bias generator of the selected DAC(s), output amplifier,
resistor string, and other associated linear circuitry are shut
down when the power-down mode is activated. However, the
contents of the DAC register are unaffected when in power­down. The time to exit power-down is typically 5 µs for

= 5 V and for VDD = 3 V, see Figure 33.

V

DD

Any combination of DACs can be powered up by setting PD1
and PD0 to 0 (normal operation). The output powers up to the
value in the input register (

DAC register before powering down (

low) or to the value in the

LDAC

high).

LDAC

CLEAR CODE REGISTER

The AD5678 has a hardware
clear input. The
the

DAC registers to the data contained in the user-configurable
CLR
function can be used in system calibration to load zero scale,
midscale, or full scale to all channels together. These clear code
values are user-programmable by setting two bits, Bit DB1 and Bit
DB0, in the

setting clears the outputs to 0 V. Command 0101 is reserved for
loading the clear code register, see .

The part exits clear code mode on the 32
next write to the part. If

sequence, the write is aborted.

The

the output starts to change—is typically 280 ns. However, if the
value is outside the linear region, it typically takes 520 ns after
executing

See Tab le 1 4 for contents of the input shift register during the
loading clear code register operation.

line low clears the contents of the input register and the

CLR

register and sets the analog outputs accordingly. This

CLR

pulse activation time—the falling edge of

CLR

CLR

input is falling edge sensitive . Bringing

CLR

control register. See . The default

CLR

for the output to start changing. See . Figure 43

pin that is an asynchronous

CLR

Tabl e 1 3

Tabl e 7

nd

falling edge of the

is activated during a write

CLR

to when

Rev. C | Page 23 of 28

AD5678

V

Table 9. Internal Reference Register

Internal REF Register (DB0) Action
0 Reference off (default)
1 Reference on

Table 10. 32-Bit Input Shift Register Contents for Reference Set-Up Function

MSB
DB31 to DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 to DB1 DB0

X 1 0 0 0 X X X X X 1/0
Don’t cares Command bits (C3 to C0) Address bits (A3 to A0) Don’t cares

Table 11. Power-Down Modes of Operation

DB9 DB8 Operating Mode

0 0 Normal operation
Power-down modes
0 1 1 kΩ to GND
1 0 100 kΩ to GND
1 1 Three-state

Table 12. 32-Bit Input Shift Register Contents for Power-Down/Power-Up Function

MSB LSB

DB31
to
DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20

X 0 1 0 0 X X X X X PD1 PD0 DAC H DAC G DAC F DAC E DAC D DAC C DAC B DAC

Don’t
cares

DB19
to
DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Command bits (C3 to C0) Address bits (A3 to A0)—

don’t cares

Don’t
cares

Power-

down mode

Power-down/power-up channel selection—set bit to 1 to select

FB

LSB

Internal REF
register

A

RESISTOR

STRING DAC

AMPLIFIER

POWER-DOW N

CIRCUITRY

RESISTOR
NETWORK

V

OUT

05299-010

Figure 50. Output Stage During Power-Down

Table 13. Clear Code Register

Clear Code Register
DB1 DB0
CR1 CR0 Clears to Code

0 0 0x0000
0 1 0x8000
1 0 0xFFFF
1 1 No operation

Table 14. 32-Bit Input Shift Register Contents for Clear Code Function

MSB

LSB

DB31 to DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 to DB2 DB1 DB0

X 0 1 0 1 X X X X X CR1 CR0
Don’t cares Command bits (C3 to C0) Address bits (A3 to A0)—don’t cares Don’t cares Clear code register

Rev. C | Page 24 of 28

AD5678

FUNCTION

LDAC

The outputs of all DACs can be updated simultaneously using
the hardware

Synchronous
are updated on the falling edge of the 32

pin.

LDAC

: After new data is read, the DAC registers

LDAC

nd

SCLK pulse.

LDAC

can be permanently low or pulsed as in . Figure 2

Asynchronous
time that the input registers are written to. When

: The outputs are not updated at the same

LDAC

LDAC

goes low,

the DAC registers are updated with the contents of the input register.

Alternatively, the outputs of all DACs can be updated simulta­neously using the software

function by writing to Input

LDAC
Register n and updating all DAC registers. Command 0011 is
reserved for this software

An
over the hardware

register gives the user extra flexibility and control

LDAC

LDAC

function.

LDAC

pin. This register allows the user to

select which combination of channels to simultaneously update
when the hardware

pin is executed. Setting the

LDAC

LDAC

bit

register to 0 for a DAC channel means that this channel’s update
is controlled by the

pin. If this bit is set to 1, this channel

LDAC

updates synchronously; that is, the DAC register is updated
after new data is read, regardless of the state of the

effectively sees the
for the

register mode of operation.) This flexibility is

LDAC

pin as being tied low. (See

LDAC

LDAC

Tabl e 15

pin. It

useful in applications where the user wants to simultaneously
update select channels while the rest of the channels are
synchronously updating.

POWER SUPPLY BYPASSING AND GROUNDING

When accuracy is important in a circuit, it is helpful to carefully
consider the power supply and ground return layout on the
board. The printed circuit board containing the AD5678 should
have separate analog and digital sections. If the AD5678 is in a
system where other devices require an AGND-to-DGND
connection, the connection should be made at one point only.
This ground point should be as close as possible to the AD5678.

The power supply to the AD5678 should be bypassed with 10 µF
and 0.1 µF capacitors. The capacitors should physically be as
close as possible to the device, with the 0.1 µF capacitor ideally
right up against the device. The 10 µF capacitors are the tantalum
bead type. It is important that the 0.1 µF capacitor has low effective
series resistance (ESR) and low effective series inductance (ESI),
such as is typical of common ceramic types of capacitors. This

0.1 µF capacitor provides a low impedance path to ground for
high frequencies caused by transient currents due to internal
logic switching.

The power supply line should have as large a trace as possible to
provide a low impedance path and reduce glitch effects on the
supply line. Clocks and other fast switching digital signals should
be shielded from other parts of the board by digital ground. Avoid
crossover of digital and analog signals if possible. When traces
cross on opposite sides of the board, ensure that they run at right
angles to each other to reduce feedthrough effects through the
board. The best board layout technique is the microstrip technique,
where the component side of the board is dedicated to the ground
plane only and the signal traces are placed on the solder side.
However, this is not always possible with a 2-layer board.

pin

pin. DAC channels see LDAC as 0.

DB19
to
DB8

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Don’t
cares

Setting

LDAC

bit to 1 overrides

LDAC

A

pin

Writing to the DAC using command 0110 loads the 8-bit

LDAC
register (DB7 to DB0). The default for each channel is 0; that is,
the
DAC channel is updated regardless of the state of the

pin. See for the contents of the input shift register
during the load

Table 15.

LDAC

0 1/0
1 X—don’t care

Table 16. 32-Bit Input Shift Register Contents for

MSB LSB

DB31
to
DB28

X 0 1 1 0 X X X X X DAC H DAC G DAC F DAC E DAC D DAC C DAC B DAC

Don’t
cares

pin works normally. Setting the bits to 1 means the

LDAC

LDAC

Tabl e 1 6

register mode of operation.

LDAC

Register

LDAC

Load DAC Register

Bits (DB7 to DB0)

LDAC

Pin

Operation

LDAC

Determined by LDAC
DAC channels update, overriding the LDAC

LDAC

DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20

Command bits (C3 to C0) Address bits (A3 to A0)—

don’t cares

Overwrite Function

Rev. C | Page 25 of 28

AD5678

OUTLINE DIMENSIONS

5.10

5.00

4.90

4.50

4.40

4.30

PIN 1

1.05

1.00

0.80

0.15

0.05

COPLANARITY

0.10

4.50

4.40

4.30

PIN 1

0.15

0.05

14

1

0.65 BSC

0.30

0.19

COMPLIANT TO JEDEC STANDARDS MO-153-AB-1

8

6.40
BSC

7

1.20

0.20

MAX

0.09

SEATING

PLANE

8°
0°

Figure 51. 14-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-14)

Dimensions shown in millimeters

5.10

5.00

4.90

16

0.65
BSC

COPLANARITY

COMPLIANT TO JEDEC STANDARDS MO-153-AB

0.10

0.30

0.19

9

6.40
BSC

81

1.20
MAX

SEATING

PLANE

0.20

0.09
8°

0°

Figure 52. 16-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-16)

Dimensions shown in millimeters

0.75

0.60

0.45

0.75

0.60

0.45

061908-A

ORDERING GUIDE

Package

Model1 Temperature Range Package Description

Option

AD5678BRUZ-1 −40°C to +105°C 14-Lead TSSOP RU-14 Zero ±16 LSB INL 1.25 V
AD5678BRUZ-1REEL7 −40°C to +105°C 14-Lead TSSOP RU-14 Zero ±16 LSB INL 1.25 V
AD5678BRUZ-2 −40°C to +105°C 16-Lead TSSOP RU-16 Zero ±16 LSB INL 2.5 V
AD5678BRUZ-2REEL7 −40°C to +105°C 16-Lead TSSOP RU-16 Zero ±16 LSB INL 2.5 V
AD5678ARUZ-2 −40°C to +105°C 16-Lead TSSOP RU-16 Zero ±32 LSB INL 2.5 V
AD5678ARUZ-2REEL7 −40°C to +105°C 16-Lead TSSOP RU-16 Zero ±32 LSB INL 2.5 V

1

Z = RoHS Compliant Part.

Rev. C | Page 26 of 28

Power-On
Reset to Code

Accuracy

Internal
Reference

AD5678

NOTES

Rev. C | Page 27 of 28

AD5678

NOTES

©2005–2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05299–0–2/11(C)

Rev. C | Page 28 of 28