ANALOG DEVICES AD5669R Service Manual

Octal, 12-/16-Bit, I2C, denseDACs

V

/

A

FEATURES

Low power octal DACs

AD5629R: 12 bits

AD5669R: 16 bits 16-lead LFCSP and 16-lead TSSOP On-chip 1.25 V/2.5 V, 5 ppm/°C reference Power down to 400 nA at 5 V, 200 nA at 3 V

2.7 V to 5.5 V power supply Guaranteed monotonic by design Power-on reset to zero scale or midscale 3 power-down functions Hardware

2

I

C-compatible serial interface supports standard (100 kHz)

LDAC

and fast (400 kHz) modes

APPLICATIONS

Process control Data acquisition systems Portable battery-powered instruments Digital gain and offset adjustment Programmable voltage and current sources

GENERAL DESCRIPTION

The AD5629R/AD5669R devices are low power, octal, 12-/16bit, buffered voltage-output DACs. All devices are guaranteed monotonic by design.

The AD5629R/AD5669R have an on-chip reference with an internal gain of 2. The AD5629R-1/AD5669R-1 have a 1.25 V, 5 ppm/°C reference, giving a full-scale output range of 2.5 V. The AD5629R-2/AD5629R-3 and the AD5669R-2/AD5669R-3 have a 2.5 V 5 ppm/°C reference, giving a full-scale output range of 5 V depending on the option selected. Devices with 1.25 V reference selected operate from a single 2.7 V to 5.5 V supply. Devices with 2.5 V reference selected operate from 4.5 V to 5.5 V. The on-chip reference is off at power-up, allowing the use of an external reference. The internal reference is enabled via a software write.

and

CLR

functions

with 5 ppm/°C On-Chip Reference

AD5629R/AD5669R

FUNCTIONAL BLOCK DIAGRAM

DD

AD5629R/AD5669R

SCL

SD

LDAC

INTERFACE LOGIC

A0

LDAC

CLR GND

INPUT

REGISTER

INPUT

REGISTER

INPUT

REGISTER

INPUT

REGISTER

INPUT

REGISTER

INPUT

REGISTER

INPUT

REGISTER

INPUT

REGISTER

POWER-ON RESET POWER-DOWN LOGIC

DAC

REGISTER

DAC

REGISTER

DAC

REGISTER

DAC

REGISTER

DAC

REGISTER

DAC

REGISTER

DAC

REGISTER

DAC

REGISTER

Figure 1.

The parts incorporate a power-on reset circuit to ensure that the DAC output powers up to 0 V (AD5629R-1/AD5629R-2, AD5669R-1/AD5669R-2) or midscale (AD5629R-3/AD5669R-3) and remains powered up at this level until a valid write takes place. The part contains a power-down feature that reduces the current consumption of the device to 400 nA at 5 V and provides software-selectable output loads while in power-down mode for any or all DAC channels.

PRODUCT HIGHLIGHTS

1. Octal, 12-/16-bit DACs.

2. On-chip 1.25 V/2.5 V, 5 ppm/°C reference.

3. Available in 16-lead LFCSP and TSSOP.

4. Power-on reset to 0 V or midscale.

5. Power-down capability. When powered down, the DAC

typically consumes 200 nA at 3 V and 400 nA at 5 V.

REFIN

STRING

V

REFOUT

1.25V/2.5V REF

DAC A

DAC B

DAC C

DAC D

DAC E

DAC F

DAC G

DAC H

BUFFER

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

A

B

C

D

E

F

G

H

08819-001

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

AD5629R/AD5669R

REVISION HISTORY

12/10—Rev. 0 to Rev. A

Changes to Features, General Description, and Product

Highlights Sections........................................................................... 1

Changes to AD5629R Relative Accuracy Parameter, Reference Output (1.25 V) Reference Input Range Parameter, and Reference

Output (2.5 V) Reference Input Range Parameter (Table 1) ...... 3

Changes to Relative Accuracy Parameter, Reference Tempco

Parameter (Table 2) .......................................................................... 5

Changes to Output Voltage Settling Time Parameter (Table 3) . 6

Changes to Table 5............................................................................ 9

Changes to

Added Figure 32 and Figure 33..................................................... 15

Added Figure 46.............................................................................. 17

Changes to Internal Reference Section........................................ 20

Changes to Power-On Reset Section............................................ 23

Changes to Clear Code Register Section ..................................... 24

Updated Outline Dimensions....................................................... 27

Changes to Ordering Guide.......................................................... 28

10/10—Revision 0: Initial Version

CLR

Pin Description (Table 6)................................. 10

Rev. A | Page 2 of 28

AD5629R/AD5669R

SPECIFICATIONS

VDD = 4.5 V to 5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, V

Table 1.

A Grade1 B Grade1 Parameter Min Typ Max Min Typ Max Unit Test Conditions/Comments

STATIC PERFORMANCE

2

AD5629R

Resolution 12 12 Bits Relative Accuracy ±0.5 ±4 ±0.5 ±1 LSB See Figure 6 Differential Nonlinearity ±0.25 ±0.25 LSB

AD5669R

Resolution 16 16 Bits Relative Accuracy ±8 ±32 ±8 ±16 LSB See Figure 5 Differential Nonlinearity ±1 ±1 LSB

Zero-Code Error 6 19 6 19 mV All 0s loaded to DAC register (see Figure 18)

Zero-Code Error Drift ±2 ±2 µV/°C

Full-Scale Error −0.2 −1 −0.2 −1 % FSR All 1s loaded to DAC register (see Figure 19)

Gain Error ±1 ±1 % FSR

Gain Temperature Coefficient ±2.5 ±2.5 ppm Of FSR/°C

Offset Error ±6 ±19 ±6 ±19 mV

DC Power Supply Rejection

–80 –80 dB V

Ratio

DC Crosstalk

10 10 µV

(External Reference) 5 5 µV/mA Due to load current change 10 10 µV Due to powering down (per channel) DC Crosstalk

25 25 µV

(Internal Reference) 10 10 µV/mA Due to load current change

OUTPUT CHARACTERISTICS3

Output Voltage Range 0 VDD 0 VDD V Capacitive Load Stability 2 2 nF RL = ∞ 10 10 nF RL = 2 kΩ DC Output Impedance 0.5 0.5 Ω Short-Circuit Current 30 30 mA VDD = 5 V Power-Up Time 4 4 µs Coming out of power-down mode, VDD = 5 V

REFERENCE INPUTS

Reference Current 40 50 40 50 µA V Reference Input Range 0 VDD 0 VDD V Reference Input Impedance 14.6 14.6 kΩ

REFERENCE OUTPUT (1.25 V)

Output Voltage 1.247 1.253 1.247 1.253 µA TA = 25°C

Reference Input Range

±15

Output Impedance 7.5 7.5 kΩ

REFERENCE OUTPUT (2.5 V)

Output Voltage 2.495 2.505 2.495 2.505 µA TA = 25°C

Reference Input Range

±15



Output Impedance 7.5 7.5 kΩ

= VDD. All specifications T

REFIN

±5 ±15

±5 ±10



ppm/°C

MIN

to T

, unless otherwise noted.

MAX

Guaranteed monotonic by design (see Figure 8)

Guaranteed monotonic by design (see Figure 7)

± 10%

DD

Due to full-scale output change, R

= 2 kΩ to GND or VDD

L

Due to full-scale output change,

= 2 kΩ to GND or VDD

R

L

= VDD = 5.5 V (per DAC channel)

REFIN

Rev. A | Page 3 of 28

AD5629R/AD5669R

A Grade1 B Grade1 Parameter Min Typ Max Min Typ Max Unit Test Conditions/Comments

LOGIC INPUTS3

Input Current ±3 ±3 µA All digital inputs Input Low Voltage, V Input High Voltage, V Pin Capacitance 3 3 pF

POWER REQUIREMENTS

VDD 4.5 5.5 4.5 5.5 V

IDD (Normal Mode)4 VIH = VDD and VIL = GND

VDD = 4.5 V to 5.5 V 1.3 1.8 1.3 1.8 mA Internal reference off 2 2.5 2 2.5 mA Internal reference on

IDD (All Power-Down Modes)5

VDD = 4.5 V to 5.5 V 0.4 1 0.4 1 µA VIH = VDD and VIL = GND

1

Temperature range is −40°C to +105°C, typical at 25°C.

2

Linearity calculated using a reduced code range of the AD5629R (Code 32 to Code 4064) and the AD5669R (Code 512 to 65,024). Output unloaded.

3

Guaranteed by design and characterization; not production tested.

4

Interface inactive. All DACs active. DAC outputs unloaded.

5

All eight DACs powered down.

0.8 0.8 V VDD = 5 V

INL

2 2 V VDD = 5 V

INH

All digital inputs at 0 or V DAC active, excludes load current

,

DD

Rev. A | Page 4 of 28

AD5629R/AD5669R

VDD = 2.7 V to 3.6 V, RL = 2 kΩ to GND, CL = 200 pF to GND, V

Table 2.

A Grade1 B Grade1 Parameter Min Typ Max Min Typ Max Unit Conditions/Comments

STATIC PERFORMANCE

2

AD5629R

Resolution 12 12 Bits

Relative Accuracy ±0.5 ±4 ±0.5 ±1 LSB See Figure 6

Differential Nonlinearity ±0.25 ±0.25 LSB Guaranteed monotonic by design (see Figure 8) AD5669R

Resolution 16 16 Bits

Relative Accuracy ±8 ±32 ±8 ±16 LSB See Figure 5

Differential Nonlinearity ±1 ±1 LSB Guaranteed monotonic by design (see Figure 7) Zero-Code Error 6 19 6 19 mV All 0s loaded to DAC register (see Figure 18) Zero-Code Error Drift ±2 ±2 µV/°C Full-Scale Error −0.2 −1 −0.2 −1 % FSR All 1s loaded to DAC register (see Figure 19) Gain Error ±1 ±1 % FSR Gain Temperature Coefficient ±2.5 ±2.5 ppm Of FSR/°C Offset Error ±6 ±19 ±6 ±19 mV DC Power Supply Rejection

–80 –80 dB V

Ratio DC Crosstalk

10 10 µV

(External Reference) 5 5 µV/mA Due to load current change 10 10 µV Due to powering down (per channel) DC Crosstalk

25 25 µV

(Internal Reference) 10 10 µV/mA Due to load current change

OUTPUT CHARACTERISTICS3

Output Voltage Range 0 VDD 0 VDD V Capacitive Load Stability 2 2 nF RL = ∞ 10 10 nF RL = 2 kΩ DC Output Impedance 0.5 0.5 Ω Short-Circuit Current 30 30 mA VDD = 3 V Power-Up Time 4 4 µs Coming out of power-down mode, VDD = 3 V

REFERENCE INPUTS

Reference Current 40 50 40 50 µA V Reference Input Range 0 VDD 0 VDD Reference Input Impedance 14.6 14.6 kΩ

REFERENCE OUTPUT

Output Voltage AD5629R/AD5669R 1.247 1.253 1.247 1.253 V TA = 25°C Reference Tempco3 ±15 ±5 ±15 ppm/°C Reference Output Impedance 7.5 7.5 kΩ

LOGIC INPUTS3

Input Current ±3 ±3 µA All digital inputs Input Low Voltage, V Input High Voltage, V

0.8 0.8 V VDD = 3 V

INL

2 2 V VDD = 3 V

INH

Pin Capacitance 3 3 pF

= VDD. All specifications T

REFIN

MIN

± 10%

DD

to T

, unless otherwise noted.

MAX

Due to full-scale output change, R

= 2 kΩ to GND or VDD

L

Due to full-scale output change,

= 2 kΩ to GND or VDD

R

L

= VDD = 3.6 V (per DAC channel)

REFIN

Rev. A | Page 5 of 28

AD5629R/AD5669R

A Grade1 B Grade1 Parameter Min Typ Max Min Typ Max Unit Conditions/Comments

POWER REQUIREMENTS

VDD 2.7 3.6 2.7 3.6 V

All digital inputs at 0 or V DAC active, excludes load current

IDD (Normal Mode)4 V

= VDD and VIL = GND

IH

VDD = 2.7 V to 3.6 V 1.0 1.5 1.0 1.5 mA Internal reference off

1.8 2.25 1.7 2.25 mA Internal reference on

IDD (All Power-Down Modes)5

VDD = 2.7 V to 3.6 V 0.2 1 0.2 1 µA VIH = VDD and VIL = GND

1

Temperature range is −40°C to +105°C, typical at 25°C.

2

Linearity calculated using a reduced code range of the AD5629R (Code 32 to Code 4064) and the AD5669R (Code 512 to 65,024). Output unloaded.

3

Guaranteed by design and characterization; not production tested.

4

Interface inactive. All DACs active. DAC outputs unloaded.

5

All eight DACs powered down.

AC CHARACTERISTICS

VDD = 2.7 V to 5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, V

= VDD. All specifications T

REFIN

MIN

to T

, unless otherwise noted.

MAX

,

DD

Table 3.

Parameter

1, 2

Min Typ Max Unit Conditions/Comments3

Output Voltage Settling Time 2.5 7 µs ¼ to ¾ scale settling to ±2 LSB Slew Rate 1.2 V/µs Digital-to-Analog Glitch Impulse 4 nV-s 1 LSB change around major carry (see Figure 34) 19 nV-s From Code 59904 to Code 59903 Digital Feedthrough 0.1 nV-s Reference Feedthrough −90 dB V

= 2 V ± 0.1 V p-p, frequency = 10 Hz to 20 MHz

REFIN

Digital Crosstalk 0.2 nV-s Analog Crosstalk 0.4 nV-s DAC-to-DAC Crosstalk 0.8 nV-s Multiplying Bandwidth 320 kHz V Total Harmonic Distortion −80 dB V

= 2 V ± 0.2 V p-p

REFIN

= 2 V ± 0.1 V p-p, frequency = 10 kHz

REFIN

Output Noise Spectral Density 120 nV/√Hz DAC code = 0x8400, 1 kHz 100 nV/√Hz DAC code = 0x8400, 10 kHz

1

Guaranteed by design and characterization; not production tested.

2

See the Terminology section.

3

Temperature range is −40°C to +105°C, typical at 25°C.

Rev. A | Page 6 of 28

AD5629R/AD5669R

I2C TIMING CHARACTERISTICS

VDD = 2.7 V to 5.5 V; all specifications T

Table 4.

Parameter Conditions Min Max Unit Description

1

f

Standard mode 100 kHz Serial clock frequency

SCL

Fast mode 400 kHz t1 Standard mode 4 s t Fast mode 0.6 s t2 Standard mode 4.7 s t Fast mode 1.3 s t3 Standard mode 250 ns t Fast mode 100 ns t4 Standard mode 0 3.45 s t Fast mode 0 0.9 s t5 Standard mode 4.7 s t Fast mode 0.6 s t6 Standard mode 4 s t Fast mode 0.6 s t7 Standard mode 4.7 s t Fast mode 1.3 s t8 Standard mode 4 s t Fast mode 0.6 s t9 Standard mode 1000 ns t Fast mode 300 ns t10 Standard mode 300 ns t Fast mode 300 ns t11 Standard mode 1000 ns t Fast mode 300 ns t

Standard mode 1000 ns

11A

Fast mode 300 ns t12 Standard mode 300 ns t Fast mode 300 ns t13 Standard mode 10 ns Fast mode 10 ns t14 Standard mode 300 ns

Fast mode 300 ns t15 Standard mode 20 ns Fast mode 20 ns

2

t

Fast mode 0 50 ns Pulse width of spike suppressed

SP

1

The SDA and SCL timing is measured with the input filters enabled. Switching off the input filters improves the transfer rate but has a negative effect on the EMC

behavior of the part.

2

Input filtering on the SCL and SDA inputs suppresses noise spikes that are less than 50 ns for fast mode or less than 10 ns for high speed mode.

MIN

to T

, f

= 400 kHz, unless otherwise noted.

MAX

SCL

HIGH

LOW

SU;DAT

HD;DAT

SU;STA

HD;STA

BUF

SU;STO

RDA

FDA

RCL

t

RCL1

after an acknowledge bit

FCL

LDAC

Falling edge of ninth SCL clock pulse of last byte of a valid write to the LDAC falling edge

CLR

, SCL high time

, SCL low time

, data setup time

, data hold time

, setup time for a repeated start condition

, hold time (repeated) start condition

, bus-free time between a stop and a start condition

, setup time for a stop condition

, rise time of SDA signal

, fall time of SDA signal

, rise time of SCL signal

, rise time of SCL signal after a repeated start condition and

, fall time of SCL signal

pulse width low

Rev. A | Page 7 of 28

AD5629R/AD5669R

t

SCL

SDA

t

7

PS S P

LDAC*

CLR

*ASYNCHRONOUS LDAC UPDAT E MODE.

2

t

6

11

t

4

t

12

t

1

t

3

t

15

t

6

t

5

t

10

t

8

t

14

t

9

t

13

08819-002

Figure 2. Serial Write Operation

Rev. A | Page 8 of 28

AD5629R/AD5669R

ABSOLUTE MAXIMUM RATINGS

T

= 25°C, unless otherwise noted.

A

Table 5.

Parameter Rating

VDD to GND −0.3 V to +7 V Digital Input Voltage to GND −0.3 V to VDD + 0.3 V V

to GND −0.3 V to VDD + 0.3 V

OUT

V

REFIN/VREFOUT

Operating Temperature Range

Industrial −40°C to +105°C

Storage Temperature Range −65°C to +150°C Junction Temperature (TJ Power Dissipation (TJ Thermal Impedance, θJA

16-Lead TSSOP (4-Layer Board) 112.6°C/W 16-Lead LFCSP (4-Layer Board) 30.4°C/W

Reflow Soldering Peak Temperature

Pb Free 260°C

to GND −0.3 V to VDD + 0.3 V

) +150°C

MAX

− TA)/θJA

MAX

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

Rev. A | Page 9 of 28

ANALOG DEVICES AD5669R Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

PRODUCT HIGHLIGHTS

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

AC CHARACTERISTICS

I2C TIMING CHARACTERISTICS

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION