ANALOG DEVICES AD5669R Service Manual

Octal, 12-/16-Bit, I2C, denseDACs

V

/

A

FEATURES

Low power octal DACs

AD5629R: 12 bits

AD5669R: 16 bits 16-lead LFCSP and 16-lead TSSOP On-chip 1.25 V/2.5 V, 5 ppm/°C reference Power down to 400 nA at 5 V, 200 nA at 3 V

2.7 V to 5.5 V power supply Guaranteed monotonic by design Power-on reset to zero scale or midscale 3 power-down functions Hardware

2

I

C-compatible serial interface supports standard (100 kHz)

LDAC

and fast (400 kHz) modes

APPLICATIONS

Process control Data acquisition systems Portable battery-powered instruments Digital gain and offset adjustment Programmable voltage and current sources

GENERAL DESCRIPTION

The AD5629R/AD5669R devices are low power, octal, 12-/16bit, buffered voltage-output DACs. All devices are guaranteed monotonic by design.

The AD5629R/AD5669R have an on-chip reference with an internal gain of 2. The AD5629R-1/AD5669R-1 have a 1.25 V, 5 ppm/°C reference, giving a full-scale output range of 2.5 V. The AD5629R-2/AD5629R-3 and the AD5669R-2/AD5669R-3 have a 2.5 V 5 ppm/°C reference, giving a full-scale output range of 5 V depending on the option selected. Devices with 1.25 V reference selected operate from a single 2.7 V to 5.5 V supply. Devices with 2.5 V reference selected operate from 4.5 V to 5.5 V. The on-chip reference is off at power-up, allowing the use of an external reference. The internal reference is enabled via a software write.

and

CLR

functions

with 5 ppm/°C On-Chip Reference

AD5629R/AD5669R

FUNCTIONAL BLOCK DIAGRAM

DD

AD5629R/AD5669R

SCL

SD

LDAC

INTERFACE LOGIC

A0

LDAC

CLR GND

INPUT

REGISTER

INPUT

REGISTER

INPUT

REGISTER

INPUT

REGISTER

INPUT

REGISTER

INPUT

REGISTER

INPUT

REGISTER

INPUT

REGISTER

POWER-ON RESET POWER-DOWN LOGIC

DAC

REGISTER

DAC

REGISTER

DAC

REGISTER

DAC

REGISTER

DAC

REGISTER

DAC

REGISTER

DAC

REGISTER

DAC

REGISTER

Figure 1.

The parts incorporate a power-on reset circuit to ensure that the DAC output powers up to 0 V (AD5629R-1/AD5629R-2, AD5669R-1/AD5669R-2) or midscale (AD5629R-3/AD5669R-3) and remains powered up at this level until a valid write takes place. The part contains a power-down feature that reduces the current consumption of the device to 400 nA at 5 V and provides software-selectable output loads while in power-down mode for any or all DAC channels.

PRODUCT HIGHLIGHTS

1. Octal, 12-/16-bit DACs.

2. On-chip 1.25 V/2.5 V, 5 ppm/°C reference.

3. Available in 16-lead LFCSP and TSSOP.

4. Power-on reset to 0 V or midscale.

5. Power-down capability. When powered down, the DAC

typically consumes 200 nA at 3 V and 400 nA at 5 V.

REFIN

STRING

V

REFOUT

1.25V/2.5V REF

DAC A

DAC B

DAC C

DAC D

DAC E

DAC F

DAC G

DAC H

BUFFER

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

A

B

C

D

E

F

G

H

08819-001

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

AD5629R/AD5669R

REVISION HISTORY

12/10—Rev. 0 to Rev. A

Changes to Features, General Description, and Product

Highlights Sections........................................................................... 1

Changes to AD5629R Relative Accuracy Parameter, Reference Output (1.25 V) Reference Input Range Parameter, and Reference

Output (2.5 V) Reference Input Range Parameter (Table 1) ...... 3

Changes to Relative Accuracy Parameter, Reference Tempco

Parameter (Table 2) .......................................................................... 5

Changes to Output Voltage Settling Time Parameter (Table 3) . 6

Changes to Table 5............................................................................ 9

Changes to

Added Figure 32 and Figure 33..................................................... 15

Added Figure 46.............................................................................. 17

Changes to Internal Reference Section........................................ 20

Changes to Power-On Reset Section............................................ 23

Changes to Clear Code Register Section ..................................... 24

Updated Outline Dimensions....................................................... 27

Changes to Ordering Guide.......................................................... 28

10/10—Revision 0: Initial Version

CLR

Pin Description (Table 6)................................. 10

Rev. A | Page 2 of 28

AD5629R/AD5669R

SPECIFICATIONS

VDD = 4.5 V to 5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, V

Table 1.

A Grade1 B Grade1 Parameter Min Typ Max Min Typ Max Unit Test Conditions/Comments

STATIC PERFORMANCE

2

AD5629R

Resolution 12 12 Bits Relative Accuracy ±0.5 ±4 ±0.5 ±1 LSB See Figure 6 Differential Nonlinearity ±0.25 ±0.25 LSB

AD5669R

Resolution 16 16 Bits Relative Accuracy ±8 ±32 ±8 ±16 LSB See Figure 5 Differential Nonlinearity ±1 ±1 LSB

Zero-Code Error 6 19 6 19 mV All 0s loaded to DAC register (see Figure 18)

Zero-Code Error Drift ±2 ±2 µV/°C

Full-Scale Error −0.2 −1 −0.2 −1 % FSR All 1s loaded to DAC register (see Figure 19)

Gain Error ±1 ±1 % FSR

Gain Temperature Coefficient ±2.5 ±2.5 ppm Of FSR/°C

Offset Error ±6 ±19 ±6 ±19 mV

DC Power Supply Rejection

–80 –80 dB V

Ratio

DC Crosstalk

10 10 µV

(External Reference) 5 5 µV/mA Due to load current change 10 10 µV Due to powering down (per channel) DC Crosstalk

25 25 µV

(Internal Reference) 10 10 µV/mA Due to load current change

OUTPUT CHARACTERISTICS3

Output Voltage Range 0 VDD 0 VDD V Capacitive Load Stability 2 2 nF RL = ∞ 10 10 nF RL = 2 kΩ DC Output Impedance 0.5 0.5 Ω Short-Circuit Current 30 30 mA VDD = 5 V Power-Up Time 4 4 µs Coming out of power-down mode, VDD = 5 V

REFERENCE INPUTS

Reference Current 40 50 40 50 µA V Reference Input Range 0 VDD 0 VDD V Reference Input Impedance 14.6 14.6 kΩ

REFERENCE OUTPUT (1.25 V)

Output Voltage 1.247 1.253 1.247 1.253 µA TA = 25°C

Reference Input Range

±15

Output Impedance 7.5 7.5 kΩ

REFERENCE OUTPUT (2.5 V)

Output Voltage 2.495 2.505 2.495 2.505 µA TA = 25°C

Reference Input Range

±15



Output Impedance 7.5 7.5 kΩ

= VDD. All specifications T

REFIN

±5 ±15

±5 ±10



ppm/°C

MIN

to T

, unless otherwise noted.

MAX

Guaranteed monotonic by design (see Figure 8)

Guaranteed monotonic by design (see Figure 7)

± 10%

DD

Due to full-scale output change, R

= 2 kΩ to GND or VDD

L

Due to full-scale output change,

= 2 kΩ to GND or VDD

R

L

= VDD = 5.5 V (per DAC channel)

REFIN

Rev. A | Page 3 of 28

AD5629R/AD5669R

A Grade1 B Grade1 Parameter Min Typ Max Min Typ Max Unit Test Conditions/Comments

LOGIC INPUTS3

Input Current ±3 ±3 µA All digital inputs Input Low Voltage, V Input High Voltage, V Pin Capacitance 3 3 pF

POWER REQUIREMENTS

VDD 4.5 5.5 4.5 5.5 V

IDD (Normal Mode)4 VIH = VDD and VIL = GND

VDD = 4.5 V to 5.5 V 1.3 1.8 1.3 1.8 mA Internal reference off 2 2.5 2 2.5 mA Internal reference on

IDD (All Power-Down Modes)5

VDD = 4.5 V to 5.5 V 0.4 1 0.4 1 µA VIH = VDD and VIL = GND

1

Temperature range is −40°C to +105°C, typical at 25°C.

2

Linearity calculated using a reduced code range of the AD5629R (Code 32 to Code 4064) and the AD5669R (Code 512 to 65,024). Output unloaded.

3

Guaranteed by design and characterization; not production tested.

4

Interface inactive. All DACs active. DAC outputs unloaded.

5

All eight DACs powered down.

0.8 0.8 V VDD = 5 V

INL

2 2 V VDD = 5 V

INH

All digital inputs at 0 or V DAC active, excludes load current

,

DD

Rev. A | Page 4 of 28

AD5629R/AD5669R

VDD = 2.7 V to 3.6 V, RL = 2 kΩ to GND, CL = 200 pF to GND, V

Table 2.

A Grade1 B Grade1 Parameter Min Typ Max Min Typ Max Unit Conditions/Comments

STATIC PERFORMANCE

2

AD5629R

Resolution 12 12 Bits

Relative Accuracy ±0.5 ±4 ±0.5 ±1 LSB See Figure 6

Differential Nonlinearity ±0.25 ±0.25 LSB Guaranteed monotonic by design (see Figure 8) AD5669R

Resolution 16 16 Bits

Relative Accuracy ±8 ±32 ±8 ±16 LSB See Figure 5

Differential Nonlinearity ±1 ±1 LSB Guaranteed monotonic by design (see Figure 7) Zero-Code Error 6 19 6 19 mV All 0s loaded to DAC register (see Figure 18) Zero-Code Error Drift ±2 ±2 µV/°C Full-Scale Error −0.2 −1 −0.2 −1 % FSR All 1s loaded to DAC register (see Figure 19) Gain Error ±1 ±1 % FSR Gain Temperature Coefficient ±2.5 ±2.5 ppm Of FSR/°C Offset Error ±6 ±19 ±6 ±19 mV DC Power Supply Rejection

–80 –80 dB V

Ratio DC Crosstalk

10 10 µV

(External Reference) 5 5 µV/mA Due to load current change 10 10 µV Due to powering down (per channel) DC Crosstalk

25 25 µV

(Internal Reference) 10 10 µV/mA Due to load current change

OUTPUT CHARACTERISTICS3

Output Voltage Range 0 VDD 0 VDD V Capacitive Load Stability 2 2 nF RL = ∞ 10 10 nF RL = 2 kΩ DC Output Impedance 0.5 0.5 Ω Short-Circuit Current 30 30 mA VDD = 3 V Power-Up Time 4 4 µs Coming out of power-down mode, VDD = 3 V

REFERENCE INPUTS

Reference Current 40 50 40 50 µA V Reference Input Range 0 VDD 0 VDD Reference Input Impedance 14.6 14.6 kΩ

REFERENCE OUTPUT

Output Voltage AD5629R/AD5669R 1.247 1.253 1.247 1.253 V TA = 25°C Reference Tempco3 ±15 ±5 ±15 ppm/°C Reference Output Impedance 7.5 7.5 kΩ

LOGIC INPUTS3

Input Current ±3 ±3 µA All digital inputs Input Low Voltage, V Input High Voltage, V

0.8 0.8 V VDD = 3 V

INL

2 2 V VDD = 3 V

INH

Pin Capacitance 3 3 pF

= VDD. All specifications T

REFIN

MIN

± 10%

DD

to T

, unless otherwise noted.

MAX

Due to full-scale output change, R

= 2 kΩ to GND or VDD

L

Due to full-scale output change,

= 2 kΩ to GND or VDD

R

L

= VDD = 3.6 V (per DAC channel)

REFIN

Rev. A | Page 5 of 28

AD5629R/AD5669R

A Grade1 B Grade1 Parameter Min Typ Max Min Typ Max Unit Conditions/Comments

POWER REQUIREMENTS

VDD 2.7 3.6 2.7 3.6 V

All digital inputs at 0 or V DAC active, excludes load current

IDD (Normal Mode)4 V

= VDD and VIL = GND

IH

VDD = 2.7 V to 3.6 V 1.0 1.5 1.0 1.5 mA Internal reference off

1.8 2.25 1.7 2.25 mA Internal reference on

IDD (All Power-Down Modes)5

VDD = 2.7 V to 3.6 V 0.2 1 0.2 1 µA VIH = VDD and VIL = GND

1

Temperature range is −40°C to +105°C, typical at 25°C.

2

Linearity calculated using a reduced code range of the AD5629R (Code 32 to Code 4064) and the AD5669R (Code 512 to 65,024). Output unloaded.

3

Guaranteed by design and characterization; not production tested.

4

Interface inactive. All DACs active. DAC outputs unloaded.

5

All eight DACs powered down.

AC CHARACTERISTICS

VDD = 2.7 V to 5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, V

= VDD. All specifications T

REFIN

MIN

to T

, unless otherwise noted.

MAX

,

DD

Table 3.

Parameter

1, 2

Min Typ Max Unit Conditions/Comments3

Output Voltage Settling Time 2.5 7 µs ¼ to ¾ scale settling to ±2 LSB Slew Rate 1.2 V/µs Digital-to-Analog Glitch Impulse 4 nV-s 1 LSB change around major carry (see Figure 34) 19 nV-s From Code 59904 to Code 59903 Digital Feedthrough 0.1 nV-s Reference Feedthrough −90 dB V

= 2 V ± 0.1 V p-p, frequency = 10 Hz to 20 MHz

REFIN

Digital Crosstalk 0.2 nV-s Analog Crosstalk 0.4 nV-s DAC-to-DAC Crosstalk 0.8 nV-s Multiplying Bandwidth 320 kHz V Total Harmonic Distortion −80 dB V

= 2 V ± 0.2 V p-p

REFIN

= 2 V ± 0.1 V p-p, frequency = 10 kHz

REFIN

Output Noise Spectral Density 120 nV/√Hz DAC code = 0x8400, 1 kHz 100 nV/√Hz DAC code = 0x8400, 10 kHz

1

Guaranteed by design and characterization; not production tested.

2

See the Terminology section.

3

Temperature range is −40°C to +105°C, typical at 25°C.

Rev. A | Page 6 of 28

AD5629R/AD5669R

I2C TIMING CHARACTERISTICS

VDD = 2.7 V to 5.5 V; all specifications T

Table 4.

Parameter Conditions Min Max Unit Description

1

f

Standard mode 100 kHz Serial clock frequency

SCL

Fast mode 400 kHz t1 Standard mode 4 s t Fast mode 0.6 s t2 Standard mode 4.7 s t Fast mode 1.3 s t3 Standard mode 250 ns t Fast mode 100 ns t4 Standard mode 0 3.45 s t Fast mode 0 0.9 s t5 Standard mode 4.7 s t Fast mode 0.6 s t6 Standard mode 4 s t Fast mode 0.6 s t7 Standard mode 4.7 s t Fast mode 1.3 s t8 Standard mode 4 s t Fast mode 0.6 s t9 Standard mode 1000 ns t Fast mode 300 ns t10 Standard mode 300 ns t Fast mode 300 ns t11 Standard mode 1000 ns t Fast mode 300 ns t

Standard mode 1000 ns

11A

Fast mode 300 ns t12 Standard mode 300 ns t Fast mode 300 ns t13 Standard mode 10 ns Fast mode 10 ns t14 Standard mode 300 ns

Fast mode 300 ns t15 Standard mode 20 ns Fast mode 20 ns

2

t

Fast mode 0 50 ns Pulse width of spike suppressed

SP

1

The SDA and SCL timing is measured with the input filters enabled. Switching off the input filters improves the transfer rate but has a negative effect on the EMC

behavior of the part.

2

Input filtering on the SCL and SDA inputs suppresses noise spikes that are less than 50 ns for fast mode or less than 10 ns for high speed mode.

MIN

to T

, f

= 400 kHz, unless otherwise noted.

MAX

SCL

HIGH

LOW

SU;DAT

HD;DAT

SU;STA

HD;STA

BUF

SU;STO

RDA

FDA

RCL

t

RCL1

after an acknowledge bit

FCL

LDAC

Falling edge of ninth SCL clock pulse of last byte of a valid write to the LDAC falling edge

CLR

, SCL high time

, SCL low time

, data setup time

, data hold time

, setup time for a repeated start condition

, hold time (repeated) start condition

, bus-free time between a stop and a start condition

, setup time for a stop condition

, rise time of SDA signal

, fall time of SDA signal

, rise time of SCL signal

, rise time of SCL signal after a repeated start condition and

, fall time of SCL signal

pulse width low

Rev. A | Page 7 of 28

AD5629R/AD5669R

t

SCL

SDA

t

7

PS S P

LDAC*

CLR

*ASYNCHRONOUS LDAC UPDAT E MODE.

2

t

6

11

t

4

t

12

t

1

t

3

t

15

t

6

t

5

t

10

t

8

t

14

t

9

t

13

08819-002

Figure 2. Serial Write Operation

Rev. A | Page 8 of 28

AD5629R/AD5669R

ABSOLUTE MAXIMUM RATINGS

T

= 25°C, unless otherwise noted.

A

Table 5.

Parameter Rating

VDD to GND −0.3 V to +7 V Digital Input Voltage to GND −0.3 V to VDD + 0.3 V V

to GND −0.3 V to VDD + 0.3 V

OUT

V

REFIN/VREFOUT

Operating Temperature Range

Industrial −40°C to +105°C

Storage Temperature Range −65°C to +150°C Junction Temperature (TJ Power Dissipation (TJ Thermal Impedance, θJA

16-Lead TSSOP (4-Layer Board) 112.6°C/W 16-Lead LFCSP (4-Layer Board) 30.4°C/W

Reflow Soldering Peak Temperature

Pb Free 260°C

to GND −0.3 V to VDD + 0.3 V

) +150°C

MAX

− TA)/θJA

MAX

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

Rev. A | Page 9 of 28

AD5629R/AD5669R

V

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

AD5629R/AD5669R

LDAC

SCL

16 A0

SDA 13

15

14

1

V

DD

2

V

A

OUT

V

OUT

V

OUT

NOTES

1. EXPOSED PAD MUST BE TIED TO GND.

C E

3 4

TOP VIEW

(Not to Scale)

6

5 G

OUT

V

REFOUT

/V

REFIN

V

Figure 3. 16-Lead LFCSP (CP-16-17)

12

GND

B

11

V

OUT

10

D

V

OUT

9

F

V

OUT

8

7

H

CLR

OUT

V

08819-003

REFIN/VREFOUT

LDAC

V

OUT

V

OUT

V

OUT

V

OUT

V

A0

DD

A C E G

1

2

3

AD5629R/

AD5669R

4

5

(Not to Scale)

6

7

8

TOP VIEW

Figure 4. 16-Lead TSSOP (RU-16)

Table 6. Pin Function Descriptions

Pin No.

16-Lead LFCSP

15

16-Lead TSSOP Mnemonic

1

LDAC

Description

Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data. This allows all DAC outputs to simultaneously update. Alternatively, this pin can

be tied permanently low. 16 2 A0 Address Input. Sets the least significant bit of the 7-bit slave address. 1 3 V

DD

Power Supply Input. These parts can be operated from 2.7 V to 5.5 V. Decouple the supply

with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND. 2 4 V 3 5 V 4 6 V 5 7 V 6 8 V

A Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.

OUT

C Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.

OUT

E Analog Output Voltage from DAC E. The output amplifier has rail-to-rail operation.

OUT

G Analog Output Voltage from DAC G. The output amplifier has rail-to-rail operation.

OUT

REFIN/VREFOUT

The AD5629R/AD5669R have a common pin for reference input and reference output.

When using the internal reference, this is the reference output pin. When using an external

reference, this is the reference input pin. The default for this pin is as a reference input. 7 9

Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is low, all LDAC

CLR

pulses are ignored. When CLR

updated with the data contained in the CLR

is activated, the input register and the DAC register are

code register—zero scale, midscale, or full

scale. The default setting clears the output to 0 V. 8 10 V 9 11 V 10 12 V 11 13 V 12 14 GND 13 15 SDA

H Analog Output Voltage from DAC H. The output amplifier has rail-to-rail operation.

OUT

F Analog Output Voltage from DAC F. The output amplifier has rail-to-rail operation.

OUT

D Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.

OUT

B Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.

OUT

Ground Reference Point for All Circuitry on the Parts.

Serial Data Input. This is used in conjunction with the SCL line to clock data into or out of

the 32-bit input shift register. It is a bidirectional, open-drain data line that should be

14 16 SCL

pulled to the supply with an external pull-up resistor.

Serial Clock Line. This is used in conjunction with the SDA line to clock data into or out of

the 32-bit input shift register. 17 N/A Exposed Pad (EPAD) The exposed pad must be tied to GND.

16

SCL

15

SDA

14

GND

13

V

B

OUT

12

V

D

OUT

11

V

F

OUT

10

H

V

OUT

9

CLR

08819-004

Rev. A | Page 10 of 28

AD5629R/AD5669R

TYPICAL PERFORMANCE CHARACTERISTICS

10

8

6

4

2

0

INL (LSB)

–2

–4

–6

–8

–10

0 10k 20k 30k 40k 50k 60k 65535

CODES

VDD = 5V EXT REF = 5V T

Figure 5. INL AD5669R—External Reference

= 25°C

A

08819-106

0.20 VDD = 5V

EXT REF = 5V

0.15

T

= 25°C

A

0.10

0.05

0

DNL (LSB)

–0.05

–0.10

–0.15

–0.20

0 500 1000 1500 2000 2500 3000 3500 4095

CODES

Figure 8. DNL AD5629R—External Reference

08819-111

1.0

0.8

0.6

0.4

0.2

0

INL (LSB)

–0.2

–0.4

–0.6

–0.8

–1.0

0 500 1000 1500 2000 2500 3000 3500 4095

CODES

VDD = 5V EXT REF = 5V T

Figure 6. INL AD5629R—External Reference

1.0 VDD = 5V

EXT REF = 5V

0.8 T

= 25°C

A

0.6

0.4

0.2

0

DNL (LSB)

–0.2

–0.4

–0.6

–0.8

–1.0

0 10k 20k 30k 40k 50k 60k 65535

CODES

Figure 7. DNL AD5669R—External Reference

= 25°C

A

10

5

0

INL (LSB)

–5

–10

0 10k 20k 30k 40k 50k 60k 65535

08819-108

CODES

VDD = 5V INT REF = 2.5V T

= 25°C

A

08819-112

Figure 9. INL AD5669R-2—Internal Reference

1.0

0.5

0

INL (LSB)

–0.5

–1.0

0 500 1000 1500 2000 2500 3000 3500 4095

08819-109

CODES

VDD = 5V INT REF = 2.5V T

= 25°C

A

08819-114

Figure 10. INL AD5629R-2—Internal Reference

Rev. A | Page 11 of 28

AD5629R/AD5669R

1.0 VDD = 5V

INT REF = 2.5V T

A

0.5

= 25°C

1.0 VDD = 3V

INT REF = 1.25V T

= 25°C

A

0.5

0

DNL (LSB)

–0.5

–1.0

0 10k 20k 30k 40k 50k 60k 65535

CODES

Figure 11. DNL AD5669R-2—Internal Reference

0.20 VDD = 5V

INT REF = 2.5V

0.15

T

= 25°C

A

0.10

0.05

0

DNL (LSB)

–0.05

–0.10

–0.15

–0.20

0 500 1000 1500 2000 2500 3000 3500 4095

CODES

Figure 12. DNL AD5629R-2— Internal Reference

0

INL (LSB)

–0.5

–1.0

0 500 1000 1500 2000 2500 3000 3500 4095

08819-115

CODES

08819-120

Figure 14. INL AD5629R-1—Internal Reference

1.0

0.5

0

DNL (LSB)

–0.5

–1.0

0 10k 20k 30k 40k 50k 60k 65535

08819-117

CODES

VDD = 3V INT REF = 1.25V T

= 25°C

A

08819-121

Figure 15. DNL AD5669R-1—Internal Reference

10

8

6

4

2

0

INL (LSB)

–2

–4

–6

–8

–10

0 10k 20k 30k 40k 50k 60k 65535

CODES

VDD = 3V INT REF = 1.25V T

= 25°C

A

Figure 13. INL AD5669R-1—Internal Reference

08819-118

Rev. A | Page 12 of 28

0.20

0.15

0.10

0.05

0

DNL (LSB)

–0.05

–0.10

–0.15

–0.20

0 500 1000 1500 2000 2500 3000 3500 4095

CODES

VDD = 3V INT REF = 1.25V T

A

Figure 16. DNL AD5629R-1—Internal Reference

= 25°C

08819-123

AD5629R/AD5669R

–

–0.05

0

VDD = 5V

1.95

1.90

TA = 25°C

–0.10

FULL-SCALE ERROR

GAIN ERROR

TEMPERATURE ( °C)

ERROR (% F SR)

–0.15

–0.20

–0.25

–0.30

–40 1251109580655035205–10–25

Figure 17. Gain Error and Full-Scale Error vs. Temperature

6

VDD = 5V

5

OFFSET ERRO R

4

ZERO-CODE ERROR

3

ERROR (mV)

2

1.85

1.80

1.75

ERROR (mV)

1.70

1.65

1.60

1.55

08819-124

2.7 5.55.14.74.33.93.53.1

OFFSET ERROR

ZERO-CODE ERROR

VDD (V)

08819-127

Figure 20. Zero-Code Error and Offset Error vs. Supply Voltage

21

18

15

12

9

NUMBER OF HITS

6

1

0

–40 1251109580655035205–10–25

TEMPERATURE ( °C)

Figure 18. Zero-Code Error and Offset Error vs. Temperature

0.16 FULL-SCALE ERROR

GAIN ERROR

VDD (V)

ERROR (% F SR)

–0.17

–0.18

–0.19

–0.20

–0.21

–0.22

–0.23

–0.24

–0.25

–0.26

2.7 5.55.14.74.33.93.53.1

Figure 19. Gain Error and Full-Scale Error vs. Supply Voltage

TA = 25°C

3

0

0.85 0.90 0.95 1.00 1.05

08819-125

18

16

14

12

10

8

6

NUMBER OF HITS

4

2

0

1.65 1.70 1.75 1.80 1.85 1.90

08819-126

IDD WITH EXT ERNAL REF E RENCE (mA)

Figure 21. I

Figure 22. I

Histogram with External Reference

DD

IDD WITH INTERNAL REFERENCE ( mA)

Histogram with Internal Reference

DD

8819-128

8819-129

Rev. A | Page 13 of 28

AD5629R/AD5669R

0.4 T

= 25°C

A

0.3

0.2

0.1

V

= 3V, INT REF = 1.25V

DD

0

–0.1

–0.2

ERROR VOLTAGE (V)

–0.3

–0.4

–0.5

VDD = 5V, INT REF = 2.5V

–10–8–6–4–20246810

SOURCE/SINK CURRE NT ( mA)

08819-130

Figure 23. Headroom at Rails vs. Source and Sink

1.8 TA = 25°C

1.7

1.6

1.5

1.4

1.3

(mA)

DD

I

1.2

1.1

1.0

0.9

0.8

0 10k 20k 30k 40k 50k 60k

VDD = 5V

V

= 3V

DD

DIGITAL CODES (Decimal )

Figure 26. Supply Current vs. Code

08819-133

6

VDD = 5V INT REF = 2.5V T

= 25°C

5

A

4

3

(V)

OUT

V

2

1

0

–1

–0.03 –0.02 –0.01 0 0.01 0.02 0.03

SOURCE AND SINK CURRENT ( mA)

FULL SCALE

3/4 SCALE

MIDSCALE

1/4 SCALE

ZERO CODE

Figure 24. AD5669R-2 Source and Sink Capability

4.0 VDD = 3V

INT REF = 1.25V

3.5 T

= 25°C

A

3.0

2.5

2.0

(V)

1.5

OUT

V

1.0

0.5

0

–0.5

–1.0

–0.03 –0.02 –0.01 0 0.01 0.02 0.03

MIDSCALE

1/4 SCALE

ZERO CODE

SOURCE AND SINK CURRENT ( mA)

FULL SCALE

3/4 SCALE

Figure 25. AD5669R-1 Source and Sink Capability

2.0 TA = 25°C

1.9

1.8

1.7

= 5.5V

1.6

1.5

(mA)

DD

I

1.4

1.3

1.2

1.1

1.0

–40 –25 –10 5 20 35 50 65 80 95 110 125

08819-131

TEMPERATURE ( °C)

V

DD

VDD = 3.6V

08819-134

Figure 27. Supply Current vs. Temperature

1.48 TA = 25°C

1.46

1.44

1.42

(mA)

DD

I

1.40

1.38

1.36

1.34

2.7 5.55.14.74.33.93.53.1

08819-132

VDD (V)

08819-135

Figure 28. Supply Current vs. Supply Voltage

Rev. A | Page 14 of 28

AD5629R/AD5669R

5.5

2.3 TA = 25°C

2.1

1.9

1.7

=3V

V

LOGIC

VDD =5V

(V)

1.5

(mA)

DD

I

1.3

1.1

V

0.9

0.7

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

DD

Figure 29. Supply Current vs. Logic Input Voltage

6

VDD = 5V EXT REF = 5V T

= 25°C

A

5

4

(V)

3

OUT

V

2

1

0

–2 86420

TIME (µs)

Figure 30. Full-Scale Settling Time, 5 V

08819-136

08819-137

VDD = 5V

5.0

EXT REF = 5V T

= 25°C

A

4.5

4.0

3.5

3.0

2.5

2.0

VOLTAGE (V)

1.5

1.0

0.5 0

–0.5

–0.0010 0.00100.00060.0002–0.0002–0.0006

5.5 VDD = 5V

5.0

EXT REF = 5V T

= 25°C

A

4.5

4.0

3.5

3.0

2.5

2.0

VOLTAGE (V)

1.5

1.0

0.5

0

–0.5

–10 1050–5

V

DD

V

A

OUT

TIME (s)

Figure 32. Power-On Reset to Midscale

24TH CLK RISING EDGE

V

TIME (µs)

Figure 33. Exiting Power-Down to Midscale

OUT

08819-139

A

08819-140

5.5 VDD = 5V

5.0

EXT REF = 5V T

= 25°C

A

4.5

4.0

3.5

3.0

2.5

2.0

VOLTAGE (V)

1.5

1.0

0.5

0

–0.5

–0.0010 0.00100.00060.0002–0.0002–0.0006

V

DD

V

OUT

TIME (s)

Figure 31. Power-On Reset to 0 V

T

V

3

A

4

08819-138

CH3 10.0mV

B

W

CH4 5.0V

OUT

TH

CLK RISING EDG E

24

M400ns A CH4 1.50V

T 17.0%

A

VDD = 5V EXT REF = 5V T

= 25°C

A

08819-141

Figure 34. Digital-to-Analog Glitch Impulse (Negative)

Rev. A | Page 15 of 28

AD5629R/AD5669R

0.0010

0.0005

–0.0005

GLITCH AMPLITUDE ( V )

–0.0010

–0.0015

0.0020

0.0015

0.0010

0.0005

–0.0005

GLITCH AMPLITUDE ( V )

–0.0010

VDD = 5V EXT REF = 5V T

= 25°C

A

0

0987654321

0

TIME (µs)

Figure 35. Analog Crosstalk

VDD = 5V EXT REF = 5V T

= 25°C

A

0.20 EXT REF = 2.5V

DAC CODE = 0xFF00

0.15

0.10

0.05

0

–0.05

OUTPUT NOISE (V)

–0.10

–0.15

–0.20

01897654321

08819-142

TIME (s)

0

08819-145

Figure 38. 0.1 Hz to 10 Hz Output Noise Plot, Internal Reference

0.20

INT REF = 1.25V DAC CODE = 0xFF00

0.15

0.10

0.05

0

–0.05

OUTPUT NOISE (V)

–0.10

–0.15

–0.0015

087654321

TIME (µs)

Figure 36. DAC-to-DAC Crosstalk

0.06 VDD = 5.5V

EXT REF = 5V DAC CODE = 0xFF00

0.04

0.02

0

–0.02

OUTPUT VOLTAGE (V)

–0.04

–0.06

–0.08

01897654321

TIME (s)

Figure 37. 0.1 Hz to 10 Hz Output Noise Plot, External Reference

–0.20

01897654321

08819-143

Figure 39. 0.1 Hz to 10 Hz Output Noise Plot, Internal Reference

800

700

600

500

400

300

OUTPUT NOISE (nV/ Hz)

200

100

0

08819-144

100 1M100k10k1k

V

REF

V

= 1.25V

REF

= 2.5V

FREQUENCY (Hz)

Figure 40. Noise Spectral Density, Internal Reference

TIME (s)

= 5.5V

V

DD

DAC CODE = 0x8400

0

08819-146

08819-147

Rev. A | Page 16 of 28

AD5629R/AD5669R

THD (dB)

SETTLING TIME (µs)

0

VDD = 5.5V EXT REF = 5V T

= 25°C

–20

A

V

= 2V ± 0.1V p-p

REF

FREQUENCY = 10kHz

–40

–60

–80

–100

–120

–140

0 10,0008000600040002000

9

TA = 25°C

8

7

6

5

4

3

2

1

0

010987654321

Figure 42. Settling Time vs. Capacitive Load

FREQUENCY (Hz)

Figure 41. Total Harmonic Distortion

VDD = EXTERNAL RE FERENCE = 5V

V

= EXTERNAL REFERENCE = 3V

DD

CAPACITIVE LOAD (nF)

10

0

–10

–20

–30

(dBm)

–40

OUT

V

–50

–60

–70

–80

08819-148

CH A CH B CH C CH D CH E CH F CH G CH H –3dB

10 100M10M1M100k1k01k100

VDD = 5.5V EXT REF = 5V T

= 25°C

A

V

= 2V ± 0.2V p-p

REF

FREQUENCY (Hz)

08819-151

Figure 44. Multiplying Bandwidth

1.2510

1.2508

1.2506

1.2504

1.2502

1.2500

1.2498

1.2496

REFERENCE (ppm/°C)

1.2494

1.2492

1.2490

08819-149

–40 25 105

TEMPERATURE (°C)

VDD = 5.5V

08819-152

Figure 45. 1.25 V Reference Temperature Coefficient vs. Temperature

5.5

5.0

4.5

4.0

3.5

3.0

2.5

2.0

VOLTAGE (V)

1.5

1.0

0.5 0

–0.5

–10 1050–5

CLR PULSE

TIME (µs)

Figure 43. Hardware

V

CLR

OUT

EXT REF = 5V

A

08819-150

2.503

2.502

2.501

2.500

2.499

2.498

REFERENCE (ppm/°C)

2.497

2.496

2.495 105 25 –40

TEMPERATURE ( °C)

Figure 46. 2.5 V Reference Temperature Coefficient vs. Temperature

08819-153

Rev. A | Page 17 of 28

AD5629R/AD5669R

TERMINOLOGY

Relative Accuracy

For the DAC, relative accuracy, or integral nonlinearity (INL), is a measure of the maximum deviation in LSBs from a straight line passing through the endpoints of the DAC transfer function. Figure 5, Figure 6, Figure 9, Figure 10, Figure 13, and Figure 14 show plots of typical INL vs. code.

Differential Nonlinearity

Differential nonlinearity (DNL) is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ±1 LSB maximum ensures monotonicity. This DAC is guaranteed monotonic by design. Figure 7, Figure 8, Figure 11, Figure 12, Figure 15, and Figure 16 show plots of typical DNL vs. code.

Offset Error

Offset error is a measure of the difference between the actual V

and the ideal V

OUT

, expressed in millivolts in the linear

OUT

region of the transfer function. Offset error is measured on the AD5669R between Code 512 and Code 65024 loaded into the DAC register. It can be negative or positive and is expressed in millivolts.

Zero-Code Error

Zero-code error is a measure of the output error when zero code (0x0000) is loaded into the DAC register. Ideally, the output should be 0 V. The zero-code error is always positive because the output of the DAC cannot go below 0 V. It is due to a combination of the offset errors in the DAC and output amplifier. Zero-code error is expressed in millivolts. Figure 18 shows a plot of typical zero-code error vs. temperature.

Gain Error

Gain error is a measure of the span error of the DAC. It is the deviation in slope of the DAC transfer characteristic from the ideal, expressed as a percentage of the full-scale range.

Zero-Code Error Drift

Zero-code error drift is a measure of the change in zero-code error with a change in temperature. It is expressed in μV/°C.

Gain Error Drift

Gain error drift is a measure of the change in gain error with changes in temperature. It is expressed in (ppm of full-scale range)/°C.

Full-Scale Error

Full-scale error is a measure of the output error when full-scale code (0xFFFF) is loaded into the DAC register. Ideally, the output should be V

− 1 LSB. Full-scale error is expressed as

REF

a percentage of the full-scale range. Figure 17 shows a plot of typical full-scale error vs. temperature.

Digital-to-Analog Glitch Impulse

Digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the DAC register changes state. It is normally specified as the area of the glitch in nV-s and is measured when the digital input code is changed by 1 LSB at the major carry transition (0x7FFF to 0x8000). Figure 34 shows a typical digital-to-analog glitch impulse plot.

DC Power Supply Rejection Ratio (PSRR)

PSRR indicates how the output of the DAC is affected by changes in the supply voltage. PSRR is the ratio of the change in V a change in V 2 V, and V

for full-scale output of the DAC. V

DD

is varied ±10%. It is measured in decibels.

DD

REF

to

OUT

is held at

DC Crosstalk

DC crosstalk is the dc change in the output level of one DAC in response to a change in the output of another DAC. It is measured with a full-scale output change on one DAC (or soft power-down and power-up) while monitoring another DAC kept at midscale. It is expressed in microvolts.

DC crosstalk due to load current change is a measure of the impact that a change in load current on one DAC has on another DAC kept at midscale. It is expressed in microvolts per milliamp.

Digital Feedthrough

Digital feedthrough is a measure of the impulse injected into the analog output of a DAC from the digital input pins of the device, but is measured when the DAC is not being written to. It is specified in nV-s and measured with a full-scale change on the digital input pins, that is, from all 0s to all 1s or vice versa.

Digital Crosstalk

Digital crosstalk is the glitch impulse transferred to the output of one DAC at midscale in response to a full-scale code change (all 0s to all 1s or vice versa) in the input register of another DAC. It is measured in standalone mode and is expressed in nV-s.

Analog Crosstalk

Analog crosstalk is the glitch impulse transferred to the output of one DAC due to a change in the output of another DAC. It is measured by loading one of the input registers with a full-scale code change (all 0s to all 1s or vice versa) while keeping

LDAC

high and then pulsing

low and monitoring the output of

LDAC

the DAC whose digital code has not changed. The area of the glitch is expressed in nV-s.

Rev. A | Page 18 of 28

AD5629R/AD5669R

DAC-to-DAC C rosst a l k

DAC-to-DAC crosstalk is the glitch impulse transferred to the output of one DAC due to a digital code change and subsequent output change of another DAC. This includes both digital and analog crosstalk. It is measured by loading one of the DACs with a full-scale code change (all 0s to all 1s or vice versa) with LDAC

low and monitoring the output of another DAC. The

energy of the glitch is expressed in nV-s.

Multiplying Bandwidth

The amplifiers within the DAC have a finite bandwidth. The multiplying bandwidth is a measure of this. A sine wave on the reference (with full-scale code loaded to the DAC) appears on the output. The multiplying bandwidth is the frequency at which the output amplitude falls to 3 dB below the input.

Total Harmonic Distortion (THD)

Total harmonic distortion is the difference between an ideal sine wave and its attenuated version using the DAC. The sine wave is used as the reference for the DAC, and the THD is a measure of the harmonics present on the DAC output. It is measured in decibels.

Rev. A | Page 19 of 28

AD5629R/AD5669R

V

THEORY OF OPERATION

DIGITAL-TO-ANALOG CONVERTER (DAC) SECTION

The AD5629R/AD5669R are fabricated on a CMOS process. The architecture consists of a string of DACs followed by an output buffer amplifier. Each part includes an internal

1.25 V/2.5 V, 5 ppm/°C reference with an internal gain of 2. Figure 47 and Figure 48 show block diagrams of the DAC architecture.

REFIN/VREFOUT

RESISTOR STRING

The resistor string section is shown in Figure 49. It is simply a string of resistors, each of value R. The code loaded into the DAC register determines at which node on the string the voltage is tapped off to be fed into the output amplifier. The voltage is tapped off by closing one of the switches connecting the string to the amplifier. Because it is a string of resistors, it is guaranteed monotonic.

INTERNAL

REFERENCE

1

CAN BE OVERDRIVEN

BY V

REFIN/VREFOUT

Figure 47. DAC Architecture for Internal Reference Configuration

1

DAC

REGISTER

.

REF (+)

RESISTOR

STRING

REF (–)

GND

OUTPUT AMPLIFIER GAIN = ×2

V

OUT

08819-045

REFIN/VREFOUT

REF

R

Figure 48. DAC Architecture for External Reference Configuration

BUFFER

REF (+)

RESISTOR

STRING

REF (–)

GND

OUTPUT AMPLIFIER GAIN = ×2

V

OUT

08819-046

Because the input coding to the DAC is straight binary, the ideal output voltage when using an external reference is given by

OUT

VV

REFIN

⎟

⎜

N

2

⎠

⎝

D

⎞

⎛

×=

The ideal output voltage when using the internal reference is given by

D

⎞

⎛

VV

2

××=

⎟

REFOUTOUT

⎜

N

2

⎠

⎝

where:

D = decimal equivalent of the binary code that is loaded to the

DAC register as follows: 0 to 4095 for AD5629R (12 bits). 0 to 65,535 for AD5669R (16 bits).

N = the DAC resolution.

R

Figure 49. Resistor String

TO OUTPUT AMPLIFIER

08819-047

INTERNAL REFERENCE

The AD5629R/AD5669R have an on-chip reference with an internal gain of 2. The AD5629R-1/AD5669R-1 have a 1.25 V, 5 ppm/°C reference, giving a full-scale output of 2.5 V or the AD5629R-2/AD5629R-3/AD5669R-2/AD5629R-3 have a 2.5 V, 5 ppm/°C reference, working between a supply from 4.5 V to

5.5 V giving a full-scale output of 5 V. The on-board reference is off at power-up, allowing the use of an external reference. The internal reference is enabled via a write to the control register (see Tabl e 8 ).

The internal reference associated with each part is available at the V used to drive external loads. When using the internal reference, it is recommended that a 100 nF capacitor be placed between the reference output and GND for reference stability.

Individual channel power-down is not supported while using the internal reference.

pin. A buffer is required if the reference output is

REFOUT

Rev. A | Page 20 of 28

AD5629R/AD5669R

(

OUTPUT AMPLIFIER

The output buffer amplifier can generate rail-to-rail voltages on its output, which gives an output range of 0 V to V

DD

. The amplifier is capable of driving a load of 2 kΩ in parallel with 1000 pF to GND. The source and sink capabilities of the output amplifier can be seen in Figure 24 and Figure 25. The slew rate is 1.5 V/μs with a ¼ to ¾ scale settling time of 10 μs.

SERIAL INTERFACE

The AD5629R/AD5669R have 2-wire I2C-compatible serial interfaces (refer to January 2000, available from Philips Semiconductor). The AD5629R/AD5669R can be connected to an I device under the control of a master device. See Figure 2 for a timing diagram of a typical write sequence.

The AD5629R/AD5669R support standard (100 kHz) and fast (400 kHz) modes. High speed operation is only available on selected models. See the Ordering Guide for a full list of models. Support is not provided for 10-bit addressing and general call addressing.

The AD5629R/AD5669R each have a 7-bit slave address. The parts have a slave address whose five MSBs are 10101, and the two LSBs are set by the state of the A0 address pin, which determines the state of the A0 and A1 address bits.

The facility to make hardwired changes to the A0 pin allows the user to incorporate up to three of these devices on one bus, as outlined in Tab l e 7 .

Table 7. ADDR Pin Settings

A0 Pin Connection A1 A0

VDD 0 0 NC 1 0 GND 1 1

The 2-wire serial bus protocol operates as follows:

The master initiates data transfer by establishing a start

1.

condition when a high-to-low transition on the SDA line occurs while SCL is high. The following byte is the address byte, which consists of the 7-bit slave address. The slave

SCL

The I2C-Bus Specification, Version 2.1,

2

C bus as a slave

19 91

address corresponding to the transmitted address responds by pulling SDA low during the ninth clock pulse (this is termed the acknowledge bit). At this stage, all other devices on the bus remain idle while the selected device waits for data to be written to or read from its shift register.

Data is transmitted over the serial bus in sequences of nine

2. clock pulses (eight data bits followed by an acknowledge bit). The transitions on the SDA line must occur during the low period of SCL and remain stable during the high period of SCL.

When all data bits have been read or written, a stop

3. condition is established. In write mode, the master pulls

th

the SDA line high during the 10

clock pulse to establish a stop condition. In read mode, the master issues a no acknowledge for the ninth clock pulse (that is, the SDA line remains high). The master brings the SDA line low

th

before the 10

clock pulse and then high during the 10th

clock pulse to establish a stop condition.

WRITE OPERATION

When writing to the AD5629R/AD5669R, the user must begin

W

with a start command followed by an address byte (R/

= 0), after which the DAC acknowledges that it is prepared to receive data by pulling SDA low. The AD5629R/AD5669R require two bytes of data for the DAC and a command byte that controls various DAC functions. Three bytes of data must, therefore, be written to the DAC, the command byte followed by the most significant data byte and the least significant data byte, as shown in Figure 50

. After these data bytes are acknowledged by the

AD5629R/AD5669R, a stop condition follows.

READ OPERATION

When reading data back from the AD5629R/AD5669R, the user begins with a start command followed by an address byte

W

= 1), after which the DAC acknowledges that it is prepared

(R/ to transmit data by pulling SDA low. Two bytes of data are then read from the DAC, which are both acknowledged by the master as shown in . A stop condition follows. Figure 51

SDA

START BY

MASTER

SCL

CONTINUED)

SDA

(CONTINUED)

191

DB15 DB14 DB13 DB12 DB11 DB10 DB9

FRAME 1

SLAVE ADDRESS

MOST SIGNIFICANT

FRAME 3

DATA BYTE

R/W

ACK. BY

AD5629R/AD5669R

Figure 50. I

DB23A0A11101 0 DB22 DB21 DB20 DB19 DB18 DB17 DB16

FRAME 2

COMMAND BYTE

DB8

ACK. BY

AD5629R/AD5669R

Rev. A | Page 21 of 28

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

FRAME 4

LEAST SIGNIFICANT

2

C Write Operation

DATA BYTE

ACK. BY

AD5629R/AD5669R

9

ACK. BY

AD5629R/AD5669R

STOP BY MASTER

08819-048

AD5629R/AD5669R

(

SCL

SDA

CONTINUED)

(CONTINUED)

19 91

START BY

MASTER

SCL

SDA

191

DB15 DB14 DB13 DB12 DB11 DB10 DB9

FRAME 1

SLAVE ADDRESS

MOST SIGNIFICANT

FRAME 3

DATA BYTE

R/W

AD5629R/AD5669R

Figure 51. I

Table 8. Command Definitions

Command

C3 C2 C1 C0 Description

0 0 0 0 Write to Input Register n 0 0 0 1 Update DAC Register n 0 0 1 0

Write to Input Register n; update all

(software LDAC) 0 0 1 1 Write to and update DAC Channel n 0 1 0 0 Power down/power up DAC 0 1 0 1 Load clear code register 0 1 1 0

Load LDAC

register 0 1 1 1 Reset (power-on reset) 1 0 0 0 Set up internal REF register 1 0 0 1 Enable multiple byte mode 1 0 1 0 Reserved – – – – Reserved 1 1 1 1 Reserved

Table 9. Address Commands

Address (n)

A3 A2 A1 A0 Selected DAC Channel

0 0 0 0 DAC A 0 0 0 1 DAC B 0 0 1 0 DAC C 0 0 1 1 DAC D 0 1 0 0 DAC E 0 1 0 1 DAC F 0 1 1 0 DAC G 0 1 1 1 DAC H 1 1 1 1 All DACs

ACK. BY

DB8

DB23A0A11101 0 DB22 DB21 DB20 DB19 DB18 DB17 DB16

FRAME 2

COMMAND BYTE

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

ACK. BY MASTER

2

C Read Operation

FRAME 4

LEAST SI GNIFICANT

DATA BYT E

INPUT SHIFT REGISTER

The input shift register is 24 bits wide. Data is loaded into the device as a 24-bit word under the control of a serial clock input, SCL. The input register contents for this operation is shown in Figure 52 and Figure 53. The eight MSBs make up the command byte. DB23 to DB20 are the command bits, C3, C2, C1, and C0, that control the mode of operation of the device (see Ta b le 9 for details). The last four bits of the first byte are the address bits, A3, A2, A1, and A0, (see Tab l e 9 for details). The rest of the bits are the 16-/12-bit data-word.

The AD5669R data-word comprises the 16-bit input code (see Figure 52) while the AD5629R data word is comprised of 12bits followed by four don’t cares (see Figure 53).

MULTIPLE BYTE OPERATION

Multiple byte operation is supported on the AD5629R/ AD5669R. Command 1001 is reserved for multiple byte operation (see Tabl e 8 ) A 2-byte operation is useful for applications that require fast DAC updating and do not need to change the command byte. The S bit (DB22) in the command register can be set to 1 for the 2-byte mode of operation. For standard 3-byte and 4-byte operation, the S bit (DB22) in the command byte should be set to 0.

ACK. BY MASTER

9

STOP BY

NO ACK.

MASTER

08819-049

Rev. A | Page 22 of 28

AD5629R/AD5669R

INTERNAL REFERENCE REGISTER

The internal reference is available on all versions. The on-board reference is off at power-up by default. The on-board reference can be turned off or on by a user-programmable internal REF register by setting Bit DB0 high or low (see Tabl e 1 0 ). DB1 selects the internal reference value. Command 1000 is reserved for setting the internal REF register (see Tab le 8 ). Tab l e 1 1 shows how the state of the bits in the input shift register corresponds to the mode of operation of the device.

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

C3 C2 C1 C0 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

POWER-ON RESET

The AD5629R/AD5669R contain a power-on reset circuit that controls the output voltage during power-up. The AD5629R/ AD5669R DAC output powers up to 0 V and the AD5669R-3 DAC output powers up to midscale. The output remains powered up at this level until a valid write sequence is made to the DAC. This is useful in applications where it is important to know the state of the output of the DAC while it is in the process of powering up. There is also a software executable reset function that resets the DAC to the power-on reset code. Command 0111 is reserved for this reset function (see Ta b le 8 ). Any events on ignored.

LDAC

or

CLR

during power-on reset are

COMMAND

COMMAND BYTE DATA HIGH BYTE DATA LOW BYTE

DAC ADDRESS DAC DATA DAC DATA

Figure 52. AD5669R Input Register Contents

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

C3 C2 C1 C0 A3 A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X

COMMAND

COMMAND BYTE DAT A HIGH BYTE DATA LOW BYTE

DAC ADDRESS DAC DATA DAC DATA

Figure 53. AD5629R Input Register Contents

08819-050

08819-052

Rev. A | Page 23 of 28

AD5629R/AD5669R

POWER-DOWN MODES

The AD5629R/AD5669R contain four separate modes of operation. Command 0100 is reserved for the power-down function (see Tabl e 8 ). These modes are software-programmable by setting two bits, Bit DB9 and Bit DB8, in the control register.

Tabl e 1 2 shows how the state of the bits corresponds to the mode of operation of the device. Any or all DACs (DAC H to DAC A) can be powered down to the selected mode by setting the corresponding eight bits (DB7 to DB0) to 1. See Tab l e 1 3 for the contents of the input shift register during power-down/powerup operation.

When both bits are set to 0, the part works normally with its normal power consumption of 1.3 mA at 5 V. However, for the three power-down modes, the supply current falls to 0.4 μA at 5 V (0.2 μA at 3 V). Not only does the supply current fall, but the output stage is also internally switched from the output of the amplifier to a resistor network of known values. This has the advantage that the output impedance of the part is known while the part is in power-down mode. There are three different options. The output is connected internally to GND through either a 1 kΩ or a 100 kΩ resistor, or it is left open-circuited (three-state). The output stage is illustrated in Figure 54.

RESISTOR

STRING DAC

Figure 54. Output Stage During Power-Down

AMPLIFIER

POWER-DOWN

CIRCUITRY

RESISTOR NETWORK

V

OUT

08819-051

The bias generator of the selected DAC(s), output amplifier, resistor string, and other associated linear circuitry is shut down when the power-down mode is activated. The internal reference is powered down only when all channels are powered down. However, the contents of the DAC register are unaffected when in power-down. The time to exit power-down is typically 4 μs

= 5 V and for VDD = 3 V.

for V

DD

Any combination of DACs can be powered up by setting PD1 and PD0 to 0 (normal operation). The output powers up to the

LDAC

value in the input register ( DAC register before powering down (

low) or to the value in the

LDAC

high).

CLEAR CODE REGISTER

The AD5629R/AD5669R have a hardware is an asynchronous clear input. The sensitive. Bringing the

CLR

line low clears the contents of the

input register and the DAC registers to the data contained in

CLR

the user-configurable

register and sets the analog outputs accordingly. This function can be used in system calibration to load zero scale, midscale, or full scale to all channels together. These clear code values are user-programmable by setting two bits, Bit

CLR

DB1 and Bit DB0, in the

control register (see ). The default setting clears the outputs to 0 V. Command 0101 is reserved for loading the clear code register (see ).

The part exits clear code mode at the end of the next valid write

CLR

to the part. If

is activated during a write sequence, the write

is aborted.

CLR

The

pulse activation time (the falling edge of the output starts to change) is typically 280 ns. However, if outside the DAC linear region, it typically takes 520 ns after executing

CLR

for the output to start changing (see ). Figure 43

See Tab le 1 4 for the contents of the input shift register during the loading clear code register operation.

CLR

pin that

CLR

input is falling edge

Tabl e 1 5

Table 8

CLR

to when

Table 10. Internal Reference Register

Internal REF Register (DB0) Action 0 Reference off (default) 1 Reference on

Table 11. 32-Bit Input Shift Register Contents for Reference Set-Up Command

MSB DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 to DB1 DB0

1 0 0 0 X X X X X 1/0

Command bits (C3 to C0) Address bits (A3 to A0)—don’t cares Don’t cares Internal REF on/off

Rev. A | Page 24 of 28

LSB

AD5629R/AD5669R

Table 12. Power-Down Modes of Operation

DB9 DB8 Operating Mode

0 0 Normal operation Power-down modes 0 1 1 kΩ to GND 1 0 100 kΩ to GND 1 1 Three-state

Table 13. 32-Bit Input Shift Register Contents for Power-Down/Power-Up Function

MSB LSB DB23 DB22 DB21 DB20 DB19 to DB16 DB15 to DB10 DB9 DB8 DB7 to DB1 DB0

0 1 0 0 X X PD1 PD0 DAC H to DAC B DAC A

Command bits (C3 to C0) Address bits (A3 to A0)—

don’t cares

Table 14. 32-Bit Input Shift Register Contents for Clear Code Function

MSB DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 to DB2 DB1 DB0

0 1 0 1 X X X X X CR1 CR0

Command bits (C3 to C0) Address bits (A3 to A0)—don’t cares Don’t cares Clear code register

Table 15. Clear Code Register

Clear Code Register DB1 DB0 CR1 CR0 Clears to Code

0 0 0x0000 0 1 0x8000 1 0 0xFFFF 1 1 No operation

Don’t cares Power-

down mode

Power-down/power-up channel selection—

set bit to 1 to select

LSB

Rev. A | Page 25 of 28

AD5629R/AD5669R

LDAC FUNCTION

The outputs of all DACs can be updated simultaneously using

LDAC

the hardware

Synchronous

The DAC registers are updated after new data is read in. can be permanently low or pulsed as in . Figure 2

Asynchronous

The outputs are not updated at the same time that the input registers are written to. When registers are updated with the contents of the input register.

Alternatively, the outputs of all DACs can be updated simultaneously using the software Register n and updating all DAC registers. Command 0011 is reserved for this software

LDAC

An

register gives the user extra flexibility and control over the hardware to 0 for a DAC channel means that this channel’s update is

controlled by the

updates synchronously; that is, the DAC register is updated after new data is read, regardless of the state of the It effectively sees the

LDAC

for the

This flexibility is useful in applications where the user wants to simultaneously update select channels while the rest of the channels are synchronously updating. Writing to the DAC using command 0110 loads the 8-bit DB0). The default for each channel is 0, that is, the works normally. Setting the bits to 1 means the DAC channel is updated regardless of the state of the for the contents of the input shift register during the load register mode of operation.

pin.

LDAC

goes low, the DAC

LDAC

function by writing to Input

LDAC

function.

LDAC

pin. Setting the

pin. If this bit is set to 1, this channel

LDAC

pin as being tied low. See

register mode of operation.

LDAC

bit register

LDAC

Tabl e 1 6

register (DB7 to

LDAC

pin. See

Table 1 7

LDAC

pin.

LDAC

POWER SUPPLY BYPASSING AND GROUNDING

When accuracy is important in a circuit, it is helpful to carefully consider the power supply and ground return layout on the board. The printed circuit board containing the AD5629R/AD5669R should have separate analog and digital sections. If the AD5629R/ AD5669R are in a system where other devices require an AGND-to-DGND connection, the connection should be made at one point only. This ground point should be as close as possible to the AD5629R/AD5669R.

The power supply to the AD5629R/AD5669R should be bypassed with 10 μF and 0.1 μF capacitors. The capacitors should be as physically close as possible to the device, with the

0.1 μF capacitor ideally right up against the device. The 10 μF capacitors are the tantalum bead type. It is important that the

0.1 μF capacitor have low effective series resistance (ESR) and low effective series inductance (ESI), such as is typical of common ceramic types of capacitors. This 0.1 μF capacitor provides a low impedance path to ground for high frequencies caused by transient currents due to internal logic switching.

The power supply line should have as large a trace as possible to provide a low impedance path and reduce glitch effects on the supply line. Clocks and other fast switching digital signals should be shielded from other parts of the board by digital ground. Avoid crossover of digital and analog signals if possible. When traces cross on opposite sides of the board, ensure that they run at right angles to each other to reduce feedthrough effects through the board. The best board layout technique is the microstrip technique, where the component side of the board is dedicated to the ground plane only and the signal traces are placed on the solder side. However, this is not always possible with a 2-layer board.

Table 16.

LDAC

0 1/0 1 X—don’t care

Table 17. 32-Bit Input Shift Register Contents for

MSB LSB

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16

0 1 1 0 X X X X X DAC H DAC G DAC F DAC E DAC D DAC C DAC B DAC A

LDAC

Register

Load DAC Register

Bits (DB7 to DB0)

LDAC

Operation

LDAC

Determined by LDAC DAC channels update, overriding the LDAC

LDAC

Command bits (C3 to C0) Address bits (A3 to A0)—

don’t cares

pin.

pin. DAC channels see LDAC as 0.

Register Function

DB15 to DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Don’t cares

Setting

LDAC

bit to 1 overrides

LDAC

Rev. A | Page 26 of 28

AD5629R/AD5669R

S

OUTLINE DIMENSIONS

PIN 1

INDICATOR

0.80

0.75

0.70

EATING

PLANE

4.10

4.00 SQ

3.90

0.65

BSC

0.45

0.40

0.35

0.05 MAX

0.02 NOM

0.20 REF

0.35

0.30

0.25

13

12

9

8

BOTTOM VIEWTOP VIEW

COPLANARITY

0.08

N

1

P

I

D

C

I

N

I

16

EXPOSED

1

PAD

4

5

FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.

2.70

2.60 SQ

2.50

0.20 MIN

R

O

A

T

COMPLIANT

TO

JEDEC STANDARDS MO-220-WGGC.

08-16-2010-C

Figure 55. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]

4 mm × 4 mm Body, Very Very Thin Quad

(CP-16-17)

Dimensions shown in millimeters

5.10

5.00

4.90

0.15

0.05

4.50

4.40

4.30

PIN 1

16

0.65

BSC

COPLANARITY

COMPLIANT TO JEDEC S T ANDARDS MO-153-AB

0.10

0.30

0.19

9

81

1.20 MAX

SEATING PLANE

6.40

BSC

0.20

0.09 8°

0°

0.75

0.60

0.45

Figure 56. 16-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-16)

Dimensions shown in millimeters

Rev. A | Page 27 of 28

AD5629R/AD5669R

ORDERING GUIDE

Package

Model1 Temperature Range Package Description

AD5629RARUZ-1 −40°C to +105°C 16-Lead TSSOP RU-16 Zero ±4 LSB INL 1.25 V AD5629RARUZ-1-RL7 −40°C to +105°C 16-Lead TSSOP RU-16 Zero ±4 LSB INL 1.25 V AD5629RBRUZ-2 −40°C to +105°C 16-Lead TSSOP RU-16 Zero ±1 LSB INL 2.5 V AD5629RBRUZ-2-RL7 −40°C to +105°C 16-Lead TSSOP RU-16 Zero ±1 LSB INL 2.5 V AD5629RACPZ-2-RL7 −40°C to +105°C 16-Lead LFCSP_WQ CP-16-17 Zero ±4 LSB INL 2.5 V AD5629RACPZ-3-RL7 −40°C to +105°C 16-Lead LFCSP_WQ CP-16-17 Midscale ±4 LSB INL 2.5 V AD5629RBCPZ-1-RL7 −40°C to +105°C 16-Lead LFCSP_WQ CP-16-17 Zero ±1 LSB INL 1.25 V AD5629RBCPZ-2-RL7 −40°C to +105°C 16-Lead LFCSP_WQ CP-16-17 Zero ±1 LSB INL 2.5 V AD5669RARUZ-1 −40°C to +105°C 16-Lead TSSOP RU-16 Zero ±32 LSB INL 1.25 V AD5669RARUZ-1-RL7 −40°C to +105°C 16-Lead TSSOP RU-16 Zero ±32 LSB INL 1.25 V AD5669RBRUZ-2 −40°C to +105°C 16-Lead TSSOP RU-16 Zero ±16 LSB INL 2.5 V AD5669RBRUZ-2-RL7 −40°C to +105°C 16-Lead TSSOP RU-16 Zero ±16 LSB INL 2.5 V AD5669RACPZ-2-RL7 −40°C to +105°C 16-Lead LFCSP_WQ CP-16-17 Zero ±32 LSB INL 2.5 V AD5669RACPZ-3-RL7 −40°C to +105°C 16-Lead LFCSP_WQ CP-16-17 Midscale ±32 LSB INL 2.5 V AD5669RBCPZ-1-RL7 −40°C to +105°C 16-Lead LFCSP_WQ CP-16-17 Zero ±16 LSB INL 1.25 V AD5669RBCPZ-2-RL7 −40°C to +105°C 16-Lead LFCSP_WQ CP-16-17 Zero ±16 LSB INL 2.5 V AD5669RBCPZ-1500R7 −40°C to +105°C 16-Lead LFCSP_WQ CP-16-17 Zero ±16 LSB INL 1.25 V AD5669RBCPZ-2500R7 −40°C to +105°C 16-Lead LFCSP_WQ CP-16-17 Zero ±16 LSB INL 2.5 V EVAL-AD5629REBRZ Evaluation Board EVAL-AD5669REBRZ Evaluation Board

1

Z = RoHS Compliant Part.

Option

Power-On Reset to Code Accuracy

Internal Reference

I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).

Rev. A | Page 28 of 28

ANALOG DEVICES AD5669R Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

PRODUCT HIGHLIGHTS

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

AC CHARACTERISTICS

I2C TIMING CHARACTERISTICS

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

TERMINOLOGY

THEORY OF OPERATION

DIGITAL-TO-ANALOG CONVERTER (DAC) SECTION

RESISTOR STRING

INTERNAL REFERENCE

OUTPUT AMPLIFIER

SERIAL INTERFACE

WRITE OPERATION

READ OPERATION

INPUT SHIFT REGISTER

MULTIPLE BYTE OPERATION

INTERNAL REFERENCE REGISTER

POWER-ON RESET

POWER-DOWN MODES

CLEAR CODE REGISTER

LDAC FUNCTION

POWER SUPPLY BYPASSING AND GROUNDING

OUTLINE DIMENSIONS

ORDERING GUIDE