ANALOG DEVICES AD5668-EP Service Manual

Octal, 16-Bit DAC with 5 ppm/°C

V

/

On-Chip Reference in 14-Lead TSSOP

FEATURES

Enhanced product features

Supports defense and aerospace applications (AQEC)
Military temperature range (−55°C to +125°C)
Controlled manufacturing baseline
One assembly/test site
One fabrication site
Enhanced product change notification

Qualification data available on request
Low power, smallest pin-compatible octal DAC: 16 bits
16-lead TSSOP
On-chip 1.25 V, 5 ppm/°C reference
Power down to 400 nA at 5 V, 200 nA at 3 V

2.7 V to 5.5 V power supply
Guaranteed monotonic by design
Power-on reset to zero scale or midscale
3 power-down functions
Hardware

function to programmable code

CLR

LDAC

and

Rail-to-rail operation

APPLICATIONS

Process control
Data acquisition systems
Portable battery-powered instruments

GENERAL DESCRIPTION

The AD5668-EP is a low power, octal, 16-bit, buffered voltage­output digital-to-analog converter (DAC). It operates from a
single 2.7 V to 5.5 V supply and is guaranteed monotonic
by design.

The AD5668-EP has an on-chip reference with an internal gain
of 2. The AD5668-EP has a 1.25 V, 5 ppm/°C reference, giving a
full-scale output range of 2.5 V. The on-board reference is off at
power-up, allowing the use of an external reference, and the
internal reference is enabled via a software write.

The part incorporates a power-on-reset circuit that ensures that
the DAC output powers up to 0 V and remains powered up at this
level until a valid write takes place. The part contains a power­down feature that reduces the current consumption of the device
to 400 nA at 5 V and provides software-selectable output loads
while in power-down mode for any or all DAC channels. The
outputs of all DACs can be updated simultaneously using the

function, with the added functionality of user-selectable

LDAC

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

override function

LDAC

AD5668-EP

FUNCTIONAL BLOCK DIAGRAM

V

DD

AD5668-EP

DAC

REGISTER

DAC

REGISTER

DAC

REGISTER

DAC

REGISTER

DAC

REGISTER

DAC

REGISTER

DAC

REGISTER

DAC

REGISTER

SCLK

SYNC

DIN

1

RU-16 PACKAGE ONLY

LDAC

INTERFACE

LOGIC

1

LDAC

CLR

INPUT

REGISTER

INPUT

REGISTER

INPUT

REGISTER

INPUT

REGISTER

INPUT

REGISTER

INPUT

REGISTER

INPUT

REGISTER

INPUT

REGISTER

POWER-ON

RESET

1

Figure 1.

DAC channels to simultaneously update. There is also an
asynchronous

that updates all DACs to a user-

CLR

programmable code—zero scale, midscale, or full scale.

The AD5668-EP uses a versatile 3-wire serial interface that
operates at clock rates up to 50 MHz and is compatible with
standard SPI, QSPI, MICROWIRE, and DSP interface standards.

Additional application and technical information can be found
in the AD5668 data sheet.

PRODUCT HIGHLIGHTS

1. Octal, 16-bit DAC.

2. On-chip 1.25 V/2.5 V, 5 ppm/°C reference.

3. Available in 16-lead TSSOP.

4. Power-on reset to 0 V or midscale.

5. Power-down capability. When powered down, the DAC

typically consumes 200 nA at 3 V and 400 nA at 5 V.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2010 Analog Devices, Inc. All rights reserved.

REFIN

V

STRING

DAC A

STRING

DAC B

STRING

DAC C

STRING

DAC D

STRING

DAC E

STRING

DAC F

STRING

DAC G

STRING

DAC H

REFOUT

1.25V/2.5V
REF

BUFFER

BUFFER

BUFFER

BUFFER

BUFFER

BUFFER

BUFFER

BUFFER

POWER-DOW N

LOGIC

GND

V

A

OUT

B

V

OUT

V

C

OUT

V

D

OUT

E

V

OUT

V

F

OUT

G

V

OUT

H

V

OUT

09463-001

AD5668-EP

TABLE OF CONTENTS

Features .............................................................................................. 1

Timing Characteristics .................................................................5

Applications ....................................................................................... 1 

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

AC Characteristics ........................................................................ 4

REVISION HISTORY

10/10—Revision 0: Initial Version

Absolute Maximum Ratings ............................................................6

ESD Caution...................................................................................6

Pin Configurations and Function Descriptions ............................7

Typical Performance Characteristics ..............................................8

Outline Dimensions ....................................................................... 14

Ordering Guide .......................................................................... 14

Rev. 0 | Page 2 of 16

AD5668-EP

SPECIFICATIONS

VDD = 4.5 V to 5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, V
Temperature range is −55°C to +125°C, typical at +25°C.

Table 1.

Parameter Min Typ Max Unit Conditions/Comments

STATIC PERFORMANCE

1

Resolution 16 Bits
Relative Accuracy ±8 ±21 LSB See Figure 4
Differential Nonlinearity ±1 LSB Guaranteed monotonic by design (see Figure 7)
Zero-Code Error 1 14 mV All 0s loaded to DAC register (see Figure 9)
Zero-Code Error Drift ±2 µV/°C
Full-Scale Error −0.2 −1 % FSR All 1s loaded to DAC register (see Figure 10)
Gain Error ±1 % FSR
Gain Temperature Coefficient ±2.5 ppm Of FSR/°C
Offset Error ±1 ±14 mV
DC Power Supply Rejection Ratio –80 dB VDD ± 10%
DC Crosstalk (External Reference) 10 µV Due to full-scale output change, RL = 2 kΩ to GND or VDD
5 µV/mA Due to load current change
10 µV Due to powering down (per channel)
DC Crosstalk (Internal Reference) 25 µV Due to full-scale output change, RL = 2 kΩ to GND or VDD
10 µV/mA Due to load current change

OUTPUT CHARACTERISTICS2

Output Voltage Range 0 VDD V
Capacitive Load Stability 2 nF RL = ∞
10 nF RL = 2 kΩ
DC Output Impedance 0.5 Ω
Short-Circuit Current 30 mA VDD = 5 V
Power-Up Time 4 µs Coming out of power-down mode, VDD = 5 V

REFERENCE INPUTS

Reference Current 40 55 µA V
Reference Input Range 0 VDD V
Reference Input Impedance 14.6 kΩ

REFERENCE OUTPUT

Output Voltage 1.247 1.253 V At ambient
Reference Temperature Coefficient2 ±5 ppm/°C
Reference Output Impedance 7.5 kΩ

LOGIC INPUTS2

Input Current ±3 µA All digital inputs
Input Low Voltage, V
Input High Voltage, V

0.8 V VDD = 5 V

INL

2 V VDD = 5 V

INH

Pin Capacitance 3 pF

POWER REQUIREMENTS

VDD 4.5 5.5 V All digital inputs at 0 or VDD, DAC active, excludes load current
IDD (Normal Mode)3 V

VDD = 4.5 V to 5.5 V 1.3 1.8 mA Internal reference off
VDD = 4.5 V to 5.5 V 2 2.6 mA Internal reference on

IDD (All Power-Down Modes)4

VDD = 4.5 V to 5.5 V 0.4 1 µA VIH = VDD and VIL = GND

1

Linearity calculated using a reduced code range of AD5668 (Code 512 to 65,024). Output unloaded.

2

Guaranteed by design and characterization; not production tested.

3

Interface inactive. All DACs active. DAC outputs unloaded.

4

All eight DACs powered down.

= VDD. All specifications T

REFIN

= VDD = 5.5 V (per DAC channel)

REF

= VDD and VIL = GND

IH

MIN

to T

, unless otherwise noted.

MAX

Rev. 0 | Page 3 of 16

AD5668-EP

AC CHARACTERISTICS

VDD = 2.7 V to 5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, V
Temperature range is −55°C to +125°C, typical at +25°C.

Table 2.

Parameter

1

Min Typ Max Unit Conditions/Comments

Output Voltage Settling Time 6 10 µs ¼ to ¾ scale settling to ±2 LSB
Slew Rate 1.5 V/µs
Digital-to-Analog Glitch Impulse 4 nV-sec 1 LSB change around major carry (see Figure 24)
Digital Feedthrough 0.1 nV-sec
Reference Feedthrough −90 dB V
Digital Crosstalk 0.5 nV-sec
Analog Crosstalk 2.5 nV-sec
DAC-to-DAC Crosstalk 3 nV-sec
Multiplying Bandwidth 340 kHz V
Total Harmonic Distortion −80 dB V
Output Noise Spectral Density 120 nV/√Hz DAC code = 0x8400, 1 kHz
100 nV/√Hz DAC code = 0x8400, 10 kHz
Output Noise 15 V p-p 0.1 Hz to 10 Hz

1

Guaranteed by design and characterization; not production tested.

= VDD. All specifications T

REFIN

= 2 V ± 0.1 V p-p, frequency = 10 Hz to 20 MHz

REF

= 2 V ± 0.2 V p-p

REF

= 2 V ± 0.1 V p-p, frequency = 10 kHz

REF

MIN

to T

, unless otherwise noted.

MAX

Rev. 0 | Page 4 of 16

AD5668-EP

TIMING CHARACTERISTICS

All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 2.
V

= 2.7 V to 5.5 V. All specifications T

DD

Table 3.

Limit at T

MIN

, T

Parameter VDD = 2.7 V to 5.5 V Unit Conditions/Comments

1

t

20 ns min SCLK cycle time

1

t2 8 ns min SCLK high time
t3 8 ns min SCLK low time
t4 13 ns min

t5 4 ns min Data setup time
t6 4 ns min Data hold time
t7 0 ns min

t8 15 ns min
t9 13 ns min
t10 0 ns min
t11 10 ns min
t12 15 ns min
t13 5 ns min
t14 0 ns min
t15 300 ns typ

1

Maximum SCLK frequency is 50 MHz at VDD = 2.7 V to 5.5 V. Guaranteed by design and characterization; not production tested.

t

SCLK

t

8

SYNC

DIN

1

LDAC

to T

MIN

MAX

, unless otherwise noted.

MAX

to SCLK falling edge set-up time

SYNC

SCLK falling edge to SYNC
Minimum SYNC

rising edge to SCLK fall ignore

SYNC
SCLK falling edge to SYNC

pulse width low

LDAC
SCLK falling edge to LDAC

pulse width low

CLR
SCLK falling edge to LDAC

pulse activation time

CLR

10

t

4

t

6

t

5

DB31

t

1

t

t

3

2

DB0

t

9

t

7

t

11

t

14

rising edge

high time

fall ignore

rising edge

falling edge

t

12

2

LDAC

t

CLR

V

OUT

1

ASYNCHRONOUS LDAC UPDAT E MODE.

2

SYNCHRONOUS LDAC UPDAT E MODE.

13

t

15

09463-002

Figure 2. Serial Write Operation

Rev. 0 | Page 5 of 16