Analog Devices AD5662 Datasheet

2.7 V to 5.5 V, 250 µA, Rail-to-Rail Output

FEATURES

Low power (250 µA @ 5 V) single 16-bit nanoDAC
12-bit accuracy guaranteed
Tiny 8-lead SOT-23/MSOP package
Power-down to 480 nA @ 5 V, 100 nA @ 3 V
Power-on reset to zero scale/midscale

2.7 V to 5.5 V power supply
Guaranteed 16-bit monotonic by design
3 power-down functions
Serial interface with Schmitt-triggered inputs
Rail-to-rail operation
SYNC interrupt facility
Temperature range −40°C to +125°C

APPLICATIONS

Process control
Data acquisition systems
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators

GENERAL DESCRIPTION

The AD5662, a member of the nanoDAC family, is a low power,
single, 16-bit buffered voltage-out DAC that operates from a
single 2.7 V to 5.5 V supply and is guaranteed monotonic by
design.

16-Bit

nano

DACTM in a SOT-23

AD5662

FUNCTIONAL BLOCK DIAGRAM

V

REF

POWER-ON

RESET

DAC

REGISTER

INPUT

CONTROL

LOGIC

SYNC SCLK DIN

REF(+)

16-BIT

DAC

The AD5662 uses a versatile 3-wire serial interface that operates
at clock rates up to 30 MHz, and is compatible with standard
SPI®, QSPI™, MICROWIRE™, and DSP interface standards.

V

DD

GND

OUTPUT
BUFFER

POWER-DOWN

CONTROL LOGIC

Figure 1.

AD5662

RESISTOR
NETWORK

V

FB

V

OUT

04777-001

The AD5662 requires an external reference voltage to set the
output range of the DAC. The part incorporates a power-on
reset circuit that ensures the DAC output powers up to 0 V
(AD5662x-1) or to midscale (AD5662x-2), and remains there
until a valid write takes place. The part contains a power-down
feature that reduces the current consumption of the device to
480 nA at 5 V and provides software-selectable output loads
while in power-down mode.

The low power consumption of this part in normal operation
makes it ideally suited to portable battery-operated equipment.
The power consumption is 0.75 mW at 5 V, going down to

2.4 µW in power-down mode.

The AD5662’s on-chip precision output amplifier allows rail-to­rail output swing to be achieved. For remote sensing applications,
the output amplifier’s inverting input is available to the user.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

PRODUCT HIGHLIGHTS

1. 16-bit DAC—12-bit accuracy guaranteed.

2. Available in 8-lead SOT-23 and 8-lead MSOP packages.

3. Low power. Typically consumes 0.42 mW at 3 V and

0.75 mW at 5 V.

4. Power-on reset to zero scale or to midscale.

5. 10 µs max settling time.

RELATED DEVICES

Part No. Description

AD5620/AD5640/AD5660

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]
Fax: [phone] © 2005 Analog Devices, Inc. All rights reserved.

www.analog.com

3 V/5 V 12-/14-/16-bit DAC with
internal reference in SOT-23

AD5662

TABLE OF CONTENTS

Specifications..................................................................................... 3

Timing Characteristics..................................................................... 5

Absolute Maximum Ratings............................................................ 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Description .............................. 7

Typical Performance Characteristics ............................................. 8

Te r mi n ol o g y .................................................................................... 13

Theory of Operation ...................................................................... 14

DAC Section ................................................................................ 14

Resistor String............................................................................. 14

Output Amplifier........................................................................ 14

Serial Interface............................................................................ 14

Input Shift Register..................................................................... 15

Interrupt........................................................................... 15

SYNC

Power-On Reset .......................................................................... 15

Power-Down Modes .................................................................. 16

Microprocessor Interfacing....................................................... 16

Applications..................................................................................... 18

Choosing a Reference for the AD5662.................................... 18

Using a Reference as a Power Supply for the AD5662 .......... 18

Bipolar Operation Using the AD5662..................................... 19

Using the AD5662 as an Isolated, Programmable, 4-20 mA
Process Controller

Using AD5662 with a Galvanically Isolated Interface........... 20

Power Supply Bypassing and Grounding................................ 20

Outline Dimensions ....................................................................... 21

Ordering Guide .......................................................................... 22

...................................................................... 19

REVISION HISTORY

1/05—Revision 0: Initial Version

Rev. 0 | Page 2 of 24

AD5662

SPECIFICATIONS

VDD = 2.7 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; V

Table 1.

A Grade B Grade Y Version
Parameter Min Typ Max Min Typ Max Unit Conditions/Comments

STATIC PERFORMANCE

2

Resolution 16 16 Bits
Relative Accuracy ±8 ±32 ±8 ±16 LSB See Figure 4
Differential Nonlinearity ±1 ±1 LSB

Zero Code Error 2 10 2 10 mV All 0s loaded to DAC register
Full-Scale Error −0.2 −1 −0.2 −1 % FSR All 1s loaded to DAC register
Offset Error ±10 ±10 mV
Gain Error ±1.5 ±1.5 % FSR
Zero Code Error Drift
Gain Temperature Coefficient

3

±2 ±2 µV/°C

3

±2.5 ±2.5 ppm Of FSR/°C

DC Power Supply Rejection Ratio3 −100 −100 dB DAC code = midscale; VDD = 5 V/3 V ±10%

OUTPUT CHARACTERISTICS

Output Voltage Range 0 V

3

DD

Output Voltage Settling Time 8 10 8 10 µs

Slew Rate 1.5 1.5 V/µs ¼ to ¾ scale
Capacitive Load Stability 2 2 nF RL = ∞
10 10 nF RL = 2 kΩ
Output Noise Spectral Density
Output Noise (0.1 Hz to 10 Hz)

4

100 100 nV/√Hz DAC code = midscale,10 kHz

4

10 10 µV p-p DAC code = midscale
Total Harmonic Distortion (THD)4 −80 −80 dB V
Digital-to-Analog Glitch Impulse 5 5 nV-s 1 LSB change around major carry
Digital Feedthrough 0.1 0.1 nV-s
DC Output Impedance 0.5 0.5 Ω
Short-Circuit Current

4

30 30 mA VDD = 5 V, 3 V
Power-Up Time 4 4 µs

REFERENCE INPUT

3

Reference Current 40 75 40 75 µA V
30 50 30 50 µA V
Reference Input Range

5

0.75 V

DD

Reference Input Impedance 125 125 kΩ

LOGIC INPUTS3

Input Current ±2 ±2 µA All digital inputs
V

, Input Low Voltage 0.8 0.8 V VDD = 5 V, 3 V

INL

V

, Input High Voltage 2 2 V VDD = 5 V, 3 V

INH

Pin Capacitance 3 3 pF

= VDD; all specifications T

REF

0 V

0.75 V

DD

DD

to T

MIN

MAX

Guaranteed monotonic by design
See Figure 5

V

¼ to ¾ scale change settling to ±2 LSB

= 2 kΩ; 0 pF < CL < 200 pF

R

L

= 2 V ± 300 mV p-p, f = 5 kHz

REF

Coming out of power-down mode

= 5 V, 3 V

V

DD

= VDD = 5 V

REF

= VDD = 3.6 V

REF

V

, unless otherwise noted.

1

Rev. 0 | Page 3 of 24

AD5662

A Grade B Grade Y Version

1

Parameter Min Typ Max Min Typ Max Unit Conditions/Comments

POWER REQUIREMENTS

VDD 2.7 5.5 2.7 5.5 V All digital inputs at 0 V or V

DD

IDD (Normal Mode) DAC active and excluding load current
VDD = 4.5 V to 5.5 V 150 250 150 250 µA VIH = VDD and VIL = GND
VDD = 2.7 V to 3.6 V 140 225 140 225 µA VIH = VDD and VIL = GND

IDD (All Power-Down Modes)

VDD = 4.5 V to 5.5 V 0.48 1 0.48 1 µA VIH = VDD and VIL = GND
VDD = 2.7 V to 3.6 V 0.1 0.375 0.1 0.375 µA VIH = VDD and VIL = GND

POWER EFFICIENCY

I

OUT/IDD

1

Temperature range is as follows: Y version: −40°C to +125°C, typical at +25°C.

2

DC specifications tested with the outputs unloaded, unless otherwise stated. Linearity calculated using a reduced code range of 512 to 65024.

3

Guaranteed by design and characterization; not production tested.

4

Output unloaded.

5

Reference input range at ambient where ±1 LSB max DNL specification is achievable.

90 90 % I

= 2 mA. VDD = 5 V

LOAD

Rev. 0 | Page 4 of 24

AD5662

TIMING CHARACTERISTICS

All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 2.

= 2.7 V to 5.5 V; all specifications T

V

DD

Table 2.

Limit at T
Parameter VDD = 2.7 V to 3.6 V VDD = 3.6 V to 5.5 V Unit Conditions/Comments

1

t

1

t

2

t

3

t

4

t

5

t

6

t

7

t

8

t

9

t

10

1

Maximum SCLK frequency is 30 MHz at VDD = 3.6 V to 5.5 V, and 20 MHz at VDD = 2.7 V to 3.6 V.

50 33 ns min SCLK cycle time
13 13 ns min SCLK high time
13 13 ns min SCLK low time
13 13 ns min

5 5 ns min Data setup time

4.5 4.5 ns min Data hold time
0 0 ns min

50 33 ns min
13 13 ns min
0 0 ns min

MIN

to T

, unless otherwise noted.

MAX

, T

MIN

MAX

SYNC to SCLK falling edge setup time

SCLK falling edge to
Minimum

SYNC high time
SYNC rising edge to SCLK fall ignore
SCLK falling edge to

SYNC rising edge

SYNC fall ignore

t

SCLK

SYNC

DIN

10

t

8

DB23

t

4

t

6

t

5

t

1

t

t

3

2

t

DB0

t

9

7

04777-002

Figure 2. Serial Write Operation

Rev. 0 | Page 5 of 24

AD5662

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 3.

Parameter Rating

VDD to GND −0.3 V to +7 V
V

to GND −0.3 V to VDD + 0.3 V

OUT

VFB to GND −0.3 V to VDD + 0.3 V
V

to GND −0.3 V to VDD + 0.3 V

REF

Digital Input Voltage to GND −0.3 V to VDD + 0.3 V
Operating Temperature Range

Industrial (Y Version) −40°C to +125°C
Storage Temperature Range −65°C to +150°C
Junction Temperature (TJ max) 150°C

Power Dissipation (TJ max − TA)/θ
SOT-23 Package (4-Layer Board)

θJA Thermal Impedance 119°C/W
MSOP Package (4-Layer Board)

θJA Thermal Impedance 141°C/W

θJC Thermal Impedance 44°C/W
Reflow Soldering Peak Temperature

SnPb 240°C

Pb-free 260°C
ESD 2 kV

JA

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. 0 | Page 6 of 24

AD5662

V

PIN CONFIGURATION AND FUNCTION DESCRIPTION

V

V

REF

V

OUT

DD

FB

1

AD5662

2

TOP VIEW

3

(Not to Scale)

4

8

7

6

5

GND
DIN
SCLK
SYNC

04777-003

Figure 3. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Function

1 VDD Power Supply Input. These parts can be operated from 2.7 V to 5.5 V. VDD should be decoupled to GND.
2 V
3 VFB Feedback Connection for the Output Amplifier. VFB should be connected to V
4 V
5

6 SCLK

Reference Voltage Input.

REF

for normal operation.

OUT

Analog Output Voltage from DAC. The output amplifier has rail-to-rail operation.

OUT

SYNC Level-Triggered Control Input (Active Low). This is the frame synchronization signal for the input data. When SYNC

goes low, it enables the input shift register, and data is transferred in on the falling edges of the following clocks.
The DAC is updated following the 24
rising edge of

SYNC acts as an interrupt and the write sequence is ignored by the DAC.

th

clock cycle unless SYNC is taken high before this edge, in which case the

Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can
be transferred at rates up to 30 MHz.

7 DIN

Serial Data Input. This device has a 24-bit shift register. Data is clocked into the register on the falling edge of the
serial clock input.

8 GND Ground Reference Point for All Circuitry on the Part.

Rev. 0 | Page 7 of 24

AD5662

TYPICAL PERFORMANCE CHARACTERISTICS

10

VDD = V

8

T

6
4
2

0

–2

INL ERROR (LSB)

–4

–6
–8

–10

0 5k 10k 15k 20k 25k 30k 35k 40k 45k 50k 55k 60k 65k

90

VDD = V
T

80

70

60

50

40

ERROR (LSB)

30

20

10

0

511 2051110511 30511 5051140511 60511

= 5V

REF

= 25°C

A

CODE

Figure 4. Typical INL Plot

Figure 5. Typical DNL Plot

= 5V

REF

= 25°C

A

CODES

Figure 6. Typical Total Unadjusted Error Plot

04777-011

04777-019

8

6

V

= V

= 5V

DD

4

2

0

ERROR (LSB)

–2

–4

–6

–8

–40 –20 40200 1008060 120

REF

MAX DNL

MIN DNL

TEMPERATURE (°C)

Figure 7. INL Error and DNL Error vs. Temperature

10

8

6

V

= 5V

DD

4

= 25°C

T

A

2

0

–2

ERROR (LSB)

–4

–6

–8

–10

0.75 1.25 1.75 2.25 4.253.753.252.75 4.75
V

(V)

REF

Figure 8. INL and DNL Error vs. V

MAX DNL

MIN DNL

REF

8

6

= 25°C

T

A

4

2

0

ERROR (LSB)

–2

–4

–6

–8

2.7 3.2 3.7 4.74.2 5.2
VDD (V)

MAX DNL

MIN DNL

Figure 9. INL and DNL Error vs. Supply

MAX INL

MIN INL

04777-036

MAX INL

MIN INL

04777-045

MAX INL

MIN INL

04777-041

Rev. 0 | Page 8 of 24