Octal, 12-/16-Bit DAC, SPI, 5 ppm/°C On-
AD5628/AD5668 Package Note
INTE RFA CE
LOGIC
INPU T
RE G IS TER
DIN
LD AC
GN D
V
OU T
H
V
DD
LD AC
V
RE FIN
/V
RE FO UT
SY NC
SC LK
AD5628/ AD5668
CL R
1.2 5V /2 .5 V
RE F
V
OU T
A
V
OU T
B
V
OU T
C
V
OU T
D
V
OU T
E
V
OU T
F
V
OU T
G
DA C
RE G IS TER
ST RING
DAC A
BU FFE R
INPU T
RE G IS TER
DA C
RE G IS TER
ST RING
DAC B
BU FFE R
INPU T
RE G IS TER
DA C
RE G IS TER
ST RING
DAC C
BU FFE R
INPU T
RE G IS TER
DA C
RE G IS TER
ST RING
DAC D
BU FFE R
INPU T
RE G IS TER
DA C
RE G IS TER
ST RING
DAC E
BU FFE R
INPU T
RE G IS TER
DA C
RE G IS TER
ST RING
DAC F
BU FFE R
INPU T
RE G IS TER
DA C
RE G IS TER
ST RING
DAC G
BU FFE R
INPU T
RE G IS TER
DA C
RE G IS TER
ST RING
DAC H
BU FFE R
PO W E R-DOW N
LOGIC
PO W E R-O N
RESET
05302-001
Preliminary Technical Data
FEATURES
Low power, pin-compatible octal DACs
AD5668: 16 bits
AD5628: 12 bits
AD5668/AD5628 in 16-lead LFCSP
On-chip 1.25 V/2.5 V, 5 ppm/°C reference
Power down to 400 nA @ 5 V, 200 nA @ 3 V
2.7 V to 5.5 V power supply
Guaranteed monotonic by design
Power-on reset to zero scale or midscale
3 power-down functions
Hardware
function to programmable code
CLR
Rail-to-rail operation
APPLICATIONS
Optical transceivers
Power Amp control
Data acquisition systems
Digital gain and offset adjustment
GENERAL DESCRIPTION
LDAC
and
override function
LDAC
Chip Reference in 4mm X 4mm LFCSP
FUNCTIONAL BLOCK DIAGRAM
Figure 1.
The AD5628/AD5668 devices are low power, octal,
12-/16-bit, buffered voltage-output DACs. All devices operate
from a single 2.7 V to 5.5 V supply and are guaranteed monotonic
by design.
The AD5628/AD5668 have an on-chip reference with an
internal gain of 2. The AD5628/AD5648/AD5668-1 have a 1.25
V 5 ppm/°C reference, giving a full-scale output range of 2.5 V;
the AD5628/AD5668-2, -3 have a 2.5 V 5 ppm/°C reference,
giving a full-scale output range of 5 V. T he on -board reference is
off at power-up, allowing the use of an external reference. The
internal reference is enabled via a software write.
The part incorporates a power-on reset circuit that ensures that the
DAC output powers up to 0 V (AD5628/AD5668-1, -2) or
midscale (AD5668-3) and remains powered up at this level until
a valid write takes place. The part contains a power-down feature
that reduces the current consumption of the device to 400 nA at
5 V and provides software-selectable output loads while in
power-down mode for any or all DAC channels.
Rev PrA
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responsi bility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
The outputs of all DACs can be updated simultaneously
using the
function, with the added functionality of user-
LDAC
selectable DAC channels to simultaneously update. There is also
an asynchronous
that updates all DACs to a user-
CLR
programmable code—zero scale, midscale, or full scale.
The AD5628/AD5668 utilize a versatile 3-wire serial interface
that operates at clock rates of up to 50 MHz and is compatible
with standard SPI®, QSPI™, MICROWIRE™, and DSP interface
standards. The on-chip precision output amplifier enables railto-rail output swing.
PRODUCT HIGHLIGHTS
1. Octal, 12-/16-bit DAC.
2. On-chip 1.25 V/2.5 V, 5 ppm/°C reference.
3. Available in 16-lead LFCSP.
4. Power-on reset to 0 V or midscale.
5. Power-down capability. When powered down, the DAC
typically consumes 200 nA at 3 V and 400 nA at 5 V.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113 © 2010 Analog Devices, Inc. All rights reserved.
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