Datasheet AD5627R, AD5647R, AD5667R Datasheet (ANALOG DEVICES)

Dual, 12-/14-/16-Bit nanoDACs® with

A

V

V

/

A

V

V

AD5627R/AD5647R/AD5667R, AD5627/AD5667

5 ppm/°C On-Chip Reference, I

FEATURES

Low power, smallest pin-compatible, dual nanoDACs
AD5627R/AD5647R/AD5667R

12-/14-/16-bit
On-chip 1.25 V/2.5 V, 5 ppm/°C reference

AD5627/AD5667

12-/16-bit
External reference only

3 mm x 3 mm LFCSP and 10-lead MSOP

2.7 V to 5.5 V power supply
Guaranteed monotonic by design
Power-on reset to zero scale
Per channel power-down
Hardware

2

I

C-compatible serial interface supports standard (100 kHz),

LDAC

and

CLR

functions

fast (400 kHz), and high speed (3.4 MHz) modes

APPLICATIONS

Process control
Data acquisition systems
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators

FUNCTIONAL BLOCK DIAGRAMS

AD5627R/AD5647R/AD5667R

DDR

SCL

SDA

DDR

SCL

SDA

LOGIC

INTERFACE

LDAC CLR

Figure 1. AD5627R/AD5647R/AD5667R

AD5627/AD5667

LOGIC

INTERFACE

LDAC CLR

DD

INPUT

REGISTER

INPUT

REGISTER

POWER-ON

RESET

DD

INPUT

REGISTER

INPUT

REGISTER

POWER-ON

RESET

GND

DAC

REGISTER

DAC

REGISTER

GND

DAC

REGISTER

DAC

REGISTER

Figure 2. AD5627/AD5667

2C®

Interface

V

REFIN

REFOUT

1.25V/2.5V REF

BUFFER

STRING

DAC A

BUFFER

STRING

DAC B

POWER-DOWN

LOGIC

REFIN

BUFFER

STRING

DAC A

BUFFER

STRING

DAC B

POWER-DOWN

LOGIC

V

A

OUT

V

B

OUT

06342-001

V

A

OUT

V

B

OUT

06342-002

GENERAL DESCRIPTION

The AD5627R/AD5647R/AD5667R, AD5627/AD5667
members of the nanoDAC family are low power, dual, 12-, 14-,
16-bit buffered voltage-out DACs with/without on-chip
reference. All devices operate from a single 2.7 V to 5.5 V
supply, are guaranteed monotonic by design, and have an I
compatible serial interface.

The AD5627R/AD5647R/AD5667R have an on-chip reference.
The AD56x7RBCPZ have a 1.25 V, 5 ppm/°C reference, giving a
full-scale output range of 2.5 V; the AD56x7RBRMZ have a

2.5 V, 5 ppm/°C reference, giving a full-scale output range of 5
V. The on-chip reference is off at power-up, allowing the use of
an external reference. The internal reference is enabled via a
software write. The AD5667 and AD5627 require an external
reference voltage to set the output range of the DAC.

The AD56x7R/AD56x7 incorporate a power-on reset circuit
that ensures the DAC output powers up to 0 V, and remains
there until a valid write takes place. The part contains a per­channel power-down feature that reduces the current
consumption of the device to 480 nA at 5 V and provides

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

2

C-

software-selectable output loads while in power-down mode.
The low power consumption of this part in normal operation
makes it ideally suited to portable battery-operated equipment.
The on-chip precision output amplifier enables rail-to-rail
output swing.

2

The AD56x7R/AD56x7 use a 2-wire I

C-compatible serial
interface that operates in standard (100 kHz), fast (400 kHz),
and high speed (3.4 MHz) modes.

Table 1. Related Devices

Part No. Description

AD5663 2.7 V to 5.5 V, dual 16-bit DAC,

AD5623R/AD5643R/AD5663R 2.7 V to 5.5 V, dual 12-, 14-, 16-bit

AD5625R/AD5645R/AD5665R,
AD5625/AD5665

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2007 Analog Devices, Inc. All rights reserved.

external reference, SPI® interface

DACs, internal reference,
SPI interface

2.7 V to 5.5 V, quad 12-, 14-, 16-bit
DACs, with/without internal
reference, I

2

C interface

AD5627R/AD5647R/AD5667R, AD5627/AD5667

TABLE OF CONTENTS

Features.............................................................................................. 1

Applications....................................................................................... 1

Functional Block Diagrams............................................................. 1

General Description......................................................................... 1

Revision History ...............................................................................2

Specifications..................................................................................... 3

AC Characteristics........................................................................ 5

2

I

C Timing Specifications............................................................ 6

Absolute Maximum Ratings............................................................ 8

ESD Caution.................................................................................. 8

Pin Configuration and Function Descriptions............................. 9

Typical Performance Characteristics ........................................... 10

Terminology .................................................................................... 18

Theory of Operation ......................................................................20

D/A Section................................................................................. 20

Resistor String............................................................................. 20

Output Amplifier........................................................................ 20

Internal reference........................................................................20

External reference....................................................................... 20

Serial Interface............................................................................ 21

Write Operation.......................................................................... 21

Read Operation........................................................................... 21

High Speed Mode....................................................................... 21

Input Shift Register .................................................................... 23

Multiple Byte Operation............................................................ 23

Broadcast Mode.......................................................................... 23

LDAC

Function .......................................................................... 23

Power-Down Modes .................................................................. 25

Power-On Reset and Software Reset ....................................... 26

Clear Pin (

Internal Reference Setup (R Versions) .................................... 26

Application Information................................................................ 27

Using a Reference as a Power Supply for the

AD56x7R/AD56x7..................................................................... 27

Bipolar Operation Using the AD56x7R/AD56x7 .................. 27

Power Supply Bypassing and Grounding................................ 27

Outline Dimensions....................................................................... 28

Ordering Guide .......................................................................... 29

CLR

).......................................................................... 26

REVISION HISTORY

1/07—Revision 0: Initial Version

Rev. 0 | Page 2 of 32

AD5627R/AD5647R/AD5667R, AD5627/AD5667

SPECIFICATIONS

VDD = 2.7 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; V

= VDD; all specifications T

REFIN

MIN

to T

, unless otherwise noted.

MAX

Table 2.

Parameter Min Typ Max Unit Conditions/Comments

STATIC PERFORMANCE

2

1

AD5667R/AD5667

Resolution 16 Bits
Relative Accuracy ±8 ±12 LSB
Differential Nonlinearity ±1 LSB Guaranteed monotonic by design

AD5647R

Resolution 14 Bits
Relative Accuracy ±2 ±4 LSB
Differential Nonlinearity ±0.5 LSB Guaranteed monotonic by design

AD5627R/AD5627

Resolution 12 Bits
Relative Accuracy ±0.5 ±1 LSB

Differential Nonlinearity ±0.25 LSB Guaranteed monotonic by design
Zero-Code Error 2 10 mV All 0s loaded to DAC register
Offset Error ±1 ±10 mV
Full-Scale Error −0.1 ±1 % of FSR All 1s loaded to DAC register
Gain Error ±1.5 % of FSR
Zero-Code Error Drift ±2 µV/°C
Gain Temperature Coefficient ±2.5 ppm Of FSR/°C
DC Power Supply Rejection Ratio −100 dB DAC code = midscale ; VDD = 5 V ± 10%
DC Crosstalk (External Reference) 15 µV

Due to full-scale output change,

= 2 kΩ to GND or 2 kΩ to V

R

L

DD

10 µV/mA Due to load current change
8 µV Due to powering down (per channel)
DC Crosstalk (Internal Reference) 25 µV

Due to full-scale output change,
R

= 2 kΩ to GND or 2 kΩ to V

L

DD

20 µV/mA Due to load current change
10 µV Due to powering down (per channel)

OUTPUT CHARACTERISTICS

3

Output Voltage Range 0 VDD V
Capacitive Load Stability 2 nF RL = ∞
10 nF RL = 2 kΩ
DC Output Impedance 0.5 Ω
Short-Circuit Current 30 mA VDD = 5 V
Power-Up Time 4 µs Coming out of power-down mode; VDD = 5 V

REFERENCE INPUTS

Reference Current 110 130 µA V

= VDD = 5.5 V

REF

Reference Input Range 0.75 VDD V
Reference Input Impedance 50 kΩ

REFERENCE OUTPUT
(LFCSP_WD PACKAGE)

Output Voltage 1.247 1.253 V At ambient
Reference TC

3

±10 ppm/°C

Output Impedance 7.5 kΩ

REFERENCE OUTPUT (MSOP PACKAGE)

Output Voltage 2.495 2.505 V At ambient
Reference TC

3

±5 ±10 ppm/°C

Output Impedance 7.5 kΩ

Rev. 0 | Page 3 of 32

AD5627R/AD5647R/AD5667R, AD5627/AD5667

Parameter Min Typ Max Unit Conditions/Comments

LOGIC INPUTS (ADDR, CLR, LDAC)

3

1

IIN, Input Current ±1 µA
V

, Input Low Voltage 0.15 × VDD V

INL

V

, Input High Voltage 0.85 × VDD V

INH

CIN, Pin Capacitance 2 pF ADDR
20 pF

V

, Input Hysteresis 0.1 × VDD V

HYST

CLR, LDAC

LOGIC INPUTS (SDA, SCL)

IIN, Input Current ±1 µA
V

, Input Low Voltage 0.3 × VDD V

INL

V

, Input High Voltage 0.7 × VDD V

INH

CIN, Pin Capacitance 2 pF
V

, Input Hysteresis 0.1 × VDD V

HYST

LOGIC OUTPUTS (OPEN-DRAIN)

VOL, Output Low Voltage 0.4 V I

0.6 V I

= 3 mA

SINK

= 6 mA

SINK

Floating-State Leakage Current ±1 µA
Floating-State Output Capacitance 2 pF

POWER REQUIREMENTS

VDD 2.7 5.5 V
IDD (Normal Mode)

4

V

= VDD, VIL = GND

IH

VDD = 4.5 V to 5.5 V 0.4 0.5 mA Internal reference off
VDD = 2.7 V to 3.6 V 0.35 0.45 mA Internal reference off
VDD = 4.5 V to 5.5 V 0.95 1.15 mA Internal reference on
VDD = 2.7 V to 3.6 V 0.8 0.95 mA Internal reference on

IDD (All Power-Down Modes)

1

Temperature range: B grade: −40°C to +105°C.

2

Linearity calculated using a reduced code range: AD5567R/AD5667 (Code 512 to Code 65,024); AD5647R (Code 128 to Code 16,256); AD5627R/AD5627 (Code 32 to

Code 4064). Output unloaded.

3

Guaranteed by design and characterization, not production tested.

4

Interface inactive. All DACs active. DAC outputs unloaded.

5

All DACs powered down.

5

0.48 1 µA VIH = VDD, VIL = GND

Rev. 0 | Page 4 of 32

AD5627R/AD5647R/AD5667R, AD5627/AD5667

AC CHARACTERISTICS

VDD = 2.7 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; V

= VDD; all specifications T

REFIN

MIN

to T

, unless otherwise noted.

MAX

1

Table 3.

Parameter

2

Min Typ Max Unit Conditions/Comments

3

Output Voltage Settling Time

AD5627R/AD5627 3 4.5 µs ¼ to ¾ scale settling to ±0.5 LSB
AD5647R 3.5 5 µs ¼ to ¾ scale settling to ±0.5 LSB
AD5667R/AD5667 4 7 µs ¼ to ¾ scale settling to ±2 LSB

Slew Rate 1.8 V/µs
Digital-to-Analog Glitch Impulse 15 nV-s 1 LSB change around major carry transition
Digital Feedthrough 0.1 nV-s
Reference Feedthrough −90 dB V

= 2 V ± 0.1 V p-p, frequency 10 Hz to 20 MHz

REF

Digital Crosstalk 0.1 nV-s
Analog Crosstalk 1 nV-s External reference
4 nV-s Internal reference
DAC-to-DAC Crosstalk 1 nV-s External reference
4 nV-s Internal reference
Multiplying Bandwidth 340 kHz V
Total Harmonic Distortion −80 dB V

= 2 V ± 0.1 V p-p

REF

= 2 V ± 0.1 V p-p, frequency = 10 kHz

REF

Output Noise Spectral Density 120 nV/√Hz DAC code = midscale, 1 kHz
100 nV/√Hz DAC code = midscale, 10 kHz
Output Noise 15 µV p-p 0.1 Hz to 10 Hz

1

Guaranteed by design and characterization, not production tested.

2

See the Terminology section.

3

Temperature range is −40°C to +105°C, typical @ 25°C.

Rev. 0 | Page 5 of 32

AD5627R/AD5647R/AD5667R, AD5627/AD5667

I2C TIMING SPECIFICATIONS

VDD = 2.7 V to 5.5 V; all specifications T

Table 4.

Parameter Conditions2 Min Max Unit Description

3

f

Standard mode 100 kHz Serial clock frequency

SCL

Fast mode 400 kHz
High speed mode, CB = 100 pF 3.4 MHz
High speed mode, CB = 400 pF 1.7 MHz
t1 Standard mode 4 s t
Fast mode 0.6 s
High speed mode, CB = 100 pF 60 ns
High speed mode, CB = 400 pF 120 ns
t2 Standard mode 4.7 s t
Fast mode 1.3 s
High speed mode, CB = 100 pF 160 ns
High speed mode, CB = 400 pF 320 ns
t3 Standard mode 250 ns t
Fast mode 100 ns
High speed mode 10 ns
t4 Standard mode 0 3.45 s t
Fast mode 0 0.9 s
High speed mode, CB = 100 pF 0 70 ns
High speed mode, CB = 400 pF 0 150 ns
t5 Standard mode 4.7 s t
Fast mode 0.6 s
High speed mode 160 ns
t6 Standard mode 4 s t
Fast mode 0.6 s
High speed mode 160 ns
t7 Standard mode 4.7 s t
Fast mode 1.3 s
t8 Standard mode 4 s t
Fast mode 0.6 s
High speed mode 160 ns
t9 Standard mode 1000 ns t
Fast mode 300 ns
High speed mode, CB = 100 pF 10 80 ns
High speed mode, CB = 400 pF 20 160 ns
t10 Standard mode 300 ns t
Fast mode 300 ns
High speed mode, CB = 100 pF 10 80 ns
High speed mode, CB = 400 pF 20 160 ns
t11 Standard mode 1000 ns t
Fast mode 300 ns
High speed mode, CB = 100 pF 10 40 ns
High speed mode, CB = 400 pF 20 80 ns
t

Standard mode 1000 ns

11A

Fast mode 300 ns
High speed mode, CB = 100 pF 10 80 ns
High speed mode, CB = 400 pF 20 160 ns

MIN

to T

, f

= 3.4 MHz, unless otherwise noted.1

MAX

SCL

, SCL high time

HIGH

, SCL low time

LOW

, data setup time

SU;DAT

, data hold time

HD;DAT

setup time for a repeated start condition

SU;STA,

, hold time (repeated) start condition

HD;STA

, bus free time between a stop and a start condition

BUF

, setup time for a stop condition

SU;STO

, rise time of SDA signal

RDA

, fall time of SDA signal

FDA

, rise time of SCL signal

RCL

, rise time of SCL signal after a repeated start condition and after

t

RCL1

an acknowledge bit

Rev. 0 | Page 6 of 32

AD5627R/AD5647R/AD5667R, AD5627/AD5667

Parameter Conditions2 Min Max Unit Description

t12 Standard mode 300 ns t
Fast mode 300 ns
High speed mode, CB = 100 pF 10 40 ns
High speed mode, CB = 400 pF 20 80 ns
t13 Standard mode 10 ns
Fast mode 10 ns
High speed mode 10 ns
t14 Standard mode 300 ns

Fast mode 300 ns
High speed mode 30 ns
t15 Standard mode 20 ns
Fast mode 20 ns
High speed mode 20 ns

4

t

Fast mode 0 50 ns Pulse width of spike suppressed

SP

High speed mode 0 10 ns

1

See Figure 3. High speed mode timing specification applies only to the AD5627RBRMZ-2/AD5627BRMZ-2REEL7 and AD5667RBRMZ-2/AD5667BRMZ-2REEL7.

2

CB refers to the capacitance on the bus line.

3

The SDA and SCL timing is measured with the input filters enabled. Switching off the input filters improves the transfer rate but has a negative effect on EMC behavior

of the part.

4

Input filtering on the SCL and SDA inputs suppresses noise spikes that are less than 50 ns for fast mode or 10 ns for high speed mode.

t

t

SCL

SDA

t

7

PS S P

2

t

6

11

t

4

t

12

t

1

t

3

, fall time of SCL signal

FCL

LDAC pulse width low

th

Falling edge of 9

SCL clock pulse of last byte of valid write to LDAC

falling edge

CLR pulse width low

t

6

t

5

t

10

t

8

t

14

t

9

LDAC*

CLR

*ASYNCHRONOUS LDAC UPDAT E MODE.

t

15

Figure 3. 2-Wire Serial Interface Timing Diagram

t

13

06342-003

Rev. 0 | Page 7 of 32

AD5627R/AD5647R/AD5667R, AD5627/AD5667

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 5.

Parameter Rating

VDD to GND −0.3 V to +7 V
V

to GND −0.3 V to VDD + 0.3 V

OUT

V

REFIN/VREFOUT

Digital Input Voltage to GND −0.3 V to VDD + 0.3 V
Operating Temperature Range, Industrial −40°C to +105°C
Storage Temperature Range −65°C to +150°C
Junction Temperature (TJ maximum) 150°C

Power Dissipation (TJ max − TA)/θJA

θJA Thermal Impedance

LFCSP_WD Package (4-Layer Board) 61°C/W
MSOP Package 150.4°C/W

Reflow Soldering Peak Temperature, Pb-Free 260°C ± 5°C

to GND −0.3 V to VDD + 0.3 V

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

Rev. 0 | Page 8 of 32

AD5627R/AD5647R/AD5667R, AD5627/AD5667

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

V

A

OUT

V

OUT

LDAC

GND

CLR

AD5627/

2

B

AD5667

3

4

TOP VIEW

(Not to Scale)

5

EXPOSED PAD TIED TO GND

ON LFCSP PACKAGE.

Figure 4. AD5627/AD5667 Pin Configuration

10

V

REFIN

9

V

DD

8

SDA

7

SCL

6

ADDR

06342-101

1

V

A

OUT

V

OUT

GND

LDAC

CLR

AD5627R/

2

B

AD5647R/

3

AD5667R

4

TOP VIEW

(Not to Scal e)

5

EXPOSED PAD TIED TO GND

ON LFCSP PACKAGE.

10

V

REFIN/VREFOUT

9

V

DD

8

SDA

7

SCL

6

ADDR

06342-102

Figure 5. AD5627R/AD5647R/AD5667R Pin Configuration

Table 6. Pin Function Descriptions

Pin

Mnemonic Description

No.

1 V
2 V

A Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.

OUT

B Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.

OUT

3 GND Ground reference point for all circuitry on the part.
4

LDAC Pulsing this pin low allows any or all DAC registers to be updated if the inputs have new data. This allows

simultaneous updates of all DAC outputs. Alternatively, this pin can be tied permanently low.

5

CLR Asynchronous Clear Input. The CLR input is falling-edge sensitive. While CLR is low, all LDAC pulses are ignored.

CLR is activated, zero scale is loaded to all input and DAC registers. This clears the output to 0 V. The part exits

When
clear code mode on the falling edge of the 9th clock pulse of the last byte of valid write. If CLR is activated during a
write sequence, the write is aborted. If

CLR is activated during high speed mode the part will exit high speed mode.
6 ADDR Three-State Address Input. Sets the two least significant bits (Bit A1, Bit A0) of the 7-bit slave address.
7 SCL Serial Clock Line. This is used in conjunction with the SDA line to clock data into or out of the 24-bit input register.
8 SDA

Serial Data Line. This is used in conjunction with the SCL line to clock data into or out of the 24-bit input register. It is
a bidirectional, open-drain data line that should be pulled to the supply with an external pull-up resistor.

9 VDD

Power Supply Input. These parts can be operated from 2.7 V to 5.5 V, and the supply should be decoupled with a
10 F capacitor in parallel with a 0.1 F capacitor to GND.

10 V

REFIN/VREFOUT

The AD56x7R have a common pin for reference input and reference output. When using the internal reference, this is
the reference output pin. When using an external reference, this is the reference input pin. The default for this pin is
as a reference input. (The internal reference and reference output are only available on R suffix versions.) The AD56x7
has a reference input pin only.

Rev. 0 | Page 9 of 32

AD5627R/AD5647R/AD5667R, AD5627/AD5667

TYPICAL PERFORMANCE CHARACTERISTICS

10

VDD = V
T

8

6

4

2

0

–2

INL ERROR (LSB)

–4

–6

–8

–10

0 5k 10k 15k 20k 25k 30k 35k 40k 45k 50k 55k 60k 65k

= 25°C

A

REF

= 5V

CODE

Figure 6. AD5667 INL, External Reference

06342-005

1.0
VDD = V
T

0.8

0.6

0.4

0.2

0

–0.2

DNL ERROR (LSB)

–0.4

–0.6

–0.8

–1.0

0 10k 20k 30k 40k 50k 60k

= 25°C

A

REF

= 5V

CODE

Figure 9. AD5667 DNL, External Reference

6342-007

4

VDD = V
T

3

2

1

0

–1

INL ERROR (L SB)

–2

–3

–4

0 2500 5000 7500 10000 12500 15000

= 25°C

A

REF

= 5V

CODE

Figure 7. AD5647R INL, External Reference

1.0
VDD = V

T

0.8

0.6

0.4

0.2

0

–0.2

INL ERROR (L SB)

–0.4

–0.6

–0.8

–1.0

0 500 1000 1500 2000 2500 3000 3500 4000

= 25°C

A

REF

= 5V

CODE

Figure 8. AD5627 INL, External Reference

0.5
VDD = V
T

0.4

0.3

0.2

0.1

0

–0.1

DNL ERROR (LSB)

–0.2

–0.3

–0.4

–0.5

06342-006

0 2500 5000 7500 10000 12500 15000

= 25°C

A

REF

= 5V

CODE

6342-008

Figure 10. DNL AD5647R, External Reference

0.20
VDD = V

T

0.15

0.10

0.05

0

–0.05

DNL ERROR (LSB)

–0.10

–0.15

–0.20

06342-100

0 500 1000 1500 2000 2500 3000 3500 4000

= 25°C

A

REF

= 5V

CODE

6342-009

Figure 11. AD5627 DNL, External Reference

Rev. 0 | Page 10 of 32

AD5627R/AD5647R/AD5667R, AD5627/AD5667

10

VDD = 5V

8

6

4

2

0

–2

INL ERROR (LSB)

–4

–6

–8

–10

V

REFOUT

TA = 25°C

0

5000

= 2.5V

10000

15000

20000

25000

30000

CODE

Figure 12. AD5667R INL, 2.5 V Internal Reference

4

VDD=5V
V

=2.5V

REFOUT

3

TA=25°C

2

1

0

–1

INL ERROR (LSB)

–2

–3

–4

0

1250

2500

3750

5000

6250

7500

CODE

Figure 13. AD5647R INL, 2.5 V Internal Reference

35000

8750

40000

10000

45000

11250

50000

12500

55000

13750

60000

15000

65000

16250

06342-010

06342-011

1.0
VDD=5V

0.8

0.6

0.4

0.2

0

–0.2

DNL ERROR (LSB)

–0.4

–0.6

–0.8

–1.0

0

V

REFOUT

TA=25°C

5000

=2.5V

10000

15000

20000

25000

30000

CODE

Figure 15. AD5667R DNL, 2.5 V Internal Reference

0.5
VDD = 5V

0.4

0.3

0.2

0.1

0

–0.1

DNL ERROR (LSB)

–0.2

–0.3

–0.4

–0.5

V

REFOUT

TA = 25°C

0

1250

= 2.5V

2500

3750

5000

6250

7500

CODE

Figure 16. AD5647R DNL, 2.5 V Internal Reference

35000

8750

40000

10000

45000

11250

50000

12500

55000

13750

60000

15000

65000

16250

06342-013

6342-014

1.0
VDD=5V
V

REFOUT

T

A

= 25°C

=2.5V

CODE

0.8

0.6

0.4

0.2

0

–0.2

INL ERROR (LSB)

–0.4

–0.6

–0.8

–1.0

0 1000500 20001500 350030002500 4000

Figure 14. AD5627R INL, 2.5 V Internal Reference

06342-012

Rev. 0 | Page 11 of 32

0.20
VDD = 5V
V

= 2.5V

REFOUT

0.15

TA = 25°C

0.10

0.05

0

–0.05

DNL ERROR (LSB)

–0.10

–0.15

–0.20

0 1000500 200015 00 350030002500 4000

CODE

Figure 17. AD5627R DNL, 2.5 V Internal Reference

6342-015

AD5627R/AD5647R/AD5667R, AD5627/AD5667

10

VDD = 3V

8

6

4

2

0

–2

INL ERROR (LSB)

–4

–6

–8

–10

V

REFOUT

T

A

0

= 25°C

5000

= 1.25V

15000

10000

20000

25000

30000

CODE

Figure 18. AD5667R INL,1.25 V Internal Reference

35000

40000

45000

50000

55000

60000

65000

06342-016

1.0
VDD = 3V

0.8

0.6

0.4

0.2

0

–0.2

DNL ERROR (LSB)

–0.4

–0.6

–0.8

–1.0

V

REFOUT

T

A

0

= 25°C

5000

= 1.25V

15000

10000

20000

25000

30000

CODE

35000

Figure 21. AD5667R DNL,1.25 V Internal Reference

40000

45000

50000

55000

60000

65000

06342-019

4

VDD = 3V

= 1.25V

V

REFOUT

3

= 25°C

T

A

2

1

0

–1

INL ERROR (LSB)

–2

–3

–4

0

8750

7500

6250

5000

3750

2500

1250

CODE

10000

11250

Figure 19. AD5647R INL, 1.25 V Internal Reference

1.0
VDD = 3V

0.8

V

= 1.25V

REFOUT

T

= 25°C

A

0.6

0.4

0.2

0

–0.2

INL ERROR (LS B)

–0.4

–0.6

–0.8

–1.0

0 500 1000 1500 2000 2500 3000 3500 4000

CODE

Figure 20. AD5627R INL,1.25 V Internal Reference

12500

13750

15000

16250

0.5
VDD = 3V

0.4

0.3

0.2

0.1

0

–0.1

DNL ERROR (LSB)

–0.2

–0.3

–0.4

–0.5

06342-017

V
T

0

REFOUT

= 25°C

A

1250

= 1.25V

2500

3750

5000

6250

7500

CODE

8750

10000

11250

12500

13750

15000

16250

06342-020

Figure 22. AD5647R DNL,1.25 V Internal Reference

0.20
VDD = 3V

V

= 1.25V

REFOUT

0.15
T

= 25°C

A

0.10

0.05

0

–0.05

DNL ERROR (LSB)

–0.10

–0.15

–0.20

06342-018

0 500 1000 1500 2000 2500 3000 3500 4000

CODE

06342-021

Figure 23. AD5627R DNL, 1.25 V Internal Reference

Rev. 0 | Page 12 of 32

AD5627R/AD5647R/AD5667R, AD5627/AD5667

8

6

= V

V

4

2

0

ERROR (LSB)

–2

–4

–6

–8

–40 –20 4020018060

= 5V

DD

REF

TEMPERATURE (°C)

Figure 24. INL Error and DNL Error vs. Temperature

MAX INL

MAX DNL

MIN DNL

MIN INL

00

06342-022

0

VDD = 5V

–0.02

–0.04

–0.06

–0.08

–0.10

–0.12

ERROR (% FSR)

–0.14

–0.16

–0.18

–0.20

–40 –20 40200 1008060

GAIN ERROR

FULL-SCAL E ERROR

TEMPERATURE (°C)

Figure 27. Gain Error and Full-Scale Error vs. Temperature

06342-025

10

8

6

= 5V

V

DD

4

T

= 25°C

A

2

0

–2

ERROR (LSB)

–4

–6

–8

–10

0.75 1.25 1. 75 2.25 4.253.753.252.75 4.75

Figure 25. INL and DNL Error vs. V

8

6

= 25°C

T

A

4

2

0

ERROR (LSB)

–2

–4

–6

V

(V)

REF

REF

MAX INL

MAX DNL

MIN DNL

MIN INL

MAX INL

MAX DNL

MIN DNL

MIN INL

1.5

1.0

0.5

0

–0.5

ERROR (mV)

–1.0

–1.5

–2.0

–2.5

–40 –20 40200860 100

06342-023

ZERO-SCALE ERROR

OFFSET ERROR

TEMPERATURE (°C)

0

06342-026

Figure 28. Zero-Scale Error and Offset Error vs. Temperature

1.0

0.5

GAIN ERROR

0

–0.5

ERROR (% FSR)

–1.0

–1.5

FULL-SCALE ERROR

–8

2.7 3.2 3.7 4. 74. 2 5.2
VDD (V)

Figure 26. INL and DNL Error vs. Supply

06342-024

Rev. 0 | Page 13 of 32

–2.0

2.7 3.2 3.7 4.74. 2 5. 2
VDD (V)

Figure 29. Gain Error and Full-Scale Error vs. Supply

06342-027

AD5627R/AD5647R/AD5667R, AD5627/AD5667

T

1.0
= 25°C

T

A

0.5

ZERO-SCALE ERROR

0

–0.5

–1.0

ERROR (mV)

–1.5

–2.0

–2.5

2.7 3.2 4.23. 7 5.24.7
VDD (V)

Figure 30. Zero-Scale Error and Offset Error vs. Supply

1

8

1

6

1

4

1

2

1

0

8

6

NUMBER OF DEVI CES

4

2

0

IDD (mA)

Figure 31. I

Histogram with External Reference

DD

OFFSET ERROR

VDD= 3.6V

VDD= 5.5V

0.440.420.400.380.360.340.320.30

06342-028

06342-029

0.5
DAC LOADED WI TH
FULL-SCAL E

0.4
SOURCING CURRENT

0.3

DAC LOADED WI TH
ZERO-SCALE
SINKING CURRENT

0.2

VDD= 3V

0.1

AGE (V)

V

= 1.25V

REFOUT

0

–0.1

ERROR VOL

–0.2

–0.3

–0.4

–0.5

–10 –8 –6 –4 –2 0 2 4 861

VDD= 5V
V

REFOUT

= 2.5V

CURRENT (mA)

0

Figure 33. Headroom at Rails vs. Source and Sink

6

VDD= 5V
V

= 2.5V

REFOUT

5

T

= 25°C

A

4

3

(V)

OUT

V

2

FULL SCALE

3/4 SCALE

MIDSCALE

1/4 SCALE

1

0

–1

–30 –20 –10 0 10 20 30

CURRENT (mA)

ZERO SCALE

Figure 34. AD56x7R with 2.5 V Reference, Source and Sink Capability

6342-031

6342-046

1

4

= 1.25V

V

REFOUT

1

2

1

0

8

V

REFOUT

VDD= 3.6V

VDD= 5.5V

= 2.5V

6

NUMBER OF DEVI CES

4

2

0

0.74

0.75

0.76

0.77

0.78

0.79

0.80

0.81

0.82

0.83

0.84

0.85

0.86

0.87

0.88

0.89

0.90

0.91

0.92

0.93

0.94

0.95

0.96

0.97

0.98

0.99

1.00

1.01

1.02

1.03

1.04

06342-030

Figure 32. I

IDD (mA)

Histogram with Internal Reference

DD

4

VDD= 3V
V

= 1.25V

REFOUT

T

= 25°C

A

3

2

(V)

OUT

V

1

3/4 SCALE

MIDSCALE

1/4 SCALE

0

–1

–30 –20 –10 0 10 20 30

CURRENT (mA)

FULL SCAL E

ZERO SCALE

Figure 35. AD56x7R with 1.25 V Reference, Source and Sink Capability

6342-047

Rev. 0 | Page 14 of 32

AD5627R/AD5647R/AD5667R, AD5627/AD5667

0.9
TA = 25°C

0.8

0.7

0.6

0.5

(mA)

DD

0.4

I

0.3

0.2

0.1

0

512 10512 20512 30512 40512 50512 60512

V

DD

= 5V, V

= V

V

DD

REFOUT

REF

= 5V

CODE

= 2.5V

VDD = V
T
FULL-SCALE CODE CHANGE
0x0000 TO 0xFFF F
OUTPUT L OADED WIT H 2kΩ
AND 200pF TO GND

V

= 909mV/DIV

OUT

1

6342-060

TIME BASE = 4µs/DIV

= 25°C

A

REF

= 5V

06342-048

Figure 36. Supply Current vs. Code

0.40

0.35

0.30

0.25

0.20

(mA)

DD

I

0.15

0.10

0.05

= 25°C

T

A

0

3.22.7

3.7 4.2 4. 7 5.2

SUPPLY VOLTAGE (V)

Figure 37. Supply Current vs. Supply Voltage

0.45

0.40

0.35

0.30

0.25

(mA)

0.20

DD

I

0.15

0.10

0.05

0

–40 –20 0 20 40 60 80 100

VDD = V

V

DD

TEMPERATURE (° C)

= V

REFIN

REFIN

= 5V

= 3V

Figure 38. Supply Current vs. Temperature

Figure 39. Full-Scale Settling Time, 5 V

VDD = V
T

V

1

2

06342-061

DD

V

OUT

CH1 2.0V CH2 500mV M100µs 125MS/s

A CH1 1.28V

= 25°C

A

= 5V

REF

MAX(C2)

420.0mV

8.0ns/p t

06342-049

Figure 40. Power-On Reset to 0 V

SYNC

1

3

2

CH1 5.0V

06342-063

CH3 5.0V

SLCK

V

OUT

CH2 500mV M400ns A CH1 1.4V

VDD = 5V

6342-050

Figure 41. Exiting Power-Down to Midscale

Rev. 0 | Page 15 of 32

AD5627R/AD5647R/AD5667R, AD5627/AD5667

V

V
V

2.538

2.537

2.536

2.535

2.534

2.533

2.532

2.531

(V)

2.530

2.529

OUT

V

2.528

2.527

2.526

2.525

2.524

2.523

2.522

2.521
0 50 100 150 350 400200 250 300 450 512

VDD= V
T
5ns/SAMPL E NUMBER
GLITCH IMPULSE = 9.494nV
1LSB CHANGE AROUND
MIDSCALE (0x8000 TO 0x7FF F)

SAMPLE NUMBER

= 25°C

A

REF

= 5V

Figure 42. Digital-to-Analog Glitch Impulse (Negative)

6342-058

VDD = V
T
DAC LOADED WITH MIDSCALE

1

2µV/DI

= 25°C

A

REF

= 5V

4s/DIV

Figure 45. 0.1 Hz to 10 Hz Output Noise Plot, External Reference

06342-051

2.498

2.497

2.496

2.495

(V)

OUT

V

2.494

2.493

2.492

2.491
0 50 100 150 350 400200 250 300 450 512

VDD= V
T
5ns/SAMPL E NUMBER
ANALOG CROS STALK = 0. 424nV

SAMPLE NUMBER

= 25°C

A

REF

= 5V

Figure 43. Analog Crosstalk, External Reference

2.496

2.494

2.492

2.490

2.488

2.486

2.484

2.482

2.480

2.478

(V)

2.476

OUT

2.474

V

2.472

2.470

2.468

2.466

2.464

2.462

2.460

2.458

2.456
0 50 100 150 350 400200 250 300 450 512

VDD= 5V
V

= 2.5V

REFOUT

T

= 25°C

A

5ns/SAMPL E NUMBER
ANALOG CROS STALK = 4.462nV

SAMPLE NUMBER

Figure 44. Analog Crosstalk, Internal Reference

VDD = 5V
V

= 2.5V

REFOUT

T

= 25°C

A

DAC LOADED WITH MIDSCALE

1

10µV/DI

6342-059

5s/DIV

06342-052

Figure 46. 0.1 Hz to 10 Hz Output Noise Plot, 2.5 V Internal Reference

VDD = 3V
V

= 1.25V

REFOUT

T

= 25°C

A

DAC LOADED WITH MIDSCALE

1

5µV/DI

6342-062

4s/DIV

06342-053

Figure 47. 0.1 Hz to 10 Hz Output Noise Plot,1.25 V Internal Reference

Rev. 0 | Page 16 of 32

AD5627R/AD5647R/AD5667R, AD5627/AD5667

–

800

TA = 25°C
MIDSCALE LOADED

700

600

500

16

14

12

V

= V

REF

TA = 25°C

DD

=

V

3V

DD

400

300

OUTPUT NOISE (nV/√Hz)

200

VDD= 3V

100

V

REFOUT

0

100 10k1k 100k 1M

= 1.25V

VDD= 5V
V

= 2.5V

REFOUT

FREQUENCY (Hz)

Figure 48. Noise Spectral Density, Internal Reference

20

VDD = 5V
T

= 25°C

A

–30

DAC LOADED WITH FULL S CALE
V

= 2V ± 0.3V p -p

REF

–40

–50

–60

(dB)

–70

–80

–90

–100

2k 4k 6k 8k 10k

FREQUENCY (Hz)

Figure 49. Total Harmonic Distortion

10

TIME (µs)

=

V

5V

8

6

4

6342-054

012 34 567 981

CAPACITANCE (nF)

DD

0

6342-056

Figure 50. Settling Time vs. Capacitive Load

5

0

–5

–10

–15

(dB)

–20

–25

–30

–35

–40

6342-055

10k 100k 1M 10M

FREQUENCY (Hz)

VDD = 5V

= 25°C

T

A

06342-057

Figure 51. Multiplying Bandwidth

Rev. 0 | Page 17 of 32

AD5627R/AD5647R/AD5667R, AD5627/AD5667

TERMINOLOGY

Relative Accuracy or Integral Nonlinearity (INL)

For the DAC, relative accuracy or integral nonlinearity is a
measurement of the maximum deviation, in LSBs, from a straight
line passing through the endpoints of the DAC transfer function.

Differential Nonlinearity (DNL)

Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent codes.
A specified differential nonlinearity of ±1 LSB maximum ensures
monotonicity. This DAC is guaranteed monotonic by design.

Zero-Code Error

Zero-code error is a measurement of the output error when
zero scale (0x0000) is loaded to the DAC register. Ideally, the
output should be 0 V. The zero-code error is always positive in
the AD5667R because the output of the DAC cannot go below
0 V due to a combination of the offset errors in the DAC and
the output amplifier. Zero-code error is expressed in mV.

Full-Scale Error

Full-scale error is a measurement of the output error when full­scale code (0xFFFF) is loaded to the DAC register. Ideally, the
output should be V

− 1 LSB. Full-scale error is expressed in %

DD

of full-scale range (FSR).

Gain Error

Gain error is a measure of the span error of the DAC. It is the
deviation in slope of the DAC transfer characteristic from ideal
expressed in % of FSR.

Zero-Code Error Drift

Zero-code error drift is a measurement of the change in zero­code error with a change in temperature. It is expressed in µV/°C.

Gain Temperature Coefficient

Gain temperature coefficient is a measurement of the change in
gain error with changes in temperature. It is expressed in ppm
of FSR/°C.

Offset Error

Offset error is a measure of the difference between V
and V

(ideal) expressed in mV in the linear region of the

OUT

(actual)

OUT

transfer function. Offset error is measured on the AD5667R
with code 512 loaded in the DAC register. It can be negative or
positive.

DC Power Supply Rejection Ratio (PSRR)

DC PSRR indicates how the output of the DAC is affected by
changes in the supply voltage. PSRR is the ratio of the change in
V

to a change in VDD for full-scale output of the DAC. It is

OUT

measured in dB. V

is held at 2 V and VDD is varied by ±10%.

REF

Output Voltage Settling Time

Output voltage settling time is the amount of time it takes for
the output of a DAC to settle to a specified level for a ¼ to ¾
full-scale input change and is measured from the rising edge of
the stop condition.

Digital-to-Analog Glitch Impulse

Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nV-s,
and is measured when the digital input code is changed by
1 LSB at the major carry transition (0x7FFF to 0x8000) (see
Figure 42).

Digital Feedthrough

Digital feedthrough is a measure of the impulse injected into
the analog output of the DAC from the digital inputs of the
DAC, but is measured when the DAC output is not updated. It
is specified in nV-s, and measured with a full-scale code change
on the data bus, that is, from all 0s to all 1s and vice versa.

Reference Feedthrough

Reference feedthrough is the ratio of the amplitude of the signal
at the DAC output to the reference input when the DAC output
is not being updated. It is expressed in dB.

Output Noise Spectral Density

Output noise spectral density is a measurement of the internally
generated random noise. Random noise is characterized as a
spectral density. It is measured by loading the DAC to midscale
and measuring noise at the output. It is measured in nV/√Hz. A
plot of noise spectral density can be seen in

Figure 48.

DC Crosstalk

DC crosstalk is the dc change in the output level of one DAC in
response to a change in the output of another DAC. It is
measured with a full-scale output change on one DAC (or soft
power-down and power-up) while monitoring another DAC kept
at midscale. It is expressed in V.

DC crosstalk due to load current change is a measure of the
impact that a change in load current on one DAC has to
another DAC kept at midscale. It is expressed in µV/mA.

Digital Crosstalk

Digital crosstalk is the glitch impulse transferred to the output
of one DAC at midscale in response to a full-scale code change
(all 0s to all 1s and vice versa) in the input register of another
DAC. It is measured in standalone mode and is expressed in nV-s.

Rev. 0 | Page 18 of 32

AD5627R/AD5647R/AD5667R, AD5627/AD5667

Analog Crosstalk

Analog crosstalk is the glitch impulse transferred to the output
of one DAC due to a change in the output of another DAC. It is
measured by loading one of the input registers with a full-scale
code change (all 0s to all 1s and vice versa), then executing a
software
digital code was not changed. The area of the glitch is expressed
in nV-s.

DAC-to-DAC C rosst a l k

DAC-to-DAC crosstalk is the glitch impulse transferred to the
output of one DAC due to a digital code change and subsequent
analog output change of another DAC. It is measured by
loading the attack channel with a full-scale code change (all 0s
to all 1s and vice versa) with
output of the victim channel that is at midscale. The energy of
the glitch is expressed in nV-s.

LDAC

and monitoring the output of the DAC whose

LDAC

low while monitoring the

Multiplying Bandwidth

The multiplying bandwidth is a measure of the finite bandwidth
of the amplifiers within the DAC. A sine wave on the reference
(with full-scale code loaded to the DAC) appears on the output.
The multiplying bandwidth is the frequency at which the output
amplitude falls to 3 dB below the input.

Total Harmonic Distortion (THD)

THD is the difference between an ideal sine wave and its
attenuated version using the DAC. The sine wave is used as the
reference for the DAC, and the THD is a measurement of the
harmonics present on the DAC output. It is measured in dB.

Rev. 0 | Page 19 of 32

AD5627R/AD5647R/AD5667R, AD5627/AD5667

V

THEORY OF OPERATION

D/A SECTION

The AD56x7R/AD56x7 DACs are fabricated on a CMOS
process. The architecture consists of a string DAC followed by
an output buffer amplifier.
the DAC architecture.

DAC

REGIS TER

Figure 52 shows a block diagram of

DD

REF (+)

RESISTOR

STRING

REF (–)

OUTPUT
AMPLIFI ER
GAIN = +2

V

OUT

R

R

R

R

TO OUTPUT
AMPLIFIER

GND

Figure 52. DAC Architecture

06342-032

Because the input coding to the DAC is straight binary, the ideal
output voltage when using an external reference is given by

OUT

VV

REFIN

⎜

⎟

N

2

⎝

⎠

D

⎛

⎞

×=

The ideal output voltage when using the internal reference is
given by

D

⎛

⎞

VV

2

××=

REFOUTOUT

⎜

⎟

N

2

⎝

⎠

where:
D is the decimal equivalent of the binary code that is loaded to

the DAC register:

0 to 4095 for AD5627R/AD5627 (12-bit).
0 to 16,383 for AD5647R (14-bit).
0 to 65,535 for AD5667R/AD5667 (16-bit).

N is the DAC resolution.

RESISTOR STRING

The resistor string is shown in Figure 53. It is simply a string of
resistors, each of value R. The code loaded to the DAC register
determines at which node on the string the voltage is tapped off
to be fed into the output amplifier. The voltage is tapped off by
closing one of the switches connecting the string to the amplifier.
Because it is a string of resistors, it is guaranteed monotonic.

OUTPUT AMPLIFIER

The output buffer amplifier can generate rail-to-rail voltages on
its output, which gives an output range of 0 V to V
a load of 2 k in parallel with 1000 pF to GND. The source and
sink capabilities of the output amplifier can be seen in
and

Figure 34. The slew rate is 1.8 V/µs with a ¼ to ¾ full-scale

settling time of 7 µs.

. It can drive

DD

Figure 33

R

6342-033

Figure 53. Resistor String

INTERNAL REFERENCE

The AD5627R/AD5647R/AD5667R feature an on-chip
reference. Versions without the R suffix require an external
reference. The on-chip reference is off at power-up and is
enabled via a write to a control register. See the
Reference Setup

section for details.

Internal

Versions packaged in a 10-lead LFCSP package have a 1.25 V
reference, giving a full-scale output of 2.5 V. These parts can be
operated with a V

supply of 2.7 V to 5.5 V. Versions packaged

DD

in a 10-lead MSOP package have a 2.5 V reference, giving a full­scale output of 5 V. The parts are functional with a V
of 2.7 V to 5.5 V, but with a V
output is clamped to V

DD

supply of less than 5 V, the

DD

. See the Ordering Guide for a full list

supply

DD

of models. The internal reference associated with each part is
available at the V

REFOUT

pin.

A buffer is required if the reference output is used to drive
external loads. When using the internal reference, it is
recommended that a 100 nF capacitor be placed between the
reference output and GND for reference stability.

EXTERNAL REFERENCE

The AD5627/AD5667 require an external reference, which is
applied at the V

pin. The V

REFIN

the use of an external reference if the application requires it.
The default condition of the on-chip reference is off at power­up. All devices can be operated from a single 2.7 V to 5.5 V supply.

pin on the AD56x7R allows

REFIN

Rev. 0 | Page 20 of 32

AD5627R/AD5647R/AD5667R, AD5627/AD5667

SERIAL INTERFACE

The AD56x7R/AD56x7 have 2-wire I2C-compatible serial
interfaces (refer to I
available from Philips Semiconductor). The AD56x7R/AD56x7
can be connected to an I
of a master device. See
typical write sequence.

The AD56x7R/AD56x7 support standard (100 kHz), fast
(400 kHz), and high speed (3.4 MHz) data transfer modes.
High speed operation is only available on select models. See
the

Ordering Guide for a full list of models. Support is not

provided for 10-bit addressing and general call addressing.
The AD56x7R/AD56x7 each have a 7-bit slave address. The five

MSBs are 00011 and the two LSBs (A1, A0) are set by the state
of the ADDR address pin. The facility to make hardwired
changes to ADDR allows the user to incorporate up to three of
these devices on one bus, as outlined in

Table 7. Device Address Selection

ADDR Pin Connection A1 A0

VDD 0 0
No Connection 1 0
GND 1 1

The 2-wire serial bus protocol operates as follows:

1. The master initiates data transfer by establishing a start

condition when a high-to-low transition on the SDA line
occurs while SCL is high. The following byte is the address
byte, which consists of the 7-bit slave address. The slave
address corresponding to the transmitted address responds
by pulling SDA low during the 9
termed the acknowledge bit). At this stage, all other devices
on the bus remain idle while the selected device waits for
data to be written to, or read from, its shift register.

2. Data is transmitted over the serial bus in sequences of nine

clock pulses (eight data bits followed by an acknowledge
bit). The transitions on the SDA line must occur during the
low period of SCL and remain stable during the high
period of SCL.

3. When all data bits have been read or written, a stop

condition is established. In write mode, the master pulls
the SDA line high during the 10
stop condition. In read mode, the master issues a no
acknowledge for the 9
remains high). The master then brings the SDA line low
before the 10
clock pulse to establish a stop condition.

2

C-Bus Specification, Version 2.1, January 2000,

2

C bus as a slave device, under the control

Figure 3 for a timing diagram of a

Table 7.

th

clock pulse (this is

th

clock pulse to establish a

th

clock pulse (that is, the SDA line

th

clock pulse, and then high during the 10th

WRITE OPERATION

When writing to the AD56x7R/AD56x7, the user must begin

W

with a start command followed by an address byte (R/

= 0),
after which the DAC acknowledges that it is prepared to receive
data by pulling SDA low. The AD56x7R/AD56x7 requires two
bytes of data for the DAC and a command byte that controls
various DAC functions. Three bytes of data must therefore be
written to the DAC, the command byte followed by the most
significant data byte and the least significant data byte, as
shown in

Figure 54. All these data bytes are acknowledged by

the AD56x7R/AD56x7. A stop condition follows.

READ OPERATION

When reading data back from the AD56x7R/AD56x7, the user
begins with a start command followed by an address byte

W

(R/

= 1), after which the DAC acknowledges that it is
prepared to transmit data by pulling SDA low. Three bytes of
data are then read from the DAC, which are acknowledged by
the master, as shown in

Figure 55. A stop condition follows.

HIGH SPEED MODE

The AD5627RBRMZ and the AD5667RBRMZ offer high speed
serial communication with a clock frequency of 3.4 MHz. See

Ordering Guide for details.

the
High speed mode communication commences after the master

addresses all devices connected to the bus with the Master Code
00001XXX to indicate that a high speed mode transfer is to
begin (see
permitted to acknowledge the high speed master code.
Therefore, the code is followed by a no acknowledge. The
master must then issue a repeated start followed by the device
address. The selected device then acknowledges its address.

All devices continue to operate in high speed mode until the
master issues a stop condition. When the stop condition is
issued, the devices return to standard/fast mode. The part also
returns to standard/fast mode when
part is in high speed mode.

Figure 56). No device connected to the bus is

CLR

is activated while the

Rev. 0 | Page 21 of 32

AD5627R/AD5647R/AD5667R, AD5627/AD5667

(

(

SCL

SDA

START BY

MASTER

SCL

CONTINUED)

SDA

(CONTINUED)

SCL

SDA

START BY

MASTER

SCL

CONTINUED)

19 91

R/W

ACK. BY

FRAME 1

191

DB15 DB14 DB13 DB12 DB11 DB10 DB9

19 91

191

SLAVE ADDRESS

MOST SI GNIFICANT

FRAME 1

SLAVE ADDRESS

FRAME 3

DATA BYT E

AD56x7

DB8

Figure 54. I

R/W

ACK. BY

AD56x7

ACK. BY

AD56x7

2

DB23A0A11000 1 DB22 DB21 DB20 DB19 DB18 DB17 DB16

FRAME 2

COMMAND BYTE

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

FRAME 4

LEAST SI GNIFICANT

DATA BYTE

C Write Operation

DB23A0A11000 1 DB22 DB21 DB20 DB19 DB18 DB17 DB16

FRAME 2

COMMAND BYTE

ACK. BY

AD56x7

9

STOP BY
MASTER

AD56x7

06342-103

9

ACK. BY

MASTER

ACK. BY

SDA

(CONTINUED)

SCL

SDA

START BY

DB15 DB14 DB13 DB12 DB11 DB10 DB9

FRAME 3

MOST SI GNIFICANT

DATA BYTE

DB8

ACK. BY
MASTER

Figure 55. I

FAST MODE HIGH-SPEED MODE

1919

0 0 0 0 1 X X X 0 0 0 1 1 A1 A0 R/W

MASTER

HS-MODE

MASTER CODE

NO ACK S R

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

FRAME 4

LEAST SI GNIFICANT

2

C Read Operation

DATA BYTE

SERIAL BUS

ADDRESS BYTE

NO ACK.

STOP BY
MASTER

ACK. BY

AD56x7

6342-104

06342-105

Figure 56. Placing the AD5627RBRMZ-2/AD5667RBRMZ-2 in High Speed Mode

Rev. 0 | Page 22 of 32

AD5627R/AD5647R/AD5667R, AD5627/AD5667

INPUT SHIFT REGISTER

The input shift register is 24 bits wide. Data is loaded into the
device as a 24-bit word under the control of a serial clock input,
SCL. The timing diagram for this operation is shown in
The 8 MSBs make up the command byte. DB23 is reserved and
should always be set to 0 when writing to the device. DB22 (S)
is used to select multiple byte operation The next three bits are
the command bits (C2, C1, C0) that control the mode of operation
of the device. See Table 8 for details. The last 3 bits of first byte
are the address bits (A2, A1, A0). See
rest of the bits are the 16-, 14-, 12-bit data word. The data word
comprises the 16-, 14-, 12-bit input code followed by two or four
don’t cares for the AD5647R and the AD5627R/AD5627,
respectively (see

Figure 59 through Figure 61).

Table 9 for details. The

Figure 3.

MULTIPLE BYTE OPERATION

Multiple byte operation is supported on the AD56x7R/AD56x7.
A 2-byte operation is useful for applications that require fast
DAC updating and do not need to change the command byte.
The S bit (DB22) in the command register can be set to 1 for 2­byte mode of operation (see
and 4-byte operation, the S bit (DB22) in the command byte
should be set to 0 (see

Figure 57). For standard 3-byte

Figure 58).

BROADCAST MODE

Broadcast addressing is supported on the AD56x7R/AD56x7.
Broadcast addressing can be used to synchronously update or
power down multiple AD56x7R/AD56x7 devices. Using the
broadcast address, the AD56x7R/AD56x7 responds regardless of
the states of the address pins. Broadcast is supported only in write
mode. The AD56x7R/AD56x7 broadcast address is 00010000.

Table 8. Command Definition

C2 C1 C0 Command

0 0 0 Write to input register n
0 0 1 Update DAC register n
0 1 0

0 1 1 Write to and update DAC channel n
1 0 0 Power up/power down
1 0 1 Reset
1 1 0

1 1 1 Internal reference setup (on/off )

Write to input register n, update all
(software

LDAC register setup

LDAC)

Table 9. DAC Address Command

A2 A1 A0 ADDRESS (n)

0 0 0 DAC A
0 0 1 DAC B
1 1 1 Both DACs

LDAC FUNCTION

The AD56x7R/AD56x7 DACs have double-buffered interfaces
consisting of two banks of registers, input registers and DAC
registers. The input registers are connected directly to the input
shift register, and the digital code is transferred to the relevant
input register on completion of a valid write sequence. The
DAC registers contain the digital codes used by the resistor strings.

LDAC

LDAC

pin.

low

LDAC

Access to the DAC registers is controlled by the
When the
the input registers can change state without affecting the
contents of the DAC registers. When
however, the DAC registers become transparent and the contents
of the input registers are transferred to them. The double-

buffered interface is useful if the user requires simultaneous
updating of all DAC outputs. The user can write to one of the
input registers individually and then, by bringing
when writing to the other DAC input register, all outputs
update simultaneously.

These parts each contain an extra feature whereby a DAC
register is not updated unless its input register has been updated
since the last time
is brought low, the DAC registers are filled with the contents of the
input registers. In the case of the AD56x7R/AD56x7, the DAC
register updates only if the input register has changed since the
last time the DAC register was updated, thereby removing
unnecessary digital crosstalk.

The outputs of all DACs can be simultaneously updated, using
the hardware

LDAC

pin is high, the DAC registers are latched and

LDAC

is brought low,

LDAC

was brought low. Normally, when

LDAC

pin.

Rev. 0 | Page 23 of 32

AD5627R/AD5647R/AD5667R, AD5627/AD5667

SLAVE

ADDRESS

S = 1
COMMAND

BYTE

BLOCK 1

MOST SIG NIFICANT

DATA BYT E

LEAST SI GNIFICANT

DATA BYT E

S = 1

MOST SI GNIFICANT

DATA BYTE

BLOCK 2

LEAST SI GNIFICANT

DATA BYT E

S = 1

MOST SIGNIFICANT

DATA BYTE

BLOCK n

LEAST SIGNIFICANT

DATA BYTE

Figure 57. Multiple Block Write with Initial Command Byte Only (S = 1)

SLAVE

ADDRESS

S = 0
COMMAND

BYTE

BLOCK 1

MOST SIGNIFICANT

DATA BYTE

S = 0

LEAST SIGNIFICANT

DATA BYTE

COMMAND

BYTE

Figure 58. Multiple Block Write with Command Byte in Each Block (S = 0)

BLOCK 2

MOST SI G N I F ICANT

DATA BYTE

LEAST SIGNIF ICANT

DATA BYTE

S = 0
COMMAND

BYTE

BLOCK n

MOST SIGNIFICANT

DATA BYTE

LEAST SIGNIFICANT

DATA BYTE

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

R S

RESERVED

C2 C1 C0 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

COMMAND DAC ADDRESS DAC DATA DAC DATA

BYTE

SELECTION

COMMAND BYTE DATA HIGH BYTE DATA LOW BYTE

Figure 59. AD5667R/AD5667 Input Shift Register (16-Bit DAC)

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

R S

C2 C1 C0 A2 A1 A0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X

STOP

STOP

06342-106

06342-107

06342-108

COMMAND DAC ADDRESS DAC DATA DAC DATA

BYTE

RESERVED

SELECTION

COMMAND BYTE DATA HIGH BYTE DATA LOW BYTE

Figure 60. AD5647R Input Shift Register (14-Bit DAC)

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

R S

RESERVED

C2 C1 C0 A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X

COMMAND DAC ADDRESS DAC DATA DAC DATA

BYTE

SELECTION

COMMAND BYTE DATA HIGH BYT E DATA LOW BYTE

Figure 61. AD5627R/AD5627 Input Shift Register (12-Bit DAC)

06342-109

06342-110

Rev. 0 | Page 24 of 32

AD5627R/AD5647R/AD5667R, AD5627/AD5667

Synchronous

The DAC registers are updated after new data is read in.

LDAC

LDAC

can be permanently low or pulsed.

Asynchronous

LDAC

The outputs are not updated at the same time that the input

LDAC

registers are written to. When

goes low, the DAC

registers are updated with the contents of the input register.

LDAC

The
the hardware

register gives the user full flexibility and control over

LDAC

pin. This register allows the user to select
which combination of channels to simultaneously update when
the hardware

LDAC

pin is executed. Setting the

LDAC

bit

register to 0 for a DAC channel means that the update of this

LDAC

channel is controlled by the

pin. If this bit is set to 1, this
channel synchronously updates, that is, the DAC register is
updated after new data is read in, regardless of the state of the
LDAC

pin. It effectively sees the

See

Table 10 for the

LDAC

LDAC

pin as being pulled low.

register mode of operation. This
flexibility is useful in applications when the user wants to
simultaneously update select channels while the rest of the
channels are synchronously updating.

Writing to the DAC using Command 110 loads the 2-bit

LDAC

register [DB1:DB0]. The default for each channel is 0, that is,

LDAC

the
DAC register is updated, regardless of the state of the
pin. See
the

Table 10.

pin works normally. Setting the bits to 1 means the

Figure 63 for contents of the input shift register during

LDAC

register setup command.

LDAC

Register Mode of Operation:

LDAC

Load DAC Register

Bits

LDAC

Pin

(DB1 to DB0)

LDAC

0 1/0

1 x = don’t care

Operation

LDAC

Determined by

LDAC pin.

The DAC registers are updated
after new data is read in.

POWER-DOWN MODES

Command 100 is reserved for the power-up/down function.
The power-up/down modes are programmed by setting Bit
DB5 and Bit DB4. This defines the output state of the DAC

amplifier, as shown in
to which DAC or DACs the power-up/down command is
applied. Setting one of these bits to 1 applies the power-up/down
state defined by DB5 and DB4 to the corresponding DAC. If a
bit is 0, the state of the DAC is unchanged.
contents of the input shift register for the power up/down
command.

When Bit DB5 and Bit DB4 are set to 0, the part works normally
with its normal power consumption of 400 µA at 5 V. However,
for the three power-down modes, the supply current falls to
480 nA at 5 V. Not only does the supply current fall, but the
output stage is also internally switched from the output of the
amplifier to a resistor network of known values. This allows the
output impedance of the part to be known while the part is in
power-down mode. The outputs can either be connected
internally to GND through a 1 k or 100 k resistor, or left
open-circuited (three-state) as shown in

Table 11. Modes of Operation for the AD56x7R/AD56x7

DB5 DB4 Operating Mode

0 0 Normal operation
Power-down modes
0 1 1 kΩ pull-down to GND
1 0 100 kΩ pull-down to GND
1 1 Three-state, high impedance

RESISTOR

STRING DAC

Figure 62. Output Stage During Power-Down

The bias generator, the output amplifier, the resistor string, and
other associated linear circuitry are shut down when power­down mode is activated. However, the contents of the DAC
register are unaffected when in power-down. The time to exit
power-down is typically 4 µs for V

Table 11. Bit DB1and Bit DB0 determine

Figure 65 shows the

Figure 62.

AMPLIFIER

POWER-DOW N

CIRCUITRY

= 5 V.

DD

RESISTOR
NETWORK

V

OUT

06342-038

R S C2 C1 C0 A2 A1 A0 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 X

RESERVED

1 1 0 A2 A1 A0 X X X X X X X X X X X X X X DACB DACA

COMMAND

CARE

DON’T

DAC ADDRESS

(DON’T CARE)

DON’T CARE DON’T CARE

LDAC

Figure 63.

Rev. 0 | Page 25 of 32

Setup Command

(0 = LDAC PIN ENABL ED)

DAC SELECT

06342-111

AD5627R/AD5647R/AD5667R, AD5627/AD5667

POWER-ON RESET AND SOFTWARE RESET

The AD56x7R/AD56x7 contain a power-on reset circuit that
controls the output voltage during power-up. The device powers
up to 0 V and the output remains powered up at this level until
a valid write sequence is made to the DAC. This is useful in
applications where it is important to know the state of the
output of the DAC while it is in the process of powering up. Any
events on

LDAC

There is also a software reset function. Command 101 is the
software reset command. The software reset command contains
two reset modes that are software programmable by setting Bit
DB0 in the input shift register.

Table 12 shows how the state of the bit corresponds to the
software reset modes of operation of the devices.
shows the contents of the input shift register during the
software reset mode of operation.

Table 12. Software Reset Modes for the AD56x7R/AD56x7

DB0 Registers reset to zero

0 DAC register
Input shift register
1 (Power-On Reset) DAC register
Input shift register

Power-down register
Internal reference setup register

X S C2 C1 C0 A2 A1 A0 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 X

CLR

or

during power-on reset are ignored.

Figure 64

LDAC register

1 0 1 X X X X X X X X X X X X X X X X X X RST

CLEAR PIN (CLR)

The AD56x7R/AD56x7 has an asynchronous clear input. The
CLR

input is falling-edge sensitive. While

CLR

pulses are ignored. When

is activated, zero scale is loaded

CLR

is low, all

LDAC

to all input and DAC registers. This clears the output to 0 V. The

th

part exits clear code mode on the on the falling edge of the 9
clock pulse of the last byte of valid write. If
during a write sequence, the write is aborted. If

CLR

is activated

CLR

is activated
during high speed mode, the part exits high speed mode to
standard/fast mode.

INTERNAL REFERENCE SETUP (R VERSIONS)

The on-chip reference is off at power-up by default. It can be
turned on by sending the reference setup command (111) and
setting DB0 in the input shift register.
state of the bit corresponds to the mode of operation. See
for the contents of the input shift register during the internal
reference setup command.

Table 13. Reference Setup Command

DB0 Action

0 Internal reference off (default)
1 Internal reference on

Table 13 shows how the

Figure 66

COMMAND

CARE

DON’T

RESERVED

DAC ADDRESS

(DON’T CARE)

DON’T CARE DON’T CARE

Figure 64. Software Reset Command

R S C2 C1 C0 A2 A1 A0 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 X

RESERVED

1 0 0 X X X X X X X X X X X X X PD1 PD0 X X DACB DACA

DON’T

CARE

COMMAND

DAC ADDRESS

(DON’T CARE)

DON’T CARE DON’T CARE

Figure 65. Power Up/Down Command

POWER-

DOWN MODE

DON’T CARE

(1 = DAC SELECTED)

R S C2 C1 C0 A2 A1 A0 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 X

RESERVED

1 1 1 X X X X X X X X X X X X X X X X X X REF

COMMAND

CARE

DON’T

DAC ADDRESS

(DON’T CARE)

DON’T CARE DON’T CARE

Figure 66. Reference Setup Command

Rev. 0 | Page 26 of 32

DAC SELECT

MODE

RESET

MODE

REFERENCE

06342-113

06342-112

06342-114

AD5627R/AD5647R/AD5667R, AD5627/AD5667

V

+5V

APPLICATION INFORMATION

USING A REFERENCE AS A POWER SUPPLY FOR THE AD56x7R/AD56x7

Because the supply current required by the AD56x7R/AD56x7 is
extremely low, an alternative option is to use a voltage reference
to supply the required voltage to the part (see Figure 67). This is
especially useful if the power supply is quite noisy, or if the
system supply voltages are at some value other than 5 V or 3 V,
for example, 15 V. The voltage reference outputs a steady supply
voltage for the AD56x7R/AD56x7. If the low dropout REF195 is
used, it must supply 450 μA of current to the AD56x7R/AD56x7
with no load on the output of the DAC. When the DAC output is
loaded, the REF195 also needs to supply the current to the load.
The total current required (with a 5 kΩ load on the DAC
output) is

450 μA + (5 V/5 kΩ) = 1.45 mA

The load regulation of the REF195 is typically 2 ppm/mA,
resulting in a 2.9 ppm (14.5 μV) error for the 1.45 mA current
drawn from it. This corresponds to a 0.191 LSB error.

15

5V

REF195

V

2-WIRE

SERIAL

INTERFACE

Figure 67. REF195 as Power Supply to the AD56x7R/AD56x7

SCL

SDA

BIPOLAR OPERATION USING THE AD56x7R/AD56x7

The AD56x7R/AD56x7 has been designed for single-supply
operation, but a bipolar output range is also possible using the
circuit in Figure 68. The circuit gives an output voltage range of
±5 V. Rail-to-rail operation at the amplifier output is achieved
using an AD820 or an OP295 as the output amplifier.

The output voltage for any input code can be calculated as
follows:

⎡

⎛

×=

VV

⎜

⎢

O

⎣

where

D represents the input code in decimal (0 to 65535).

With V

= 5 V, R1 = R2 = 10 kΩ,

DD

10

⎛

V

⎜

O

⎝

This is an output voltage range of ±5 V, with 0x0000 corre­sponding to a −5 V output, and 0xFFFF corresponding to a
+5 V output.

×=D

536,65

536,65

⎝

⎞

V5

−

⎟
⎠

AD5627R/
AD5647R/
AD5667R/

AD5627/

AD5667

⎞

⎛

×

⎟

⎜
⎝

⎠

DD

GND

R1

V

= 0V TO 5V

OUT

06342-043

⎤

R2R1D

+

⎞
⎟
⎠

R2

⎛

V

DDDD

⎞

×−

⎜

⎟

⎥

R1

⎝

⎠

⎦

R2 = 10kΩ

R1 = 10kΩ

V

0.1µF10µF

Figure 68. Bipolar Operation with the AD56x7R/AD56x7

DD

AD5627R/
AD5647R/
AD5667R/

AD5627/

AD5667

2-WIRE

SERIAL

INTERFACE

V

OUT

SDASCLGND

+5V

AD820/
OP295

–5V

V
±5V

O

06342-044

POWER SUPPLY BYPASSING AND GROUNDING

When accuracy is important in a circuit, it is helpful to carefully
consider the power supply and ground return layout on the
board. The printed circuit board containing the AD56x7R/AD56x7
should have separate analog and digital sections, each having its
own area of the board. If the AD56x7R/AD56x7 are in a system
where other devices require an AGND to DGND connection, the
connection should be made at one point only. This ground point
should be as close as possible to the AD56x7R/AD56x7.

The power supply to the AD56x7R/AD56x7 should be bypassed
with 10 μF and 0.1 μF capacitors. The capacitors should be
located as close as possible to the device, with the 0.1 μF capacitor
ideally right up against the device. The 10 μF capacitor should be
the tantalum bead type. It is important that the 0.1 μF capacitor
have low effective series resistance (ESR) and effective series
inductance (ESI), for example, common ceramic types of
capacitors. This 0.1 μF capacitor provides a low impedance path
to ground for high frequencies caused by transient currents due
to internal logic switching.

The power supply line itself should have as large a trace as
possible to provide a low impedance path and to reduce glitch
effects on the supply line. Clocks and other fast switching
digital signals should be shielded from other parts of the board
by digital ground. Avoid crossover of digital and analog signals
if possible. When traces cross on opposite sides of the board,
ensure that they run at right angles to each other to reduce
feedthrough effects through the board. The best board layout
technique is the microstrip technique where the component
side of the board is dedicated to the ground plane only and the
signal traces are placed on the solder side. However, this is not
always possible with a two-layer board.

Rev. 0 | Page 27 of 32

AD5627R/AD5647R/AD5667R, AD5627/AD5667

S

OUTLINE DIMENSIONS

INDEX

1.50

BCS SQ

0.80

0.75

0.70

EATING

PLANE

AREA

3.00

BSC SQ

TOP VIEW

SIDE VIEW

0.30

0.23

0.18

0.80 MAX

0.55 TYP

0.50

BSC

0.50

0.40

0.30

0.20 REF

0.05 MAX

0.02 NOM

Figure 69. 10-Lead Lead Frame Chip Scale Package [LFCSP_WD]

3 mm x 3 mm Body, Very Very Thin, Dual Lead

(CP-10-9)

Dimensions shown in millimeters

3.10

3.00

2.90

6

10

3.10

3.00

2.90

1

PIN 1

0.50 BSC

0.95

0.85

0.75

0.15

0.05

0.33

0.17

COPLANARITY

0.10

COMPLIANT TO JEDEC STANDARDS MO-187-BA

Figure 70. 10-Lead Mini Small Outline Package [MSOP]

5.15

4.90

4.65

5

1.10 MAX

SEATING
PLANE

0.23

0.08

(RM-10)

Dimensions shown in millimeters

10

EXPOSED

(BOTTOM VIEW)

6

8°
0°

PIN 1
INDICATOR

PAD

1.74

1.64

1.49

1

2.48

2.38

2.23

5

0.80

0.60

0.40

Rev. 0 | Page 28 of 32

AD5627R/AD5647R/AD5667R, AD5627/AD5667

ORDERING GUIDE

Temperature

Model

AD5627BCPZ-R2

1

−40°C to +105°C ±1 LSB INL None 400 kHz 10-Lead LFCSP_WD CP-10 -9 DA1

Range

Accuracy

AD5627BCPZ-REEL71 −40°C to +105°C ±1 LSB INL None 400 kHz 10-Lead LFCSP_WD CP-10-9 DA1
AD5627BRMZ1 −40°C to +105°C ±1 LSB INL None 400 kHz 10-Lead MSOP RM-10 DA1
AD5627BRMZ-REEL71 −40°C to +105°C ±1 LSB INL None 400 kHz 10-Lead MSOP RM-10 DA1
AD5627RBCPZ-R21 −40°C to +105°C ±1 LSB INL 1.25 V 400 kHz 10-Lead LFCSP_WD CP-10-9 D9J
AD5627RBCPZ-REEL71 −40°C to +105°C ±1 LSB INL 1.25 V 400 kHz 10-Lead LFCSP_WD CP-10-9 D9J
AD5627RBRMZ-11 −40°C to +105°C ±1 LSB INL 2.5 V 400 kHz 10-Lead MSOP RM-10 DA7
AD5627RBRMZ-1REEL71 −40°C to +105°C ±1 LSB INL 2.5 V 400 kHz 10-Lead MSOP RM-10 DA7
AD5627RBRMZ-21 −40°C to +105°C ±1 LSB INL 2.5 V 3.4 MHz 10-Lead MSOP RM-10 DA8
AD5627RBRMZ-2REEL71 −40°C to +105°C ±1 LSB INL 2.5 V 3.4 MHz 10-Lead MSOP RM-10 DA8
AD5647RBCPZ-R21 −40°C to +105°C ±4 LSB INL 1.25 V 400 kHz 10-Lead LFCSP_WD RU-14 D9G
AD5647RBCPZ-REEL71 −40°C to +105°C ±4 LSB INL 1.25 V 400 kHz 10-Lead LFCSP_WD RU-14 D9G
AD5647RBRMZ1 −40°C to +105°C ±4 LSB INL 2.5 V 400 kHz 10-Lead MSOP RM-10 D9G
AD5647RBRMZ-REEL71 −40°C to +105°C ±4 LSB INL 2.5 V 400 kHz 10-Lead MSOP RM-10 D9G
AD5667BCPZ-R21 −40°C to +105°C ±12 LSB INL None 400 kHz 10-Lead LFCSP_WD CP-10-9 D9Z
AD5667BCPZ-REEL71 −40°C to +105°C ±12 LSB INL None 400 kHz 10-Lead LFCSP_WD CP-10-9 D9Z
AD5667BRMZ1 −40°C to +105°C ±12 LSB INL None 400 kHz 10-Lead MSOP RM-10 D9Z
AD5667BRMZ-REEL71 −40°C to +105°C ±12 LSB INL None 400 kHz 10-Lead MSOP RM-10 D9Z
AD5667RBCPZ-R21 −40°C to +105°C ±12 LSB INL 1.25 V 400 kHz 10-Lead LFCSP_WD CP-10-9 D8X
AD5667RBCPZ-REEL71 −40°C to +105°C ±12 LSB INL 1.25 V 400 kHz 10-Lead LFCSP_WD CP-10-9 D8X
AD5667RBRMZ-11 −40°C to +105°C ±12 LSB INL 2.5 V 400 kHz 10-Lead MSOP RM-10 DA5
AD5667RBRMZ-1REEL71 −40°C to +105°C ±12 LSB INL 2.5 V 400 kHz 10-Lead MSOP RM-10 DA5
AD5667RBRMZ-21 −40°C to +105°C ±12 LSB INL 2.5 V 3.4 MHz 10-Lead MSOP RM-10 DA6
AD5667RBRMZ-2REEL71 −40°C to +105°C ±12 LSB INL 2.5 V 3.4 MHz 10-Lead MSOP RM-10 DA6
EVAL-AD5667REBZ1 Evaluation Board

1

Z = Pb-free part.

On-Chip
Reference

Max I
Speed

2

C

Package
Description

Package
Option

Branding

Rev. 0 | Page 29 of 32

AD5627R/AD5647R/AD5667R, AD5627/AD5667

NOTES

Rev. 0 | Page 30 of 32

AD5627R/AD5647R/AD5667R, AD5627/AD5667

NOTES

Rev. 0 | Page 31 of 32

AD5627R/AD5647R/AD5667R, AD5627/AD5667

NOTES

Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent
Rights to use these components in an I

2

C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.

©2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06342-0-1/07(0)

Rev. 0 | Page 32 of 32