Datasheet AD5624 Datasheet (ANALOG DEVICES)

2.7 V to 5.5 V, 450 μA, Rail-to-Rail Output,

FEATURES

Low power, quad nanoDACs

AD5664: 16 bits

AD5624: 12 bits
Relative accuracy: ±12 LSBs max
Guaranteed monotonic by design
10-lead MSOP and 3 mm × 3 mm LFCSP_WD

2.7 V to 5.5 V power supply
Power-on reset to zero
Per channel power-down
Serial interface, up to 50 MHz

APPLICATIONS

Process control
Data acquisition systems
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators

Quad, 12-/16-Bit nanoDACs

AD5624/AD5664

FUNCTIONAL BLOCK DIAGRAM

SCLK

SYNC

V

DD

INPUT

REGISTER

INTERFACE

LOGIC

DIN

INPUT

REGISTER

INPUT

REGISTER

INPUT

REGISTER

POWER-ON

RESET

GND

REGISTER

REGISTER

REGISTER

REGISTER

Figure 1.

Table 1. Related Devices

Part No. Description

AD5624R/AD5644R/AD5664R

V

REF

AD5624/AD5664

STRING

DAC

DAC

DAC

DAC

DAC A

STRING

DAC B

STRING

DAC C

STRING

DAC D

BUFFER

BUFFER

BUFFER

BUFFER

POWER-DOWN

LOGIC

2.7 V to 5.5 V quad, 12-, 14-,
16-bit DACs with internal
reference

®

V

A

OUT

V

B

OUT

V

C

OUT

V

D

OUT

05943-001

GENERAL DESCRIPTION

The AD5624/AD5664, members of the nanoDAC family, are
low power, quad, 12-, 16-bit buffered voltage-out DACs that
operate from a single 2.7 V to 5.5 V supply and are guaranteed
monotonic by design.

The AD5624/AD5664 require an external reference voltage to
set the output range of the DAC. The part incorporates a power­on reset circuit that ensures the DAC output powers up to 0 V
and remains there until a valid write takes place. The parts
contain a power-down feature that reduces the current
consumption of the device to 480 nA at 5 V and provides
software-selectable output loads while in power-down mode.

The low power consumption of these parts in normal operation
makes them ideally suited to portable battery-operated
equipment. The power consumption is 2.25 mW at 5 V, going
down to 2.4 µW in power-down mode.

The AD5624/AD5664 on-chip precision output amplifier allows
rail-to-rail output swing to be achieved.

The AD5624/AD5664 use a versatile 3-wire serial interface that
operates at clock rates up to 50 MHz, and are compatible with
standard SPI®, QSPI™, MICROWIRE™, and DSP interface
standards.

PRODUCT HIGHLIGHTS

1. Relative accuracy: ±12 LSBs maximum.

2. Available in 10-lead MSOP and 10-lead, 3 mm × 3 mm,

LFCSP_WD.

3. Low power, typically consumes 1.32 mW at 3 V and

2.25 mW at 5 V.

4. Maximum settling time of 4.5 s (AD5624) and 7 s

(AD5664).

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2006 Analog Devices, Inc. All rights reserved.

AD5624/AD5664

TABLE OF CONTENTS

Features.............................................................................................. 1

Serial Interface............................................................................ 15

Applications....................................................................................... 1

Functional Block Diagram ..............................................................1

General Description......................................................................... 1

Product Highlights........................................................................... 1

Specifications..................................................................................... 3

AC Characteristics........................................................................ 4

Timing Characteristics ................................................................ 5

Timing Diagram........................................................................... 5

Absolute Maximum Ratings............................................................ 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

Typical Performance Characteristics............................................. 8

Terminology .................................................................................... 13

Theory of Operation ......................................................................15

D/A Section................................................................................. 15

Resistor String............................................................................. 15

Output Amplifier........................................................................ 15

Input Shift Register .................................................................... 16

SYNC

Interrupt ..........................................................................16

Power-On Reset.......................................................................... 16

Software Reset............................................................................. 17

Power-Down Modes .................................................................. 17

LDAC Function ..........................................................................18

Microprocessor Interfacing....................................................... 19

Applications..................................................................................... 20

Choosing a Reference for the AD5624/AD5664.................... 20

Using a Reference as a Power Supply for the

AD5624/AD5664........................................................................ 20

Bipolar Operation Using the AD5624/AD5664..................... 21

Using AD5624/AD5664 with a Galvanically Isolated

Interface....................................................................................... 21

Power Supply Bypassing and Grounding................................ 21

Outline Dimensions....................................................................... 22

Ordering Guide .......................................................................... 22

REVISION HISTORY

6/06—Revision 0: Initial Version

Rev. 0 | Page 2 of 24

AD5624/AD5664

SPECIFICATIONS

VDD = +2.7 V to +5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; V

Table 2.

A Grade

1

Parameter Min Typ Max Min Typ Max Unit Conditions/Comments

STATIC PERFORMANCE

2

AD5664

Resolution 16 16 Bits
Relative Accuracy ±8 ±16 ±6 ±12 LSB
Differential Nonlinearity ±1 ±1 LSB

AD5624

Resolution 12 Bits
Relative Accuracy ±0.5 ±1 LSB
Differential Nonlinearity ±0.25 LSB

Zero-Code Error 2 10 2 10 mV

Offset Error ±1 ±10 ±1 ±10 mV
Full-Scale Error −0.1 ±1 −0.1 ±1 % of FSR All ones loaded to DAC register
Gain Error ±1.5 ±1.5 % of FSR
Zero-Code Error Drift ±2 ±2 μV/°C
Gain Temperature

±2.5 ±2.5 ppm of FSR/°C

Coefficient

DC Power Supply Rejection

−100 −100 dB

Ratio

DC Crosstalk 10 10 μV

10 10 μV/mA Due to load current change
5 5 μV

OUTPUT CHARACTERISTICS

3

Output Voltage Range 0 VDD 0 VDD V

Capacitive Load Stability 2 2 nF RL = ∞

10 10 nF RL = 2 kΩ

DC Output Impedance 0.5 0.5 Ω

Short-Circuit Current 30 30 mA VDD = 5 V

Power-Up Time 4 4

REFERENCE INPUTS

Reference Current 170 200 170 200 μA V

Reference Input Range 0.75 VDD 0.75 VDD V

Reference Input Impedance 26 26 kΩ

LOGIC INPUTS

3

Input Current ±2 ±2 μA All digital inputs

V

, Input Low Voltage 0.8 0.8 V VDD = 5 V, 3 V

INL

V

, Input High Voltage 2 2 V VDD = 5 V, 3 V

INH

Pin Capacitance 3 3 pF

= VDD; all specifications T

REF

B Grade

1

MIN

to T

, unless otherwise noted.

MAX

Guaranteed monotonic by
design

Guaranteed monotonic by
design

All zeroes loaded to DAC
register

DAC code = midscale ; V
10%

Due to full-scale output
change
RL = 2 kΩ to GND or VDD

Due to powering down (per
channel)

μs

Coming out of power-down
mode; V

DD

= 5 V

= VDD = 5.5 V

REF

±

DD

Rev. 0 | Page 3 of 24

AD5624/AD5664

A Grade

1

B Grade

1

Parameter Min Typ Max Min Typ Max Unit Conditions/Comments

POWER REQUIREMENTS

VDD 2.7 5.5 2.7 5.5 V

IDD (Normal Mode)

4

V

= VDD, VIL = GND

IH

VDD = 4.5 V to 5.5 V 0.45 0.9 0.45 0.9 mA
VDD = 2.7 V to 3.6 V 0.44 0.85 0.44 0.85 mA

IDD (All Power-Down

Modes)

5

V

= VDD, VIL = GND

IH

VDD = 4.5 V to 5.5 V 0.48 1 0.48 1 μA
VDD = 2.7 V to 3.6 V 0.2 1 0.2 1 μA

1

Temperature range: A grade and B grade: −40°C to +105°C.

2

Linearity calculated using a reduced code range: AD5664 (Code 512 to Code 65,024); AD5624 (Code 32 to Code 4064); output unloaded.

3

Guaranteed by design and characterization, not production tested.

4

Interface inactive. All DACs active. DAC outputs unloaded.

5

All DACs powered down.

AC CHARACTERISTICS

VDD = 2.7 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; V

Table 3.

Parameter

2, 3

Min Typ Max Unit Conditions/Comments

Output Voltage Settling Time

AD5664 4 7 μs ¼ to ¾ scale settling to ±2 LSB

AD5624 3 4.5 μs ¼ to ¾ scale settling to ±0.5 LSB
Slew Rate 1.8 V/μs
Digital-to-Analog Glitch Impulse 10 nV-s 1 LSB change around major carry
Digital Feedthrough 0.1 nV-s
Reference Feedthrough −90 dBs V
Digital Crosstalk 0.1 nV-s
Analog Crosstalk 1 nV-s
DAC-to-DAC Crosstalk 1 nV-s
Multiplying Bandwidth 340 kHz V
Total Harmonic Distortion −80 dB V
Output Noise Spectral Density 120 nV/√Hz DAC code = midscale, 1 kHz
100 nV/√Hz DAC code = midscale, 10 kHz
Output Noise 15

1

Guaranteed by design and characterization, not production tested.

2

Temperature range: −40°C to +105°C; typical at 25°C.

3

See the Terminology section.

= VDD; all specifications T

REF

μV p-p

to T

MIN

= 2 V ± 0.1 V p-p, frequency 10 Hz to 20 MHz

REF

= 2 V ± 0.1 V p-p

REF

= 2 V ± 0.1 V p-p, frequency = 10 kHz

REF

, unless otherwise noted.

MAX

0.1 Hz to 10 Hz

1

Rev. 0 | Page 4 of 24

AD5624/AD5664

TIMING CHARACTERISTICS

All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2 (see Figure 2).
V

= 2.7 V to 5.5 V; all specifications T

DD

Table 4.

Limit at T
Parameter

2

t

1

1

VDD = 2.7 V to 5.5 V Unit Conditions/Comments

20 ns min SCLK cycle time
t2 9 ns min SCLK high time
t3 9 ns min SCLK low time
t4 13 ns min

t5 5 ns min Data setup time
t6 5 ns min Data hold time
t7 0 ns min

t8 15 ns min
t9 13 ns min
t10 0 ns min

1

Guaranteed by design and characterization, not production tested.

2

Maximum SCLK frequency is 50 MHz at VDD = 2.7 V to 5.5 V.

MIN

MIN

, T

to T

MAX

, unless otherwise noted.

MAX

SYNC to SCLK falling edge setup time

SCLK falling edge to
Minimum

SYNC high time

SYNC rising edge

SYNC rising edge to SCLK fall ignore
SCLK falling edge to

SYNC fall ignore

TIMING DIAGRAM

SCLK

SYNC

DIN

t

10

t

8

t

4

t

6

t

5

t

1

t

t

3

2

t

9

t

7

DB0DB23

05943-002

Figure 2. Serial Write Operation

Rev. 0 | Page 5 of 24

AD5624/AD5664

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 5.

Parameter Rating

VDD to GND −0.3 V to +7 V
V

to GND −0.3 V to VDD + 0.3 V

OUT

V

to GND −0.3 V to VDD + 0.3 V

REF

Digital Input Voltage to GND −0.3 V to VDD + 0.3 V
Operating Temperature Range

Industrial (A Grade, B Grade) −40°C to +105°C
Storage Temperature Range −65°C to +150°C
Junction Temperature (TJ max) 150°C

Power Dissipation (TJ max − TA)/θJA
LFCSP_WD Package (4-Layer Board)

θJA Thermal Impedance 61°C/W
MSOP Package (4-Layer Board)

θJA Thermal Impedance 142°C/W

θJC Thermal Impedance 43.7°C/W
Reflow Soldering Peak Temperature

Pb-Free 260°C ± 5°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. 0 | Page 6 of 24

AD5624/AD5664

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

V

A

OUT

V

OUT

GND

V

OUT

V

OUT

2

B

3

4

C

5

D

AD5624/

AD5664

TOP VIEW

(Not to Scale)

10

V

REF

9

V

DD

8

DIN

7

SCLK

6

SYNC

5943-003

Figure 3. Pin Configuration

Table 6. Pin Function Descriptions

Pin No. Mnemonic Description

1 V
2 V

A Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.

OUT

B Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.

OUT

3 GND Ground Reference Point for All Circuitry on the Part.
4 V
5 V
6

C Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.

OUT

D Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.

OUT

SYNC Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it

powers on the SCLK and DIN buffers and enables the input shift register. Data is transferred in on the falling edges
of the next 24 clocks. If

SYNC is taken high before the 24th falling edge, the rising edge of SYNC acts as an interrupt

and the write sequence is ignored by the device.

7 SCLK

Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can
be transferred at rates up to 50 MHz.

8 DIN

Serial Data Input. This device has a 24-bit input shift register. Data is clocked into the register on the falling edge of
the serial clock input.

9 VDD

Power Supply Input. These parts can be operated from 2.7 V to 5.5 V. The supply should be decoupled with a 10 μF
capacitor in parallel with a 0.1 μF capacitor to GND.

10 V

Reference Voltage Input.

REF

Rev. 0 | Page 7 of 24

AD5624/AD5664

TYPICAL PERFORMANCE CHARACTERISTICS

10

VDD = V

8

T

6

4

2

0

–2

INL ERROR (LSB)

–4

–6

–8

–10

0 5k 10k 15k 20k 25k 30k 35k 40k 45k 50k 55k 60k 65k

= 25°C

A

REF

= 5V

CODE

Figure 4. INL AD5664

1.0
VDD = V

T

0.8

0.6

0.4

0.2

0

–0.2

INL ERROR (LSB)

–0.4

–0.6

–0.8

–1.0

0 500 1000 1500 2000 2500 3000 3500 4000

= 25°C

A

REF

= 5V

CODE

Figure 5. INL AD5624

1.0

VDD = V
T

0.8

0.6

0.4

0.2

0

–0.2

DNL ERROR (LSB)

–0.4

–0.6

–0.8

–1.0

0 10k 20k 30k 40k 50k 60k

= 25°C

A

REF

= 5V

CODE

Figure 6. DNL AD5664

05943-004

05943-005

05943-006

0.20
VDD = V

T

0.15

0.10

0.05

0

–0.05

DNL ERROR (LSB)

–0.10

–0.15

–0.20

0 500 1000 1500 2000 2500 3000 3500 4000

= 25°C

A

REF

= 5V

CODE

Figure 7. DNL AD5624

8

6

V

= V

= 5V

DD

4

2

0

ERROR (LSB)

–2

–4

–6

–8

–40 –20 40200 1008060

REF

TEMPERATURE (°C)

Figure 8. INL Error and DNL Error vs. Temperature

10

8

6

= 5V

V

DD

4

= 25°C

T

A

2

0

–2

ERROR (LSB)

–4

–6

–8

–10

0.75 1.25 1.75 2.25 4.253.753.252. 75 4.75

Figure 9. INL and DNL Error vs. V

V

(V)

REF

REF

05943-007

MAX INL

MAX DNL

MIN DNL

MIN INL

05856-022

MAX INL

MAX DNL

MIN DNL

MIN INL

05943-009

Rev. 0 | Page 8 of 24

AD5624/AD5664

C

8

6

= 25°C

T

A

4

2

0

ERROR (LSB)

–2

–4

–6

–8

2.7 3.2 3.7 4.74.2 5.2
VDD (V)

MAX INL

MAX DNL

MIN DNL

MIN INL

Figure 10. INL and DNL Error vs. Supply

0

VDD = 5V

–0.02

–0.04

–0.06

–0.08

–0.10

–0.12

ERROR (% F SR)

–0.14

–0.16

–0.18

–0.20

–40 –20 40200 1008060

GAIN ERROR

FULL-SCALE ERROR

TEMPERATURE (°C)

Figure 11. Gain Error and Full-Scale Error vs. Temperature

1.5

1.0

0.5

ZERO-SCALE ERROR

05943-010

05943-011

1.0

0.5

GAIN ERROR

0

–0.5

ERROR (% FSR)

–1.0

–1.5

–2.0

FULL-SCAL E ERROR

2.7 3. 2 3.7 4.74.2 5.2
VDD (V)

Figure 13. Gain Error and Full-Scale Error vs. Supply

1.0
= 25°C

T

A

0.5

0

–0.5

–1.0

ERROR (mV)

–1.5

–2.0

–2.5

2.7 3.2 4.23.7 5.24.7

ZERO-SCALE ERROR

VDD (V)

Figure 14. Zero-Scale Error and Offset Error vs. Supply

VDD= 5.5V

6

= 25°C

T

A

5

05943-013

OFFSET ERROR

05943-014

0

–0.5

ERROR (mV)

–1.0

–1.5

OFFSET ERROR

–2.0

–2.5

–40 –20 40200860 100

TEMPERATURE (°C)

0

Figure 12. Zero-Scale Error and Offset Error vs. Temperature

05943-012

Y

4

3

FREQUEN

2

1

0

0.41 0.42 0.43 0.44 0.45

Figure 15. I

IDD (mA)

Histogram with VDD = 5.5 V

DD

05943-017

Rev. 0 | Page 9 of 24

AD5624/AD5664

8

VDD= 3.6V
T

= 25°C

A

7

6

5

4

FREQUENCY

3

2

1

0

0.39 0.40 0.41 0.42 0.43

Figure 16. I

0.20
VDD= V

T

0.15

0.10

0.05

0

–0.05

–0.10

ERROR VOLTAGE (V)

–0.15

–0.20

–0.25

–5 –4 –3 –2 –1 0 1 2 435

= 5V, 3V

REF

= 25°C

A

DAC LOADED WITH
FULL SCALE –
SOURCING CURRENT

IDD (mA)

Histogram with VDD = 3.6 V

DD

DAC LOADED WITH
ZERO SCALE –
SINKING CURRENT

I (mA)

Figure 17. Headroom at Rails vs. Source and Sink Current

0.50

0.45

0.40

0.35

0.30

0.25

(mA)

DD

I

0.20

0.15

0.10

0.05
TA = 25°C

0

–40 –20 0 20 40 60 80 100

= V

V

DD

REFIN

V

= V

DD

REFIN

TEMPERATURE ( °C)

= 5V

= 3V

Figure 18. Supply Current vs. Temperature

VDD = V
T
FULL-SCALE CODE CHANGE
0x0000 TO 0xFFFF
OUTPUT L OADED WIT H 2kΩ
AND 200pF TO G ND

V

= 909mV/DIV

OUT

1

05943-018

TIME BASE = 4µs/DIV

= 25°C

A

REF

= 5V

05943-021

Figure 19. Full-Scale Settling Time, 5 V

VDD = V
T

V

1

2

05943-016

DD

V

OUT

CH1 2.0V CH2 500mV M100µ s 125MS/s

A CH1 1.28V

= 25°C

A

= 5V

REF

MAX(C2)

420.0mV

8.0ns/p t

05943-022

Figure 20. Power-On Reset to 0 V

SYNC

1

3

2

05943-026

CH1 5.0V
CH3 5.0V

SLCK

V

OUT

CH2 500mV M400ns A CH1 1.4V

VDD = 5V

05943-023

Figure 21. Exiting Power-Down to Midscale

Rev. 0 | Page 10 of 24

AD5624/AD5664

–

√

2.538

2.537

2.536

2.535

2.534

2.533

2.532

2.531

(V)

2.530

2.529

OUT

V

2.528

2.527

2.526

2.525

2.524

2.523

2.522

2.521
0 50 100 150 350 400200 250 300 450 512

VDD= V
T
5ns/SAMPL E NUMBER
GLITCH IMPULSE = 9.494nV
1LSB CHANGE AROUND
MIDSCALE (0x8000 TO 0x7FFF)

SAMPLE NUMBER

= 25°C

A

REF

= 5V

Figure 22. Digital-to-Analog Glitch Impulse (Negative)

(V)

V

OUT

2.498

2.497

2.496

2.495

2.494

2.493

VDD= V
T
5ns/SAMPL E NUMBER
ANALOG CROS STALK = 0.424nV

= 25°C

A

REF

= 5V

05943-024

16

V

= V

REF

DD

TA = 25°C

14

V

3V

=

12

10

TIME (µs)

8

6

4

012 34 567 981

CAPACITANCE (nF)

DD

V

5V

=

DD

Figure 25. Settling Time vs. Capacitive Load

VDD = V
T
DAC LOADED WITH MIDSCALE

1

= 25°C

A

REF

= 5V

05943-028

0

2.492

2.491
0 50 100 150 350 400200 250 300 450 512

SAMPLE NUMBER

Figure 23. Analog Crosstalk

20

VDD = 5V
T

= 25°C

A

–30

DAC LOADED WIT H FULL SCALE
V

= 2V ± 0.3V p -p

REF

–40

–50

–60

(dB)

–70

–80

–90

–100

2k 4k 6k 8k 10k

(Hz)

Figure 24. Total Harmonic Distortion

05943-025

Y AXIS = 2µV/DIV
X AXIS = 4s/DIV

05943-029

Figure 26. 0.1 Hz to 10 Hz Output Noise Plot

800

VDD = V
T

700

600

Hz)

500

400

300

OUTPUT NOISE (nV/

200

100

05943-027

0

10 100k10k1k100 1M

= 25°C

A

REF

= 5V

FREQUENCY (Hz)

05943-030

Figure 27. Noise Spectral Density

Rev. 0 | Page 11 of 24

AD5624/AD5664

5

0

–5

–10

–15

(dB)

–20

–25

–30

–35

–40

10k 100k 1M 10M

FREQUENCY (Hz)

Figure 28. Multiplying Bandwidth

VDD = 5V
T

= 25°C

A

05943-031

Rev. 0 | Page 12 of 24

AD5624/AD5664

TERMINOLOGY

Relative Accuracy or Integral Nonlinearity (INL)

For the DAC, relative accuracy or integral nonlinearity is a
measurement of the maximum deviation, in LSBs, from a
straight line passing through the endpoints of the DAC transfer
function. A typical INL vs. code plot can be seen in
and

Figure 5.

Figure 4

Differential Nonlinearity (DNL)

Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ±1 LSB maximum
ensures monotonicity. This DAC is guaranteed monotonic by
design. A typical DNL vs. code plot can be seen in

Figure 6 and

Figure 7.

Zero-Scale Error

Zero-scale error is a measurement of the output error when
zero code (0x0000) is loaded to the DAC register. Ideally, the
output should be 0 V. The zero-code error is always positive in
the AD5624/AD5664 because the output of the DAC cannot go
below 0 V. It is due to a combination of the offset errors in the
DAC and the output amplifier. Zero-code error is expressed in
mV. A plot of zero-code error vs. temperature can be seen in
Figure 12.

Full-Scale Error

Full-scale error is a measurement of the output error when full­scale code (0xFFFF) is loaded to the DAC register. Ideally, the
output should be V

− 1 LSB. Full-scale error is expressed in %

DD

of FSR. A plot of full-scale error vs. temperature can be seen in
Figure 11.

Gain Error

This is a measure of the span error of the DAC. It is the
deviation in slope of the DAC transfer characteristic from ideal
expressed as a % of FSR.

Zero-Code Error Drift

This is a measurement of the change in zero-code error with a
change in temperature. It is expressed in µV/°C.

Gain Temperature Coefficient

This is a measurement of the change in gain error with changes
in temperature. It is expressed in ppm of FSR/°C.

Offset Error

Offset error is a measure of the difference between V
and V

(ideal) expressed in mV in the linear region of the

OUT

(actual)

OUT

transfer function. Offset error is measured on the AD5624/
AD5664 with code 512 loaded in the DAC register. It can be
negative or positive.

DC Power Supply Rejection Ratio (PSRR)

This indicates how the output of the DAC is affected by changes
in the supply voltage. PSRR is the ratio of the change in V
a change in V
in dB. V

for full-scale output of the DAC. It is measured

DD

is held at 2 V, and VDD is varied by ±10%.

REF

OUT

to

Output Voltage Settling Time

This is the amount of time it takes for the output of a DAC to
settle to a specified level for a ¼ to ¾ full-scale input change
and is measured from the 24

th

falling edge of SCLK.

Digital-to-Analog Glitch Impulse

Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nV-s,
and is measured when the digital input code is changed by
1 LSB at the major carry transition (0x7FFF to 0x8000) as
shown in

Figure 22.

Digital Feedthrough

Digital feedthrough is a measure of the impulse injected into
the analog output of the DAC from the digital inputs of the
DAC, but is measured when the DAC output is not updated. It
is specified in nV-s, and measured with a full-scale code change
on the data bus, that is, from all 0s to all 1s and vice versa.

Total Harmonic Distortion (THD)

This is the difference between an ideal sine wave and its
attenuated version using the DAC. The sine wave is used as the
reference for the DAC, and the THD is a measurement of the
harmonics present on the DAC output. It is measured in dB.

Noise Spectral Density

This is a measurement of the internally generated random
noise. Random noise is characterized as a spectral density
(nV/√Hz). It is measured by loading the DAC to midscale and
measuring noise at the output. It is measured in nV/√Hz. A plot
of noise spectral density can be seen in

Figure 27.

DC Crosstalk

DC crosstalk is the dc change in the output level of one DAC in
response to a change in the output of another DAC. It is
measured with a full-scale output change on one DAC (or soft
power-down and power-up) while monitoring another DAC kept
at midscale. It is expressed in V.

DC crosstalk due to load current change is a measure of the
impact that a change in load current on one DAC has to
another DAC kept at midscale. It is expressed in V/mA.

Rev. 0 | Page 13 of 24

AD5624/AD5664

Digital Crosstalk

This is the glitch impulse transferred to the output of one DAC
at midscale in response to a full-scale code change (all 0s to all
1s and vice versa) in the input register of another DAC. It is
measured in standalone mode and is expressed in nV-s.

Analog Crosstalk

This is the glitch impulse transferred to the output of one DAC
due to a change in the output of another DAC. It is measured by
loading one of the input registers with a full-scale code change
(all 0s to all 1s and vice versa). Then execute a software LDAC
and monitor the output of the DAC whose digital code was
not changed. The area of the glitch is expressed in nV-s (see
Figure 23).

DAC-to-DAC C rosst a l k

This is the glitch impulse transferred to the output of one DAC
due to a digital code change and subsequent analog output
change of another DAC. It is measured by loading the attack
channel with a full-scale code change (all 0s to all 1s and vice
versa) using the command write to and update while
monitoring the output of the victim channel that is at midscale.
The energy of the glitch is expressed in nV-s.

Multiplying Bandwidth

The amplifiers within the DAC have a finite bandwidth. The
multiplying bandwidth is a measure of this. A sine wave on the
reference (with full-scale code loaded to the DAC) appears on
the output. The multiplying bandwidth is the frequency at
which the output amplitude falls to 3 dB below the input.

Rev. 0 | Page 14 of 24

AD5624/AD5664

V

THEORY OF OPERATION

D/A SECTION

The AD5624/AD5664 DACs are fabricated on a CMOS process.
The architecture consists of a string DAC followed by an output
buffer amplifier.

Figure 29 shows a block diagram of the DAC

architecture.

DAC

REGISTER

DD

REF (+)

RESISTOR

STRING

REF (–)

GND

Figure 29. DAC Architecture

OUTPUT
AMPLIFIER
(GAIN = +2)

V

OUT

05943-032

Since the input coding to the DAC is straight binary, the ideal
output voltage is given by

D

⎞

⎛

OUT

VV

REFIN

×=

⎟

⎜

N

2

⎠

⎝

where:
D is the decimal equivalent of the binary code that is loaded to

the DAC register:

0 to 4095 for AD5624 (12 bit).
0 to 65535 for AD5664 (16 bit).

N is the DAC resolution.

RESISTOR STRING

The resistor string is shown in Figure 30. It is simply a string of
resistors, each of value R. The code loaded to the DAC register
determines at which node on the string the voltage is tapped off
to be fed into the output amplifier. The voltage is tapped off by
closing one of the switches connecting the string to the
amplifier. Because it is a string of resistors, it is guaranteed
monotonic.

OUTPUT AMPLIFIER

The output buffer amplifier can generate rail-to-rail voltages on
its output, which gives an output range of 0 V to V
a load of 2 kΩ in parallel with 1000 pF to GND. The source and
sink capabilities of the output amplifier can be seen in
The slew rate is 1.8 V/µs with a ¼ to ¾ full-scale settling time of
7 µs.

. It can drive

DD

Figure 17.

SERIAL INTERFACE

The AD5624/AD5664 have a 3-wire serial interface (
SCLK, and DIN) that is compatible with SPI, QSPI, and

MICROWIRE interface standards as well as with most DSPs.
See

Figure 2 for a timing diagram of a typical write sequence.

The write sequence begins by bringing the
from the DIN line is clocked into the 24-bit shift register on the

falling edge of SCLK. The serial clock frequency can be as high
as 50 MHz, making the AD5624/AD5664 compatible with high
speed DSPs. On the 24
clocked in and the programmed function is executed, that is, a
change in DAC register contents and/or a change in the mode
of operation. At this stage, the

brought high. In either case, it must be brought high for a
minimum of 15 ns before the next write sequence so that a
falling edge of

the

SYNC
does when V
write sequences for even lower power operation. It must,
however, be brought high again just before the next write

sequence.

R

R

R

R

R

Figure 30. Resistor String

th

falling clock edge, the last data bit is

can initiate the next write sequence. Since

SYNC

TO OUTPUT
AMPLIFIER

SYNC

line can be kept low or be

SYNC

5943-033

,

SYNC

line low. Data

buffer draws more current when VIN = 2.0 V than it

= 0.8 V,

IN

should be idled low between

SYNC

Rev. 0 | Page 15 of 24

AD5624/AD5664

S

INPUT SHIFT REGISTER

The input shift register is 24 bits wide The first two bits are
don’t care bits. The next three bits are the Command bits, C2 to
C0 (see
(see
comprises the 16-, 12- bit input code followed by 0 or 4 don’t
care bits for the AD5664 and AD5624 respectively (see
31
register on the 24

Table 7. Command Definition

C2 C1 C0 Command

0 0 0 Write to input register n
0 0 1 Update DAC register n
0 1 0

0 1 1 Write to and update DAC channel n
1 0 0 Power down DAC (power-up)
1 0 1 Reset
1 1 0 Load LDAC register
1 1 1 Reserved

Table 8. Address Command

A2 A1 A0 ADDRESS (n)

0 0 0 DAC A

Table 7), followed by the 3-bit DAC address, A2 to A0

Table 8), and then the 16-, 12-bit data-word. The data-word

Figure

and Figure 32). These data bits are transferred to the DAC

th

falling edge of SCLK.

Write to input register n, update all
(software LDAC)

SYNC INTERRUPT

In a normal write sequence, the
24 falling edges of SCLK, and the DAC is updated on the 24

falling edge. However, if

SYNC

falling edge, then this acts as an interrupt to the write sequence.
The input shift register is reset and the write sequence is seen as
invalid. Neither an update of the DAC register contents nor a
change in the operating mode occurs (see

line is kept low for at least

SYNC

th

is brought high before the 24th

Figure 33).

POWER-ON RESET

The AD5624/AD5664 family contains a power-on reset circuit
that controls the output voltage during power-up. The AD5624/
AD5664 DAC outputs power up to 0 V and the output remains
there until a valid write sequence is made to the DAC. This is
useful in applications where it is important to know the state of
the output of the DAC while it is in the process of powering up.

0 0 1 DAC B
0 1 0 DAC C
0 1 1 DAC D
1 1 1 All DACs

DB23 (MSB) DB0 (LSB)

X X C2 C1 C0 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

COMMAND BITS ADDRESS BITS

Figure 31. AD5664 Input Shift Register Contents

DB23 (MSB) DB0 (LSB)

X X C2 C1 C0 A2 A1 A0 XXXXD11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

COMMAND BITS ADDRESS BITS

Figure 32. AD5624 Input Shift Register Contents

SCLK

YNC

DIN

DB23 DB23 DB0DB0

INVALID WRITE SEQUENCE:

SYNC HIGH BEFORE 24

TH

FALLING EDGE

Figure 33.

SYNC

Interrupt Facility

DATA BIT S

DATA BITS

VALID WRITE SEQUENCE, OUTPUT UPDATES

ON THE 24

TH

FALLING EDGE

05943-034

05943-035

05943-036

Rev. 0 | Page 16 of 24

AD5624/AD5664

SOFTWARE RESET

The AD5624/AD5664 contain a software reset function.
Command 110 is reserved for the software reset function (see
Table 7). The software reset command contains two reset modes
that are software programmable by setting Bit DB0 in the
control register.

Table 9 shows how the state of the bit
corresponds to the software reset modes of operation of the
devices.

Table 9. Software Reset Modes for the AD5624/AD5664

DB0 Registers Reset to Zero

0 DAC register
Input shift register
1 (Power-On Reset) DAC register
Input shift register
LDAC register
Power-down register

POWER-DOWN MODES

The AD5624/AD5664 contain four separate modes of operation.
Command 100 is reserved for the power-down function (see
Table 7). These modes are software programmable by setting two
bits (DB5 and DB4) in the control register.
the state of the bits corresponds to the mode of operation of the
device. All DACs (DAC D to DAC A) can be powered down to
the selected mode by setting the corresponding four bits (DB3,
DB2, DB1, and DB0) to 1. By executing the same Command 100,
any combination of DACs is powered up by setting Bit DB5 and
Bit DB4 to normal operation mode. To select which combination
of DAC channels to power-up, set the corresponding four bits
(DB3, DB2, DB1, and DB0) to 1. See
input shift register during the power-down/power-up operation.

Table 10 shows how

Table 11 for contents of the

Table 10. Modes of Operation for the AD5624/AD5664

DB5 DB4 Operating Mode

0 0 Normal operation
Power-down modes
0 1 1 kΩ to GND
1 0 100 kΩ to GND
1 1 Three-state

When both bits are set to 0, the parts work normally with their
normal power consumption of 450 µA at 5 V. However, for the
three power-down modes, the supply current falls to 480 nA at
5 V (200 nA at 3 V). Not only does the supply current fall, but
the output stage is also internally switched from the output of
the amplifier to a resistor network of known values. This allows
the output impedance of the part to be known while the part is
in power-down mode.

The outputs can either be connected internally to GND through
a 1 kΩ or 100 kΩ resistor, or left open-circuited (three-state)
(see

Figure 34).

RESISTOR

STRING DAC

Figure 34. Output Stage During Power-Down

AMPLI FIER

POWER-DOW N

CIRCUITRY

RESISTOR
NETWORK

V

OUT

05943-037

The bias generator, the output amplifier, the resistor string, and
other associated linear circuitry are shut down when power­down mode is activated. However, the contents of the DAC
register are unaffected when in power-down. The time to exit
power-down is typically 4 µs for V
(see

Figure 21).

= 5 V and for VDD = 3 V

DD

Table 11. 24-Bit Input Shift Register Contents of Power-Down/Power-Up Operation

DB23 to
DB22 (MSB) DB21 DB20 DB19 DB18 DB17 DB16

DB15
to DB6 DB5 DB4 DB3 DB2 DB1

DB0
(LSB)

x 1 0 0 x x x x PD1 PD0 DAC D DAC C DAC B DAC A

Don’t care Command bits (C2 to C0)

Address bits (A2 to A0); don’t
care

Don’t
care

Power­down mode

Power-down/power-up channel
selection, set bit to 1 to select
channel

Rev. 0 | Page 17 of 24

AD5624/AD5664

LDAC FUNCTION

The AD5624/AD5664 DACs have double-buffered interfaces
consisting of two banks of registers: input registers and DAC
registers. The input registers are connected directly to the input
shift register and the digital code is transferred to the relevant
input register on completion of a valid write sequence. The
DAC registers contain the digital code used by the resistor
strings.

The double-buffered interface is useful if the user requires
simultaneous updating of all DAC outputs. The user can write
to three of the input registers individually and then write to the
remaining input register and update all DAC registers, the
outputs update simultaneously. Command 010 is reserved for
this software LDAC.

Access to the DAC registers is controlled by the LDAC
function. The LDAC registers contain two modes of operation
for each DAC channel. The DAC channels are selected by
setting the bits of the 4-bit LDAC register (DB3, DB2, DB1, and
DB0). Command 110 is reserved for setting up the LDAC
register. When the LDAC bit register is set low, the
corresponding DAC registers are latched and the input
registers can change state without affecting the contents of the

DAC registers. When the LDAC bit register is set high,
however, the DAC registers become transparent and the
contents of the input registers are transferred to them on the
falling edge of the 24

LDAC

an

hardware pin tied permanently low for the selected
DAC channel, that is, synchronous update mode. See
for the LDAC register mode of operation. See

th

SCLK pulse. This is equivalent to having

Table 12

Table 13 for
contents of the input shift register during the LDAC register set­up command.

This flexibility is useful in applications where the user wants to
update select channels simultaneously, while the rest of the
channels update synchronously.

Table 12. LDAC Register Mode of Operation

Load DAC Register
LDAC Bits

(DB3 to DB0)

0

1

LDAC Mode of Operation

Normal operation (default), DAC register
update is controlled by write command.

The DAC registers are updated after new
data is read in on the falling edge of the

th

SCLK pulse.

24

Table 13. 24-Bit Input Shift Register Contents for LDAC Setup Command for the AD5624/AD5664

DB23 to
DB22
(MSB)

x 1 1 0 x x x x DacD DacC DacB DacA

Don’t Care Command bits (C2 to C0) Address bits (A3 to A0); don’t care

DB21

DB20

DB19

DB18

DB17

DB16

DB15 to
DB4

Don’t
cares

DB3

Set bit to 0 or 1 for required mode of
operation on respective channel

DB2

DB1

DB0
(LSB)

Rev. 0 | Page 18 of 24

AD5624/AD5664

MICROPROCESSOR INTERFACING

AD5624/AD5664 to Blackfin® ADSP-BF53x Interface

Figure 35 shows a serial interface between the AD5624/AD5664 and

the Blackfin ADSP-BF53x microprocessor. The ADSP-BF53x
processor family incorporates two dual-channel synchronous serial
ports, SPORT1 and SPORT0, for serial and multiprocessor commu­nications. Using SPORT0 to connect to the AD5624/AD5664, the
setup for the interface is as follows. DTOPRI drives the DIN pin of
the AD5624/AD5664, while TSCLK0 drives the SCLK of the part.
The

AD5624/AD5664 to 68HC11/68L11 Interface

Figure 36 shows a serial interface between the AD5624/AD5664
and the 68HC11/68L11 microcontroller. SCK of the 68HC11/
68L11 drives the SCLK of the AD5624/AD5664, while the
MOSI output drives the serial data line of the DAC.

The
conditions for correct operation of this interface are as follows.

The 68HC11/68L11 is configured with its CPOL bit as a 0 and
its CPHA bit as a 1. When data is being transmitted to the DAC,
the

configured as described previously, data appearing on the MOSI
output is valid on the falling edge of SCK. Serial data from the
68HC11/68L11 is transmitted in 10-bit bytes with only eight
falling clock edges occurring in the transmit cycle. Data is
transmitted MSB first. To load data to the AD5624/AD5664,
PC7 is left low after the first eight bits are transferred, and a
second serial write operation is performed to the DAC; PC7 is
taken high at the end of this procedure.

is driven from TFS0.

SYNC

ADSP-BF53x

1

ADDITIONAL PINS OMITTED FO R CLARITY.

Figure 35. Blackfin ADSP-BF53x Interface to AD5624/AD5664

signal is derived from a port line (PC7). The setup

SYNC

line is taken low (PC7). When the 68HC11/68L11 is

SYNC

68HC11/68L11

1

TFS0

1

PC7

AD5624/

AD5664

SYNC

DINDTOPRI

SCLKTSCLK0

AD5624/

AD5664

SYNC

SCLKSCK

DINMOSI

1

1

05943-038

AD5624/AD5664 to 80C51/80L51 Interface

Figure 37 shows a serial interface between the AD5624/AD5664
and the 80C51/80L51 microcontroller. The setup for the interface
is as follows. TxD of the 80C51/80L51 drives SCLK of the
AD5624/AD5664, while RxD drives the serial data line of the
part. The

signal is derived from a bit-programmable pin

SYNC

on the port. In this case, port line P3.3 is used. When data is
transmitted to the AD5624/AD5664, P3.3 is taken low. The
80C51/80L51 transmits data in 10-bit bytes only; thus only eight
falling clock edges occur in the transmit cycle. To load data to the
DAC, P3.3 is left low after the first eight bits are transmitted, and
a second write cycle is initiated to transmit the second byte of
data. P3.3 is taken high following the completion of this cycle.
The 80C51/80L51 output the serial data in a format that has the
LSB first. The AD5624/AD5664 must receive data with the MSB
first. The 80C51/80L51 transmit routine should take this into
account.

80C51/80L51

1

ADDITIONAL PINS OMITTED FOR CLARITY.

Figure 37. 80C51/80L51 Interface to AD5624/AD5664

1

P3.3

AD5624/
AD5664

SYNC

SCLKTxD

DINRxD

1

05943-040

AD5624/AD5664 to MICROWIRE Interface

Figure 38 shows an interface between the AD5624/AD5664 and
any MICROWIRE-compatible device. Serial data is shifted out
on the falling edge of the serial clock and is clocked into the
AD5624/AD5664 on the rising edge of the SK.

MICROWIRE

1

ADDITIONAL PINS OMITTED FOR CLARITY.

Figure 38. MICROWIRE Interface to AD5624/AD5664

1

CS

AD5624/
AD5664

SYNC

SCLKSK

DINSO

1

05943-041

1

ADDITIONAL PINS OMITTED FOR CLARITY.

Figure 36. 68HC11/68L11 Interface to AD5624/AD5664

05943-039

Rev. 0 | Page 19 of 24

AD5624/AD5664

V

APPLICATIONS

CHOOSING A REFERENCE FOR THE AD5624/AD5664

To achieve the optimum performance from the AD5624/
AD5664, thought should be given to the choice of a precision
voltage reference. The AD5624/AD5664 have only one
reference input, V
to supply the positive input to the DAC. Therefore, any error in
the reference is reflected in the DAC.

When choosing a voltage reference for high accuracy applica­tions, the sources of error are initial accuracy, ppm drift, long­term drift, and output voltage noise. Initial accuracy on the
output voltage of the DAC leads to a full-scale error in the DAC.
To minimize these errors, a reference with high initial accuracy
is preferred. Choosing a reference with an output trim
adjustment, such as the
trim out system errors by setting a reference voltage to a voltage
other than the nominal. The trim adjustment can also be used
at temperature to trim out any error.

Long-term drift is a measurement of how much the reference
drifts over time. A reference with a tight long-term drift
specification ensures that the overall solution remains relatively
stable during its entire lifetime.

The temperature coefficient of a reference’s output voltage
affects INL, DNL, and TUE. A reference with a tight temperature
coefficient specification should be chosen to reduce temperature
dependence of the DAC output voltage in ambient conditions.

In high accuracy applications, which have a relatively low noise
budget, reference output voltage noise needs to be considered. It
is important to choose a reference with as low an output noise
voltage as practical for the system noise resolution required.
Precision voltage references such as the
output noise in the 0.1 Hz to10 Hz range. Examples of recom­mended precision references for use as supply to the
AD5624/AD5664 are shown in the

. The voltage on the reference input is used

REF

ADR423, allows a system designer to

ADR425 produce low

Table 1 4.

USING A REFERENCE AS A POWER SUPPLY FOR THE AD5624/AD5664

Because the supply current required by the AD5624/AD5664 is
extremely low, an alternative option is to use a voltage reference
to supply the required voltage to the part (see
especially useful if the power supply is quite noisy, or if the
system supply voltages are at some value other than 5 V or 3 V,
for example, 15 V. The voltage reference outputs a steady supply
voltage for the AD5624/AD5664 (see
reference). If the low dropout

Table 14 for a suitable

REF195 is used, it must supply

450 µA of current to the AD5624/AD5664, with no load on the
output of the DAC. When the DAC output is loaded, the

REF195 also needs to supply the current to the load. The total

current required (with a 5 kΩ load on the DAC output) is

450 µA + (5 V/5 kΩ) = 1.45 mA

The load regulation of the

REF195 is typically 2 ppm/mA,

which results in a 2.9 ppm (14.5 µV) error for the 1.45 mA
current drawn from it. This corresponds to a 0.191 LSB error.

15

REF195

3-WIRE

SERIAL

INTERFACE

Figure 39. REF195 as Power Supply to the AD5624/AD5664

SYNC

SCLK

DIN

5V

V

DD

AD5624/

AD5664

Figure 39). This is

500mA

V

REF

V

OUT

= 0V TO 5V

05943-042

Table 14. Partial List of Precision References for Use with the AD5624/AD5664

Part No. Initial Accuracy (mV max)

Temp Drift (ppmoC max)

0.1 Hz to 10 Hz Noise (μV p-p typ)

V

OUT

(V)

ADR425 ±2 3 3.4 5
ADR395 ±6 25 5 5
REF195 ±2 5 50 5
AD780 ±2 3 4 2.5/3
ADR423 ±2 3 3.4 3

Rev. 0 | Page 20 of 24

AD5624/AD5664

BIPOLAR OPERATION USING THE AD5624/AD5664

The AD5624/AD5664 have been designed for single-supply
operation, but a bipolar output range is also possible using the
circuit in

Figure 40. The circuit gives an output voltage range of
±5 V. Rail-to-rail operation at the amplifier output is achievable
using an

AD820 or an OP295 as the output amplifier.

The output voltage for any input code can be calculated as
follows:

⎡

⎛

VV

×=

⎜

⎢

O

⎝

⎣

⎞
⎟

536,65

⎠

R2R1D

+

R1

⎞

V

⎟

DDDD

⎠

⎛

×

⎜
⎝

⎤

R2

⎞

⎛

×−

⎟

⎜

⎥

R1

⎠

⎝

⎦

where D represents the input code in decimal (0 to 65536).
With V

= 5 V, R1 = R2 = 10 kΩ,

DD

×

D

10

⎛

=

V

⎜

O

⎝

⎞

V5

−

⎟

536,65

⎠

This is an output voltage range of ±5 V, with 0x0000 corre­sponding to a −5 V output, and 0xFFFF corresponding to a
+5 V output.

R2 = 10kΩ

+5V

0.1µF10µF

Figure 40. Bipolar Operation with the AD5624/AD5664

R1 = 10kΩ

V

DDVOUT

AD5624/

AD5664

3-WIRE
SERIAL

INTERFACE

+5V

AD820/

OP295

–5V

±5V

05943-043

USING AD5624/AD5664 WITH A GALVANICALLY ISOLATED INTERFACE

In process control applications in industrial environments, it is
often necessary to use a galvanically isolated interface to protect
and isolate the controlling circuitry from any hazardous
common-mode voltages that might occur in the area where the
DAC is functioning. Isocouplers provide isolation in excess of
3 kV. The AD5624/AD5664 use a 3-wire serial logic interface,
so the ADuM130x 3-channel digital isolator provides the
required isolation (see
also needs to be isolated, which is done by using a transformer.
On the DAC side of the transformer, a 5 V regulator provides
the 5 V supply required for the AD5624/AD5664.

Figure 41). The power supply to the part

POWER

SCLK

DATA

Figure 41. AD5624/AD5664 with a Galvanically Isolated Interface

SDI

V1A

ADuM1300

V1B

V1C

VOA

VOB

VOC

POWER SUPPLY BYPASSING AND GROUNDING

When accuracy is important in a circuit, it is helpful to consider
carefully the power supply and ground return layout on the
board. The printed circuit board containing the AD5624/
AD5664 should have separate analog and digital sections, each
having its own area of the board. If the AD5624/AD5664 is in a
system where other devices require an AGND-to-DGND
connection, the connection should be made at one point only.
This ground point should be as close as possible to the
AD5624/AD5664.

The power supply to the AD5624/AD5664 should be bypassed
with 10 µF and 0.1 µF capacitors. The capacitors should be
located as close as possible to the device, with the 0.1 µF capacitor
ideally right up against the device. The 10 µF capacitor is the
tantalum bead type. It is important that the 0.1 µF capacitor has
low effective series resistance (ESR) and effective series
inductance (ESI), for example, common ceramic types of
capacitors. This 0.1 µF capacitor provides a low impedance path
to ground for high frequencies caused by transient currents due
to internal logic switching.

The power supply line itself should have as large a trace as
possible to provide a low impedance path and to reduce glitch
effects on the supply line. Clocks and other fast switching
digital signals should be shielded from other parts of the board
by digital ground. Avoid crossover of digital and analog signals
if possible. When traces cross on opposite sides of the board,
ensure that they run at right angles to each other to reduce
feedthrough effects through the board. The best board layout
technique is the microstrip technique where the component
side of the board is dedicated to the ground plane only and the
signal traces are placed on the solder side. However, this is not
always possible with a 2-layer board.

5V

REGULATOR

SCLK

SYNC

DIN

V

DD

AD5624/

AD5664

GND

V

10µF

OUT

0.1µF

05943-044

Rev. 0 | Page 21 of 24

AD5624/AD5664

S

OUTLINE DIMENSIONS

INDEX

1.50

BCS SQ

0.80

0.75

0.70

EATING

PLANE

AREA

3.00

BSC SQ

TOP VIEW

SIDE VIEW

0.30

0.23

0.18

0.80 MAX

0.55 TYP

0.50

BSC

0.50

0.40

0.30

0.05 MAX

0.02 NOM

0.20 REF

10

Figure 42. 10-Lead Lead Frame Chip Scale Package [LFCSP_WD]

3 mm × 3 mm Body, Very Very Thin, Dual Lead

(CP-10-9)

Dimensions shown in millimeters

3.10

3.00

2.90

6

0.95

0.85

0.75

3.10

3.00

2.90

0.15

0.05

PIN 1

10

1

0.50 BSC

0.33

0.17

COPLANARITY

0.10

COMPLIANT TO JEDEC STANDARDS MO-187-BA

5.15

4.90

4.65

5

1.10 MAX

SEATING
PLANE

0.23

0.08

Figure 43. 10-Lead Mini Small Outline Package [MSOP]

(RM-10)

Dimensions shown in millimeters

EXPOSED

PAD

(BOTTOM VIEW)

6

1.74

1.64

1.49

8°
0°

PIN 1
INDICATOR

1

5

0.80

0.60

0.40

2.48

2.38

2.23

ORDERING GUIDE

Model

AD5624BRMZ −40°C to +105°C ±1 LSB INL 10-Lead MSOP RM-10 D5J
AD5624BRMZ-REEL7 −40°C to +105°C ±1 LSB INL 10-Lead MSOP RM-10 D5J
AD5624BCPZ-250RL7 −40°C to +105°C ±1 LSB INL 10-Lead LFCSP_WD CP-10-9 D5J
AD5624BCPZ-REEL7 −40°C to +105°C ±1 LSB INL 10-Lead LFCSP_WD CP-10-9 D5J
AD5664ARMZ −40°C to +105°C ±16 LSB INL 10-Lead MSOP RM-10 D7C
AD5664ARMZ-REEL7 −40°C to +105°C ±16 LSB INL 10-Lead MSOP RM-10 D7C
AD5664BRMZ −40°C to +105°C ±12 LSB INL 10-Lead MSOP RM-10 D78
AD5664BRMZ-REEL7 −40°C to +105°C ±12 LSB INL 10-Lead MSOP RM-10 D78
AD5664BCPZ-250RL7 −40°C to +105°C ±12 LSB INL 10-Lead LFCSP_WD CP-10-9 D78
AD5664BCPZ-REEL7 −40°C to +105°C ±12 LSB INL 10-Lead LFCSP_WD CP-10-9 D78

Temperature Range

Accuracy

Rev. 0 | Page 22 of 24

Package
Description

Package
Option

Branding

AD5624/AD5664

NOTES

Rev. 0 | Page 23 of 24

AD5624/AD5664

NOTES

©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05943-0-6/06(0)

Rev. 0 | Page 24 of 24