Datasheet AD5620, AD5640, AD5660 Datasheet (ANALOG DEVICES)

Single, 12-/14-/16-Bit nanoDAC with

5 ppm/°C On-Chip Reference in SOT-23

FEATURES

Low power, single nanoDACs

AD5660: 16 bits
AD5640: 14 bits

AD5620: 12 bits
12-bit accuracy guaranteed
On-chip, 1.25 V/2.5 V, 5 ppm/°C reference
Tiny 8-lead SOT-23/MSOP packages
Power-down to 480 nA @ 5 V, 200 nA @ 3 V
3 V/5 V single power supply
Guaranteed 16-bit monotonic by design
Power-on reset to zero/midscale
3 power-down functions
Serial interface with Schmitt-triggered inputs
Rail-to-rail operation

interrupt facility

SYNC

APPLICATIONS

Process control
Data acquisition systems
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators

PRODUCT HIGHLIGHTS

1. 12-/14-/16-bit nanoDAC—12-bit accuracy guaranteed.

2. On-chip, 1.25 V/2.5 V, 5 ppm/°C reference.

3. Available in 8-lead SOT-23 and 8-lead MSOP packages.

4. Power-on reset to 0 V or midscale.

5. 10 μs settling time.

Table 1. Related Device

Part No. Description

AD5662

2.7 V to 5.5 V, 16-bit DAC in SOT-23, external
reference

AD5620/AD5640/AD5660

FUNCTIONAL BLOCK DIAGRAM

V

REFOUT

POWER-ON

RESET

DAC

REGISTER

INPUT

CONTROL

LOGIC

SYNC SCLK DIN

1.25/2.5V
REF

REF(+)

16-BIT

DAC

POWER-DOWN

CONTROL LOGIC

GENERAL DESCRIPTION

The AD5620/AD5640/AD5660, members of the nanoDAC™
family of devices, are low power, single, 12-/14-/16-bit, buffered
voltage-out DACs and are guaranteed monotonic by design.

The AD5620/AD5640/AD5660-1 parts include an internal,

1.25 V, 5 ppm/°C reference, giving a full-scale output voltage
range of 2.5 V. The AD5620/AD5640/AD5660-2-3 parts include
an internal, 2.5 V, 5 ppm/°C reference, giving a full-scale output
voltage range of 5 V. The reference associated with each part is
available at the V

The parts incorporate a power-on reset circuit to ensure that the
DAC output powers up to 0 V (AD5620/AD5640/AD5660-1-2)
or midscale (AD5620-3 and AD5660-3) and remains there until
a valid write takes place. The parts contain a power-down
feature that reduces the current consumption of the device to
480 nA at 5 V and provides software-selectable output loads
while in power-down mode. The power consumption is

2.5 mW at 5 V, reducing to 1 μW in power-down mode.

The AD5620/AD5640/AD5660 on-chip precision output
amplifier allows rail-to-rail output swing to be achieved. For
remote sensing applications, the output amplifier’s inverting
input is available to the user. The AD5620/AD5640/AD5660 use
a versatile 3-wire serial interface that operates at clock rates up
to 30 MHz and is compatible with standard SPI®, QSPI™,
MICROWIRE™, and DSP interface standards.

REFOUT

pin.

V

GND

DD

AD5620/AD5640/AD5660

OUTPUT
BUFFER

Figure 1.

RESISTOR
NETWORK

V

FB

V

OUT

04539-001

Rev. F

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2005–2010 Analog Devices, Inc. All rights reserved.

AD5620/AD5640/AD5660

TABLE OF CONTENTS

Features .............................................................................................. 1

Internal Reference ...................................................................... 17

Applications ....................................................................................... 1 

Product Highlights ........................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

AD5620/AD5640/AD5660-2-3 .................................................. 3

AD5620/AD5640/AD5660-1 ...................................................... 5

Timing Characteristics ................................................................ 7

Absolute Maximum Ratings ............................................................ 8

ESD Caution .................................................................................. 8

Pin Configurations and Function Descriptions ........................... 9

Typical Performance Characteristics ........................................... 10

Terminology .................................................................................... 16

Theory of Operation ...................................................................... 17

Output Amplifier ........................................................................ 17

Serial Interface ............................................................................ 17

Input Shift Register .................................................................... 18

Interrupt .......................................................................... 18

SYNC

Power-On Reset .......................................................................... 19

Power-Down Modes .................................................................. 19

Microprocessor Interfacing ....................................................... 19

Applications Information .............................................................. 21

Using a REF19x as a Power Supply for the

AD5620/AD5640/AD5660 ....................................................... 21

Bipolar Operation Using the AD5660 ..................................... 21

Using the AD5660 as an Isolated, Programmable, 4 mA to

20 mA Process Controller ......................................................... 22

Using the AD5620/AD5640/AD5660 with a Galvanically

Isolated Interface ........................................................................ 22

Power Supply Bypassing and Grounding ................................ 23







D/A Section ................................................................................. 17

Resistor String ............................................................................. 17

REVISION HISTORY

12/10—Rev. E to Rev. F

Changes to Ordering Guide .......................................................... 25

7/10—Rev. D to Rev. E

Moved Using the AD5660 as an Isolated, Programmable, 4 mA

to 20 mA Process Controller Section ........................................... 22

Moved Power Supply Bypassing and Grounding Section ......... 23

Changes to Ordering Guide .......................................................... 25

3/10—Rev. C to Rev. D

Changes to Ordering Guide .......................................................... 24

10/09—Rev. B to Rev. C

Changes to Ordering Guide .......................................................... 23

Outline Dimensions ....................................................................... 24

Ordering Guide .......................................................................... 25

5/06—Rev. A to Rev. B

Updated Formatted ............................................................ Universal

Updated Temperature Range ............................................ Universal

Changes to Table 2 ............................................................................. 3

Changes to Table 5 ............................................................................. 8

Replaced Figure 17, Figure 18, and Figure 19 ............................. 12

Changes to Ordering Guides .................................................. 23, 24

9/05—Rev. 0 to Rev. A

Changes to Specifications ................................................................. 5

Changes to Outline Dimensions .................................................. 23

7/05—Revision 0: Initial Version

Rev. F | Page 2 of 28

AD5620/AD5640/AD5660

SPECIFICATIONS

AD5620/AD5640/AD5660-2-3

VDD = 4.5 V to 5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, C

Table 2.

Parameter A Grade1 B Grade1 C Grade1 Unit Conditions/Comments

STATIC PERFORMANCE2

AD5660

Resolution 16 16 16 Bits min
Relative Accuracy ±32 ±16 ±16 LSB max
Differential Nonlinearity ±1 ±1 ±1 LSB max Guaranteed monotonic by design

AD5640

Resolution 14 14 14 Bits min
Relative Accuracy ±8 ±4 ±4 LSB max
Differential Nonlinearity ±0.5 ±0.5 ±0.5 LSB max Guaranteed monotonic by design

AD5620

Resolution 12 12 12 Bits min
Relative Accuracy ±6 ±1 ±1 LSB max

Differential Nonlinearity ±0.25 ±0.25 ±0.25 LSB max Guaranteed monotonic by design
Zero-Code Error 2 2 2 mV typ All 0s loaded to DAC register
10 10 10 mV max
Offset Error ±10 ±10 ±10 mV max
Full-Scale Error −0.15 −0.15 −0.15 % FSR typ All 1s loaded to DAC register
±1 ±1 ±1 % FSR max
Gain Error ±1.5 ±1.5 ±1.5 % FSR max
Zero-Code Error Drift ±2 ±2 ±2 μV/°C typ
Gain Temperature Coefficient ±2.5 ±2.5 ±2.5 ppm typ Of FSR/°C
DC Power Supply Rejection Ratio −75 −75 −75 dB typ DAC code = midscale; VDD = 5 V ± 10%

OUTPUT CHARACTERISTICS3

Output Voltage Range 0 0 0 V min
V

V

DD

V

DD

Output Voltage Settling Time 8 8 8 μs typ ¼ to ¾ scale change settling to ±2 LSB
10 10 10 μs max RL = 2 kΩ; 0 pF < CL < 200 pF
Slew Rate 1.5 1.5 1.5 V/μs typ ¼ to ¾ scale
Capacitive Load Stability 2 2 2 nF typ RL = ∞
10 10 10 nF typ RL = 2 kΩ
Output Noise Spectral Density 80 80 80 nV/√Hz typ DAC code = midscale, 10 kHz
Output Noise (0.1 Hz to 10 Hz) 45 45 45 μV p-p typ DAC code = midscale
Digital-to-Analog Glitch Impulse 5 5 5 nV-s typ 1 LSB change around major carry
Digital Feedthrough 0.1 0.1 0.1 nV-s typ
DC Output Impedance 0.5 0.5 0.5 Ω typ
Short-Circuit Current 30 30 30 mA typ VDD = 5 V
Power-Up Time 5 5 5 μs typ Coming out of power-down mode; VDD = 5 V

REFERENCE OUTPUT

Output Voltage 2.495 2.495 2.495 V min At ambient

2.505 2.505 2.505 V max
Reference TC3 ±10 ±10 ±5 ppm/°C typ
±10 ppm/°C max
Output Impedance 7.5 7.5 7.5 kΩ typ

= 100 nF; all specifications T

REFOUT

V max

DD

MIN

to T

, unless otherwise noted.

MAX

Rev. F | Page 3 of 28

AD5620/AD5640/AD5660

Parameter A Grade1 B Grade1 C Grade1 Unit Conditions/Comments

LOGIC INPUTS3

Input Current ±2 ±2 ±2 μA max All digital inputs
V

, Input Low Voltage 0.8 0.8 0.8 V max VDD = 5 V

INL

V

, Input High Voltage 2 2 2 V min VDD = 5 V

INH

Pin Capacitance 3 3 3 pF typ

POWER REQUIREMENTS

VDD 4.5 4.5 4.5 V min All digital inputs at 0 V or VDD

5.5 5.5 5.5 V max DAC active and excluding load current
IDD (Normal Mode)

VDD = 4.5 V to 5.5 V 0.55 0.55 0.55 mA typ VIH = VDD and VIL = GND
VDD = 4.5 V to 5.5 V 1 1 1 mA max VIH = VDD and VIL = GND

IDD (All Power-Down Modes)

VDD = 4.5 V to 5.5 V 0.48 0.48 0.48 μA typ VIH = VDD and VIL = GND
VDD = 4.5 V to 5.5 V 1 1 1 μA max VIH = VDD and VIL = GND

1

Temperature range is −40°C to +105°C, typical at +25°C.

2

Linearity calculated using a reduced code range: AD5660 (Code 511 to Code 65024); AD5640 (Code 128 to Code 16256); AD5620 (Code 32 to Code 4064). Output

unloaded. Linearity tested with VDD = 5.5 V. If part is operated with a VDD < 5 V, the output is clamped to V

3

Guaranteed by design and characterization; not production tested.

DD.

Rev. F | Page 4 of 28

AD5620/AD5640/AD5660

AD5620/AD5640/AD5660-1

1

V

= 2.7 V to 3.3 V, RL = 2 kΩ to GND, CL = 200 pF to GND, C

DD

Table 3.

Parameter A Grade2 B Grade2 C Grade2 Unit Conditions/Comments

STATIC PERFORMANCE3

AD5660

Resolution 16 16 16 Bits min

Relative Accuracy ±32 ±16 ±16 LSB max

Differential Nonlinearity ±1 ±1 ±1 LSB max Guaranteed monotonic by design
AD5640

Resolution 14 14 14 Bits min

Relative Accuracy ±8 ±4 ±4 LSB max

Differential Nonlinearity ±0.5 ±0.5 ±0.5 LSB max Guaranteed monotonic by design
AD5620

Resolution 12 12 12 Bits min

Relative Accuracy ±6 ±1 ±1 LSB max

Differential Nonlinearity ±0.25 ±0.25 ±0.25 LSB max Guaranteed monotonic by design
Zero-Code Error 2 2 2 mV typ All 0s loaded to DAC register
8 8 8 mV max
Offset Error ±9 ±9 ±9 mV max
Full-Scale Error ±0.15 ±0.15 ±0.15 % FSR typ All 1s loaded to DAC register
±0.85 ±0.85 ±0.85 % FSR max
Gain Error ±0.85 ±0.85 ±0.85 % FSR max
Zero-Code Error Drift ±2 ±2 ±2 μV/°C typ
Gain Temperature Coefficient ±2.5 ±2.5 ±2.5 ppm typ Of FSR/°C
DC Power Supply Rejection Ratio −60 −60 −60 dB typ DAC code = midscale; VDD = 3 V ± 10%

OUTPUT CHARACTERISTICS4

Output Voltage Range 0 0 V min
V

V

DD

V

DD

Output Voltage Settling Time 8 8 8 μs typ ¼ to ¾ scale change settling to ±2 LSB
10 10 10 μs max RL = 2 kΩ; 0 pF < CL < 200 pF
Slew Rate 1.5 1.5 1.5 V/μs typ ¼ to ¾ scale
Capacitive Load Stability 2 2 2 nF typ RL = ∞
10 10 10 nF typ RL = 2 kΩ
Output Noise Spectral Density 80 80 80 nV/√Hz typ DAC code = midscale, 10 kHz
Output Noise (0.1 Hz to 10 Hz) 20 20 20 μV p-p typ DAC code = midscale
Digital-to-Analog Glitch Impulse 5 5 5 nV-s typ 1 LSB change around major carry
Digital Feedthrough 0.1 0.1 0.1 nV-s typ
DC Output Impedance 0.5 0.5 0.5 Ω typ
Short-Circuit Current 30 30 30 mA typ VDD = 3 V
Power-Up Time 6 6 6 μs typ Coming out of power-down mode; VDD = 3 V

REFERENCE OUTPUT

Output Voltage 1.247 1.247 1.247 V min At ambient

1.253 1.253 1.253 V max
Reference TC4 ±10 ±10 ±5 ppm/°C typ
±15 ppm/°C max
Output Impedance 7.5 7.5 7.5 kΩ typ

= 100 nF; all specifications T

REFOUT

V max

DD

MIN

to T

, unless otherwise noted.

MAX

Rev. F | Page 5 of 28

AD5620/AD5640/AD5660

Parameter A Grade2 B Grade2 C Grade2 Unit Conditions/Comments

LOGIC INPUTS4

Input Current ±1 ±1 ±1 μA max All digital inputs
V

, Input Low Voltage 0.8 0.8 0.8 V max VDD = 3 V

INL

V

, Input High Voltage 2 2 2 V min VDD = 3 V

INH

Pin Capacitance 3 3 3 pF max

POWER REQUIREMENTS

VDD 2.7 2.7 2.7 V min All digital inputs at 0 V or VDD

3.3 3.3 3.3 V max DAC active and excluding load current
IDD (Normal Mode)

VDD = 2.7 V to 3.3 V 0.55 0.55 0.55 mA typ VIH = VDD and VIL = GND
VDD = 2.7 V to 3.3 V 0.65 0.65 0.65 mA max VIH = VDD and VIL = GND

IDD (All Power-Down Modes)

VDD = 2.7 V to 3.3 V 0.2 0.2 0.2 μA typ VIH = VDD and VIL = GND
VDD = 2.7 V to 3.3 V 0.25 0.25 0.25 μA max VIH = VDD and VIL = GND

1

Part is functional with VDD up to 5.5 V.

2

Temperature range is −40°C to +105°C, typical at +25°C.

3

Linearity calculated using a reduced code range: AD5660 (Code 511 to Code 65024); AD5640 (Code 128 to Code 16256); AD5620 (Code 32 to Code 4064). Output

unloaded.

4

Guaranteed by design and characterization; not production tested.

Rev. F | Page 6 of 28

AD5620/AD5640/AD5660

TIMING CHARACTERISTICS

All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 2.
V

= 2.7 V to 5.5 V; all specifications T

DD

Table 4.

Limit at T
Parameter V

1

t

50 33 ns min SCLK cycle time

1

= 2.7 V to 3.6 V VDD = 3.6 V to 5.5 V Unit Conditions/Comments

DD

t2 13 13 ns min SCLK high time
t3 13 13 ns min SCLK low time
t4 13 13 ns min

t5 5 5 ns min Data setup time
t6 4.5 4.5 ns min Data hold time
t7 0 0 ns min
t8 50 33 ns min

t9 13 13 ns min
t10 0 0 ns min

1

Maximum SCLK frequency is 30 MHz at VDD = 3.6 V to 5.5 V and 20 MHz at VDD = 2.7 V to 3.6 V.

t

10

SCLK

t

8

to T

MIN

t

4

, unless otherwise noted.

MAX

, T

MIN

MAX

t

1

t

t

3

2

to SCLK falling edge setup time

SYNC

SCLK falling edge to SYNC
Minimum SYNC

rising edge to SCLK fall ignore

SYNC

high time

SCLK falling edge to SYNC

t

9

t

7

rising edge

fall ignore

SYNC

DIN

LSB = DB0
MSB = DB23 FOR AD5660
MSB = DB15 FOR AD5620/AD5640

MSB

t

6

t

5

LSB

04539-002

Figure 2. Serial Write Operation

Rev. F | Page 7 of 28

AD5620/AD5640/AD5660

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 5.

Parameter Rating

VDD to GND −0.3 V to +7 V
V

to GND −0.3 V to VDD + 0.3 V

OUT

VFB to GND −0.3 V to VDD + 0.3 V
V

to GND −0.3 V to VDD + 0.3 V

REFOUT

Digital Input Voltage to GND −0.3 V to VDD + 0.3 V
Operating Temperature Range

Industrial −40°C to +105°C
Storage Temperature Range −65°C to +150°C
Junction Temperature (TJ max) 150°C

Power Dissipation (TJ max − TA)/θJA
SOT-23 Package (4-Layer Board)

θJA Thermal Impedance 119°C/W
MSOP Package (4-Layer Board)

θJA Thermal Impedance 141°C/W

θJC Thermal Impedance 44°C/W
Reflow Soldering Peak Temperature

SnPb 240°C

Pb-Free 260°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

Rev. F | Page 8 of 28

AD5620/AD5640/AD5660

V

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

V

1

DD

AD5620/
AD5640/

REFOUT

V

V

OUT

FB

2

AD5660

3

TOP VIEW

(Not to Scale)

4

V

Figure 3. SOT-23 Pin Configuration

8

7

6

5

GND
DIN
SCLK
SYNC

04539-003

V

REFOUT

V

V

OUT

DD

FB

1

AD5620/

2

AD5640/

AD5660

3

TOP VIEW

4

(Not to Scale)

8
7
6
5

GND
DIN
SCLK
SYNC

Figure 4. MSOP Pin Configuration

04539-004

Table 6. Pin Function Descriptions

Pin No. Mnemonic Description

1 VDD Power Supply Input. These parts can operate from 2.7 V to 5.5 V. VDD should be decoupled to GND.
2 V
3 VFB Feedback Connection for the Output Amplifier. VFB should be connected to V
4 V
5

Reference Voltage Output.

REFOUT

for normal operation.

OUT

Analog Output Voltage from DAC. The output amplifier has rail-to-rail operation.

OUT

Level-Triggered Control Input (Active Low). This is the frame synchronization signal for the input data. When

SYNC

SYNC

goes low, it enables the input shift register and data is transferred in on the falling edges of the following

clocks. The DAC is updated following the 24

th

clock cycle for the AD5660 and the 16th clock cycle for
AD5620/AD5640 unless SYNC is taken high before this edge. In this case, the rising edge of SYNC acts as an
interrupt, and the write sequence is ignored by the DAC.

6 SCLK

Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data
can be transferred at rates up to 30 MHz.

7 DIN

Serial Data Input. The AD5660 has a 24-bit shift register, and the AD5620/AD5640 have a 16-bit shift register.
Data is clocked into the register on the falling edge of the serial clock input.

8 GND Ground Reference Point for all Circuitry on the Part.

Rev. F | Page 9 of 28

AD5620/AD5640/AD5660

TYPICAL PERFORMANCE CHARACTERISTICS

10

VDD = 5V
V

REFOUT

TA = 25°C

0

5000

= 2.5V

10000

15000

20000

25000

30000

CODE

35000

40000

45000

50000

55000

60000

04539-005

65000

8

6

4

2

0

–2

INL ERROR (LSB)

–4

–6

–8

–10

Figure 5. INL—AD5660-2/AD5660-3

1.0
VDD = 5V

0.8

V

= 2.5V

REFOUT

TA = 25°C

0.6

0.4

0.2

0

–0.2

DNL ERROR (LSB)

–0.4

–0.6

–0.8

60000

04539-008

65000

–1.0

0

5000

10000

15000

20000

25000

30000

CODE

35000

40000

45000

50000

55000

Figure 8. DNL—AD5660-2/AD5660-3

4

VDD = 5V
V

= 2.5V

REFOUT

3

TA = 25°C

2

1

0

–1

INL ERROR (LSB)

–2

–3

–4

0

8750

7500

6250

5000

3750

2500

1250

CODE

10000

11250

Figure 6. INL—AD5640-2/AD5640-3

1.0
VDD = 5V
V

REFOUT

TA = 25°C

= 2.5V

CODE

0.8

0.6

0.4

0.2

0

–0.2

INL ERROR (LSB)

–0.4
–0.6

–0.8
–1.0

0 1000500 20001500 350030002500 4000

Figure 7. INL—AD5620-2/AD6520-3

12500

13750

15000

04539-006

16250

04539-007

0.5
VDD = 5V

0.4

V

= 2.5V

REFOUT

TA = 25°C

0.3

0.2

0.1

0

–0.1

DNL ERROR (LSB)

–0.2

–0.3

–0.4
–0.5

0

8750

7500

6250

5000

3750

2500

1250

CODE

10000

11250

Figure 9. DNL—AD5640-2/AD5640-3

0.20
VDD = 5V
V

= 2.5V

REFOUT

0.15

TA = 25°C

0.10

0.05

0

–0.05

DNL ERROR (LSB)

–0.10

–0.15

–0.20

0 1000500 20001500 350030002500 4000

CODE

Figure 10. DNL—AD5620-2/AD6520-3

12500

13750

15000

04539-009

16250

04539-010

Rev. F | Page 10 of 28

AD5620/AD5640/AD5660

10

VDD = 3V

= 1.25V

V

8

REFOUT

= 25C

T

A

6

4

2

0

–2

INL ERROR (LSB)

–4

–6

–8

60000

04539-017

65000

–10

0

5000

10000

15000

20000

25000

30000

CODE

35000

40000

45000

50000

55000

Figure 11. INL—AD5660-1

1.0

VDD = 3V

= 1.25V

V

0.8

REFOUT

= 25C

T

A

0.6

0.4

0.2

0

–0.2

DNL ERROR (LSB)

–0.4

–0.6

–0.8

60000

04539-020

65000

–1.0

0

5000

10000

15000

20000

25000

30000

CODE

35000

40000

45000

50000

55000

Figure 14. DNL—AD5660-1

4

VDD = 3V

= 1.25V

V

REFOUT

3

= 25C

T

A

2

1

0

–1

INL ERROR (LSB)

–2

–3

–4

0

8750

7500

6250

5000

3750

2500

1250

CODE

10000

11250

Figure 12. INL—AD5640-1

1.0
VDD = 3V

0.8

0.6

0.4

0.2

0

–0.2

INL ERROR (LSB)

–0.4

–0.6

–0.8
–1.0

0 500 1000 1500 2000 2500 3000 3500 4000

V

REFOUT

= 25C

T

A

= 1.25V

CODE

Figure 13. INL—AD5620-1

12500

13750

15000

04539-018

16250

04539-019

0.5
VDD = 3V

0.4

0.3

0.2

0.1

0

–0.1

DNL ERROR (LSB)

–0.2

–0.3

–0.4

–0.5

V

REFOUT

T

A

0

= 25C

1250

= 1.25V

3750

2500

5000

6250

7500

CODE

8750

10000

11250

Figure 15. DNL—AD5640-1

0.20
VDD = 3V

= 1.25V

V

REFOUT

0.15
= 25C

T

A

0.10

0.05

0

–0.05

DNL ERROR (LSB)

–0.10

–0.15

–0.20

0 500 1000 1500 2000 2500 3000 3500 4000

CODE

Figure 16. DNL—AD5620-1

12500

13750

15000

04539-021

16250

04539-025

Rev. F | Page 11 of 28

AD5620/AD5640/AD5660

12

VDD=5V

10

8
6

MAX INL

4
2
0

–2

ERROR (LS B)

–4

MAX DNL

MIN DNL

–6

–8
–10
–12

–40–200 20406080100

MIN INL

TEMPERATURE (°C)

Figure 17. INL Error and DNL Error vs. Temperature

0.4
VDD=5V

0.2

GAIN ERROR

0

ERROR (%FSR)

FULL SCALE ERROR

–0.2

–0.4

–40 –20 0 20 40 60 80 100

TEMPERATURE (°C)

Figure 18. Gain Error and Full-Scale Error vs. Temperature

04539-011

04539-012

200

180

160

140

120

100

80

60

NUMBER OF DEVICES

40

VDD = 3.3V

20

0

0.45

0.46

0.47

0.48

0.49

0.50

0.51

0.52

0.53

0.54

0.55

0.56

0.57

0.58

IDD (mA)

0.59

0.60

0.61

0.62

VDD = 5V
T

= 25C

A

0.63

0.64

0.65

0.66

Figure 20. IDD Histogram

0.50
DAC LOADED WITH
FULL-SCALE

0.40
SOURCING CURRENT

0.30

0.20

VDD= 3V

0.10

V

= 1.25V

REFOUT

0

–0.10

ERROR VOLTAGE (V)

–0.20

–0.30

–0.40
–0.50

–10–8–6–4–2 0 2 4 8610

VDD= 5V
V

REFOUT

= 2.5V

CURRENT (mA)

DAC LOADED WITH
ZERO-SCALE
SINKING CURRENT

Figure 21. Headroom at Rails vs. Source and Sink

04539-014

0.67

04539-022

1.6
VDD=5V

1.4

1.2

1.0

ZERO CODE ERROR

0.8

ERROR (mV )

0.6

0.4

OFFSET ERROR

0.2

0

–40 –20 0 20 40 60 80 100

TEMPERATURE (°C)

Figure 19. Zero-Code and Offset Error vs. Temperature

04539-013

Rev. F | Page 12 of 28

6.00
VDD= 5V

V

= 2.5V

REFOUT

5.00

T

= 25C

A

4.00

3.00

(V)

OUT

V

2.00

1.00

0

–1.00

–30 –20 –10 0 10 20 30

CURRENT (mA)

FULL SCALE

3/4 SCALE

MIDSCALE

1/4 SCALE

ZERO SCALE

Figure 22. Source and Sink Capability—AD5660-2/AD5660-3

04539-023

AD5620/AD5640/AD5660

4.00
VDD= 3V

V

= 1.25V

REFOUT

T

= 25C

A

(V)

V

OUT

3.00

2.00

1.00

3/4 SCALE

MIDSCALE

1/4 SCALE

0

FULL SCALE

ZERO SCALE

VDD = 5V
T

= 25C

A

FULL-SCALE CODE CHANGE
0x0000 TO 0xFFFF
OUTPUT LOADED WITH 2k
AND 200pF TO GND

V

= 909mV/DIV

OUT

1

–1.00

–30 –20 –10 0 10 20 30

CURRENT (mA)

Figure 23. Source and Sink Capability—AD5660-1

0.7
TA = 25C

0.6

0.5

0.4

(mA)

DD

I

0.3

0.2

0.1

0

512 2051210512 30512 40512 50512 60512

VDD = 5V

VDD = 3V

CODE

Figure 24. Supply Current vs. Code

04539-024

04539-015

TIME BASE = 4s/DIV

Figure 26. Full-Scale Settling Time, 5 V

V

DD

1

2

V

OUT

3

CH1 2.00V

CH3 100mV

CH2 2.00V M40.0ms CH1

Figure 27. Power-On Reset to 0 V—AD5660-2

04539-028

V

REF

04539-029

1400

TA = 25C

1200

1000

800

(A)

DD

I

600

400

200

0

021345

VDD = 3V

V

LOGIC

VDD = 5V

04539-016

(V)

Figure 25. Supply Current vs. Logic Input Voltage

Rev. F | Page 13 of 28

V

DD

1

2

3

V

CH1 2.00V

CH3 200mV

REF

V

OUT

CH2 2.00V M20.0s CH1 1.88V

Figure 28. Power-On Reset to Midscale—AD5660-3

04539-030

AD5620/AD5640/AD5660

1.250800

1.250600

V

DD

1

2

3

V

CH1 1.20V

CH3 100mV

REF

V

OUT

CH2 1.00V M100s CH1 1.87V

Figure 29. Power-On Reset to 0 V—AD5660-1

04539-031

1.250400

1.250200

1.250000

1.249800

1.249600

1.249400

AMPLITUDE

1.249200

1.249000

1.248800

1.248600

1.248400
0 150 200 25050 100 300 350 400 450 500 550

VDD = 3V
V

= 1.25V

REFOUT

T

= 25C

A

13nS/SAMPLE NUMBER
1LSB CHANGE AROUND MIDSCALE
(0x7FFF TO 0x8000)
GLITCH IMPULSE = 0.284nV-s

SAMPLE NUMBER

Figure 32. Digital-to-Analog Glitch Impulse—AD5660-1

04539-033

VDD= 3V

V

OUT

1

3

CH1 2.00V

CH3 50.0mV

SCLK

M1.00s CH2 520mV

Figure 30. Exiting Power-Down to Midscale

2.501250

2.501000

2.500750

2.500500

2.500250

2.500000

2.499750

2.499500

AMPLITUDE

2.499250

2.499000

2.498750

2.498500

2.498250

2.498000
0 150 200 25050 100 300 350 400 450 500 550

VDD = 5V
V

= 2.5V

REFOUT

T

= 25C

A

13nS/SAMPLE NUMBER
1LSB CHANGE AROUND MIDSCALE
(0x7FFF TO 0x8000)
GLITCH IMPULSE = 0.497nV-s

SAMPLE NUMBER

Figure 31. Digital-to-Analog Glitch Impulse—AD5660-2/AD5660-3

04539-055

04539-032

2.500250

2.500200

2.500150

2.500100

2.500050

2.500000

2.499950

2.499900

AMPLITUDE

2.499850

2.499800

2.499750

2.499700

2.499650

2.499600
0 150 200 25050 100 300 350 400 450 500 550

VDD = 5V
T

= 25C

A

20nS/SAMPLE NUMBER
DAC LOADED WITH MIDSCALE
DIGITAL FEEDTHROUGH = 0.06nV-s

SAMPLE NUMBER

Figure 33. Digital Feedthrough

16

TA = 25C

14

V

3V

=

12

s)



10

TIME (

8

6

4

01234567 9810

CAPACITANCE (nF)

DD

V

5V

=

DD

Figure 34. Settling Time vs. Capacitive Load

04539-034

04539-036

Rev. F | Page 14 of 28

AD5620/AD5640/AD5660

VDD = 5V
V

= 2.5V

REFOUT

T

= 25C

A

DAC LOADEDWITH MIDSCALE

800

TA = 25C
MIDSCALE LOADED

700

600

500

1

10V/DIV

5s/DIV

Figure 35. 0.1 Hz to 10 Hz Output Noise—AD5660-2/AD5660-3

VDD = 3V
V

= 1.25V

REFOUT

T

= 25C

A

DAC LOADEDWITH MIDSCALE

1

5V/DIV

4s/DIV

Figure 36. 0.1 Hz to 10 Hz Output Noise—AD5660-1

04539-037

04539-054

400

300

OUTPUT NOISE (nVHz)

200

VDD= 3V

100

V

REFOUT

0

100 100001000 100000 1000000

= 1.25V

VDD= 5V
V

= 2.5V

REFOUT

FREQUENCY (Hz)

04539-038

Figure 37. Noise Spectral Density

Rev. F | Page 15 of 28

AD5620/AD5640/AD5660

TERMINOLOGY

Relative Accuracy

For the DAC, relative accuracy, or integral nonlinearity (INL), is
a measurement of the maximum deviation, in LSBs, from a
straight line passing through the endpoints of the DAC transfer
function. Figure 5 through Figure 7 show typical INL vs. code.

Differential Nonlinearity (DNL)

Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ±1 LSB maximum
ensures monotonicity. This DAC is guaranteed monotonic by
design. Figure 8 through Figure 10 show typical DNL vs. code.

Offset Error

Offset error is a measurement of the difference between V
(actual) and V

(ideal) expressed in mV in the linear region of

OUT

OUT

the transfer function. Offset error is measured on the AD5660
with Code 512 loaded into the DAC register. It can be negative
or positive.

DC Power Supply Rejection Ratio (PSRR)

This indicates how the output of the DAC is affected by changes
in the supply voltage. PSRR is the ratio of the change in V
the change in V
measured in dB. V

for the full-scale output of the DAC. It is

DD

is held at 2.5 V, and VDD is varied by ±10%.

REF

OUT

to

Zero-Code Error

Zero-code error is a measurement of the output error when
zero code (0x0000) is loaded to the DAC register. Ideally, the
output should be 0 V. The zero-code error is always positive in
the AD5620/AD5640/AD5660, because the output of the DAC
cannot go below 0 V. It is due to a combination of the offset
errors in the DAC and the output amplifier. Zero-code error is
expressed in mV. Figure 19 shows a plot of zero-code error vs.
temperature.

Full-Scale Error

Full-scale error is a measurement of the output error when full­scale code (0xFFFF) is loaded to the DAC register. Ideally, the
output should be V

− 1 LSB. Full-scale error is expressed as a

DD

percentage of the full-scale range. Figure 18 shows a plot of full­scale error vs. temperature.

Gain Error

This is a measurement of the span error of the DAC. It is the
deviation in slope of the DAC transfer characteristic from the
ideal, expressed as a percentage of the full-scale range.

Zero-Code Error Drift

This is a measurement of the change in zero-code error with a
change in temperature. It is expressed in μV/°C.

Gain Temperature Coefficient

This is a measurement of the change in gain error with changes
in temperature. It is expressed in (ppm of full-scale range)/°C.

Output Voltage Settling Time

This indicates the amount of time for the output of a DAC to
settle to a specified level for a ¼ to ¾ full-scale input change. It
is measured from the 24

th

falling edge of SCLK.

Digital-to-Analog Glitch Impulse

Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nV-s
and is measured when the digital input code is changed by
1 LSB at the major carry transition (0x7FFF to 0x8000). See
Figure 31 and Figure 32.

Digital Feedthrough

Digital feedthrough is a measurement of the impulse injected
into the analog output of the DAC from the digital inputs of the
DAC, but is measured when the DAC output is not updated. It
is specified in nV-s and measured with a full-scale code change
on the data bus, that is, from all 0s to all 1s or vice versa.

Noise Spectral Density

This is a measurement of the internally generated random
noise. Random noise is characterized as a spectral density
(voltage per √Hz). It is measured by loading the DAC to
midscale and measuring noise at the output. It is measured
in nV/√Hz. Figure 37 shows a plot of noise spectral density.

Rev. F | Page 16 of 28

AD5620/AD5640/AD5660

THEORY OF OPERATION

D/A SECTION

The AD5620/AD5640/AD5660 DACs are fabricated on a CMOS
process. The architecture consists of a string DAC followed by an
output buffer amplifier. The parts include an internal 1.25 V/2.5 V,
5 ppm/°C reference that is internally gained up by 2. Figure 38
shows a block diagram of the DAC architecture.

V

DAC REGISTER

DD

REF (+)

RESISTOR

STRING



REF (–)

GND

Figure 38. DAC Architecture

R

R

OUTPUT

AMPLIFIER

V

FB

V

OUT

04777-022

Because the input coding to the DAC is straight binary, the ideal
output voltage is given by

D





REFOUT

VV

2

OUT







N

2





where:
D is the decimal equivalent of the binary code that is loaded to
the DAC register.
0 to 4095 for AD5620 (12 bit)
0 to 16383 for AD5640 (14 bit)
0 to 65535 for AD5660 (16 bit)
N is the DAC resolution.

R

R

R

R

R

Figure 39. Resistor String

TO OUTPUT
AMPLIFIER

04539-040

RESISTOR STRING

The resistor string section is shown in Figure 39. It is simply a
string of resistors, each of value R. The code loaded to the DAC
register determines at which node on the string the voltage is
tapped off to be fed into the output amplifier. The voltage is

tapped off by closing one of the switches connecting the
string to the amplifier. Because it is a string of resistors, it is
guaranteed monotonic.

INTERNAL REFERENCE

The AD5620/AD5640/AD5660-1 parts include an internal,

1.25 V, 5 ppm/°C reference, giving a full-scale output voltage of

2.5 V. The AD5620/AD5640/AD5660-2-3 parts include an
internal, 2.5 V, 5 ppm/°C reference, giving a full-scale output
voltage of 5 V. The reference associated with each part is
available at the V

pin. A buffer is required if the reference

REFOUT

output is used to drive external loads. It is recommended that a
100 nF capacitor is placed between the reference output and
GND for reference stability.

OUTPUT AMPLIFIER

The output buffer amplifier can generate rail-to-rail voltages on
its output, which gives an output range of 0 V to V

. This output

DD

buffer amplifier has a gain of 2 derived from a 50 kΩ resistor
divider network in the feedback path. The inverting input of the
output amplifier is available to the user, allowing for remote
sensing. This V

pin must be connected to V

FB

for normal

OUT

operation. It can drive a load of 2 kΩ in parallel with 1000 pF to
GND. Figure 21 shows the source and sink capabilities of the
output amplifier. The slew rate is 1.5 V/μs with a ¼ to ¾ full­scale settling time of 10 μs.

SERIAL INTERFACE

The AD5620/AD5640/AD5660 have a 3-wire serial interface

SYNC

, SCLK, and DIN) that is compatible with SPI, QSPI, and

(
MICROWIRE interface standards as well as most DSPs.
See Figure 2 for a timing diagram of a typical write sequence.

The write sequence begins by bringing the
Data from the DIN line is clocked into the 16-bit shift register
(AD5620/AD5640) or the 24-bit shift register (AD5660) on the
falling edge of SCLK. The serial clock frequency can be as high
as 30 MHz, making the AD5620/AD5640/AD5660 compatible
with high speed DSPs. On the 16th falling clock edge (AD5620/
AD5640) or the 24th falling clock edge (AD5660), the last data
bit is clocked in and the programmed function is executed, that
is, a change in the DAC register contents and/or a change in the
mode of operation is executed. At this stage, the
be kept low or be brought high. In either case, it must be brought
high for a minimum of 33 ns before the next write sequence so

SYNC

that a falling edge of
Because the

SYNC

buffer draws more current when VIN = 2 V

than it does when V

can initiate the next write sequence.

= 0.8 V,

IN

SYNC
write sequences for even lower power operation of the parts. As
is mentioned previously, however,

SYNC

again just before the next write sequence.

SYNC

line low.

SYNC

line can

should be idled low between

must be brought high

Rev. F | Page 17 of 28

AD5620/AD5640/AD5660

INPUT SHIFT REGISTER

AD5620/AD5640

The input shift register is 16 bits wide for the AD5620/AD5640
(see Figure 40 and Figure 41). The first two bits are control bits
that control which mode of operation the part is in (normal
mode or any of the three power-down modes). The next
14/12 bits, respectively, are the data bits. These are transferred
to the DAC register on the 16

AD5660

The input shift register is 24 bits wide for the AD5660 (see
Figure 42). The first six bits are don’t care bits. The next two are
control bits that control which mode of operation the part is in
(normal mode or any of the three power-down modes). For a more
complete description of the various modes, see the Power-Down
Modes section. The next 16 bits are the data bits. These are
transferred to the DAC register on the 24

th

falling edge of SCLK.

th

falling edge of SCLK.

DB15 (MSB) DB0 (LSB)

PD1 PD0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X

Figure 40. AD5620 Input Register Contents

DB15 (MSB) DB0 (LSB)

DATA BITS

INTERRUPT

SYNC

In a normal write sequence for the AD5660, the

SYNC

line is
kept low for at least 24 falling edges of SCLK, and the DAC is
updated on the 24
high before the 24

th

falling edge. However, if

th

falling edge, this acts as an interrupt to the

SYNC

is brought

write sequence. The shift register is reset, and the write sequence
is seen as invalid. Neither an update of the DAC register contents
nor a change in the operating mode occurs (see Figure 43).
Similarly, in a normal write sequence for the AD5620/AD5640,

SYNC

the
and the DAC is updated on the 16
SYNC

line is kept low for at least 16 falling edges of SCLK,

th

falling edge. However, if

is brought high before the 16th falling edge, this acts as

an interrupt to the write sequence.

04539-041

PD1 PD0 D11 D10D13 D12 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

DATA BITS

Figure 41. AD5640 Input Register Contents

DB23 (MSB) DB0 (LSB)

PD1 PD0 D15 D14 D13 D12X X X X X X D10 D9 D8 D7 D6 D5 D4 D3 D2 D1

DATA BITS

Figure 42. AD5660 Input Register Contents

SCLK

SYNC

DIN

MSB MSB LSBLSB

INVALID WRITE SEQUENCE:

SYNC HIGH BEFORE 16

TH

/24TH FALLING EDGE

Figure 43.

SYNC

Interrupt Facility

VALID WRITE SEQUENCE, OUTPUT UPDATES

ON THE 16TH/24TH FALLING EDGE

04539-042

D0

04539-043

04539-044

Rev. F | Page 18 of 28

AD5620/AD5640/AD5660

POWER-ON RESET

The AD5620/AD5640/AD5660 family contains a power-on
reset circuit that controls the output voltage during power-up.
The AD5620/AD5640/AD5660-1-2 DAC output powers up to
0 V, and the AD5620/AD5660-3 DAC output powers up to
midscale. The output remains at this level until a valid write
sequence is made to the DAC, which is useful in applications
where it is important to know the state of the DAC output while
it is in the process of powering up.

POWER-DOWN MODES

The AD5620/AD5640/AD5660 have four separate modes of
operation. These modes are software-programmable by setting
two bits in the control register. Table 7 and Table 8 show how
the state of the bits corresponds to the operating mode of the
device.

Table 7. Modes of Operation for the AD5660

DB17 DB16 AD5660 Operating Mode

0 0 Normal operation
Power-down modes:
0 1 1 kΩ to GND
1 0 100 kΩ to GND
1 1 Three-state

Table 8. Modes of Operation for the AD5620/AD5640

DB15 DB14 AD5620/AD5640 Operating Mode

0 0 Normal operation
Power-down modes:
0 1 1 kΩ to GND
1 0 100 kΩ to GND
1 1 Three-state

When both bits are set to 0, the part works normally with its
normal power consumption of 550 μA at 5 V. However, for the
three power-down modes, the supply current falls to 480 nA
at 5 V (200 nA at 3 V). Not only does the supply current fall,
but the output stage is internally switched from the output of
the amplifier to a resistor network of known values. The advan­tage is that the output impedance of the part is known while the
part is in power-down mode. There are three options: the out­put is connected internally to GND through a 1 kΩ or a 100 kΩ
resistor, or it is left open-circuited (three-stated). The output
stage is shown in Figure 44.

The bias generator, output amplifier, reference, resistor string,
and other associated linear circuitry are all shut down when
power-down mode is activated. However, the contents of the
DAC register are unaffected when in power-down. The time to
exit power-down is typically 5 μs for V
(see Figure 30).

MICROPROCESSOR INTERFACING

AD5660-to-Blackfin® ADSP-BF53x Interface

Figure 45 shows a serial interface between the AD5660 and the
Blackfin ADSP-BF53x microprocessor. The ADSP-BF53x
processor family incorporates two dual-channel synchronous
serial ports, SPORT1 and SPORT0, for serial and multi­processor communications. Using SPORT0 to connect to the
AD5660, the setup for the interface is as follows: DT0PRI drives
the DIN pin of the AD5660, while TSCLK0 drives the SCLK of
the part and

1

RESISTOR

STRING DAC

Figure 44. Output Stage During Power-Down

SYNC

ADSP-BF53x

DTOPRI
TSCLK0

ADDITIONAL PINS OMITTED FOR CLARITY

Figure 45. AD5660-to-Blackfin ADSP-BF53x Interface

AMPLIFIER

POWER-DOWN

CIRCUITRY

is driven from TFS0.

1

TFS0

V

OUT

RESISTOR
NETWORK

04539-045

= 5 V and VDD = 3 V

DD

1

AD5660

SYNC
DIN
SCLK

04539-046

Rev. F | Page 19 of 28

AD5620/AD5640/AD5660

AD5660-to-68HC11/68L11 Interface

Figure 46 shows a serial interface between the AD5660 and the
68HC11/68L11 microcontroller. SCK of 68HC11/68L11 drives
the SCLK of AD5660, and the MOSI output drives the serial

SYNC

data line of the DAC. The

signal is derived from a port
line (PC7). The setup conditions for correct operation of this
interface are as follows: The 68HC11/68L11 should be con­figured so that its CPOL bit is 0, and its CPHA bit is 1. When

SYNC

data is being transmitted to the DAC, the

line is taken
low (PC7). When the 68HC11/68L11 is configured in this way,
data appearing on the MOSI output is valid on the falling edge
of SCK. Serial data from the 68HC11/68L11 is transmitted in
8-bit bytes with only eight falling clock edges occurring in the
transmit cycle. Data is transmitted MSB first. To load data to the
AD5660, PC7 is left low after the first eight bits are transferred, a
second serial write operation is performed to the DAC, and PC7
is taken high at the end of this procedure.

68HC11/68L11

1

ADDITIONAL PINS OMITTED FOR CLARITY

1

PC7

SCK

MOSI

Figure 46. AD5660-to-68HC11/68L11 Interface

AD5660

SYNC
SCLK
DIN

1

AD5660-to-80C51/80L51 Interface

Figure 47 shows a serial interface between the AD5660 and the
80C51/80L51 microcontroller. The setup for the interface is as
follows: TxD of the 80C51/80L51 drives SCLK of the AD5660,

SYNC

and RxD drives the serial data line of the part. The

signal
is again derived from a bit-programmable pin on the port. In
this case, Port Line P3.3 is used. When data is to be transmitted
to the AD5660, P3.3 is taken low. The 80C51/80L51 transmit

04539-047

data only in 8-bit bytes; therefore, only eight falling clock edges
occur in the transmit cycle. To load data to the DAC, P3.3 is left
low after the first eight bits are transmitted, and a second write
cycle is initiated to transmit the second byte of data. P3.3 is taken
high following the completion of this cycle. The 80C51/80L51
output the serial data LSB first; however, the AD5660 requires
its data with the MSB as the first bit received. The 80C51/80L51
transmit routine should take this into account.

80C51/80L51

1

ADDITIONAL PINS OMITTED FOR CLARITY

1

P3.3

TxD

RxD

Figure 47. AD5660-to-80C51/80L51 Interface

AD5660

SYNC
SCLK
DIN

1

AD5660-to-MICROWIRE Interface

Figure 48 shows an interface between the AD5660 and any
MICROWIRE-compatible device. Serial data is shifted out on
the falling edge of the serial clock and is clocked into the
AD5660 on the rising edge of the SK.

MICROWIRE

1

ADDITIONAL PINS OMITTED FOR CLARITY

1

CS
SK

SO

Figure 48. AD5660-to-MICROWIRE Interface

AD5660

SYNC
SCLK
DIN

1

04539-048

04539-049

Rev. F | Page 20 of 28

AD5620/AD5640/AD5660

APPLICATIONS INFORMATION

USING A REF19x AS A POWER SUPPLY FOR THE AD5620/AD5640/AD5660

Because the supply current required by the AD5620/AD5640/
AD5660 is extremely low, an alternative option is to use a REF19x
voltage reference (REF195 for 5 V or REF193 for 3 V) to supply
the required voltage to the part (see Figure 49). This is especially
useful if the power supply is quite noisy or if the system supply
voltages are at some value other than 5 V or 3 V, for example, 15 V.
The REF19x outputs a steady supply voltage for the AD5620/
AD5640/AD5660. If the low dropout REF195 is used, the current
it needs to supply to the AD5660 is 500 μA. This is with no load
on the output of the DAC. When the DAC output is loaded, the
REF195 also must supply the current to the load. The total current
required (with a 5 kΩ load on the DAC output) is

500 μA + (5 V/5 kΩ) = 1.5 mA

The load regulation of the REF195 is typically 2 ppm/mA,
which results in an error of 3 ppm (15 μV) for the 1.5 mA
current drawn from it. This corresponds to a 0.197 LSB error
for the AD5660.

15V

5V

AD5660

V

OUT

= 0V TO 5V

04539-050

INTERFACE

REF195

3-WIRE

SERIAL

SYNC
SCLK

DIN

Figure 49. REF195 as the Power Supply to the AD5660

BIPOLAR OPERATION USING THE AD5660

The AD5660 is designed for single-supply operation, but a
bipolar output range is also possible using the circuit in
Figure 50. Figure 50 gives an output voltage range of ±5 V.
Rail-to-rail operation at the amplifier output is achievable
using an AD820 or an OP295 as the output amplifier.

The output voltage for any input code can be calculated as

R2R1D





VV



O






65536





R1



















where D represents the input code in decimal (0 to 65535).
When V

= 5 V, R1 = R2 = 10 kΩ,

DD

10

D

65536










V



O



V5

This results in an output voltage range of ±5 V, with 0x0000
corresponding to a −5 V output and 0xFFFF corresponding to a
+5 V output.

V

DD

AD5660

INTERFACE

R1

10k

3-WIRE
SERIAL

V

FB

V

OUT

+5V

0.1F10F

Figure 50. Bipolar Operation with the AD5660

R2








R1



R2

10k

+5V

AD820/
OP295

–5V









±5V



V

DDDD

04539-051

Rev. F | Page 21 of 28

AD5620/AD5640/AD5660

R2

18.5k
P2

4mA

ADJUST

SERIAL

LOAD

AD5660

R1

4.7k

P1

20mA

ADJUST

R3

1.5k

Figure 51. Programmable 4 mA to 20 mA Process Controller

USING THE AD5660 AS AN ISOLATED, PROGRAMMABLE, 4 mA TO 20 mA PROCESS CONTROLLER

In many process-control system applications, 2-wire current
transmitters are used to transmit analog signals through noisy
environments. These current transmitters use a zero-scale signal
current of 4 mA to power the signal conditioning circuitry of
the transmitter. The full-scale output signal in these transmitters
is 20 mA. The converse approach to process control can also be
used, in which a low-power, programmable current source is
used to control remotely located sensors or devices in the loop.

A circuit that performs this function is shown in Figure 51.
Using the AD5660 as the controller, the circuit provides a
programmable output current of 4 to 20 mA, proportional to
the digital code of the DAC. Biasing for the controller is provided
by the ADR02 and requires no external trim for two reasons: first,
the ADR02’s tight initial output voltage tolerance, and second,
the low supply current consumption of both the AD8627 and
the AD5660. The entire circuit, including optocouplers, consumes
less than 3 mA from the total budget of 4 mA. The AD8627
regulates the output current to satisfy the current summation
at the noninverting node of the AD8627.

AD8627

ADR02

R6

3.3k

100

Q1
2N3904

D1

R7

4–20mA

V

LOOP

12V TO 36V

RL

04539-052

Without this diode, such transients could cause phase reversal
of the AD8627 and possible latch-up of the controller. The loop
supply voltage compliance of the circuit is limited by the maximum
applied input voltage to the ADR02 and is from 12 V to 40 V.

USING THE AD5620/AD5640/AD5660 WITH A GALVANICALLY ISOLATED INTERFACE

For process-control applications in industrial environments, it
is often necessary to use a galvanically isolated interface to
protect and isolate the controlling circuitry from hazardous
common-mode voltages that might occur in the area where
the DAC is functioning. The iCoupler® provides isolation in
excess of 2.5 kV. The AD5620/AD5640/AD5660 use a 3-wire
serial logic interface; therefore, the ADuM1300 3-channel
digital isolator provides the required isolation (see Figure 52).
The power supply to the part also must be isolated, which is
done by using a transformer. On the DAC side of the trans­former, a 5 V regulator provides the 5 V supply required for the
AD5620/AD5640/AD5660.

5V

POWER

REGULATOR

10F

0.1F

= 1/R7 (V

I

OUT

× R3/R1 + V

DAC

× R3/R2)

REF

For the values shown in Figure 51,

= 0.2435 μA × D + 4 mA

I

OUT

where D = 0 ≤ D ≤ 65,535, giving a full-scale output current of
20 mA when the AD5660’s digital code equals 0xFFFF. Offset
trim at 4 mA is provided by P2, and P1 provides the circuit gain
trim at 20 mA. These two trims do not interact because
the noninverting input of the AD8627 is at virtual ground. The
Schottky diode, D1, is required in this circuit to prevent loop
supply power-on transients from pulling the noninverting input
of the AD8627 more than 300 mV below its inverting input.

Rev. F | Page 22 of 28

V

SCLK

SDI

DATA

V

1A

V

1B

V

1C

ADuM1300

V

OA

V

OB

V

OC

SCLK

SYNC

DIN

DD

AD56x0

GND

V

OUT

Figure 52. AD5620/AD5640/AD5660 with a Galvanically Isolated Interface

04539-053

AD5620/AD5640/AD5660

POWER SUPPLY BYPASSING AND GROUNDING

When accuracy is important in a circuit, it is helpful to carefully
consider the power supply and ground return layout on the
board. The printed circuit board containing the AD5620/
AD5640/AD5660 should have separate analog and digital
sections, each having its own area of the board. If the AD5620/
AD5640/AD5660 are in a system where other devices require
an AGND-to-DGND connection, the connection should be
made at one point only. This ground point should be as close as
possible to the AD5620/AD5640/AD5660.

The power supply to the AD5620/AD5640/AD5660 should be
bypassed with 10 μF and 0.1 μF capacitors. The capacitors
should be as close as physically possible to the device, with the

0.1 μF capacitor ideally right up against the device. The 10 μF
capacitors are the tantalum bead type. It is important that the

0.1 μF capacitor has a low effective series resistance (ESR) and
low effective series inductance (ESI), such as is typical of
common ceramic types of capacitors. This 0.1 μF capacitor
provides a low impedance path to ground for high frequencies
caused by transient currents due to internal logic switching.

The power supply line itself should have as large a trace as
possible to provide a low impedance path and reduce glitch
effects on the supply line. Clocks and other components with
fast switching digital signals should be shielded from other
parts of the board by digital ground. Avoid crossover of digital
and analog signals if possible. When traces cross on opposite
sides of the board, ensure that they run at right angles to each
other to reduce feedthrough effects on the board. The best
board layout technique is the microstrip technique, where the
component side of the board is dedicated to the ground plane
only and the signal traces are placed on the solder side.
However, this is not always possible with a 2-layer board.

Rev. F | Page 23 of 28

AD5620/AD5640/AD5660

0

0

OUTLINE DIMENSIONS

3.00

2.90

2.80

76

1.70

1.60

1.50

PIN 1

INDICATOR

1.30

1.15

0.90

.15 MAX
.05 MIN

8

1234

1.95
BSC

5

0.38 MAX

0.22 MIN

0.65 BSC

1.45 MAX

0.95 MIN

3.00

2.80

2.60

SEATING
PLANE

0.22 MAX

0.08 MIN

8°

0.60

4°

BSC

0°

0.60

0.45

0.30

COMPLIANT TO JEDEC STANDARDS MO-178-BA

12-16-2008-A

Figure 53. 8-Lead Small Outline Transistor Package [SOT-23]

(RJ-8)

Dimensions shown in millimeters

3.20

3.00

2.80

8

5

3.20

3.00

2.80

PIN 1

IDENTIFIER

0.95

0.85

0.75

0.15

0.05

COPLANARITY

1

0.65 BSC

0.10

COMPLIANT TO JEDEC STANDARDS MO-187-AA

Figure 54. 8-Lead Mini Small Outline Package [MSOP]

5.15

4.90

4.65

4

15° MAX

6°
0°

0.23

0.09

0.40

0.25

1.10 MAX

(RM-8)

Dimensions shown in millimeters

0.80

0.55

0.40

10-07-2009-B

Rev. F | Page 24 of 28

AD5620/AD5640/AD5660

ORDERING GUIDE

Te mp e ra tu r e

Model1

AD5620ARJ-1500RL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 D2K Zero ±6 LSB INL 1.25 V
AD5620ARJZ-1500RL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 D6V Zero ±6 LSB INL 1.25 V
AD5620ARJ-1REEL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 D2K Zero ±6 LSB INL 1.25 V
AD5620ARJ-2500RL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 D2L Zero ±6 LSB INL 2.5 V
AD5620ARJZ-2500RL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 D5D Zero ±6 LSB INL 2.5 V
AD5620ARJ-2REEL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 D2L Zero ±6 LSB INL 2.5 V
AD5620ARJZ-2REEL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 D5D Zero ±6 LSB INL 2.5 V
AD5620ARMZ-2 −40°C to +105°C 8-Lead MSOP RM-8 DGY Zero ±6 LSB INL 2.5 V
AD5620ARMZ-2REEL7 −40°C to +105°C 8-Lead MSOP RM-8 DGY Zero ±6 LSB INL 2.5 V
AD5620BRJ-1500RL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 D2H Zero ±1 LSB INL 1.25 V
AD5620BRJZ-1500RL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 D87 Zero ±1 LSB INL 1.25 V
AD5620BRJ-1REEL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 D2H Zero ±1 LSB INL 1.25 V
AD5620BRJ-2500RL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 D2J Zero ±1 LSB INL 2.5 V
AD5620BRJZ-2500RL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 D5C Zero ±1 LSB INL 2.5 V
AD5620BRJ-2REEL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 D2J Zero ±1 LSB INL 2.5 V
AD5620BRJZ-2REEL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 D5C Zero ±1 LSB INL 2.5 V
AD5620CRM-1 −40°C to +105°C 8-Lead MSOP RM-8 D2M Zero ±1 LSB INL 1.25 V
AD5620CRMZ-1 −40°C to +105°C 8-Lead MSOP RM-8 DGM Zero ±1 LSB INL 1.25 V
AD5620CRM-1REEL7 −40°C to +105°C 8-Lead MSOP RM-8 D2M Zero ±1 LSB INL 1.25 V
AD5620CRMZ-1REEL7 −40°C to +105°C 8-Lead MSOP RM-8 DGM Zero ±1 LSB INL 1.25 V
AD5620CRM-2 −40°C to +105°C 8-Lead MSOP RM-8 D2N Zero ±1 LSB INL 2.5 V
AD5620CRM-2REEL7 −40°C to +105°C 8-Lead MSOP RM-8 D2N Zero ±1 LSB INL 2.5 V
AD5620CRMZ-2 −40°C to +105°C 8-Lead MSOP RM-8 D59 Zero ±1 LSB INL 2.5 V
AD5620CRMZ-2REEL7 −40°C to +105°C 8-Lead MSOP RM-8 D59 Zero ±1 LSB INL 2.5 V
AD5620CRM-3 −40°C to +105°C 8-Lead MSOP RM-8 D2P Midscale ±1 LSB INL 2.5 V
AD5620CRMZ-3 −40°C to +105°C 8-Lead MSOP RM-8 DGN Midscale ±1 LSB INL 2.5 V
AD5620CRM-3REEL7 −40°C to +105°C 8-Lead MSOP RM-8 D2P Midscale ±1 LSB INL 2.5 V
AD5620CRMZ-3REEL7 −40°C to +105°C 8-Lead MSOP RM-8 DGN Midscale ±1 LSB INL 2.5 V
EVAL-AD5620EBZ Evaluation Board
AD5640ARJ-2500RL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 D2T Zero ±8 LSB INL 2.5 V
AD5640ARJZ-2500RL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 DC6 Zero ±8 LSB INL 2.5 V
AD5640ARJ-2REEL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 D2T Zero ±8 LSB INL 2.5 V
AD5640ARJZ-2REEL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 DC6 Zero ±8 LSB INL 2.5 V
AD5640BRJ-1500RL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 D2Q Zero ±4 LSB INL 1.25 V
AD5640BRJZ-1500RL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 DC3 Zero ±4 LSB INL 1.25 V
AD5640BRJ-1REEL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 D2Q Zero ±4 LSB INL 1.25 V
AD5640BRJZ-1REEL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 DC3 Zero ±4 LSB INL 1.25 V
AD5640BRJ-2500RL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 D2R Zero ±4 LSB INL 2.5 V
AD5640BRJZ-2500RL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 DC0 Zero ±4 LSB INL 2.5 V
AD5640BRJ-2REEL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 D2R Zero ±4 LSB INL 2.5 V
AD5640BRJZ-2REEL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 DC0 Zero ±4 LSB INL 2.5 V
AD5640CRM-1 −40°C to +105°C 8-Lead MSOP RM-8 D2U Zero ±4 LSB INL 1.25 V
AD5640CRM-1REEL7 −40°C to +105°C 8-Lead MSOP RM-8 D2U Zero ±4 LSB INL 1.25 V
AD5640CRMZ-1 −40°C to +105°C 8-Lead MSOP RM-8 DG1 Zero ±4 LSB INL 1.25 V
AD5640CRMZ-1REEL7 −40°C to +105°C 8-Lead MSOP RM-8 DG1 Zero ±4 LSB INL 1.25 V
AD5640CRM-2 −40°C to +105°C 8-Lead MSOP RM-8 D2V Zero ±4 LSB INL 2.5 V
AD5640CRM-2REEL7 −40°C to +105°C 8-Lead MSOP RM-8 D2V Zero ±4 LSB INL 2.5 V
AD5640CRMZ-2 −40°C to +105°C 8-Lead MSOP RM-8 DEW Zero ±4 LSB INL 2.5 V
AD5640CRMZ-2REEL7 −40°C to +105°C 8-Lead MSOP RM-8 DEW Zero ±4 LSB INL 2.5 V

Range

Package
Description

Package
Option Branding

Power-On
Reset to Code Accuracy

Internal
Reference

Rev. F | Page 25 of 28

AD5620/AD5640/AD5660

Te mp e ra tu r e

Model1

Range

AD5660ARJ-1500RL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 D30 Zero ±32 LSB INL 1.25 V
AD5660ARJZ-1500RL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 D5G Zero ±32 LSB INL 1.25 V
AD5660ARJ-1REEL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 D30 Zero ±32 LSB INL 1.25 V
AD5660ARJZ-1REEL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 D5G Zero ±32 LSB INL 1.25 V
AD5660ARJ-2500RL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 D31 Zero ±32 LSB INL 2.5 V
AD5660ARJZ-2500RL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 D6K Zero ±32 LSB INL 2.5 V
AD5660ARJ-2REEL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 D31 Zero ±32 LSB INL 2.5 V
AD5660ARJZ-2REEL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 D6K Zero ±32 LSB INL 2.5 V
AD5660ARJ-3500RL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 D32 Midscale ±32 LSB INL 2.5 V
AD5660ARJZ-3500RL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 DAV Midscale ±32 LSB INL 2.5 V
AD5660ARJ-3REEL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 D32 Midscale ±32 LSB INL 2.5 V
AD5660ARJZ-3REEL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 DAV Midscale ±32 LSB INL 2.5 V
AD5660BRJ-1500RL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 D2X Zero ±16 LSB INL 1.25 V
AD5660BRJZ-1500RL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 D6C Zero ±16 LSB INL 1.25 V
AD5660BRJ-1REEL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 D2X Zero ±16 LSB INL 1.25 V
AD5660BRJZ-1REEL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 D6C Zero ±16 LSB INL 1.25 V
AD5660BRJ-2500RL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 D2Y Zero ±16 LSB INL 2.5 V
AD5660BRJZ-2500RL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 D6L Zero ±16 LSB INL 2.5 V
AD5660BRJ-2REEL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 D2Y Zero ±16 LSB INL 2.5 V
AD5660BRJZ-2REEL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 D6L Zero ±16 LSB INL 2.5 V
AD5660BRJ-3500RL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 D2Z Midscale ±16 LSB INL 2.5 V
AD5660BRJZ-3500RL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 DAN Midscale ±16 LSB INL 2.5 V
AD5660BRJ-3REEL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 D2Z Midscale ±16 LSB INL 2.5 V
AD5660BRJZ-3REEL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 DAN Midscale ±16 LSB INL 2.5 V
AD5660CRM-1 −40°C to +105°C 8-Lead MSOP RM-8 D33 Zero ±16 LSB INL 1.25 V
AD5660CRM-1REEL7 −40°C to +105°C 8-Lead MSOP RM-8 D33 Zero ±16 LSB INL 1.25 V
AD5660CRMZ-1 −40°C to +105°C 8-Lead MSOP RM-8 DEX Zero ±16 LSB INL 1.25 V
AD5660CRMZ-1REEL7 −40°C to +105°C 8-Lead MSOP RM-8 DEX Zero ±16 LSB INL 1.25 V
AD5660CRM-2 −40°C to +105°C 8-Lead MSOP RM-8 D34 Zero ±16 LSB INL 2.5 V
AD5660CRM-2REEL7 −40°C to +105°C 8-Lead MSOP RM-8 D34 Zero ±16 LSB INL 2.5 V
AD5660CRMZ-2 −40°C to +105°C 8-Lead MSOP RM-8 DEY Zero ±16 LSB INL 2.5 V
AD5660CRMZ-2REEL7 −40°C to +105°C 8-Lead MSOP RM-8 DEY Zero ±16 LSB INL 2.5 V
AD5660CRM-3 −40°C to +105°C 8-Lead MSOP RM-8 D35 Midscale ±16 LSB INL 2.5 V
AD5660CRM-3REEL7 −40°C to +105°C 8-Lead MSOP RM-8 D35 Midscale ±16 LSB INL 2.5 V
AD5660CRMZ-3 −40°C to +105°C 8-Lead MSOP RM-8 DBY Midscale ±16 LSB INL 2.5 V
AD5660CRMZ-3REEL7 −40°C to +105°C 8-Lead MSOP RM-8 DBY Midscale ±16 LSB INL 2.5 V
EVAL-AD5660EBZ Evaluation Board
EVAL-AD5660DKZ Demonstration Board

1

Z = RoHS Compliant Part.

Package
Description

Package
Option Branding

Power-On
Reset to Code Accuracy

Internal
Reference

Rev. F | Page 26 of 28

AD5620/AD5640/AD5660

NOTES

Rev. F | Page 27 of 28

AD5620/AD5640/AD5660

NOTES

©2005–2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04539-0-12/10(F)

Rev. F | Page 28 of 28