ANALOG DEVICES AD5590 Service Manual

16 Input, 16 Output Analog I/O Port

V

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FEATURES

Input channels

12-bit successive approximation ADC 16 inputs with sequencer Fast throughput rate: 1 MSPS Wide input bandwidth: 70 dB SNR at f

Output channels

16 outputs with 12-bit DACs On-chip 2.5 V reference Hardware

function to programmable code

CLR Rail-to-rail operation

Operational amplifiers

LDAC

and

DSCLK

DSYNC1

DSYNC2

DDIN

LDAC

CLR

override function

LDAC

POWER-ON

INTERFACE

ADCV

RESET

DAC

LOGIC

= 50 kHz

IN

DD

DACVDD (×2)

with Integrated Amplifiers

Offset voltage: 2.2 mV maximum Low input bias current: 1 pA maximum Single supply operation Low noise: 22 nV/√Hz Unity gain stable Flexible serial interface

SPI-/QSPI-/MICROWIRE-/DSP-compatible

−40°C to +85°C operation

APPLICATIONS

Optical line cards Base stations General-purpose analog I/O Monitoring and control

FUNCTIONAL BLOCK DIAGRAM

REFIN1/VREFOUT1

1.25V/2.5V

STRING

DAC 0

STRING

DAC 7

STRING

DAC 8

REF

BUFFER

INPUT

REGISTER

INPUT

REGISTER

INPUT

REGIS TER

V1+

V2+

LDAC

REGIS TER

REGISTER

V1– V2–

DAC

POWER-DOWN

LOGIC

AD5590

VOUT0

VOUT7

VOUT8

INPUT

REGIS TER

V

DRIVE

ASCLK

ASYNC

ADIN

ADOUT

IN0(–)

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

INTERFACE

LOGIC

IN0(+)

ADC

OUT0

IN7(–)

SEQUENCER

IN7(+)

REGISTER

OUT7

DAC

1.25V/2.5V REF

12-BIT

SUCCESSIVE

APPROXIMAT ION

DACGND (×2)

Figure 1.

STRING DAC 15

ADC

BUFFER

T/H

ADCGND

POWER-DOWN

LOGIC

INPUT

MUX

AD5590

VOUT15

V

REFIN2/VREFOUT2

VIN0

VINI5

V

REFA

07691-001

AD5590

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REVISION HISTORY

10/08—Revision 0: Initial Version

Rev. 0 | Page 2 of 44

AD5590

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GENERAL DESCRIPTION

The AD5590 is a 16-channel input and 16-channel output analog I/O port with eight uncommitted amplifiers, operating from a single 4.5 V to 5.25 V supply. The AD5590 comprises 16 input channels multiplexed into a 1 MSPS, 12-bit successive approximation ADC with a sequencer to allow a preprogrammed selection of channels to be converted sequentially. The ADC contains a low noise, wide bandwidth track-and-hold amplifier that can handle input frequencies in excess of 1 MHz.

The conversion process and data acquisition are controlled using ASYNC

and the serial clock signal, allowing the device to easily interface with microprocessors or DSPs. The input signal is sampled on the falling edge of initiated at this point. There are no pipeline delays associated with the ADC. By setting the relevant bits in the control register, the analog input range for the ADC can be selected to be a 0 V to V

input or a 0 V to 2 × V

REFA

or twos complement output coding. The conversion time is determined by the ASCLK frequency because it is also used as the master clock to control the conversion.

ASYNC

and conversion is also

with either straight binary

REFA

The DAC section of the AD5590 comprises sixteen 12-bit DACs divided into two groups of eight. Each group has an on-chip reference. The on-board references are off at power-up, allowing the use of external references. The internal references are enabled via a software write.

The AD5590 incorporates a power-on reset circuit that ensures that the DAC outputs power up to 0 V and remain powered up at this level until a valid write takes place. The DAC contains a power-down feature that reduces the current consumption of the device and provides software-selectable output loads while in power-down mode for any or all DAC channels. The outputs of all DACs can be updated simultaneously using the function, with the added functionality of user-selectable DAC channels to simultaneously update. There is also an asynchronous CLR

that updates all DACs to a user-programmable code: zero

scale, midscale, or full scale.

The AD5590 contains eight low noise, single-supply amplifiers. These amplifiers can be used for signal conditioning for the ADCs, DACs, or other independent circuitry, if required.

LDAC

Rev. 0 | Page 3 of 44

AD5590

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SPECIFICATIONS

ADC SPECIFICATIONS

ADCVDD = V

= 2.7 V to 5.25 V

DRIVE

= 2.5 V, f

REFA

1

= 20 MHz, TA = T

SCLK

MIN

to T

, unless otherwise noted.

MAX

Table 1.

Parameter Min Typ Max Unit Test Conditions/Comments

DYNAMIC PERFORMANCE fIN = 50 kHz sine wave, f

2

= 20 MHz

SCLK

Signal-to-(Noise + Distortion) (SINAD)3 68.5 70 dB @ 5 V

70.5 dB @ 3 V Signal-to-Noise Ratio (SNR)3 69 70 dB @ 5 V

70.5 dB @ 3 V Total Harmonic Distortion (THD)

3

−74 −82 dB @ 5 V

−82 dB @ 3 V Peak Harmonic or Spurious Noise (SFDR)

3

−75 −86 dB @ 5 V

−80 dB @ 3 V Intermodulation Distortion (IMD)

3, 4

fa = 40.1 kHz, fb = 41.5 kHz

Second-Order Terms −85 dB

Third-Order Terms −85 dB Aperture Delay4 10 ns Aperture Jitter Channel-to-Channel Isolation

4

50 ps

3, 4

−82 dB f

= 400 kHz

IN

Full Power Bandwidth4 8.2 MHz @ 3 dB

1.6 MHz @ 0.1 dB

DC ACCURACY

3

Resolution 12 Bits Integral Nonlinearity −1 +1 LSB Differential Nonlinearity −1 +1.5 LSB Guaranteed no missing codes to 12 bits 0 V to V

Input Range Straight binary output coding

REFA

Offset Error −10 ±0.6 +10 LSB

Offset Error Match 3.5 LSB

Gain Error −2 +2 LSB

Gain Error Match −0.8 +0.8 LSB 0 V to 2 × V

Input Range

REFA

−V

REFA

to +V

biased about V

REFA

with

twos complement output coding offset Positive Gain Error −2 +2 LSB Positive Gain Error Match −0.8 +0.8 LSB Zero-Code Error −8 ±0.6 +8 LSB Zero-Code Error Match 2 LSB Negative Gain Error −1 +1 LSB Negative Gain Error Match −0.8 +0.8 LSB

ANALOG INPUT

Input Voltage Ranges 0 to V 0 to 2 × V

V Range bit set to 1

REFA

V

REFA

Range bit set to 0, ADCV

to 5.25 V for 0 V to 2 × V

DD/VDRIVE

REFAS

= 4.75 V

DC Leakage Current −1 +1 µA

4

Input Capacitance

20 pF

REFERENCE INPUT

V

Input Voltage 2.5 V ±1% specified performance

REFA

DC Leakage Current −1 +1 µA V

Input Impedance

REFA

4

36 kΩ f

SAMPLE

= 1 MSPS

Rev. 0 | Page 4 of 44

AD5590

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Parameter Min Typ Max Unit Test Conditions/Comments

2

LOGIC INPUTS

Input High Voltage, V Input Low Voltage, V Input Current, I

IN

Input Capacitance, C

0.7 × V

INH

0.3 × V

INL

V

DRIVE

V

DRIVE

−1 +1 µA Typically 10 nA

1, 4

IN

10 pF

LOGIC OUTPUTS

Output High Voltage, VOH V Output Low Voltage, VOL 0.4 V I Floating State Leakage Current ±10 µA

Floating State Output Capacitance4 10 pF

− 0.2 V I

DRIVE

= 200 µA; VDD = 2.7 V to 5.25 V

SOURCE

= 200 µA

SINK

weak/TRI weak/TRI

bit set to 0

bit set to 0 Output Coding Straight (Natural) Binary coding bit set to 1 Twos Complement coding bit set to 0

CONVERSION RATE4

Conversion Time 800 ns 16 ASCLK cycles, ASCLK = 20 MHz Track-and-Hold Acquisition Time

3

300 ns Sine wave input

300 ns Full-scale step input Throughput Rate 1 MSPS @ 5 V (see the Serial Interface section)

POWER REQUIREMENTS

ADCVDD 2.7 5.25 V V

2.7 5.25 V

DRIVE

I

0.15 µA

DRIVE

5

I

DD

Digital inputs = 0 V or V

DRIVE

Normal Mode, Static 750 µA VDD = 4.75 V to 5.25 V, ASCLK on or off Normal Mode, Operational

= Maximum Throughput)

(f

S

2.5 mA V

Autostandby Mode 1.55 mA f

= 4.75 V to 5.25 V, f

DD

= 500 kSPS

SAMPLE

= 20 MHz

SCLK

100 µA Static Autoshutdown Mode 960 µA f

= 250 kSPS

SAMPLE

0.5 µA Static Full Shutdown Mode 0.02 0.5 µA ASCLK on or off

Power Dissipation

Normal Mode, Operational 12.5 mW ADCVDD = 5 V, f

= 20 MHz

SCLK

Autostandby Mode, Static 500 µW ADCVDD = 5 V Autoshutdown Mode, Static 2.5 µW ADCVDD = 5 V Full Shutdown Mode 2.5 µW ADCVDD = 5 V

1

Specifications apply for f

2

Temperature range: −40°C to +85°C.

3

See the Terminology section.

4

Guaranteed by design and characterization. Not production tested.

5

See the ADC Power vs. Throughput Rate section.

up to 20 MHz. For serial interfacing requirements, see the Timing Specifications section.

SCLK

Rev. 0 | Page 5 of 44

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DAC SPECIFICATIONS

DACVDD = 4.5 V to 5.25 V, RL = 2 kΩ to DACGND, CL = 200 pF to DACGND, V unless otherwise noted.

REFIN1

= V

= DACVDD. All specifications T

REFIN1

MIN

to T

MAX

,

Table 2.

Parameter Min Typ Max Unit Conditions/Comments

2

STATIC PERFORMANCE

1

Resolution 12 Bits Integrated Nonlinearity (INL) −3 ±0.5 +3 LSB See Figure 6 Differential Nonlinearity (DNL) −0.25 +0.25 LSB Guaranteed monotonic by design; see Figure 7 Zero-Code Error 1 12 mV All 0s loaded to DAC register; see Figure 11 Zero-Code Error Drift

3

±2 µV/°C

Full-Scale Error −1 −0.2 % FSR All 1s loaded to DAC register Gain Error −1 +1 % FSR Gain Temperature Coefficient

3

±2.5 ppm Of FSR/°C

Offset Error −11 ±5 +11 mV

3

DC Power Supply Rejection Ratio DC Crosstalk

3

External Reference 10 µV

–80 dB DACVDD ± 10%

Due to full-scale output change, R DACV

= 2 kΩ to DACGND or

DD

L

5 µV/mA Due to load current change 10 µV Due to powering down (per channel) Internal Reference 25 µV

Due to full-scale output change, R DACV

DD

= 2 kΩ to DACGND or

L

10 µV/mA Due to load current change

OUTPUT CHARACTERISTICS

3

Output Voltage Range 0 DACVDD V Capacitive Load Stability 2 nF RL = ∞ 10 nF RL = 2 kΩ DC Output Impedance 0.5 Ω Short-Circuit Current 30 mA DACVDD = 5 V Power-Up Time 4 µs Coming out of power-down mode, DACVDD = 5 V

REFERENCE INPUTS

Reference Current 40 50 µA V

= DACVDD = 5.5 V (per DAC channel)

REFINx

Reference Input Range 0 DACVDD V Reference Input Impedance

3

14.6 kΩ

REFERENCE OUTPUT

Output Voltage 2.495 2.505 V At ambient Reference Temperature Coefficient Reference Output Impedance

3

±10 ppm/°C

3

7.5 kΩ

LOGIC INPUTS

Input Current −3 +3 µA All digital inputs Input Low Voltage, V Input High Voltage, V Pin Capacitance

0.8 V DACVDD = 5 V

INL

2 V DACVDD = 5 V

INH

3

5 pF

Rev. 0 | Page 6 of 44

AD5590

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Parameter Min Typ Max Unit Conditions/Comments

1

POWER REQUIREMENTS

DACVDD 4.5 5.5 V

All digital inputs at 0 or DACV

, DAC active, excludes load

DD

current

IDD (Normal Mode)

4

V

= DACVDD = 4.5 V to 5.5 V, VIL = DACGND

IH

2.6 3.2 mA Internal reference off 4 5 mA Internal reference on DACIDD (All Power-Down Modes)

5

DACVDD 0.8 2 µA VIH = DACVDD = 4.5 V to 5.5 V, VIL = DACGND

1

Temperature range is −40°C to +85°C, typical at 25°C.

2

Linearity calculated using a reduced code range of Code 32 to Code 4064. Output unloaded.

3

Guaranteed by design and characterization; not production tested.

4

Interface inactive. All DACs active. DAC outputs unloaded.

5

All sixteen DACs powered down.

DAC AC Characteristics

DACVDD = 4.5 V to 5.25 V, RL = 2 kΩ to DACGND, CL = 200 pF to DACGND, V

REFIN1

= V

= DACVDD. All specifications T

REFIN1

unless otherwise noted.

Table 3.

Parameter

1, 2

Min Typ Max Unit Conditions/Comments

3

Output Voltage Settling Time 6 10 µs ¼ to ¾ scale settling to ±2 LSB Slew Rate 1.5 V/µs Digital-to-Analog Glitch Impulse 4 nV-sec 1 LSB change around major carry (see Figure 17) Digital Feedthrough 0.1 nV-sec Reference Feedthrough −90 dB V

REFIN1

= V

= 2 V ± 0.1 V p-p, frequency = 10 Hz to 20 MHz

REFIN2

Digital Crosstalk 0.5 nV-sec Analog Crosstalk 2.5 nV-sec DAC-to-DAC Crosstalk 3 nV-sec Multiplying Bandwidth 340 kHz V Total Harmonic Distortion −80 dB V

REFIN1

= V

= 2 V ± 0.2 V p-p

REFIN2

= V

= 2 V ± 0.1 V p-p, frequency = 10 kHz

REFIN2

Output Noise Spectral Density 120 nV/√Hz DAC Code = 0x8400, 1 kHz 100 nV/√Hz DAC Code = 0x8400, 10 kHz Output Noise 15 V p-p 0.1 Hz to 10 Hz

1

Guaranteed by design and characterization; not production tested.

2

See the Terminology section.

3

Temperature range is −40°C to +85°C, typical at 25°C.

MIN

to T

MAX

,

Rev. 0 | Page 7 of 44

AD5590

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OPERATIONAL AMPLIFIER SPECIFICATIONS

Electrical characteristics @ VSY = 5 V, VCM = VSY/2, TA = 25°C, unless otherwise noted.

Table 4.

Parameter Symbol Min Typ Max Unit Conditions

INPUT CHARACTERISTICS

Offset Voltage VOS 0.4 2.2 mV −0.3 V < VCM < +5.3 V

2.2 mV −40°C < TA < +85°C, −0.3 V < VCM < +5.2 V Offset Voltage Drift Input Bias Current 110 pA −40°C < TA < +85°C Input Offset Current 50 pA −40°C < TA < +85°C Common-Mode Rejection Ratio CMRR 95 dB 0 V < VCM < 5 V 68 dB −40°C < TA < +85°C Large Signal Voltage Gain AVO 235 400 V/mV RL = 10 kΩ, 0.5 V < V

Input Capacitance1 C C OUTPUT CHARACTERISTICS

Output Voltage High VOH 4.95 4.98 V IL = 1 mA

4.9 V −40°C to +85°C

4.7 V IL = 10 mA

4.50 V −40°C to +85°C

Output Voltage Low VOL 20 30 mV IL = 1 mA

50 mV −40°C to +85°C

190 275 mV IL = 10 mA

335 mV −40°C to +85°C

Short-Circuit Current

Closed-Loop Output Impedance POWER SUPPLY

Power Supply Span (V+ to V−) 5 V

Power Supply Rejection Ratio PSRR 67 94 dB 1.8 V < VSY < 5 V

64 dB −40°C < TA < +85°C

Supply Current per Amplifier ISY 38 µA V 50 60 µA −40°C <TA < +85°C DYNAMIC PERFORMANCE1

Slew Rate SR 0.1 V/µs RL = 10 kΩ

Settling Time 0.1% t

Gain Bandwidth Product GBP 400 kHz RL = 100 kΩ

350 kHz RL = 10 kΩ

Phase Margin ØO 70 Degrees RL = 10 kΩ, RL = 100 kΩ, CL = 20 pF NOISE PERFORMANCE1

Peak-to-Peak Noise 2.3 3.5 µV

Voltage Noise Density en 25 nV/√Hz f = 1 kHz

22 nV/√Hz f = 10 kHz

Current Noise Density in 0.05 pA/√Hz f = 1 kHz

1

Guaranteed by design and characterization. Not production tested.

1

I

1

I

1

I

1

Z

VOS/T 1 4.5 µV/°C −40°C < TA < +85°C

0.2 1 pA

B

0.1 0.5 pA

OS

2 pF

DIFF

7 pF

CM

±80 mA

SC

15 Ω f = 10 kHz, AV = 1

OUT

= VSY/2

OUT

S

23 s G = ±1, 2 V step, CL = 20 pF, RL = 1 kΩ

OUT

< 4.5 V

Rev. 0 | Page 8 of 44

AD5590

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TIMING SPECIFICATIONS

ADC Timing Characteristics

ADCVDD = 2.7 V to 5.25 V, V

Table 5.

Parameter

f

SCLK

1

Limit at T

2 10 kHz min 20 MHz min t

16 × t

CONVER T

t

50 ns min

QUIET

t2 10 ns min

3

t

14 ns max

3

t3b4 20 ns min Data hold time

3

t

40 ns max Data access time after ASCLK falling edge

4

t5 0.4 × t t6 0.4 × t t7 15 ns min ASCLK to ADOUT valid hold time

5

t

8

15/50 ns min/max ASCLK falling edge to ADOUT high impedance t9 20 ns min ADIN setup time prior to ASCLK falling edge t10 5 ns min ADIN Hold time prior to ASCLK falling edge t11 20 ns min

t12 1 µs max

1

Guaranteed by design and characterization. Not production tested. All input signals are specified with tr = tf = 5 ns (10% to 90% of ADCVDD) and timed from a voltage

level of 1.6 V.

2

Maximum ASCLK frequency is 50 MHz at ADCVDD = 2.7 V to 5.5 V. Guaranteed by design and characterization; not production tested.

3

Measured with the load circuit of Figure 3 and defined as the time required for the output to cross 0.4 V or 0.7 × V

4

t3b represents a worst-case figure for having ADD3 available on the ADOUT line, that is, if the ADC goes back into three-state at the end of a conversion and some

other device takes control of the bus between conversions, the user needs to wait a maximum time of t3b before having ADD3 valid on the ADOUT line. If the ADOUT line is weakly driven to ADD3 between conversions, then the user typically needs to wait 17 ns at 3 V and 12 ns at 5 V after the valid on ADOUT.

5

t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 3. The measured number is then extrapolated

back to remove the effects of charging or discharging the 25 pF capacitor. This means that the time, t8, quoted in the timing characteristics, is the true bus relinquish time of the part and is independent of bus loading.

≤ ADCVDD, V

DRIVE

, T

MIN

MHz max

ASCLK

; ADCVDD = 5 V Unit Conditions/Comments

MAX

= 2.5 V; All specifications T

REFA

to T

MIN

to ASCLK setup time

ASYNC

MAX

Delay from ASYNC

ns min ASCLK low pulse width

ASCLK

ns min ASCLK high pulse width

ASCLK

th

ASCLK falling edge to ASYNC high

16 Power-up time from full power-down/autoshutdown/

autostandby modes

, unless otherwise noted.

until ADOUT three-state disabled

.

DRIVE

ASYNC

falling edge before seeing ADD3

ASYNC

ASCLK

DOUT

ADIN

t

THREE-

STATE

t

2

1 2 3 4 5 6 13 14 15 16

t

b

3

ADD3

3

ADD2 ADD1 ADD0 DB 11 DB10 DB2 DB1 DB0

t

FOUR IDENTIFICATION BITS

9

WRITE SEQ ADD3 ADD2 ADD1 ADD0 DONTC DONTC DONTC

t

4

t

6

CONVERT

t

10

t

7

B

t

5

Figure 2. ADC Timing Characteristics

200µA I

O OUTPUT

C

L

25pF

200µA I

Figure 3. Load Circuit for ADC Digital Output Timing Specifications

Rev. 0 | Page 9 of 44

OL

1.6V

OH

07691-003

t

11

t

8

t

QUIET

THREE-

STATE

07691-002

AD5590

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DAC Timing Characteristics

All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 4. DACV

Table 6.

Parameter

t

1

t2 8 ns min DSCLK high time t3 8 ns min DSCLK low time t4 13 ns min

t5 4 ns min Data setup time t6 4 ns min Data hold time t7 0 ns min t8 15 ns min

t9 13 ns min t10 0 ns min t11 10 ns min t12 15 ns min t13 5 ns min t14 0 ns min t15 300 ns typ

1

Sample tested at 25°C to ensure compliance.

2

Maximum DSCLK frequency is 50 MHz at VDD = 2.7 V to 5.5 V. Guaranteed by design and characterization; not production tested.

= 4.5 V to 5.5 V. All specifications T

DD

1

2

Limit at T

20 ns min DSCLK cycle time

MIN

, T

; DACVDD = 2.7 V to 5.5 V Unit Conditions/Comments

MAX

MIN

to T

, unless otherwise noted.

MAX

to DSCLK falling edge setup time

DSYNC

DSCLK falling edge to DSYNC Minimum DSYNC

rising edge to DSCLK fall ignore

DSYNC DSCLK falling edge to DSYNC

pulse width low

LDAC DSCLK falling edge to LDAC

pulse width low

CLR DSCLK falling edge to LDAC

pulse activation time

CLR

t

DSCLK

DSYNCx

DDIN

LDAC

10

t

8

1

DB31

t

4

t

6

t

5

t

1

t

3

2

DB0

t

9

t

7

t

11

t

14

rising edge

high time

fall ignore

rising edge

falling edge

t

12

2

LDAC

t

CLR

VOUTx

1

ASYNCHRONOUS LDAC UPDAT E MODE.

2

SYNCHRONOUS LDAC UPDAT E MODE.

13

t

15

Figure 4. DAC Timing Characteristics

Rev. 0 | Page 10 of 44

07691-004

AD5590

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ABSOLUTE MAXIMUM RATINGS

TA = 25°C unless otherwise noted. VDD refers to DACVDD or ADCV

. GND refers to DACGND or ADCGND.

DD

Table 7.

Parameter Rating

VDD to GND −0.3 V to +7 V V

to GND −0.3 V to VDD + 0.3 V

DRIVE

Op Amp Supply Voltage 6 V Op Amp Input Voltage

Op Amp Differential Input Voltage ±6 V Op Amp Output Short-Circuit

Duration to GND Analog Input Voltage to GND −0.3 V to VDD + 0.3 V Digital Input Voltage to GND −0.3 V to +7 V Digital Output Voltage to GND −0.3 V to VDD +0.3 V V

to GND −0.3 V to VDD +0.3 V

REFA

V

REFIN/VREFOUT

Input Current to Any ADC Pin

Except Supplies Operating Temperature Range −40°C to +85°C Storage Temperature Range −65°C to +150°C Junction Temperature (TJ max) 150°C

to GND −0.3 V to VDD +0.3 V

(V1− or V2−) − 0.3 V to (V1+ or V2+) + 0.3 V

Indefinite

±10 mA

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device soldered in a 4-layer JEDEC thermal test board for surfacemount packages.

Table 8. Thermal Resistance

Package Type θJA Unit

80-Ball CSP_BGA 40 °C/W

Table 9. Junction Temperature

Parameter

Junction Temperature

1

P

TOTAL

2

θ

JA

is the sum of ADC, DAC, and operational amplifier supply currents.

is the package thermal resistance.

Max Unit Comments

1, 2

130 °C TJ = TA + P

TOTAL

× θ

JA

ESD CAUTION

Rev. 0 | Page 11 of 44

AD5590

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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

121110987654321

VOUT14

VIN12

OUT7

IN7(–)

IN7(+)

IN6(+)

IN6(–)

V2–

OUT6

OUT5

IN5(–)

VOUT10

VIN10

VOUT9

VOUT11

VOUT13

VOUT15

V

REFIN2

V

REFOUT2

VIN15

V

REFA

VIN14

VIN11

/

VOUT8

VOUT12

VIN13

DACGND

VOUT1

V2+

LDAC

DACV

ADIN

DD

DDIN

DSYNC2

ASCLK

DSCLK

CLR

V

DRIVE

DSYNC1

DACGND

VIN1

DACV

VOUT3

VIN3

VOUT5

VOUT7

VIN8

VOUT2

VOUT4

VOUT6

V

REFIN1

REFOUT1

VIN5

V1–

VIN7

VIN6

VIN4

VOUT0

/

DD

VIN9

V

VIN2

OUT2

IN2(+)

IN2(–)

IN3(+)

IN3(–)

OUT3

OUT1

IN1(–)

IN1(+)

OUT0

A

B

C

D

E

F

G

H

J

K

L

IN5(+)

IN4(+)

IN4(–)

OUT4

Table 10. Pin Function Descriptions

Pin No. Mnemonic Description

M7

Frame Synchronization Signal. Active low logic input. This input provides the dual function of

ASYNC

initiating ADC conversions and also frames the serial data transfer.

J11 V

REFA

Reference Input for the ADC Block. An external reference must be applied to this input. The voltage range for the external reference is 2.5 V ± 1% for specified performance.

M8 ADCVDD

Power Supply Input for the ADC Block. The ADC can operate from 4.5 V to 5.25 V, and the supply should be decoupled with a 10 µF in parallel with a 0.1 µF capacitor to ADCGND.

M5 ADCGND

Ground Reference Point for the ADC Block. All ADC analog/digital input/output signals and any external reference signal should be referred to this ADCGND voltage.

M4, L5, L3, L4, L2, G2, K2, J2, B2, B3, B11, L11, B12, L10, K11, H11

VIN0 to VIN15

Analog Input 0 through Analog Input 15. Sixteen single-ended analog input channels that are multiplexed into the on-chip track and hold. The analog input channel to be converted is selected by using the ADD3 through ADD0 address bits of the control register. The address bits in conjunction with the SEQ and shadow bits allow the sequence register to be programmed. The input range for all input channels can extend from 0 V to V control register. Any unused input channels should be connected to GND to avoid noise pickup.

L8 ADIN

ADC Data In. Logic input. Data to be written to the control register of the ADC is provided on this input and is clocked into the register on the falling edge of ASCLK (see the Accessing the ADC Block section).

M6 ADOUT

Data Out. Logic output. The conversion result from the ADC block is provided on this output as a serial data stream. The bits are clocked out on the falling edge of the ASCLK input. The data stream consists of four address bits indicating which channel the conversion result corresponds to, followed by the 12 bits of conversion data, which is provided MSB first. The output coding can be selected as straight binary or twos complement via the coding bit in the control register.

ASYNC

ADCV

DD

Figure 5. Pin Configuration

ADOUT

ADCGND

or 0 V to 2 × V

REFA

VIN0

V1+

IN0(+)

IN0(–)

M

7691-005

, as selected via the range bit in the

REFA

Rev. 0 | Page 12 of 44

AD5590

www.BDTIC.com/ADI

Pin No. Mnemonic Description

L7 ASCLK

L6 V

DRIVE

A4, B8 DACVDD

A9, B5 DACGND

A8

A5

B7

B6

LDAC

DSYNC1

DSYNC2

Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is low, all LDAC pulses are

CLR

A7 DDIN

A6 DSCLK

A1, B9, C2, B4, D2, A3, E2, A2

A10, C11, B11, D11, B10, E11, A12, F11

F2

G11

VOUT0 to VOUT7

VOUT8 to VOUT15

/

V

REFIN1

V

REFOUT1

/

V

REFIN2

V

REFOUT2

M3 V1+

H2 V1− Negative Supply Input for Amplifier 0 to Amplifier 3. L9 V2+

H12 V2− Negative Supply Input for Amplifier 4 to Amplifier 7. M1, J1, D1, F1, M10,

L12, G12, D12 M2, K1, C1, E1, M11,

M12, F12, E12 L1, H1, B1, G1, M9,

K12, J12, C12

IN0(−) to IN7(−)

IN0(+) to IN7(+)

OUT0 to OUT7

Serial Clock. Logic input. ASCLK provides the serial clock for accessing data from the ADC block. This clock input is also used as the clock source for the conversion process of the ADC.

Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the serial interface of the ADC block operates.

Power Supply Input for the DAC Block. The DAC can operate from 4.5 V to 5.25 V, and the supply should be decoupled with a 10 µF in parallel with a 0.1 µF capacitor to DACGND. The two DACV

DD

must be connected together. Ground Reference Point for the DAC Block. All DAC analog/digital input/output signals and any

external reference signal should be referred to this DACGND voltage. The two DACGND pins should be connected together.

Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data. This allows all DAC outputs to simultaneously update. Alternatively, this pin can be tied permanently low.

Active Low Control Input. This is the frame synchronization signal for the input data of DAC channels

VOUT0 to VOUT7. When DSYNC1 input shift register. Data is transferred in on the falling edges of the next 32 clocks. If DSYNC1

nd

high before the 32

falling edge, the rising edge of DSYNC1 acts as an interrupt and the write

goes low, it powers on the DSCLK and DDIN buffers and enables the

is taken

sequence is ignored by the device.

Active Low Control Input. This is the frame synchronization signal for the input data of DAC channels

VOUT8 to VOUT15. When DSYNC2 input shift register. Data is transferred in on the falling edges of the next 32 clocks. If DSYNC2 high before the 32

nd

falling edge, the rising edge of DSYNC2 acts as an interrupt and the write

goes low, it powers on the DSCLK and DDIN buffers and enables the

is taken

sequence is ignored by the device.

ignored. When CLR

is activated, the input register and the DAC register are updated with the data contained in the CLR code register—zero scale, midscale, or full scale. Default setting clears the output to 0 V.

DAC Data Input. This DAC has a 32-bit shift register. Data is clocked into the register on the falling edge of the serial clock input.

DAC Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at rates of up to 50 MHz.

Analog Output Voltage from DAC0 to DAC7. DSYNC1 is the frame synchronization signal for writing data to these DACs. The DAC is updated automatically if LDAC

is low, or on the falling edge of LDAC if

it is high. The output amplifiers have rail-to-rail operation. Analog Output Voltage from DAC8 to DAC15. DSYNC2 is the frame synchronization signal for writing data to these DACs. The DAC is updated automatically if LDAC

is low, or on the falling edge of LDAC if

it is high. The output amplifiers have rail to rail operation. Reference Input/Output Pin for DAC0 to DAC7. The DACs have a common pin for reference input and

reference output. When using the internal reference, this is the reference output pin. When using an external reference, this is the reference input pin. The default for this pin is as a reference input.

Reference Input/Output Pin for DAC8 to DAC15. The DACs have a common pin for reference input and reference output. When using the internal reference, this is the reference output pin. When using an external reference, this is the reference input pin. The default for this pin is as a reference input.

Positive Supply Input for the amplifier 0 to amplifier 3. The supply for these amplifiers is independent of other supplies and can be operated with a different supply if required. The pin should be decoupled to V1− with a 10 µF in parallel with a 0.1 µF capacitor.

Positive Supply Input for Amplifier 4 to Amplifier 7. The supply for these amplifiers is independent of other supplies and can be operated with a different supply if required. The pin should be decoupled to V2− with a 10 µF in parallel with a 0.1 µF capacitor.

Inverting Input Terminals for Operational Amplifier 0 to Amplifier 7.

Noninverting Input Terminals for Operational Amplifier 0 to Amplifier 7.

Output Terminals for Operational Amplifier 0 to Amplifier 7.

pins

Rev. 0 | Page 13 of 44

AD5590

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TYPICAL PERFORMANCE CHARACTERISTICS

DAC

DACVDD and ADCVDD = 5 V, VSY = 5 V, unless otherwise noted.

1.0 DACVDD = V

T

= 25°C

0.8

A

0.6

0.4

0.2

0

–0.2

INL ERROR (LSB)

–0.4

–0.6

–0.8

–1.0

0 500 1000 1500 2000 2500 3000 3500 4000

REF

= 5V

CODE

Figure 6. DAC INL, External Reference Figure 9. DAC DNL, Internal Reference

07691-006

0.20 DACVDD = 5V V

= 2.5V

REFOUT

0.15

TA = 25°C

0.10

0.05

0

–0.05

DNL ERRO R (LSB)

–0.10

–0.15

–0.20

01000500 20001500 350030002500 4000

CODE

7691-009

0.20 DACVDD = V

T

= 25°C

A

0.15

0.10

0.05

0

–0.05

DNL ERROR (LSB)

–0.10

–0.15

–0.20

0 500 1000 1500 2000 2500 3000 3500 4000

REF

= 5V

CODE

Figure 7. DAC DNL, External Reference Figure 10. DAC Gain Error and Full-Scale Error vs. Temperature

1.0 DACVDD = 5V V

REFOUT

T

= 25°C

A

= 2.5V

CODE

0.8

0.6

0.4

0.2

0

–0.2

INL ERRO R (LS B)

–0.4

–0.6

–0.8

–1.0

01000500 20001500 350030002500 4000

Figure 8. DAC INL, Internal Reference Figure 11. DAC Zero-Scale Error and Offset Error vs. Temperature

0

DACVDD = 5V

–0.02

–0.04

–0.06

–0.08

–0.10

–0.12

ERROR (% F SR)

–0.14

–0.16

–0.18

–0.20

7691-007

7691-008

–40 –20 40200 1008060

1.5

1.0

0.5

0

–0.5

ERROR (mV)

–1.0

–1.5

OFFSET ERROR

–2.0

–2.5

–40 –20 40200860 100

GAIN ERROR

FULL-SCAL E ERROR

TEMPERATURE (°C)

ZERO-SCALE ERROR

TEMPERATURE (°C)

07691-010

0

07691-011

Rev. 0 | Page 14 of 44

ANALOG DEVICES AD5590 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

FUNCTIONAL BLOCK DIAGRAM

TABLE OF CONTENTS

REVISION HISTORY

GENERAL DESCRIPTION

SPECIFICATIONS

ADC SPECIFICATIONS

DAC SPECIFICATIONS

DAC AC Characteristics

OPERATIONAL AMPLIFIER SPECIFICATIONS

TIMING SPECIFICATIONS

ADC Timing Characteristics

DAC Timing Characteristics

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS