ANALOG DEVICES AD5541 Service Manual
2.7 V to 5.5 V, Serial-Input,
V
S
V
FEATURES
Full 16-bit performance
3 V and 5 V single-supply operation
Low 0.625 mW power dissipation
1 μs settling time
Unbuffered voltage output capable of driving 60 kΩ
loads directly
SPI-/QSPI-/MICROWIRE-compatible interface standards
Power-on reset clears DAC output to 0 V (unipolar mode)
5 kV HBM ESD classification
APPLICATIONS
Digital gain and offset adjustment
Automatic test equipment
Data acquisition systems
Industrial process control
Voltage-Output, 16-Bit DACs
AD5541/AD5542
FUNCTIONAL BLOCK DIAGRAMS
DD
8
REF
CLK
REFF
REFS
DIN
CS
3
4
6
5
6
5
AD5541
CONTROL
LOGIC
AD5542
16-BIT DAC LATCH
SERIAL INPUT REGISITER
DGND
Figure 1. AD5541
DD
14
R
INV
16-BIT DAC
7
16-BIT DAC
R
FB
1
2
1
13
2
3
V
OUT
AGND
RFB
INV
V
OUT
AGNDF
07557-001
GENERAL DESCRIPTION
The AD5541/AD5542 are single, 16-bit, serial input, voltage
output digital-to-analog converters (DACs) that operate from
a single 2.7 V to 5.5 V supply. The DAC output range extends
from 0 V to V
These DACs are guaranteed monotonic, providing 1 LSB INL at
16 bits without adjustment over the full temperature range.
Offering unbuffered outputs, the AD5541/AD5542 achieve low
power consumption and low offset errors.
The AD5542 can be operated in bipolar mode, which generates
a ±V
output swing. The AD5542 also includes Kelvin sense
REF
connections for the reference and analog ground pins to reduce
layout sensitivity.
REF
.
CS
LDAC
SCLK
DIN
11
10
7
8
CONTROL
LOGIC
16-BIT DAC LATCH
SERIAL INPUT REGISITER
12
DGND
4
AGNDS
07557-002
Figure 2. AD5542
The AD5541/AD5542 utilize a versatile 3-wire interface that is
compatible with SPI, QSPI™, MICROWIRE™ and DSP interface
standards. The AD5541/AD5542 are available in 8-lead and
14-lead SOIC packages.
PRODUCT HIGHLIGHTS
1. Single-Supply Operation. The AD5541 and AD5542 are
fully specified and guaranteed for a single 2.7 V to 5.5 V
supply.
2. Low Power Consumption. These parts consume typically
0.6 mW with a 5 V supply.
3. 3-Wire Serial Interface.
4. Unbuffered Output Capable of Driving 60 kΩ Loads. This
reduces power consumption because there is no internal
buffer to drive.
5. Power-On Reset Circuitry.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2008–2010 Analog Devices, Inc. All rights reserved.
AD5541/AD5542
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagrams ............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Timing Characteristics ................................................................ 4
Absolute Maximum Ratings ............................................................ 5
ESD Caution .................................................................................. 5
Pin Configurations and Function Descriptions ........................... 6
Typical Performance Characteristics ............................................. 7
Terminology .................................................................................... 10
Theory of Operation ...................................................................... 11
Digital-to-Analog Section ......................................................... 11
Serial Interface ............................................................................ 11
Unipolar Output Operation ...................................................... 11
Bipolar Output Operation ......................................................... 12
Output Amplifier Selection ....................................................... 12
Force Sense Amplifier Selection ............................................... 12
Reference and Ground ............................................................... 12
Power-On Reset .......................................................................... 13
Power Supply and Reference Bypassing .................................. 13
Microprocessor Interfacing ........................................................... 14
AD5541/AD5542 to ADSP-21xx Interface ............................. 14
AD5541/AD5542 to 68HC11/68L11 Interface ....................... 14
AD5541/AD5542 to MICROWIRE Interface ........................ 14
AD5541/AD5542 to 80C51/80L51 Interface .......................... 14
Applications Information .............................................................. 15
Optocoupler Interface ................................................................ 15
Decoding Multiple AD5541/AD5542s .................................... 15
Outline Dimensions ....................................................................... 16
Ordering Guide .......................................................................... 17
REVISION HISTORY
4/10—Rev. B to Rev. C
Changes to General Description Section ...................................... 1
Changes to Features List .................................................................. 1
Changes to Product Highlights ....................................................... 1
Changes to Table 1 ............................................................................ 3
Changes to Table 3 ............................................................................ 5
Changes to Figure 16, Figure 17, and Figure 19 ....................... 8, 9
Changes to Theory of Operations Section .................................. 11
Changes to Microprocessor Interfacing Section ........................ 14
Changes to Outline Dimensions ................................................... 16
Changes to Ordering Guide .......................................................... 17
8/08—Rev. A to Rev. B
Updated Format .................................................................. Universal
Changes to Timing Characteristics Section .................................. 4
Changes to Table 3 ............................................................................ 5
Updated Outline Dimensions ....................................................... 16
Changes to Ordering Guide .......................................................... 17
10/99—Rev. 0 to Rev. A
Rev. C | Page 2 of 20
AD5541/AD5542
SPECIFICATIONS
VDD = 2.7 V to 5.5 V, 2.5 V ≤ V
Table 1.
Parameter1 Min Typ Max Unit Test Conditions
STATIC PERFORMANCE
Resolution 16 Bits
Relative Accuracy (INL) ±0.5 ±1.0 LSB L, C grades
±0.5 ±2.0 LSB B, J grades
±0.5 ±4.0 LSB A grade
Differential Nonlinearity (DNL) ±0.5 ±1.0 LSB Guaranteed monotonic
±1.5 LSB J grade
Gain Error +0.5 ±2 LSB TA = 25°C
±3 LSB
Gain Error Temperature Coefficient ±0.1 ppm/°C
Unipolar Zero Code Error ±0.3 ±0.7 LSB TA = 25°C
±1.5 LSB
Unipolar Zero Code Temperature Coefficient ±0.05 ppm/°C
AD5542
Bipolar Resistor Matching 1.000 Ω/Ω RFB/R
±0.0015 ±0.0076 % Ratio error
Bipolar Zero Offset Error ±1 ±5 LSB TA = 25°C
±6 LSB
Bipolar Zero Temperature Coefficient ±0.2 ppm/°C
Bipolar Zero Code Offset Error ±1 ±5 LSB TA = 25°C
Bipolar Gain Error +1 ±5 LSB TA = 25°C
Bipolar Gain Temperature Coefficient ±0.1 ppm/°C
OUTPUT CHARACTERISTICS
Output Voltage Range 0 V
−V
Output Voltage Settling Time 1 μs To 1/2 LSB of FS, CL = 10 pF
Slew Rate 17 V/μs CL = 10 pF, measured from 0% to 63%
Digital-to-Analog Glitch Impulse 1.1 nV-sec 1 LSB change around the major carry
Digital Feedthrough 0.2 nV-sec All 1s loaded to DAC, V
DAC Output Impedance 6.25 kΩ Tolerance typically 20%
Power Supply Rejection Ratio ±1.0 LSB ΔVDD ± 10%
DAC REFERENCE INPUT
Reference Input Range 2.0 VDD V
Reference Input Resistance2 9 kΩ Unipolar operation
7.5 kΩ AD5542, bipolar operation
LOGIC INPUTS
Input Current ±1 μA
Input Low Voltage, V
Input High Voltage, V
Input Capacitance3 10 pF
Hysteresis Voltage3
REFERENCE 3
Reference −3 dB Bandwidth 2.2 MHz All 1s loaded
Reference Feedthrough 1 mV p-p All 0s loaded, V
Signal-to-Noise Ratio 92 dB
Reference Input Capacitance 26 pF Code 0x0000
26 pF Code 0xFFFF
0.8 V
INL
2.4 V
INH
≤ VDD, AGND = DGND = 0 V. All specifications TA = T
REF
±6
±6
− 1 LSB V Unipolar operation
REF
V
REF
− 1 LSB V AD5542 bipolar operation
REF
0.15 V
Rev. C | Page 3 of 20
MIN
LSB
to T
, unless otherwise noted.
MAX
INV
LSB
, typically RFB = R
= 1 V p-p at 100 kHz
REF
= 28 kΩ
INV
= 2.5 V
REF
AD5541/AD5542
Parameter
1
Min Typ Max Unit Test Conditions
POWER REQUIREMENTS Digital inputs at rails
VDD 2.7 5.5 V
IDD 125 150 μA
Power Dissipation 0.625 0.825 mW
1
Temperature ranges are as follows: A, B, C versions: −40°C to +85°C; J, L versions: 0°C to 70°C.
2
Reference input resistance is code-dependent, minimum at 0x8555.
3
Guaranteed by design, not subject to production test.
TIMING CHARACTERISTICS
VDD = 2.7 V to 5.5 V ±10%, V
+85°C, unless otherwise noted.
Table 2.
1, 2
Parameter
f
25 MHz max SCLK cycle frequency
SCLK
t1 40 ns min SCLK cycle time
t2 20 ns min SCLK high time
t3 20 ns min SCLK low time
t4 10 ns min
t5 15 ns min
t6 30 ns min
t7 20 ns min
t8 15 ns min Data setup time
t9 4 ns min Data hold time (V
t9 7.5 ns min Data hold time (V
t10 30 ns min
t11 30 ns min
t12 30 ns min
1
Guaranteed by design and characterization. Not production tested
2
All input signals are specified with tR = tF = 1 ns/V and timed from a voltage level of (V
SCLK
CS
= 2.5 V, V
REF
= 3 V and 90% of VDD, V
INH
= 0 V and 10% of VDD, AGND = DGND = 0 V; −40°C < TA <
INL
Limit Unit Description
low to SCLK high setup
CS
high to SCLK high setup
CS
SCLK high to CS
SCLK high to CS
pulsewidth
LDAC
high to LDAC low setup
CS
high time between active periods
CS
t
1
t
6
t
4
t
12
t
8
t
5
t
2
t
3
low hold time
high hold time
INH
INH
+ V
)/2.
INL
INH
= 90% of VDD, V
= 3V, V
t
7
= 0 V)
INL
t
5
= 10% of VDD)
INL
DIN
LDAC*
*AD5542 ONLY. CAN BE TIED PERMANENT LY LOW IF REQUIRE D.
DB15
Figure 3. Timing Diagram
Rev. C | Page 4 of 20
t
11
t
10
07557-003
AD5541/AD5542
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter Rating
VDD to AGND −0.3 V to +6 V
Digital Input Voltage to DGND −0.3 V to VDD + 0.3 V
V
to AGND −0.3 V to VDD + 0.3 V
OUT
AGND, AGNDF, AGNDS to DGND −0.3 V to +0.3 V
Input Current to Any Pin Except Supplies ±10 mA
Operating Temperature Range
Industrial (A, B, C Versions) −40°C to +85°C
Commercial (J, L Versions) 0°C to 70°C
Storage Temperature Range −65°C to +150°C
Maximum Junction Temperature (TJ max) 150°C
Package Power Dissipation ( TJ max – TA)/θJA
Thermal Impedance, θJA
SOIC (R-8) 149.5°C/W
SOIC (R-14) 104.5°C/W
Lead Temperature, Soldering
Peak Temperature1 260°C
ESD2 5 kV
1
As per JEDEC Standard 20.
2
HBM Classification
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. C | Page 5 of 20
AD5541/AD5542
A
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
V
1
OUT
CS
AD5541
2
3
TOP VIEW
(Not to S cale)
4
AGND
REF
Figure 4. AD5541 Pin Configuration
Table 4. AD5541 Pin Function Descriptions
Pin No. Mnemonic Description
1 V
Analog Output Voltage from the DAC.
OUT
2 AGND Ground Reference Point for Analog Circuitry.
3 REF Voltage Reference Input for the DAC. Connect to an external 2.5 V reference. Reference can range from 2 V to VDD.
CS
4
Logic Input Signal. The chip select signal is used to frame the serial data input.
5 SCLK Clock Input. Data is clocked into the input register on the rising edge of SCLK. Duty cycle must be between 40% and 60%.
6 DIN Serial Data Input. This device accepts 16-bit words. Data is clocked into the input register on the rising edge of SCLK.
7 DGND Digital Ground. Ground reference for digital circuitry.
8 VDD Analog Supply Voltage, 5 V ± 10%.
RFB
1
V
2
OUT
3
AGNDF
GNDS
REFS
REFF
Figure 5. AD5542 Pin Configuration
AD5542
TOP VIEW
4
(Not to Scale)
5
6
7
CS
NC = NO CONNECT
8
7
6
5
14
13
12
11
10
9
8
V
DD
DGND
DIN
SCLK
V
DD
INV
DGND
LDAC
DIN
NC
SCLK
07557-004
07557-005
Table 5. AD5542 Pin Function Descriptions
Pin No. Mnemonic Description
1 RFB Feedback Resistor Pin. In bipolar mode, connect this pin to the external op amp output.
2 V
Analog Output Voltage from the DAC.
OUT
3 AGNDF Ground Reference Point for Analog Circuitry (Force).
4 AGNDS Ground Reference Point for Analog Circuitry (Sense).
5 REFS Voltage Reference Input (Sense) for the DAC. Connect to an external 2.5 V reference. Reference can range from 2 V to VDD.
6 REFF Voltage Reference Input (Force) for the DAC. Connect to an external 2.5 V reference. Reference can range from 2 V to VDD.
CS
7
Logic Input Signal. The chip select signal is used to frame the serial data input.
8 SCLK Clock Input. Data is clocked into the input register on the rising edge of SCLK. Duty cycle must be between 40% and 60%.
9 NC No Connect.
10 DIN Serial Data Input. This device accepts 16-bit words. Data is clocked into the input register on the rising edge of SCLK.
11
LDAC Input. When this input is taken low, the DAC register is simultaneously updated with the contents of the
LDAC
input register.
12 DGND Digital Ground. Ground reference for digital circuitry.
13 INV
Connected to the Internal Scaling Resistors of the DAC. Connect the INV pin to external op amps inverting input in
bipolar mode.
14 VDD Analog Supply Voltage, 5 V ± 10%.
Rev. C | Page 6 of 20
Loading...