Analog Devices AD5535 pre Datasheet
32-Channel, 14-Bit DAC with Full-Scale Output
Voltage Programmable from 50 V to 200 V
Preliminary Technical Data
FEATURES
High integration: 32-channel, 14-bit DAC with integrated,
high voltage output amplifier
Guaranteed monotonic
Housed in 15 × 15 mm CSP-BGA package
Full-scale output voltage programmable from 50 V to 200 V
via reference input
700 µA drive capability
Integrated silicon diode for temperature monitoring
DSP-/microcontroller-compatible serial interface
Channel update rate: 1.2 MHz
Asynchronous
Temperature range: –10°C to +85°C
APPLICATIONS
Optical micro-electromechanical systems (MEMS)
Optical cross-point switches
Micropositioning applications using Piezo Flextures
Level setting in automotive test and measurement
RESET
facility
DV
CC
AV
CC
FUNCTIONAL BLOCK DIAGRAM
REF_IN
AD5535
GENERAL DESCRIPTION
The AD5535 is a 32-channel, 14-bit DAC with an on-chip high
voltage output amplifier. This device is targeted for optical
micro-electromechanical systems. The output voltage range is
programmable via the REFIN pin. Output range is 0 V to 50 V
with REFIN = 1 V and is 0 V to 200 V with REFIN = 4 V. Each
amplifier can source 700 µA, which is ideal for the deflection
and control of optical MEMS mirrors.
The selected DAC register is written to via the 3-wire interface.
The serial interface operates at clock rates of up to 30 MHz and
is compatible with DSP and microcontroller interface standards.
The device is operated with AV
to 5.25 V, V
= −4.75 V to −5.25 V, V+ = +4.75 V to +5.25 V, VPP
–
= 210 V. REF_IN is buffered internally on the AD5535 and
should be driven from a stable reference source.
V
PP
PGND
= 4.75 to 5.25 V, DVCC = 2.7 V
CC
V
–
V
+
RESET
DAC_GND
AGND
DGND
Rev. PrE
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However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
AD5535
INTERFACE
CONTROL
LOGIC
SCLK
D
IN
DAC
14-BIT BUS
DAC
DAC
DAC
SYNC
Figure 1.
ANODE
CATHODE
R1
RF
R1
RF
R1
RF
R1
RF
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
www.analog.com
V
0
OUT
V
1
OUT
V
30
OUT
31
V
OUT
05068-001
AD5535 Preliminary Technical Data
TABLE OF CONTENTS
Specifications..................................................................................... 3
Timing Characteristics ................................................................ 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Te r m in o l o g y ...................................................................................... 9
Typical Performance Characteristics........................................... 10
Functional Description ..................................................................11
Digital-to-Analog Section......................................................... 11
Reset Function ............................................................................11
Serial Interface............................................................................ 11
REVISION HISTORY
10/04—Revision PrE: Preliminary Version
Microprocessor Interfacing....................................................... 11
Applications Information.............................................................. 13
MEMS Mirror Control Application......................................... 13
AD5535 Board Layout to Ensure Compliance with IPC-221
Specification
Power Supply Sequencing and Decoupling Recommendations
....................................................................................................... 14
Guidelines for Printed Circuit Board Layout......................... 14
Outline Dimensions....................................................................... 15
Ordering Guide .......................................................................... 15
................................................................................ 13
Rev. PrE | Page 2 of 16
Preliminary Technical Data AD5535
SPECIFICATIONS
VPP = 210 V, V− = −5 V, V+ = +5 V; AVCC = 5.25 V; DVCC = 2.7 V to 5.25 V; AGND = DGND = DAC_GND = 0 V; REF_IN = 4.096 V;
all outputs unloaded. All specifications T
MIN
to T
Table 1.
Parameter
1
DC PERFORMANCE
Resolution
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
Zero Code Voltage
Offset Error –45
Offset Drift
Voltage Gain 47.5 50 52.5 V/V
Gain Temperature Coefficient
Channel-to-Channel Gain Match
Full-Scale Voltage Drift
OUTPUT CHARACTERISTICS
Output Voltage Range
3
Output Impedance
Resistive Load
Capacitive Load
4, 5
4
Short-Circuit Current
DC Crosstalk
DC Power Supply Rejection (PSRR), V
4
PP
AC CHARACTERISTICS
Settling Time
1/4 to 3/4 Scale Step
1 LSB Step
Slew Rate
–3 dB Bandwidth 5
Output Noise Spectral Density
0.1 Hz to 10 Hz Output Noise Voltage
Digital-to-Analog Glitch Impulse
Digital Crosstalk
Analog Crosstalk
Digital Feedthrough
VOLTAGE REFERENCE, REF_IN
Input Voltage Range
6
4
1
Input Current
TEMPERATURE MEASUREMENT DIODE
4
Peak Inverse Voltage, PIV
Forward Diode Drop, VF
Forward Diode Current, IF
VF Temperature Coefficient, T
C
, unless otherwise noted.
MAX
A Grade
Min Typ Max
0
1
2
Unit Conditions/Comments
14
±0.1
Bits
% of FSR
±0.5 ±1 LSB Guaranteed monotonic
2 V
0.09
TBD
5
8
50
+45 mV
VPP – 10 V
200 pF
0.7
3 LSB
70
30
100
10
10
10
3
TBD
TBD
TBD
TBD
13
TBD
LSB/°C
ppm/°C
%
ppm/°C
Ω
MΩ
mA
dB
µs No load
µs 200 pF load
µs No load
µs 200 pF load
V/µs No load
V/µs 200 pF load
kHz
nV/√Hz
µV p-p
nV–s typ 1 LSB change around major carry
nV–s typ
µV–s typ
nV–s typ
Measured at 1 kHz
AVCC must exceed REFIN by 1.25 V min
4.096 V
1 µA
5 V Cathode to anode
0.8 V IF = 2 mA, anode to cathode
2 mA Anode to cathode
–1.44
mV/°C IF = 250 µA
Rev. PrE | Page 3 of 16
AD5535 Preliminary Technical Data
2
Unit Conditions/Comments
±5 ±10 µA
0.8 V DVCC = 3 V to 5 V
200
V DVCC = 3 V to 5 V
mV
10 pF
Parameter
DIGITAL INPUTS
1
4
Input Current
Input Low Voltage
Input High Voltage 2.0
Input Hysteresis (SCLK and
SYNC
only)
Input Capacitance
A Grade
Min Typ Max
POWER-SUPPLY VOLTAGES
VPP (50 × REF_IN) +10 210 225 V
V
–
–5.25 –4.75 V
V+ 4.75 5.25 V
AVCC 4.75 5.25 V
DVCC 2.7 5.25 V
POWER-SUPPLY CURRENTS
7
IPP 75 110 µA/channel
I
−
2.5 3.5 mA
I+ 2.5 3.5 mA
AICC 16 20 mA
DICC 0.1 0.5 mA
POWER DISSIPATION7 609 mW
1
See Terminology.
2
A Grade temperature range: −10°C to +85°C; typically +25°C.
3
Linear output voltage range: +7 V to VPP − 10 V.
4
Guaranteed by design and characterization, not production tested.
5
Ensure that TJ max is not exceeded. See the section. Absolute Maximum Ratings
6
Reference input determines output voltage range. Using a 4.096 V reference (REF 198) gives an output voltage range of 0 V to 200 V. Output range is programmable
via the reference input. The full-scale output range is programmable from 50 V to 200 V. The linear output voltage range is restricted from 7 V to V
7
Outputs unloaded.
− 10 V.
PP
Rev. PrE | Page 4 of 16
Preliminary Technical Data AD5535
TIMING CHARACTERISTICS
VPP = 210 V, V− = –5 V, V+ = +5 V; AVCC = 5.25 V; DVCC = 2.7 V to 5.25 V; AGND = DGND = DAC_GND = 0 V; REF_IN = 4.096 V.
All specifications T
MIN
to T
Table 2.
Parameter1, 2,
f
UPDATE
f
CLKIN
t
13 ns min SCLK High Pulse Width
1
t
2
t
3
t
50 ns min
4
t
5
t
10 ns min DIN Setup Time
6
t
5 ns min DIN Hold Time
7
t
8
t
20 ns min
9
3
1
See timing diagrams in Figure 2.
2
Guaranteed by design and characterization, not production tested.
3
All input signals are specified with tr = tf = 5 ns (10% to 90% of DVCC) and timed from a voltage level of (VIL + VIH)/2.
SCLK
, unless otherwise noted.
MAX
A Grade Unit Conditions/Comments
1.2 MHz max Channel Update Rate
30 MHz max SCLK Frequency
13 ns min SCLK Low Pulse Width
15 ns min
10 ns min
200 ns min
t
1
1
t
t
5
2
3
34
t
2
SYNC
Falling Edge to SCLK Falling Edge Setup Time
SYNC
Low Time
SYNC
High Time
19th SCLK Falling Edge to
RESET
Pulse Width
5
SYNC
16 17 18 19
Falling Edge for Next Write
1
SYNC
D
RESET
IN
t
9
MSB
t
4
t
6
t
7
LSB
t
8
05068-002
Figure 2. Serial Interface Timing Diagram
Rev. PrE | Page 5 of 16
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