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AD5533B a
Datasheet
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Analog Devices AD5533B a Datasheet

32-Channel Precision
a
FEATURES Infinite Sample-and-Hold Capability to ⴞ0.018% Accuracy Infinite Sample-and-Hold Total Unadjusted Error ⴞ2.5 m V High Integration:
32-Channel DAC in 12 mm ⴛ 12 mm CSPBGA Per Channel Acquisition Time of 16 ␮s Max Adjustable Voltage Output Range Output Impedance 0.5 ⍀ Output Voltage Span 10 V Readback Capability DSP/Microcontroller Compatible Serial Interface Parallel Interface Temperature Range –40ⴗC to +85ⴗC
APPLICATIONS Optical Networks Automatic Test Equipment Level Setting Instrumentation Industrial Control Systems Data Acquisition Low Cost I/O
Infinite Sample-and-Hold
AD5533B

GENERAL DESCRIPTION

The AD5533B combines a 32-channel voltage translation function with an infinite output hold capability. An analog input voltage on the common input pin, V tation transferred to a chosen DAC register. V is then updated to reflect the new contents of the DAC register. Channel selection is accomplished via the parallel address inputs A0–A4 or via the serial input port. The output voltage range is determined by the offset voltage at the OFFS_IN pin and the gain of the output amplifier. It is restricted to a range from V to V
– 2 V because of the headroom of the output amplifier.
DD
The device is operated with AV to +5.25 V, V
= –4.75 V to –16.5 V, and VDD = +8 V to
SS
+16.5 V and requires a stable 3 V reference on REF_IN as well as an offset voltage on OFFS_IN.

PRODUCT HIGHLIGHTS

1. Precision infinite droopless sample-and-hold capability.
2. The AD5533B is available in a 74-lead CSPBGA with a body size of 12 mm ⫻ 12 mm.
3. In infinite sample-and-hold mode, a total unadjusted error of ±2.5 mV is achieved by laser-trimming on-chip resistors.
, is sampled and its digital represen-
IN
= +5 V ± 5%, DVCC = +2.7 V
CC
for this DAC
OUT
*
+ 2 V
SS

FUNCTIONAL BLOCK DIAGRAM

DV
AV
CC
V
IN
TRACK / RESET
BUSY
GND
DAC
AGND
DGND
SER / PAR
*Protected by U.S. Patent No. 5,969,657; other patents pending.
AD5533B
ADC
INTERFACE
CONTROL
LOGIC
DIND
CC
OUT
REF IN REF OUT
REV. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
IN
CAL
VDDV
OFFSET SEL
SS
0
V
OUT
31
V
OUT
OFFS
OUT
WR
OFFS
DAC
DAC
DAC
ADDRESS INPUT REGISTER
SYNC/ CS
A4– A0SCLK
AD5533B
Output Range from V
(VDD = +8 V to +16.5 V, VSS = –4.75 V to –16.5 V; AVCC = +4.75 V to +5.25 V;
–SPECIFICATIONS
+ 2 V to VDD – 2 V. All outputs unloaded. All specifications T
SS
DVCC = 2.7 V to 5.25 V; AGND = DGND = DAC_GND = 0 V; REF_IN = 3 V; OFFS_IN = 0 V;
MIN
to T
, unless otherwise noted.)
MAX
Parameter
1
B Version
2
Unit Conditions/Comments
ANALOG CHANNEL
VIN to V
Nonlinearity ±0.006 % typ Input Range 100 mV to 2.96 V
OUT
±0.018 % max After Gain and Offset Adjustment
Total Unadjusted Error (TUE) ±2.5 mV typ See TPC 6.
±12 mV
max Gain 3.51/3.52/3.53 min/typ/max Offset Error
ANALOG INPUT (V
±1 ±10 mV
)
IN
mV typ
max
See TPC 2.
Input Voltage Range 0 to 3 V Nominal Input Range Input Lower Dead Band 70 mV max 50 mV typ. Referred to V
IN
See Figure 5.
Input Upper Dead Band 40 mV max 12 mV typ. Referred to V
IN
See Figure 5.
Input Current 1 µA max 100 nA typ. V
one channel.
Input Capacitance
3
20 pF typ
acquired on
IN
ANALOG INPUT (OFFS_IN)
Input Voltage Range 0/4 V min/max Output Range Restricted from
+ 2 V to VDD – 2 V
V
SS
Input Current 1 µA max 100 nA typ
VOLTAGE REFERENCE
REF_IN
Nominal Input Voltage 3.0 V Input Voltage Range
3
2.85/3.15 V min/max
Input Current 1 µA max <1 nA typ
REF_OUT
Output Voltage 3 V typ Output Impedance Reference Temperature Coefficient
ANALOG OUTPUTS (V
Output Temperature Coefficient DC Output Impedance 0.5 Output Range V Resistive Load Capacitive Load Short-Circuit Current DC Power Supply Rejection Ratio
DC Crosstalk
ANALOG OUTPUT (OFFS_OUT)
Output Temperature Coefficient DC Output Impedance
3
3
0–31)
OUT
3, 5
3, 5
3
3
3
3, 4
3
3, 4
280
kΩ
typ
60 ppm/°C typ
10 ppm/°C typ
Ω
typ
+ 2/VDD – 2 V min/max 100 µA Output Load
SS
5
kΩ
min 100 pF max 7 mA typ –70 dB typ VDD= +15 V ± 5% –70 dB typ V
= –15 V ± 5%
SS
250 µV max Outputs Loaded
10 ppm/°C typ
1.3
kΩ
typ
Output Range 50 to REF_IN – 12 mV typ Output Current 10 µA max Source Current Capacitive Load 100 pF max
DIGITAL INPUTS
3
Input Current ±10 µA max 5 µA typ Input Low Voltage 0.8 V max DV
0.4 V max DV
Input High Voltage 2.4 V min DV
2.0 V min DV
= 5 V ± 5%
CC
= 3 V ± 10%
CC
= 5 V ± 5%
CC
= 3 V ± 10%
CC
Input Hysteresis (SCLK and CS Only) 200 mV typ Input Capacitance 10 pF max
.
.
–2–
REV. A
AD5533B
Parameter
1
DIGITAL OUTPUTS (BUSY, D
OUT
B Version
3
)
2
Unit Conditions/Comments
Output Low Voltage 0.4 V max DVCC = 5 V. Sinking 200 µA. Output High Voltage 4.0 V min DV
= 5 V. Sourcing 200 µA.
CC
Output Low Voltage 0.4 V max DVCC = 3 V. Sinking 200 µA. Output High Voltage 2.4 V min DV High Impedance Leakage Current ± 1 µA max D High Impedance Output Capacitance 15 pF typ D
= 3 V. Sourcing 200 µA.
CC
Only
OUT
Only
OUT
POWER REQUIREMENTS
Power Supply Voltages
V
DD
V
SS
AV
CC
DV
CC
Power Supply Currents
I
DD
I
SS
AI
CC
DI
CC
Power Dissipation
NOTES
1
See Terminology section.
2
B Version: Industrial temperature range –40°C to +85°C; typical at +25°C.
3
Guaranteed by design and characterization, not production tested.
4
AD780 as reference for the AD5533B.
5
Ensure that you do not exceed TJ (max). See Absolute Maximum Ratings.
6
Outputs unloaded.
Specifications subject to change without notice.
6
6
8/16.5 V min/max –4.75/–16.5 V min/max
4.75/5.25 V min/max
2.7/5.25 V min/max
15 mA max 10 mA typ. All channels full-scale. 15 mA max 10 mA typ. All channels full-scale. 33 mA max 26 mA typ
1.5 mA max 1 mA typ 280 mW typ VDD = +10 V, VSS = –5 V
(VDD = +8 V to +16.5 V, VSS = –4.75 V to –16.5 V; AVCC = +4.75 V to +5.25 V; DVCC = +2.7 V to +5.25 V;

AC CHARACTERISTICS

All outputs unloaded. All specifications T
Parameter B Version
Output Settling Time Acquisition Time 16 µs max OFFS_IN Settling Time Digital Feedthrough Output Noise Spectral Density @ 1 kHz AC Crosstalk
NOTES
1
B version: Industrial temperature range –40°C to +85°C; typical at 25°C.
2
Guaranteed by design and characterization, not production tested.
Specifications subject to change without notice.
2
2
2
2
AGND = DGND = DAC_GND = 0 V; REF_IN = 3 V; OFFS_IN = 0 V; Output Range from V
to T
MIN
, unless otherwise noted.)
MAX
1
Unit Conditions/Comments
3 µs max
10 µs max 500 pF, 5 kΩ Load; 0 V–3 V Step
2
0.2 nV-s typ 400 nV/√Hz typ 5nV-s typ
+ 2 V to VDD – 2 V.
SS
REV. A
–3–
AD5533B

TIMING CHARACTERISTICS

PARALLEL INTERFACE
Parameter
t
1
t
2
t
3
t
4
t
5
t
6
NOTES
1
See Parallel Interface Timing Diagram.
2
Guaranteed by design and characterization, not production tested.
Specifications subject to change without notice.
1, 2
Limit at T (B Version) Unit Conditions/Comments
0 ns min CS to WR Setup Time 0 ns min CS to WR Hold Time 50 ns min CS Pulsewidth Low 50 ns min WR Pulsewidth Low 20 ns min A4–A0, CAL, OFFS_SEL to WR Setup Time 7 ns min A4–A0, CAL, OFFS_SEL to WR Hold Time
SERIAL INTERFACE
Parameter
f
CLKIN
t
1
t
2
t
3
t
4
t
5
t
6
t
7
3
t
8
3
t
9
t
10
4
t
11
NOTES
1
See Serial Interface Timing Diagrams.
2
Guaranteed by design and characterization, not production tested.
3
These numbers are measured with the load circuit of Figure 2.
4
SYNC should be taken low while SCLK is low for readback.
Specifications subject to change without notice.
1, 2
Limit at T (B Version) Unit Conditions/Comments
20 MHz max SCLK Frequency 20 ns min SCLK High Pulsewidth 20 ns min SCLK Low Pulsewidth 15 ns min SYNC Falling Edge to SCLK Falling Edge Setup Time 50 ns min SYNC Low Time 10 ns min DIN Setup Time 5 ns min DIN Hold Time 5 ns min SYNC Falling Edge to SCLK Rising Edge Setup Time for Readback 20 ns max SCLK Rising Edge to D 60 ns max SCLK Falling Edge to D 400 ns min10th SCLK Falling Edge to SYNC Falling Edge for Readback 7 ns min SCLK Falling Edge to SYNC Falling Edge Setup Time for
MIN
MIN
, T
, T
MAX
MAX
Readback
Valid
OUT
High Impedance
OUT

PARALLEL INTERFACE TIMING DIAGRAM

CS
WR
A4– A0 , CAL,
SEL
OFFS
Figure 1. Parallel Write (ISHA Mode Only)
OUTPUT
Figure 2. Load Circuit for D
–4–
TO
PIN
C
L
50pF
200␮A
200␮A
I
OL
1.6V
I
OH
Timing Specifications
OUT
REV. A

SERIAL INTERFACE TIMING DIAGRAMS

S
t
1
SCLK
12345678 910
AD5533B
SYNC
D
SCLK
YNC
D
OUT
t
3
IN
MSB LSB
t
2
t
4
t
5
t
6
Figure 3. 10-Bit Write (ISHA Mode and Both Readback Modes)
t
7
10
t
11
t
10
t
1
213456789
t
2
t
4
t
8
MSB
10
11
12 13 14
t
9
LSB
Figure 4. 14-Bit Read (Both Readback Modes)
REV. A
–5–
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