Analog Devices AD5429 39 49 Datasheet

Dual 8-,10-,12-Bit High Bandwidth

FEATURES

10 MHz multiplying bandwidth 50 MHz serial interface

2.5 V to 5.5 V supply operation ±10 V reference input Pin compatible 8-, 10-, and 12-bit DACs Extended temperature range: −40°C to +125°C 16-lead TSSOP package Guaranteed monotonic Power-on reset Daisy-chain mode Readback function

0.5 µA typical current consumption

APPLICATIONS

Portable battery-powered applications Waveform generators Analog processing Instrumentation applications Programmable amplifiers and attenuators Digitally controlled calibration Programmable filters and oscillators Composite video Ultrasound Gain, offset, and voltage trimming

Multiplying DACs with Serial Interface

AD5429/AD5439/AD5449

FUNCTIONAL BLOCK DIAGRAM

V

A

REF

8-/10-/12-BIT R-2R DAC A

8-/10-/12-BIT R-2R DAC B

V

B

REF

RFB

R

A

FB

I

1A

OUT

I

2A

OUT

I

1B

OUT

2B

I

OUT

RFBB

RFB

R

) determines

04464-0-001

AD5429/AD5439/AD5449

V

DD

SYNC SCLK

SDIN

SDO

CLR

SHIFT

REGISTER

POWER-ON

RESET

INPUT

REGISTER

INPUT

REGISTER

DAC

REGISTER

LDAC

DAC

REGISTER

LDAC

Figure 1.

GENERAL DESCRIPTION

The AD5429/AD5439/AD54491 are CMOS 8-, 10-, and 12-bit dual-channel current output digital-to-analog converters, respectively. These devices operate from a 2.5 V to 5.5 V power supply, making them suited to battery-powered and other applications.

The applied external reference input voltage (V the full-scale output current. An integrated feedback resistor

) provides temperature tracking and full-scale voltage

(R

FB

output when combined with an external current-to-voltage precision amplifier.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Anal og Devices. Trademarks and registered trademarks are the property of their respective owners.

These DACs utilize a double-buffered, 3-wire serial interface that is compatible with SPI®, QSPI™, MICROWIRE™, and most DSP interface standards. In addition, a serial data out pin (SDO) allows daisy-chaining when multiple packages are used. Data readback allows the user to read the contents of the DAC register via the SDO pin. On power-up, the internal shift register and latches are filled with zeros and the DAC outputs are at zero scale.

As a result of manufacture on a CMOS submicron process, these parts offer excellent 4-quadrant multiplication characteristics, with large signal multiplying bandwidths of 10 MHz.

The AD5429/AD5439/AD5449 DAC are available in 16-lead TSSOP packages.

1

US Patent Number 5,689,257.

www.analog.com

AD5429/AD5439/AD5449

SPECIFICATIONS

VDD = 2.5 V to 5.5 V, V with OP1177, ac performance with AD9631, unless otherwise noted. Temperature range for Y version is −40°C to +125°C.

Table 1.

Parameter Min Typ Max Unit Conditions

STATIC PERFORMANCE AD5429

Resolution 8 Bits Relative Accuracy ±0.5 LSB Differential Nonlinearity ±1 LSB Guaranteed monotonic

AD5439

Resolution 10 Bits Relative Accuracy ±0.5 LSB Differential Nonlinearity ±1 LSB Guaranteed monotonic

AD5449

Resolution 12 Bits Relative Accuracy ±1 LSB Differential Nonlinearity −1/+2 LSB Guaranteed monotonic Gain Error ±10 mV Gain Error Temp Coefficient

Output Leakage Current ±5 nA Data = 0000H, TA = 25°C, I ±10 nA Data = 0000H, I REFERENCE INPUT1 Typical resistor TC = −50 ppm/°C

Reference Input Range ±10 V

V

A,V

B Input Resistance 8 10 12 kΩ DAC input resistance

REF

V

A/B Input Resistance Mismatch 1.6 2.5 % Typ = 25°C, max = 125°C

REF

DIGITAL INPUTS/OUTPUT1

Input High Voltage, VIH 1.7 V VDD = 2.5 V to 5.5 V

Input Low Voltage, VIL 0.8 V VDD = 2.7 V to 5.5 V

0.7 V VDD = 2.5 V to 2.7 V

Input Leakage Current, IIL 1 µA

Input Capacitance 10 pF

VDD = 4.5 V to 5.5 V

Output Low Voltage, VOL 0.4 V I Output High Voltage, VOH VDD − 1 V I

VDD = 2.5 V to 3.6 V

Output Low Voltage, VOL 0.4 V I Output High Voltage, VOH VDD − 0.5 V I

DYNAMIC PERFORMANCE1

Reference Multiplying BW 10 MHz V

Output Voltage Settling Time

AD5429 50 100 ns AD5439 55 110 ns

AD5449 90 160 ns R Digital Delay 20 40 ns Digital-to-Analog Glitch Impulse 3 nV-s

Multiplying Feedthrough Error −75 dB

= 10 V, I

REF

2A, I

OUT

1

2B = 0 V. All specifications T

OUT

±5 ppm FSR/°C

MIN

to T

= 200 µA

SINK

SOURCE

= 200 µA

SINK

SOURCE

unless otherwise noted. DC performance measured

MAX,

1

OUT

1

OUT

= 200 µA

= 5 V p-p, DAC loaded all 1s

REF

Measured to ±4 mV of FS, R

= 0s

C

LOAD

= 100 Ω,

LOAD

DAC latch alternately loaded with 0s and 1s

= 100 Ω, C

LOAD

= 15 pF

1 LSB change around major carry, V

= 0 V

REF

DAC latch loaded with all 0s, reference = 10 kHz

Rev. 0 | Page 3 of 32

AD5429/AD5439/AD5449

Parameter Min Typ Max Unit Conditions

Output Capacitance 2 pF DAC latches loaded with all 0s 4 pF DAC latches loaded with all 1s Digital Feedthrough 5 nV-s

Total Harmonic Distortion −75 dB V

−75 dB

Output Noise Spectral Density 25 nV/√Hz @ 1 kHz

SFDR PERFORMANCE (Wideband) AD5449, 65 k codes, V

Clock = 10 MHz

500 kHz fout 55 dB 100 kHz fout 63 dB 50 kHz fout 65 dB

Clock = 25 MHz

500 kHz fout 50 dB 100 kHz fout 60 dB 50 kHz fout 62 dB

SFDR PERFORMANCE (Narrow Band) AD5449, 65 k codes, V

Clock = 10 MHz

500 kHz fout 73 dB 100 kHz fout 80 dB 50 kHz fout 87 dB

Clock = 25 MHz

500 kHz fout 70 dB 100 kHz fout 75 dB 50 kHz fout 80 dB

INTERMODULATION DISTORTION AD5449, 65 k codes, V

Clock = 10 MHz

f1 = 400 kHz, f2 = 500 kHz 65 dB f1 = 40 kHz, f2 = 50 kHz 72 dB

Clock = 25 MHz

f1 = 400 kHz, f2 = 500 kHz 51 dB f1 = 40 kHz, f2 = 50 kHz 65 dB

POWER REQUIREMENTS

Power Supply Range 2.5 5.5 V IDD 10 µA Logic inputs = 0 V or VDD Power Supply Sensitivity1 0.001 %/% ∆VDD = ±5%

1

Guaranteed by design and characterization, not subject to production test.

Feedthrough to DAC output with CS high and alternate loading of all 0s and all 1s

= 5 V p-p, all 1s loaded, f = 1 kHz

REF

= 5 V, sine wave generated from

V

REF

digital code

REF

= 3.5 V

Rev. 0 | Page 4 of 32

AD5429/AD5439/AD5449

TIMING CHARACTERISTICS

VDD = 2.5 V to 5.5 V, V

See Figure 2 and Figure 3. Temperature range for Y version is −40°C to +125°C. Guaranteed by design and characterization, not subject to production test. All input signals are specified with tr = tf = ns (10% to 90% of V

= 5 V, I

REF

2 = 0 V. All specifications T

OUT

MIN

to T

, unless otherwise noted.

MAX

) and timed from a voltage level of (VIL + VIH)/2.

DD

Table 2.

Parameter Limit at T

f

50 MHz max Max clock frequency

SCLK

MIN

, T

Unit Conditions/Comments

MAX

1

t1 20 ns min SCLK cycle time t2 8 ns min SCLK high time t3 8 ns min SCLK low time t4 13 ns min

SYNC falling edge to SCLK falling edge setup time t5 5 ns min Data setup time t6 4 ns min Data hold time t7 5 ns min t8 30 ns min t9 0 ns min t10 12 ns min t

11

2

t

12

10 ns min 25 ns min SCLK active edge to SDO valid, strong SDO driver

SYNC rising edge to SCLK falling edge

Minimum

SCLK falling edge to

SYNC high time

LDAC falling edge LDAC pulse width SCLK falling edge to

LDAC rising edge

60 ns min SCLK active edge to SDO valid, weak SDO driver

1

Falling or rising edge as determined by the control bits of the serial word. Strong or weak SDO driver selected via the control register.

2

Daisy-chain and readback modes cannot operate at maximum clock frequency. SDO timing specifications are measured with a load circuit, as shown in Figure 4.

Rev. 0 | Page 5 of 32

AD5429/AD5439/AD5449

SCLK

t

4

t

8

SYNC

DB15

NOTES

1

ASYNCHRONOUS LDAC UPDATE MODE

2

SYNCHRONOUS LDAC UPDATE MODE

ALTERNATIVELY, DATA CAN BE CLOCKED INTO INPUT SHIFT REGISTER ON RISING EDGE OF SCLK AS DETERMINED BY CONTROL BITS. TIMING AS ABOVE, WITH SCLK INVERTED.

t

4

DB15

(N)

LDAC

SCLK

SYNC

SDIN

SDO

DIN

1

2

t

1

t

2

t

6

t

5

t

3

t

7

DB0

t

10

t

9

t

11

04464-0-002

Figure 2. Standalone Mode Timing Diagram

t

1

t

2

t

6

t

5

t

3

DB15

DB0

(N+1)

(N)

t

12

DB15

(N)

DB0

(N+1)

DB0

(N)

t

7

t

8

ALTERNATIVELY, DATA CAN BE CLOCKED INTO INPUT SHIFT REGISTER ON RISING EDGE OF SCLK AS DETERMINED BY CONTROL BITS. IN THIS CASE, DATA WOULD BE CLOCKED OUT OF SDO ON FALLING EDGE OF SCLK. TIMING AS ABOVE, WITH SCLK INVERTED.

04464-0-003

Figure 3. Daisy-Chain and Readback Modes Timing Diagram

TO OUTPUT

200µAI

C

L

50pF

200µAI

OL

VOH (MIN) + VOL (MAX)

OH

2

04464-0-004

Figure 4. Load Circuit for SDO Timing Specifications

Rev. 0 | Page 6 of 32

AD5429/AD5439/AD5449

ABSOLUTE MAXIMUM RATINGS

Table 3.

Parameter Rating

VDD to GND −0.3 V to +7 V V

, RFB to GND −12 V to +12 V

REF

I

1, I

OUT

2 to GND −0.3 V to +7 V

OUT

Input Current to Any Pin except Supplies ±10 mA Logic Inputs and Output

1

−0.3 V to VDD + 0.3 V

Operating Temperature Range

Extended (Y Version) −40°C to +125°C Storage Temperature Range −65°C to +150°C Junction Temperature 150°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating may be applied at any one time.

Transient currents of up to 100 mA do not cause SCR latch-up.

= 25°C unless otherwise noted.

T

A

16-Lead TSSOP θJA Thermal Impedance 150°C/W Lead Temperature, Soldering (10 s) 300°C IR Reflow, Peak Temperature (< 20 s) 235°C

1

Overvoltages at SCLK,

Current should be limited to the maximum ratings given.

SYNC

, and DIN are clamped by internal diodes.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Rev. 0 | Page 7 of 32

AD5429/AD5439/AD5449

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

1A

I

OUT

2

I

2A

OUT

3

R

A

FB

V

REF

GND

LDAC

SCLK

SDIN SDO

AD5429/

4

AD5439/

A

AD5449

5

TOP VIEW

(Not to Scale)

6

7

8

NC = NO CONNECT

16

I

1B

OUT

15

I

2B

OUT

14

R

B

FB

13

V

B

REF

12

V

DD

11

CLR

10

SYNC

9

04464-0-005

Figure 5. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Function

1 I 2 I

1A DAC A Current Output.

OUT

2A

DAC A Analog Ground. This pin should typically be tied to the analog ground of the system, but can be biased to

achieve single-supply operation. 3 RFBA DAC Feedback Resistor Pin. Establish voltage output for the DAC by connecting to an external amplifier output. 4 V

A DAC A Reference Voltage Input Pin.

REF

5 GND Ground Pin. 6

LDAC Load DAC Input. Allows asynchronous or synchronous updates to the DAC output. The DAC is asynchronously

updated when this signal goes low. Alternatively, if this line is held permanently low, an automatic or synchronous

update mode is selected whereby the DAC is updated on the 16th clock falling edge when the device is in

SYNC when in daisy-chain mode.

7 SCLK

standalone mode, or on the rising edge of

Serial Clock Input. By default, data is clocked into the input shift register on the falling edge of the serial clock

input. Alternatively, by means of the serial control bits, the device can be configured such that data is clocked into

the shift register on the rising edge of SCLK. 8 SDIN

Serial Data Input. Data is clocked into the 16-bit input register on the active edge of the serial clock input. By

default, on power-up, data is clocked into the shift register on the falling edge of SCLK. The control bits allow the

user to change the active edge to rising edge. 9 SDO

Serial Data Output. This allows a number of parts to be daisy-chained. By default, data is clocked into the shift

register on the falling edge and out via SDO on the rising edge of SCLK. Data is always clocked out on the

alternate edge to loading data to the shift register. Writing the readback control word to the shift register makes

the DAC register contents available for readback on the SDO pin, clocked out on the next 16 opposite clock edges

to the active clock edge. 10

SYNC Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it

powers on the SCLK and DIN buffers, and the input shift register is enabled. Data is loaded to the shift register on

the active edge of the following clocks. In standalone mode, the serial interface counts clocks, and data is latched

to the shift register on the16th active clock edge. 11

CLR Active Low Control Input. This pin clears the DAC output, input, and DAC registers. Configuration mode allows the

user to enable the hardware

CLR pin as a clear to zero scale or midscale as required. 12 VDD Positive Power Supply Input. These parts can be operated from a supply of 2.5 V to 5.5 V. 13 V

B DAC B Reference Voltage Input Pin.

REF

14 RFBB DAC B Feedback Resistor Pin. Establish voltage output for the DAC by connecting to an external amplifier output. 15 I

OUT

2B

DAC B Analog Ground. This pin typically should be tied to the analog ground of the system, but can be biased to achieve single-supply operation.

16 I

1B DAC B Current Output.

OUT

Rev. 0 | Page 8 of 32

AD5429/AD5439/AD5449

(

)

TERMINOLOGY

Relative Accuracy

Relative accuracy or endpoint nonlinearity is a measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is measured after adjusting for zero and full scale and is typically expressed in LSBs or as a percentage of full-scale reading.

Differential Nonlinearity

Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ±1 LSB maximum over the operating temperature range ensures monotonicity.

Gain Error

Gain error or full-scale error is a measure of the output error between an ideal DAC and the actual device output. For these DACs, ideal maximum output is V

− 1 LSB. Gain error of the

REF

DACs is adjustable to zero with external resistance.

Output Leakage Current

Output leakage current is current that flows in the DAC ladder switches when these are turned off. For the I

1 terminal, it can

OUT

be measured by loading all 0s to the DAC and measuring the

1 current. Minimum current flows in the I

I

OUT

2 line when

OUT

the DAC is loaded with all 1s.

Output Capacitance

Capacitance from I

OUT

1 or I

2 to AGND.

OUT

Output Current Settling Time

The amount of time needed for the output to settle to a specified level for a full-scale input change. For these devices, it is specified with a 100 Ω resistor to ground.

Digital-to-Analog Glitch lmpulse

The amount of charge injected from the digital inputs to the analog output when the inputs change state. This is normally specified as the area of the glitch in either pA-s or nV-s, depending upon whether the glitch is measured as a current or voltage signal.

Digital Feedthrough

When the device is not selected, high frequency logic activity on the device digital inputs is capacitively coupled through the device to show up as noise on the I

pins and subsequently

OUT

into the following circuitry. This noise is digital feedthrough.

Multiplying Feedthrough Error

The error due to capacitive feedthrough from the DAC reference input to the DAC I

1 terminal, when all 0s are

OUT

loaded to the DAC.

Digital Crosstalk

The glitch impulse transferred to the outputs of one DAC in response to a full-scale code change (all 0s to all 1s and vice versa) in the input register of the other DAC. It is expressed in nV-s.

Analog Crosstalk

The glitch impulse transferred to the output of one DAC due to a change in the output of another DAC. It is measured by loading one of the input registers with a full-scale code change (all 0s to all 1s and vice versa), while keeping

pulse

low and monitor the output of the DAC whose

LDAC

high. Then

digital code was not changed. The area of the glitch is expressed in nV-s.

Channel-to-Channel Isolation

The proportion of input signal from the reference input of one DAC that appears at the output of the other DAC. It is expressed in dB.

Total Harmonic Distortion (THD) The DAC is driven by an ac reference. The ratio of the rms sum of the harmonics of the DAC output to the fundamental value is the THD. Usually only the lower-order harmonics are included, such as second to fifth.

2

THD

2

3

=

2

log20

V

1

)

+++

VVVV

5

4

Intermodulation Distortion

The DAC is driven by two combined sine wave references of frequencies fa and fb. Distortion products are produced at sum and difference frequencies of mfa ± nfb, where m, n = 0, 1, 2, 3… Intermodulation terms are those for which m or n is not equal to zero. The second-order terms include (fa + fb) and (fa − fb) and the third-order terms are (2fa + fb), (2fa − fb), (f + 2fa + 2fb) and (fa − 2fb). IMD is defined as

IMD log20=

productsdistortiondiffandsumtheofsumrms

lfundamentatheofamplituderms

Compliance Voltage Range

The maximum range of (output) terminal voltage for which the device provides the specified characteristics.

Rev. 0 | Page 9 of 32

AD5429/AD5439/AD5449

TYPICAL PERFORMANCE CHARACTERISTICS

0.20 TA = 25°C V

= 10V

0.15

0.10

REF

V

= 5V

DD

0.20

0.15

0.10

TA = 25°C

= 10V

V

REF

= 5V

V

DD

0.05

0

INL (LSB)

–0.05

–0.10

–0.15

–0.20

0 50 100 150 200 250

CODE

Figure 6. INL vs. Code (8-Bit DAC)

0.5

TA = 25°C

0.4

V

= 10V

REF

V

= 5V

DD

0.3

0.2

0.1

0

INL (LSB)

–0.1

–0.2

–0.3

–0.4

–0.5

0 200 400 600 800 1000

CODE

Figure 7. INL vs. Code (10-Bit DAC)

1.0

TA = 25°C

INL (LSB)

0.8

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

= 10V

V

REF

= 5V

V

DD

20001500500 10000 2500 3000 3500 4000

CODE

Figure 8. INL vs. Code (12-Bit DAC)

04462-0-007

04462-0-008

04462-0-009

0.05

0

DNL (LSB)

–0.05

–0.10

–0.15

–0.20

0 50 100 150 200 250

CODE

Figure 9. DNL vs. Code (8-Bit DAC)

0.5 TA = 25°C

0.4

V

= 10V

REF

V

= 5V

DD

0.3

0.2

0.1

0

DNL (LSB)

–0.1

–0.2

–0.3

–0.4

–0.5

0 200 400 600 800 1000

CODE

Figure 10. DNL vs. Code (10-Bit DAC)

1.0

TA = 25°C

0.8

0.6

0.4

0.2

0

DNL (LSB)

–0.2

–0.4

–0.6

–0.8

–1.0

= 10V

V

REF

= 5V

V

DD

20001500500 10000 2500 3000 3500 4000

CODE

Figure 11. DNL vs. Code (12-Bit DAC)

04462-0-010

04462-0-011

04462-0-012

Rev. 0 | Page 10 of 32

Analog Devices AD5429 39 49 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

FUNCTIONAL BLOCK DIAGRAM

GENERAL DESCRIPTION

TABLE OF CONTENTS

SPECIFICATIONS

TIMING CHARACTERISTICS

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TERMINOLOGY

TYPICAL PERFORMANCE CHARACTERISTICS