ANALOG DEVICES AD 5421 BREZ Datasheet

Loop-Powered, 4 mA to 20 mA DAC

AD5421

Rev. E

nished by Analog Devices is believed to be accurate and reliable. However, no

Trademarks and registered trademarks are the property of their respective owners.

Fax: [phone] ©2011–2012 Analog Devices, Inc. All rights reserved.

R

SET

24kΩ

SYNC
SCLK

SDIN

SDO

LDAC

RANGE0
RANGE1

ALARM_CURRENT_DIRECTION

FAULT

R

INT

/R

EXT

INPUT

REGISTER
CONTROL

LOGIC

GAIN/OFFSET
ADJUSTMENT

REGISTERS

TEMPERATURE

SENSOR

REFOUT2 REFIN CINR

EXT1

R

EXT2

REFOUT1

VREF

16

16-BIT

DAC

LOOP
VOLTAGE
MONITOR

V

LOOP

DV

DD

IODV

DD

AD5421

VOLTAGE

REGULATOR

REG_SEL0 REG_SEL1 REG_SEL2 REG

OUT

REG

IN

DRIVE

LOOP–

11.5kΩ 52Ω

09128-001

COM

Data Sheet

FEATURES

16-bit resolution and monotonicity
Pin selectable NAMUR-compliant ranges

4 mA to 20 mA

3.8 mA to 21 mA

3.2 mA to 24 mA

NAMUR-compliant alarm currents

Downscale alarm current = 3.2 mA

Upscale alarm current = 22.8 mA/24 mA
Total unadjusted error (TUE): 0.05% maximum
INL error: 0.0035% FSR maximum
Output TC: 3 ppm/°C typical
Quiescent current: 300 µA maximum
Flexible SPI-compatible serial digital interface

with Schmitt triggered inputs
On-chip fault alerts via FAULT pin or alarm current
Automatic readback of fault register on each write cycle
Slew rate control function
Gain and offset adjust registers
On-chip reference TC: 4 ppm/°C maximum
Selectable regulated voltage output
Loop voltage range: 5.5 V to 52 V
Temperature range: −40°C to +105°C
TSSOP and LFCSP packages

APPLICATIONS

Industrial process control
4 mA to 20 mA loop-powered transmitters
Smart transmitters
HART network connectivity

16-Bit, Serial Input,

GENERAL DESCRIPTION

The AD5421 is a complete, loop-powered, 4 mA to 20 mA
digital-to-analog converter (DAC) designed to meet the needs
of smart transmitter manufacturers in the industrial control
indu s t r y. The DAC provides a high precision, fully integrated,
low cost solution in compact TSSOP and LFCSP packages.

The AD5421 includes a regulated voltage output that is used to
power itself and other devices in the transmitter. This regulator
provides a regulated 1.8 V to 12 V output voltage. The AD5421
also contains 1.22 V and 2.5 V references, thus eliminating the
need for a discrete regulator and voltage reference.

The AD5421 can be used with standard HART® FSK protocol
communication circuitry without any degradation in specified
performance. The high speed serial interface is capable of opera­ting at 30 MHz and allows for simple connection to commonly
used microprocessors and microcontrollers via a SPI-compatible,
3-wire interface.

The AD5421 is guaranteed monotonic to 16 bits. It provides

0.0015% integral nonlinearity, 0.0012% offset error, and

0.0006% gain error under typical conditions.

The AD5421 is available in a 28-lead TSSOP and a 32-lead
LFCSP specified over the extended industrial temperature range
of −40°C to +105°C.

COMPANION LOW POWER PRODUCTS

HART Modem: AD5700, AD5700-1
Microcontroller: ADuCM360

Information fur
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

FUNCTIONAL BLOCK DIAGRAM

Figure 1.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]

www.analog.com

AD5421 Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

General Description ......................................................................... 1

Companion Low Power Products .................................................. 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

AC Performance Characteristics ................................................ 8

Timing Characteristics ................................................................ 8

Absolute Maximum Ratings .......................................................... 10

Thermal Resistance .................................................................... 10

ESD Caution ................................................................................ 10

Pin Configuration and Function Descriptions ........................... 11

Typ i cal Performance Characteristics ........................................... 13

Terminology .................................................................................... 19

Theory of Operation ...................................................................... 20

Fault Alerts .................................................................................. 20

External Current Setting Resistor ............................................ 21

Loop Current Range Selection .................................................. 21

Connection to Loop Power Supply .......................................... 21

On-Chip ADC ............................................................................ 22

Voltage Regulator ....................................................................... 22

Loop Current Slew Rate Control .............................................. 22

Power-On Default ...................................................................... 23

HART Communications ........................................................... 23

Serial Interface ................................................................................ 25

Input Shift Register .................................................................... 25

Register Readback ...................................................................... 25

DAC Register .............................................................................. 26

Control Register ......................................................................... 27

Fault Register .............................................................................. 28

Offset Adjust Register ................................................................ 29

Gain Adjust Register .................................................................. 29

Applications Information .............................................................. 31

Determining the Expected Total Error.................................... 31

Thermal and Supply Considerations ....................................... 33

Outline Dimensions ....................................................................... 34

Ordering Guide .......................................................................... 35

REVISION HISTORY

7/12—Rev. D to Rev. E

Changes to Figure 1 and Companion Products Section ............. 1

Changes to Pin LOOP− Description ........................................... 12

Changes to Applications Information Section and Figure 49... 31

Added Figure 50 .............................................................................. 32

5/12—Rev. C to Rev. D

Changes to Features Section and Applications Section; Added

Companion Products Section ......................................................... 1

Changes to Line Regulation Parameter, Table 1 ........................... 5

Updated Outline Dimensions ....................................................... 33

12/11—Rev. B to Rev. C

Change to REFOUT1 Pin, Capacitive Load Parameter, Test

Conditions, Table 1 ........................................................................... 4

Change to REG

Conditions, Table 1 ........................................................................... 5

Changes to ESD Parameter, Table 6 ............................................. 10

12/11—Rev. A to Rev. B

Added 32-Lead LFCSP ....................................................... Universal

Changes to the Specifications Section, Table 1 ............................. 3

Output, Capacitive Load Parameter, Test

OUT

Changes to Table 7 .......................................................................... 10

Added Figure 5, Renumbered Sequentially ................................ 11

Changes to Table 8 .......................................................................... 11

Changes to Figure 33 ...................................................................... 17

Changes to the On-Chip ADC Section ....................................... 22

Changes to Figure 46 ...................................................................... 23

Changes to Figure 48 ...................................................................... 24

Changes to the Register Readback Section ................................. 25

Updated Outline Dimensions ....................................................... 33

Changes to Ordering Guide .......................................................... 34

5/11—Rev. 0 to Rev. A

Changes to REG

in Table 8 .......................................................................................... 10

Change to Figure 45 ....................................................................... 22

Changes to Input Shift Register Section, Table 11, and Register

Readback Section ............................................................................ 24

Changes to Figure 48 ...................................................................... 30

2/11—Revision 0: Initial Version

, REFOUT1, and REFOUT2 Pin Descriptions

IN

Rev. E | Page 2 of 36

Data Sheet AD5421

ACCURACY, INTERNAL R

−0.06

±0.011

+0.06

% FSR

B grade, TA = 25°C

−0.041

±0.0065

+0.041

% FSR

B grade and C grade, TA = 25°C

23.97

24.03

mA

3.2 mA to 24 mA range

TUE Long-Term Stability

40 ppm FSR

Drift after 1000 hours at TA = 125°C

SPECIFICATIONS

Loop voltage = 24 V; REFIN = 2.5 V external; RL = 250 Ω; external NMOS connected; all loop current ranges; all specifications
T

to T

MIN

Table 1.

Parameter1 Min Typ Max Unit Test Conditions/Comments

Resolution 16 Bits

Tot al Unadjusted Error (TUE)2 −0.126 +0.126 % FSR C grade

−0.041 ±0.0064 +0.041 % FSR C grade, TA = 25°C

−0.18 +0.18 % FSR B grade

−0.27 +0.27 % FSR A grade

−0.08 ±0.011 +0.08 A grade, TA = 25°C

TUE Long-Term Stability 210 ppm FSR Drift after 1000 hours at TA = 125°C

Relative Accuracy (INL) −0.0035 ±0.0015 +0.0035 % FSR C grade

−0.012 ±0.006 +0.012 % FSR B grade

−0.024 ±0.01 +0.024 % FSR A grade

Differential Nonlinearity (DNL) −1 +1 LSB Guaranteed monotonic

Offset Error −0.056 +0.056 % FSR B grade and C grade

−0.008 ±0.0008 +0.008 % FSR B grade and C grade, TA = 25°C

−0.11 ±0.0008 +0.11 % FSR A grade

Offset Error TC3 1 ppm FSR/°C

Gain Error −0.107 +0.107 % FSR B grade and C grade

−0.035 ±0.0058 +0.035 % FSR B grade and C grade, TA = 25°C

−0.2 ±0.0058 +0.2 % FSR A grade

Gain Error TC3 4 ppm FSR/°C

Full-Scale Error −0.126 +0.126 % FSR B grade and C grade

, unless otherwise noted.

MAX

SET

−0.25 ±0.0065 +0.25 % FSR A grade
Full-Scale Error TC3 5 ppm FSR/°C
Downscale Alarm Current 3.19 3.21 mA
Upscale Alarm Current 22.77 22.83 mA 4 mA to 20 mA and 3.8 mA to 21 mA

ranges

ACCURACY, EXTERNAL R

Resolution 16 Bits
Total Unadjusted Error (TUE)2 −0.048 +0.048 % FSR C grade

−0.027 ±0.002 +0.027 % FSR C grade, TA = 25°C

−0.08 +0.08 % FSR B grade

−0.04 ±0.003 +0.04 % FSR B grade, TA = 25°C

Relative Accuracy (INL) −0.0035 ±0.0015 +0.0035 % FSR C grade

−0.012 ±0.006 +0.012 % FSR B grade
Differential Nonlinearity (DNL) −1 +1 LSB Guaranteed monotonic
Offset Error −0.021 +0.021 % FSR

−0.007 ±0.0012 +0.007 % FSR TA = 25°C
Offset Error TC3 0.5 ppm FSR/°C
Gain Error −0.03 +0.03 % FSR

−0.023 ±0.0006 +0.023 % FSR TA = 25°C

(24 kΩ) Assumes ideal resistor, B grade and

SET

C grade only; not specified for A grade

Rev. E | Page 3 of 36

AD5421 Data Sheet

Downscale Alarm Current

3.08 3.21

mA

0.1 Hz to 10 Hz

50 nA p-p

Temperature Coefficient

1.5 4 ppm/°C

C grade

Thermal Hysteresis3

285 ppm

First temperature cycle

Parameter1 Min Typ Max Unit Test Conditions/Comments

Gain Error TC3 1 ppm FSR/°C
Full-Scale Error −0.047 +0.047 % FSR

−0.028 ±0.0017 +0.028 % FSR TA = 25°C
Full-Scale Error TC3 1 ppm FSR/°C

Upscale Alarm Current 22.78 23 mA 4 mA to 20 mA and 3.8 mA to 21 mA

ranges

23.99 24.01 mA 3.2 mA to 24 mA range
OUTPUT CHARACTERISTICS3

Loop Compliance Voltage4 LOOP− + 5.5 V REG
LOOP− + 12.5 V REG
Loop Current Long-Term Stability 100 ppm FSR Drift after 1000 hours at TA = 125°C,

15 ppm FSR Drift after 1000 hours at TA = 125°C,

Loop Current Error vs. REG

OUT

Load

1.2 µA/mA Loop current = 12 mA, load current

Current
Resistive Load 0 2 kΩ See Figure 20 for a load line graph
Inductive Load 50 mH Stable operation
Power Supply Sensitivity 0.1 µA/V Loop current = 12 mA
Output Impedance 12 400 MΩ
Output TC 3 ppm FSR/°C Loop current = 12 mA, internal R
1 ppm FSR/°C Loop current = 12 mA, external R
Output Noise

< 5.5 V, loop current = 24 mA

OUT

= 12 V, loop current = 24 mA

OUT

loop current = 12 mA, internal R

loop current = 12 mA, external R

from REG

= 5 mA

OUT

SET

SET

SET

SET

500 Hz to 10 kHz 0.2 mV rms HART bandwidth; measured across

500 Ω load

Noise Spectral Density 195 nA/√Hz At 1 kHz

256 nA/√Hz At 10 kHz
REFERENCE INPUT (REFIN PIN)3

Reference Input Voltage5 2.5 V For specified performance
DC Input Impedance 75 800 MΩ

REFERENCE OUTPUTS

REFOUT1 Pin

Output Voltage 2.498 2.5 2.503 V TA = 25°C

2 8 ppm/°C B grade
4 10 ppm/°C A grade
Output Noise (0.1 Hz to 10 Hz)3 7.5 µV p-p
Noise Spectral Density3 245 nV/√Hz At 1 kHz
70 nV/√Hz At 10 kHz
Output Voltage Drift vs. Time3 200 ppm Drift after 1000 hours at TA = 125°C
Capacitive Load3 10 nF Recommended operation
Load Current

3, 6

4 mA
Short-Circuit Current3 6.5 mA Short circuit to COM
Power Supply Sensitivity3 2 12 µV/V

5 ppm Second temperature cycle
Load Regulation3 0.1 0.2 mV/mA Measured at 0 mA and 1 mA loads
Output Impedance 0.1 Ω

REFOUT2 Pin

Output Voltage 1.18 1.227 1.28 V TA = 25°C
Output Impedance 72 kΩ

Rev. E | Page 4 of 36

Data Sheet AD5421

Externally Available Current

3.15

mA

Assuming 4 mA flowing in the loop

Inductive Load

50 mH

Stable operation

Load Regulation

45 mV/mA

Measured at 0 mA and 3 mA loads

Hysteresis

0.21 V

IODVDD = 1.8 V

I

0.01% FSR

I

+ 0.01% FSR

Parameter1 Min Typ Max Unit Test Conditions/Comments

REG

OUTPUT Voltage regulator output

OUT

Output Voltage 1.8 12 V See Table 10
Output Voltage TC3 110 ppm/°C
Output Voltage Accuracy −4 ±2 +4 %

Short-Circuit Current 23 mA
Line Regulation3 500 μV/V Internal NMOS
10 μV/V External NMOS
Load Regulation3 8 mV/mA

Capacitive Load 2 10 µF Recommended operation

ADC ACCURACY

Die Temperature ±5 °C
V

Input ±1 %

LOOP

DVDD OUTPUT Can be overdriven up to 5.5 V

Output Voltage 3.17 3.3 3.48 V
Externally Available Current

Short-Circuit Current 7.7 mA

3, 6

and during HART communications

3, 6

3.15 mA Assuming 4 mA flowing in the loop
and during HART communications

DIGITAL INPUTS3 SCLK,

SYNC

, SDIN,

LDAC
Input High Voltage, VIH 0.7 × IODVDD V
Input Low Voltage, VIL 0.25 × IODVDD V

0.63 V IODVDD = 3.3 V

1.46 V IODVDD = 5.5 V
Input Current −0.015 +0.015 µA Per pin
Pin Capacitance 5 pF Per pin

DIGITAL OUTPUTS3

SDO Pin

Output Low Voltage, VOL 0.4 V
Output High Voltage, VOH IODVDD − 0.5 V
High Impedance Leakage

−0.01 +0.01 µA

Current

High Impedance Output

5 pF

Capacitance

FAULT Pin

Output Low Voltage, VOL 0.4 V
Output High Voltage, VOH IODVDD − 0.5 V

FA ULT THRESHOLDS

I

Under

LOOP

I

Over

LOOP

LOOP

LOOP

−

mA
mA

Temp 140°C 133 °C Fault removed when temperature

≤ 125°C

Temp 100°C 90 °C Fault removed when temperature

≤ 85°C

V

6V 0.3 V Fault removed when V

LOOP

V

12V 0.6 V Fault removed when V

LOOP

LOOP

LOOP

≥ 0.4 V
≥ 0.7 V

Rev. E | Page 5 of 36

AD5421 Data Sheet

Parameter1 Min Typ Max Unit Test Conditions/Comments

POWER REQUIREMENTS

REGIN 5.5 52 V With respect to LOOP−
IODVDD 1.71 5.5 V With respect to COM
Quiescent Current 260 300 µA

1

Temperature range: −40°C to +105°C; typical at +25°C.

2

Total unadjusted error is the total measured error (offset error + gain error + linearity error + output drift over temperature) after factory calibration of the AD5421.

System level total error can be reduced using the offset and gain registers.

3

Guaranteed by design and characterization; not production tested.

4

The voltage between LOOP− and REGIN must be 5.5 V or greater.

5

The AD5421 is factory calibrated with an external 2.5 V reference connected to REFIN.

6

This is the current that the output is capable of sourcing. The load current originates from the loop and, therefore, contributes to the total current consumption figure.

Rev. E | Page 6 of 36

Data Sheet AD5421

ACCURACY, INTERNAL R

ACCURACY, EXTERNAL R

(24 kΩ)

Assumes ideal resistor

Loop voltage = 24 V; REFIN = REFOUT1 (2.5 V internal reference); RL = 250 Ω; external NMOS connected; all loop current ranges;
all specifications T

Table 2.

Parameter

1, 2

Total Unadjusted Error (TUE)3 −0.157 +0.157 % FSR

−0.117 ±0.0172 +0.117 % FSR TA = 25°C
Relative Accuracy (INL) −0.004 +0.004 % FSR

−0.004 ±0.0015 +0.004 % FSR TA = 25°C
Offset Error −0.04 +0.04 % FSR

−0.025 ±0.0025 +0.025 % FSR TA = 25°C
Offset Error TC 1 ppm FSR/°C
Gain Error −0.128 +0.128 % FSR

−0.093 ±0.0137 +0.093 % FSR TA = 25°C
Gain Error TC 5 ppm FSR/°C
Full-Scale Error −0.157 +0.157 % FSR

−0.117 ±0.0172 +0.117 % FSR TA = 25°C
Full-Scale Error TC 6 ppm FSR/°C

Total Unadjusted Error (TUE)3 −0.133 +0.133 % FSR

−0.133 ±0.0252 +0.133 % FSR TA = 25°C
Relative Accuracy (INL) −0.004 +0.004 % FSR

−0.004 ±0.0015 +0.004 % FSR TA = 25°C
Offset Error −0.029 +0.029 % FSR

−0.029 ±0.0038 +0.029 % FSR TA = 25°C
Offset Error TC 0.5 ppm FSR/°C
Gain Error −0.11 +0.11 % FSR

−0.106 ±0.0197 +0.106 % FSR TA = 25°C
Gain Error TC 2 ppm FSR/°C
Full-Scale Error −0.133 +0.133 % FSR

−0.133 ±0.0252 +0.133 % FSR TA = 25°C
Full-Scale Error TC 2 ppm FSR/°C

1

Temperature range: −40°C to +105°C; typical at +25°C.

2

Specifications guaranteed by design and characterization; not production tested.

3

Total unadjusted error is the total measured error (offset error + gain error + linearity error + output drift over temperature) after factory calibration of the AD5421.

System level total error can be reduced using the offset and gain registers.

to T

MIN

, unless otherwise noted.

MAX

C Grade

SET

SET

Unit Test Conditions/Comments Min Typ Max

Rev. E | Page 7 of 36

AD5421 Data Sheet

t3

17

ns min

SCLK low time

1 0 1

2619

3000

3489

ms

AC PERFORMANCE CHARACTERISTICS

Loop voltage = 24 V; REFIN = 2.5 V external; RL = 250 Ω; all specifications T

Table 3.

Parameter1 Min Typ Max Unit Test Conditions/Comments

DYNAMIC PERFORMANCE

Loop Current Settling Time 50 µs To 0.1% FSR, CIN = open circuit
Loop Current Slew Rate 400 µA/µs CIN = open circuit
AC Loop Voltage Sensitivity 1.3 µA/V 1200 Hz to 2200 Hz, 5 V p-p, RL = 3 kΩ

1

Temperature range: −40°C to +105°C; typical at +25°C.

TIMING CHARACTERISTICS

Loop voltage = 24 V; REFIN = 2.5 V external; RL = 250 Ω; all specifications T

MIN

MIN

to T

to T

, unless otherwise noted.

MAX

.

MAX

Table 4.

Parameter

1, 2, 3

Limit at T

MIN

, T

Unit Description

MAX

t1 33 ns min SCLK cycle time
t2 17 ns min SCLK high time

t4 17 ns min
t5 10 ns min SCLK falling edge to
t6 25 µs min Minimum

falling edge to SCLK falling edge setup time

SYNC

rising edge

SYNC

high time

SYNC
t7 5 ns min Data setup time
t8 5 ns min Data hold time
t9 25 µs min
t10 10 ns min
t11 70 ns max SCLK rising edge to SDO valid (C
t12 0 ns min
t13 70 ns max

1

Guaranteed by design and characterization; not production tested.

2

All input signals are specified with tR = tF = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.2 V.

3

See Figure 2 and Figure 3.

rising edge to

SYNC

pulse width low

LDAC

falling edge to SCLK rising edge setup time

SYNC

rising edge to SDO tristate (C

SYNC

LDAC

falling edge

L SDO

Table 5. SPI Watchdog Timeout Periods

Parameter1

T0 T1 T2

Min Typ Max Unit

0 0 0 43 50 59 ms
0 0 1 87 100 117 ms
0 1 0 436 500 582 ms
0 1 1 873 1000 1163 ms
1 0 0 1746 2000 2326 ms

= 30 pF)

= 30 pF)

L SDO

1 1 0 3493 4000 4652 ms
1 1 1 4366 5000 5814 ms

1

Specifications guaranteed by design and characterization; not production tested.

Rev. E | Page 8 of 36

Data Sheet AD5421

Timing Diagrams

t

1

10 11 12 22

t

2

D14 D13 D2 D1D15

t

11

24

23

D0D16D23

t

13

t

5

t9t

10

SCLK

SDIN

SDO

SYNC

t

12

2

t

7

89

t

3

t

8

D15 D14 D13 D2 D1 D0

1

t

4

t

6

LDAC

09128-002

Figure 2. Serial Interface Timing Diagram

SCLK

SDIN

SDO

SYNC

18924

D23 D15 D0

INPUT WORD SPECIFIES REGISTER TO BE READ

D16

UNDEFINED DATA

Figure 3. Readback Timing Diagram

1

D23 D0D15

SPECIFIE D RE GISTER DATA CLOCKED OUT

89

D16

NOP OR REGISTER ADDRESS

D15 D0

24

09128-003

Rev. E | Page 9 of 36

AD5421 Data Sheet

REFIN to COM

−0.3 V to +7 V

Junction Temperature (T

)

125°C

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted. Transient currents of up
to 100 mA do not cause SCR latch-up.

Table 6.

Parameter Rating

REGIN to COM −0.3 V to +60 V
REG

to COM −0.3 V to +14 V

OUT

Digital Inputs to COM,

RANGE0, RANGE1, R
ALARM_CURRENT_DIRECTION,
REG_SEL0, REG_SEL1, REG_SEL2

Digital Inputs to COM

SCLK, SDIN,

Digital Outputs to COM,

SDO, FAULT

REFOUT1, REFOUT2 −0.3 V to +4.7 V
V

to COM −0.3 V to +60 V

LOOP

LOOP− to COM −5 V to +0.3 V
DVDD to COM −0.3 V to +7 V
IODVDD to COM −0.3 V to +7 V
R

, CIN to COM −0.3 V to +4.3 V

EXT1

R

to COM −0.3 V to +0.3 V

EXT2

DRIVE to COM −0.3 V to +11 V
Operating Temperature Range (TA)

Industrial −40°C to +105°C

Storage Temperature Range −65°C to +150°C

Power Dissipation (T
Lead Temperature,

Soldering (10 sec)

ESD

Human Body Model 3 kV
Field Induced Charged Device

Model

Machine Model 200 V

SYNC

,

INT/REXT

LDAC

,

J MAX

−0.3 V to DVDD + 0.3 V
or +7 V (whichever is less)

−0.3 V to IODVDD + 0.3 V
or +7 V (whichever is less)

−0.3 V to IODVDD + 0.3 V
or +7 V (whichever is less)

− TA)/θJA

J MAX

JEDEC Industry Standard
J-STD-020

2 kV

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.

Table 7. Thermal Resistance

Package Type θJA θJC Unit

28-Lead TSSOP_EP (RE-28-2) 32 9 °C/W
24-Lead LFCSP_WQ (CP-32-11) 40 7 °C/W

ESD CAUTION

Rev. E | Page 10 of 36

Data Sheet AD5421

1
2
3
4
5
6
7
8

9
10
11
12
13
14

28
27
26
25
24
23
22
21
20
19
18
17
16
15

SDO
SCLK
SYNC

FAULT

LDAC

SDIN

IODV

DD

REG

IN

DRIVE
V

LOOP

R

EXT1

R

EXT2

LOOP–

DV

DD

ALARM_CURRENT_DIRECTION

R

INT

/R

EXT

COM
COM

RANGE1

RANGE0

C

IN

REFOUT1
REFOUT2

REG_SEL1
REG_SEL2

REG_SEL0

REFIN

REG

OUT

TOP VIEW

(Not to S cale)

AD5421

NOTES

1. THE EXPO S E D P ADDLE SHOULD BE CONNECTED TO THE SAME
POTENT IAL AS THE CO M P IN AND TO A COPP E R P LANE FOR
OPTIM UM THERMAL PERF ORMANCE.

09128-004

09128-100

PIN 1
INDICATOR

1SDIN
2LDAC
3FAULT
4COM
5DV

DD

6ALARM CURRENT DI RE CTION
7R

INT/REXT

8RANGE 0

24

V

LOOP

23 LOOP–
22 R

EXT2

21 R

EXT1

20 C

IN

19 REFOUT1
18 REFOUT2
17 REFIN

9

RANGE 1

10

COM

11

COM

12

NC

13

REG_SEL2

14

REG_SEL1

15

REG_SEL0

16NC

32

SYNC

31

SCLK

30

SDO

29

IODV

DD

28

REG

OUT

27

REG

IN

26

DRIVE

25

NC

AD5421

TOP VIEW

(Not to S cale)

NOTES

1. NO CONNECT. DO NOT CONNECT TO THIS PIN.

2. THE E X P OSED PADDLE SHOULD BE CONNECT E D TO THE
SAME POT E NTIAL AS THE COM PIN AND TO A COPPER
PLANE FO R OPTIMUM THERMAL PERF ORMANCE.

Digital Interface Supply Pin. Digital thresholds are referenced to the voltage applied to this pin. A

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Figure 4. TSSOP Pin Configuration

Table 8. Pin Function Descriptions

Pin No.

TSSOP LFCSP

Mnemonic Description

1 29 IODVDD

voltage from 1.71 V to 5.5 V can be applied to this pin.

2 30 SDO Serial Data Output. Used to clock data from the input shift register. Data is clocked out on the

rising edge of SCLK and is valid on the falling edge of SCLK.

3 31 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of SCLK. This

input operates at clock speeds up to 30 MHz.

4 32

Frame Synchronization Input, Active Low. This is the frame synchronization signal for the serial

SYNC

interface. When

is low, data is transferred on the falling edge of SCLK. The input shift

SYNC

register data is latched on the rising edge of
5 1 SDIN Serial Data Input. Data must be valid on the falling edge of SCLK.
6 2

Load DAC Input, Active Low. This pin is used to update the DAC register and, consequently, the

LDAC

output current. If

of

. If

SYNC

LDAC

is tied permanently low, the DAC register is updated on the rising edge

LDAC

is held high during the write cycle, the input register is updated, but the output

update is delayed until the falling edge of
7 3 FAU LT Fault Alert Output Pin, Active High. This pin is asserted high when a fault is detected. Detectable

faults are loss of SPI interface control, communication error (PEC), loop current out of range,

insufficient loop voltage, and overtemperature. For more information, see the Fault Alerts

section.
8 5 DVDD 3.3 V Digital Power Supply Output. This pin should be decoupled to COM with 100 nF and 4.7 µF

9 6 ALARM_

10 7 R

11, 12 8, 10 RANGE0,

CURRENT_
DIRECTION

RANGE1

Current Setting Resistor Select. When this pin is connected to DVDD, the internal current setting

INT/REXT

capacitors.

Alarm Current Direction Select. This pin is used to select whether the alarm current is upscale

(22.8 mA/24 mA) or downscale (3.2 mA). Connecting this pin to DVDD selects an upscale alarm

current (22.8 mA/24 mA); connecting this pin to COM selects a downscale alarm current (3.2 mA).

For more information, see the Power-On Default section.

resistor is selected. When this pin is connected to COM, the external current setting resistor is

selected. An external resistor can be connected between the R

Digital Input Pins. These two pins select the loop current range (see the Loop Current Range

Selection section).

Rev. E | Page 11 of 36

Figure 5. LFCSP Pin Configuration

.

SYNC

LDAC

. The

pin should not be left unconnected.

LDAC

EXT1

and R

EXT2

pins.

AD5421 Data Sheet

21

20

CIN

External Capacitor Connection and HART FSK Input. An external capacitor connected from CIN to

Voltage Input Pin. Voltage input range is 0 V to 2.5 V. The voltage applied to this pin is digitized to

N/A1

9, 16, 25

NC

No Connect. Do not connect to this pin.

Pin No.

TSSOP LFCSP

13, 14 4, 11, 12 COM Ground Reference Pin for the AD5421. It is recommended that a 4.7 V Zener diode be placed

15, 16,

13, 14, 15 REG_SEL2,

17

18 17 REFIN Reference Voltage Input. V
19 18 REFOUT2 Internal Reference Voltage Output (1.22 V). It is recommended to connect a 100 nF capacitor

20 19 REFOUT1 Internal Reference Voltage Output (2.5 V). It is recommended to connect a 100 nF capacitor from

22, 23 21, 22 R

24 23 LOOP− Loop Current Return Pin. As shown in Figure 1, the COM and LOOP− pins can be used to sense

25 23 V

26 26 DRIVE Gate Connection for External Depletion Mode MOSFET. For more information, see the

27 27 REGIN Voltage Regulator Input. The loop voltage can be connected directly to this pin. Or, to reduce on-

28 28 REG

Mnemonic Description

between the LOOP− and COM pins. See the Applications Information section for more
information.

REG_SEL1,

These three pins together select the regulator output (REG
section).

) voltage (see the Voltage Regulator

OUT

REG_SEL0

= 2.5 V for specified performance.

REFIN

from this pin to COM.

this pin to COM.

COM implements an output slew rate control function (see the Loop Current Slew Rate Control
section). HART FSK signaling can also be coupled through a capacitor to this pin (see the HART
Communications section).

, R

EXT1

Connection for External Current Setting Resistor. A precision 24 kΩ resistor can be connected

EXT2

between these pins for improved performance.

the loop current across the internal 52 Ω resistor. Note that the voltage measured at LOOP− will
be negative with respect to COM.

LOOP

eight bits, which are available in the fault register. This pin can be used for general-purpose
voltage monitoring, but it is intended for monitoring of the loop supply voltage. Connecting the
loop voltage to this pin via a 20:1 resistor divider allows the AD5421 to monitor and feedback
the loop voltage. The AD5421 also generates an alert if the loop voltage is close to the minimum
operating value (see the

Loop Voltage Fault section).

Connection to Loop Power Supply section.

chip power dissipation, an external pass transistor can be connected at this pin to stand off the
loop voltage. For more information, see the Connection to Loop Power Supply section.

Voltage Regulator Output. Pin selectable values are from 1.8 V to 12 V via the REG_SEL0,

OUT

REG_SEL1, and REG_SEL2 pins (see the Voltage Regulator section).

EPAD EPAD Exposed Pad The exposed paddle should be connected to the same potential as the COM pin and to a copper

plane for optimum thermal performance.

1

N/A means not applicable.

Rev. E | Page 12 of 36

Data Sheet AD5421

1.0

–1.0

–0.8

–0.6

–0.4

–0.2

0

0.2

0.4

0.6

0.8

0 60k50k40k30k20k10k

INL ERROR ( LSB)

DAC CODE

V

LOOP

= 24V
EXT NMOS
R

LOAD

= 250Ω

T

A

= 25°C
4mA TO 20mA RANGE
EXT V

REF

EXT R

SET

09128-005

1.0

–1.0

–0.8

–0.6

–0.4

–0.2

0

0.2

0.4

0.6

0.8

0 60k50k40k30k20k10k

DNL ERROR (L S B)

DAC CODE

V

LOOP

= 24V
EXT NMOS
R

LOAD

= 250Ω

T

A

= 25°C
4mA TO 20mA RANGE
EXT V

REF

EXT R

SET

09128-006

0.01

–0.06

–0.05

–0.04

–0.03

–0.02

–0.01

0

0 60k50k40k30k20k10k

TOTAL UNADJUS TED ERROR (% FS R)

DAC CODE

09128-007

V

REF

EXT, R

SET

EXT, NMOS EXT, 24V

V

REF

EXT, R

SET

EXT, NMOS INT, 24V

V

REF

EXT, R

SET

EXT, NMOS INT, 52V

V

REF

INT, R

SET

INT, NMOS EXT, 24V

V

REF

INT, R

SET

INT, NMOS INT, 24V

V

REF

INT, R

SET

INT, NMOS INT, 52V

R

LOAD

= 250Ω

T

A

= 25°C

4mA TO 20mA RANGE

0.015

–0.010

–0.005

0

0.005

0.010

–40 85603510–15

OFFSET ERROR (% FSR)

TEMPERATURE (°C)

EXT V

REF

, INT R

SET

EXT V

REF

, EXT R

SET

INT V

REF

, INT R

SET

INT V

REF

, EXT R

SET

V

LOOP

= 24V
4mA TO 20mA RANGE
R

LOAD

= 250Ω

EXT NMOS

09128-008

0.03

–0.06

–0.05

–0.04

–0.03

–0.02

–0.01

0

0.01

0.02

–40 85603510–15

GAIN ERROR ( % FSR)

TEMPERATURE (°C)

EXT V

REF

, INT R

SET

EXT V

REF

, EXT R

SET

INT V

REF

, INT R

SET

INT V

REF

, EXT R

SET

V

LOOP

= 24V
4mA TO 20mA RANGE
R

LOAD

= 250Ω

EXT NMOS

09128-009

0.0012

–0.0008

–0.0006

–0.0004

–0.0002

0

0.0002

0.0004

0.0006

0.0008

0.0010

–40 8560

35

MAX INL

MIN INL

10–15

INL ERROR ( % FSR)

TEMPERATURE (°C)

EXT V

REF

, INT R

SET

EXT V

REF

, EXT R

SET

INT V

REF

, INT R

SET

INT V

REF

, EXT R

SET

V

LOOP

= 24V
4mA TO 20mA RANGE
R

LOAD

= 250Ω

09128-010

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 6. Integral Nonlinearity Error vs. Code

Figure 7. Differential Nonlinearity Error vs. Code

Figure 9. Offset Error vs. Temperature

Figure 10. Gain Error vs. Temperature

Figure 8. Total Unadjusted Error vs. Code

Figure 11. Integral Nonlinearity Error vs. Temperature

Rev. E | Page 13 of 36

AD5421 Data Sheet

0.5

0.4

0.3

0.2

0.1

0

MAX DNL

V

= 24V

LOOP

4mA TO 20mA RANGE
R

= 250Ω

LOAD

–0.1

DNL ERRO R (LSB)

–0.2

MIN DNL

–0.3

–0.4

–0.5

–40 856035

10–15

TEMPERATURE (° C)

Figure 12. Differential Nonlinearity Error vs. Temperature

09128-011

0.0006

MAX INL

0.0004

0.0002

0

MIN INL

–0.0002

INL ERROR (% FSR)

R

= 250Ω

LOAD

T

= 25°C

–0.0004

–0.0006

A

3.8mA TO 21mA RANGE
EXT V

REF

EXT R

SET

0605040

302010

LOOP SUPPLY VOLTAGE (V)

Figure 15. Integral Nonlinearity Error vs. Loop Supply Voltage

09128-014

0.04

0.03

0.02

0.01

0

–0.01

V

= 24V

LOOP

–0.02

4mA TO 20mA RANGE
R

= 250Ω

LOAD

–0.03

EXT NMOS

EXT V

, INT R

REF

TOTAL UNADJUSTED ERROR (% FSR)

–0.04

–0.05

–0.06

EXT V
INT V
INT V

–40 85603510–15

REF

REF

REF

, EXT R
, INT R
, EXT R

SET

SET

SET

SET

TEMPERATURE (° C)

Figure 13. Total Unadjusted Error vs. Temperature

0.04

0.03

0.02

0.01

0

–0.01

V

= 24V

LOOP

–0.02

4mA TO 20mA RANGE
R

= 250Ω

LOAD

–0.03

EXT NMOS

EXT V

, INT R

REF

FULL-SCAL E ERROR (% FSR)

–0.04

–0.05

–0.06

EXT V
INT V
INT V

–40 85603510–15

REF

REF

REF

, EXT R
, INT R
, EXT R

SET

SET

SET

SET

TEMPERATURE (° C)

Figure 14. Full-Scale Error vs. Temperature

0.0029

0.0027

0.0025

0.0023

0.0021

0.0019
R

= 250Ω

LOAD

T

= 25°C

A

3.8mA TO 21mA RANGE

0.0017

TOTAL UNADJUSTED ERROR (% FSR)

09128-012

0.0015

EXT V

REF

EXT R

SET

0605040302010

LOOP SUPPLY VOLTAGE (V)

09128-015

Figure 16. Total Unadjusted Error vs. Loop Supply Voltage

0.0024
R

= 250Ω

LOAD

T

= 25°C

A

3.8mA TO 21mA RANGE

0.0022
EXT V

REF

EXT R

0.0020

SET

0.0018

0.0016

0.0014

OFFS ET ERRO R (% FSR)

0.0012

0.0010

0605040302010

09128-013

LOOP SUPPLY VOLTAGE (V)

09128-016

Figure 17. Offset Error vs. Loop Supply Voltage

Rev. E | Page 14 of 36

Data Sheet AD5421

0.0015

–0.0025

–0.0020

–0.0015

–0.0010

–0.0005

0

0.0005

0.0010

0 605040302010

GAIN ERROR ( % FSR)

LOOP SUPPLY VOLTAGE (V)

R

LOAD

= 250Ω

T

A

= 25°C

3.8mA TO 21mA RANG E
EXT V

REF

EXT R

SET

09128-017

0.0030

0.0025

0.0020

0.0015

0.0010

0.0005

0

–0.0005

0 605040302010

FULL-S CALE ERROR (% FS R)

LOOP SUPPLY VOLTAGE (V)

R

LOAD

= 250Ω

T

A

= 25°C

3.8mA TO 21mA RANG E
EXT V

REF

EXT R

SET

09128-018

2000

0

250

500

750

1000

1250

1500

1750

0 5040302010

LOAD RESI STANCE (Ω)

LOOP SUPPLY VOLTAGE (V)

T

A

= 25°C

EXT V

REF

I

LOOP

= 24mA

EXT R

SET

OPERATI NG AREA

09128-019

4.70

4.35

4.40

4.45

4.50

4.55

4.60

4.65

–40 100806040200–20

COMPLI ANCE V OLTAGE HE ADROOM (V)

TEMPERATURE (°C)

R

LOAD

= 250Ω

3.2mA TO 24mA RANG E
EXT V

REF

I

LOOP

= 24mA

09128-020

7

6

5

4

3

2

1

0

0 5.04.54.03.53.02.52.01.51.00.5

LOOP CURRE NT ERROR (µA)

REG

OUT

LOAD CURRENT ( mA)

V

LOOP

= 24V
EXT NMOS
R

LOAD

= 250Ω

T

A

= 25°C

I

LOOP

= 20mA

09128-021

8

–8

–6

–4

–2

0

2

4

6

0 10987654321

VOLTAGE ACROSS 250Ω LOAD RESISTOR (µV)

TIME (Seconds)

V

LOOP

= 24V
EXT NMOS
EXT V

REF

I

LOOP

= 4mA

R

LOAD

= 250Ω

T

A

= 25°C

09128-022

Figure 18. Gain Error vs. Loop Supply Voltage

Figure 19. Full-Scale Error vs. Loop Supply Voltage

Figure 21. Compliance Voltage Headroom vs. Temperature

Figure 22. Loop Current Error vs. REG

Load Current

OUT

Figure 20. Load Resistance Load Line vs. Loop Supply Voltage

(Voltage Between LOOP− and REG

)

IN

Figure 23. Loop Current Noise, 0.1 Hz to 10 Hz Bandwidth

Rev. E | Page 15 of 36

AD5421 Data Sheet

1.0

–1.0

–0.8

–0.6

–0.4

–0.2

0

0.2

0.6

0.8

0.4

0 1.00.90.8

0.70.60.50.40.30.20.1

VOLTAGE ACROSS 500Ω LOAD RESISTOR (mV)

TIME (Seconds)

V

LOOP

= 24V
EXT NMOS
INT V

REF

I

LOOP

= 4mA

R

LOAD

= 500Ω

T

A

= 25°C

1.33mV p-p

0.2mV rms

09128-023

6

5

4

3

2

1

0

–40 –30 –20 –10 0 10 20 30 40

VOLTAGE ACROSS 250Ω LOAD RESISTOR (V)

TIME (µs)

FALLING

RISING

V

LOOP

= 24V
EXT NMOS
R

LOAD

= 250Ω

T

A

= 25°C

C

IN

= OPEN CIRCUI T

09128-025

6

5

4

3

2

1

0

–1.0 –0.5 0 0.5 1.0 1.5 2.0 2.5 3.0

VOLTAGE ACROSS 250Ω LOAD RESISTOR (V)

TIME (ms)

FALLING

RISING

V

LOOP

= 24V
EXT NMOS
R

LOAD

= 250Ω

T

A

= 25°C

C

IN

= 22nF

09128-026

0.244

0.226

0.228

0.230

0.232

0.234

0.236

0.238

0.240

0.242

0 0.5 1.0 1.5 2.0

IODV

DD

CURRENT (µA)

DIGITAL LOGIC VOLTAGE (V)

DECREASING

INCREASING

IODVDD = 1.8V
T

A

= 25°C

09128-027

0.60

0.55

0.50

0.45

0.40
0 3.53.02.52.01.51.00.5

IODV

DD

CURRENT (µA)

DIGITAL LOGIC VOLTAGE (V)

IODVDD = 3.3V
T

A

= 25°C

DECREASING

INCREASING

09128-028

1.3

1.2

1.1

1.0

0.9

0.8

0.7

0.6
0 654321

IODV

DD

CURRENT (µA)

DIGITAL LOGIC VOLTAGE (V)

IODV

DD

= 5V

T

A

= 25°C

DECREASING

INCREASING

09128-029

Figure 24. Loop Current Noise, 500 Hz to 10 kHz Bandwidth

(HART Bandwidth)

Figure 25. Full-Scale Loop Current Step

Figure 27. IODVDD Current vs. Digital Logic Voltage, Increasing and

Decreasing, IODV

= 1.8 V

DD

Figure 28. IODVDD Current vs. Digital Logic Voltage, Increasing and

Decreasing, IODV

= 3.3 V

DD

Figure 26. Full-Scale Loop Current Step, CIN = 22 nF

Figure 29. IODVDD Current vs. Digital Logic Voltage, Increasing and

Decreasing, IODV

DD

= 5 V

Rev. E | Page 16 of 36

Data Sheet AD5421

1.85

1.84

1.83

1.82

1.81

1.80

1.79

1.78

1.77

1.76

0

–50

–45

–40

–35

–30

–25

–20

–15

–10

–5

0 12

0 0.250.200.150.100.05

108642

REG

OUT

VOLTAGE (V)

REG

OUT

VOLTAGE CHANGE (mV)

REG

OUT

LOAD CURRENT ( mA)

REG

OUT

LOAD CURRENT ( mA)

V

LOOP

= 24V
EXT NMOS
T

A

= 25°C

09128-030

263.5

258.5

259.0

259.5

260.0

260.5

261.0

261.5

262.0

262.5

263.0

0 605040302010

QUIESCENT CURRENT (µA)

LOOP SUPPLY VOLTAGE (V)

TA = 25°C

09128-031

266

257

258

259

260

261

262

263

264

265

–40 100806040200–20

QUIESCENT CURRENT (µA)

TEMPERATURE (°C)

V

LOOP

= 24V
EXT NMOS
V

IH

= IODV

DD

V

IL

= COM

T

A

= 25°C

09128-032

3.5

0

0

–50

–100

–150

–200

–250

0.5

1.0

1.5

2.0

2.5

3.0

0 1 2 3 4 5

DV

DD

OUTPUT VOLTAGE (V)

DV

DD

OUTPUT VOLTAGE CHANGE (mV)

DVDD LOAD CURRENT (mA)

09128-101

V

LOOP

= 24V
EXT NMOS
T

A

= 25°C

4

–4

–3

–2

–1

0

1

2

3

0 10854 976321

REFOUT1 VOLTAGE NOISE (µV)

TIME (Seconds)

V

LOOP

= 24V
EXT NMOS
T

A

= 25°C

09128-034

3.0

2.5

2.0

1.5

1.0

0.5

0

1

–5

–4

–3

–2

–1

0

0 7654321

REFOUT1 VOLTAGE (V)

REFOUT1 V OLTAGE CHANGE (mV)

REFOUT1 LOAD CURRENT (mA)

V

LOOP

= 24V
EXT NMOS
TA = 25°C

09128-035

Figure 30. REG

Voltage vs. Load Current

OUT

Figure 31. Quiescent Current vs. Loop Supply Voltage

Figure 33. DV

Output Voltage vs. Load Current

DD

Figure 34. REFOUT1 Voltage Noise, 0.1 Hz to 10 Hz Bandwidth

Figure 32. Quiescent Current vs. Temperature

Figure 35. REFOUT1 Voltage vs. Load Current

Rev. E | Page 17 of 36

AD5421 Data Sheet

2.5012

2.4994

2.4996

2.4998

2.5000

2.5002

2.5004

2.5006

2.5008

2.5010

–40 100806040200–20

REFOUT1 VOLTAGE (V)

TEMPERATURE (°C)

60 DEVICES SHOWN

09128-036

30

0

5

10

15

20

25

0

0.25

0.50

0.75

1.00

1.25

1.50

1.75

2.00

2.25

2.50

2.75

3.00

3.25

3.50

3.75

4.00

4.25

4.50

4.75

5.00

POPULATION (%)

TEMPERATURE COEFFICIENT (ppm/°C)

MEAN TC = 1.5p pm/°C

09128-037

250

0

50

100

150

200

–40 100806040200–20

ADC CODE (Decimal )

DIE TEMPERATURE (°C)

V

LOOP

= 24V
EXT NMOS
R

LOAD

= 250Ω

I

LOOP

= 3.2mA

09128-038

250

200

150

100

50

0

0 2.52.01.51.00.5

ADC CODE (Decimal )

V

LOOP

PIN INPUT VOLTAGE (V)

V

LOOP

= 24V
EXT NMOS
T

A

= 25°C

09128-039

Figure 36. REFOUT1 Voltage vs. Temperature, 60 Devices Shown

(C Grade Device)

Figure 37. REFOUT1 Temperature Coefficient Histogram

(C Grade Device)

Figure 38. On-Chip ADC Code vs. Die Temperature

Figure 39. On-Chip ADC Code vs. V

Pin Input Voltage

LOOP

Rev. E | Page 18 of 36

Data Sheet AD5421

TERMINOLOGY

Total Unadjusted Error

Tota l u nadjusted error (TUE) is a measure of the total output
error. TUE consists of INL error, offset error, gain error, and
output drift over temperature, in the case of maximum TUE.
TUE is expressed in % FSR.

Relative Accuracy or Integral Nonlinearity (INL) Error

Relative accuracy, or integral nonlinearity (INL) error, is a
measure of the maximum deviation in the output current from
a straight line passing through the endpoints of the transfer
function. INL error is expressed in % FSR.

Differential Nonlinearity (DNL) Error

Differential nonlinearity (DNL) error is the difference between
the measured change and the ideal 1 LSB change between any
two adjacent codes. A specified differential nonlinearity of
±1 LSB maximum ensures monotonicity.

Offset Error

Offset error is a measure of the output error when zero code is
loaded to the DAC register and is expressed in % FSR.

Offset Error Temperature Coefficient (TC)

Offset error TC is a measure of the change in offset error with
changes in temperature and is expressed in ppm FSR/°C.

Gain Error

Gain error is a measure of the span error of the DAC. It is the
deviation in slope of the DAC transfer function from the ideal
and is expressed in % FSR.

Gain Error Temperature Coefficient (TC)

Gain error TC is a measure of the change in gain error with
changes in temperature and is expressed in ppm FSR/°C.

Full-Scale Error

Full-scale error is a measure of the output error when full-scale
code is loaded to the DAC register and is expressed in % FSR.

Full-Scale Error Temperature Coefficient (TC)

Full-scale error TC is a measure of the change in full-scale error
with changes in temperature and is expressed in ppm FSR/°C.

Loop Compliance Voltage Headroom

Loop compliance voltage headroom is the minimum voltage
between the LOOP− and REG

pins for which the output

IN

current is equal to the programmed value.

Output Temperature Coefficient (TC)

Output TC is a measure of the change in the output current
at 12 mA with changes in temperature and is expressed in
ppm FSR/°C.

Voltage Reference Thermal Hysteresis

Voltage reference thermal hysteresis is the difference in output
voltage measured at +25°C compared to the output voltage
measured at +25°C after cycling the temperature from +25°C to

−40°C to +105°C and back to +25°C. The hysteresis is specified
for the first and second temperature cycles and is expressed in mV.

Voltage Reference Temperature Coefficient (TC)

Voltage reference TC is a measure of the change in the reference
output voltage with a change in temperature. The voltage refer­ence TC is calculated using the box method, which defines the
TC as the maximum change in the reference output voltage over
a given temperature range. Voltage reference TC is expressed in
ppm/°C as follows:



REF_MAX



=

TC



REF_NOM



−

VV

REF_MIN

×

Temp_RangeV



6



10×




where:

V

is the maximum reference output voltage measured

REF_MAX

over the total temperature range.

V

is the minimum reference output voltage measured

REF_MIN

over the total temperature range.

V

is the nominal reference output voltage, 2.5 V.

REF_NOM

Temp_Range is the specified temperature range

(−40°C to +105°C).

Rev. E | Page 19 of 36

SDIN

SYNC

SCLK

UPDATE ON SY NC HIGH

MSB

D23

LSB

D0

24-BIT DATA

24-BIT DATA TRANSFER—NO ERROR CHECKING

SDIN

FAULT

SYNC

SCLK

UPDATE AFT E R S Y NC HIGH

ONLY IF ERROR CHECK PASSE D

FAULT PIN GOES HIGH

IF ERROR CHE CK FAILS

MSB

D31

LSB

D8 D7 D0

24-BIT DATA 8-BIT FCS

32-BIT DATA TRANSFER W ITH ERROR CHECKI NG

09128-049

AD5421 Data Sheet

THEORY OF OPERATION

The AD5421 is an integrated device designed for use in loop­powered, 4 mA to 20 mA smart transmitter applications. In a
single chip, the AD5421 provides a 16-bit DAC and current
amplifier for digital control of the loop current, a voltage
regulator to power the entire transmitter, a voltage reference,
fault alert functions, a flexible SPI-compatible serial interface,
gain and offset adjust registers, as well as other features and
functions. The features of the AD5421 are described in the
following sections.

FAULT ALERTS

The AD5421 provides a number of fault alert features. All
faults are signaled to the controller via the FAULT pin and the
fault register. In the case of a loss of communication between
the AD5421 and the microcontroller (SPI fault), the AD5421
programs the loop current to an alarm value. If the controller
detects that the FAULT pin is set high, it should then read the
fault register to determine the cause of the fault.

SPI Fault

The SPI fault is asserted if there is no valid communication to
any register of the AD5421 for more than a user-defined period.
The user can program the time period using the SPI watchdog
timeout bits of the control register. The SPI fault bit of the fault
register indicates the fault on the SPI bus. Because this fault is
caused by a loss of communication between the controller and
the AD5421, the loop current is also forced to the alarm value.

The direction of the alarm current (downscale or upscale)
is selected via the ALARM_CURRENT_DIRECTION pin.
Connecting this pin to DV
(22.8 mA/24 mA); connecting this pin to COM selects a
downscale alarm current (3.2 mA).

Packet Error Checking

To verify that data has been received correctly in noisy environ­ments, the AD5421 offers the option of error checking based on
an 8-bit cyclic redundancy check (CRC). Packet error checking
(PEC) is enabled by writing to the AD5421 with a 32-bit serial
frame, where the least significant eight bits are the frame check
sequence (FCS). The device controlling the AD5421 should
generate the 8-bit FCS using the following polynomial:

The 8-bit FCS is appended to the end of the data-word, and
32 data bits are sent to the AD5421 before
If the check is valid, the data is accepted. If the check fails, the
FAULT pin is asserted and the PEC bit of the fault register is set.

C(x) = x

8

+ x 2 + x + 1

After the fault register is read, the PEC bit is reset low and the
FAULT pin returns low.

selects an upscale alarm current

DD

SYNC

is taken high.

Rev. E | Page 20 of 36

In the case of data readback, if the AD5421 is addressed with a
32-bit frame, it generates the 8-bit frame check sequence and
appends it to the end of the 24-bit data stream to create a 32-bit
data stream.

Figure 40. PEC Timing

Current Loop Fault

The current loop (I

) fault is asserted when the actual loop

LOOP

current is not within ±0.01% FSR of the programmed loop
current. If the measured loop current is less than the programmed
loop current, the I

Under bit of the fault register is set. If the

LOOP

measured loop current is greater than the programmed loop
current, the I

Over bit of the fault register is set. The FAULT

LOOP

pin is set to logic high in either case.

An I

Over condition occurs when the value of the load current

LOOP

sourced from the AD5421 (via REG
or DV
to flow in the loop. An I

) is greater than the loop current that is programmed

DD

under condition occurs when there

LOOP

, REFOUT1, REFOUT2,

OUT

is insufficient compliance voltage to support the programmed
loop current, caused by excessive load resistance or low loop
supply voltage.

Overtemperature Fault

There are two overtemperature alert bits in the fault register:
Temp 100°C and Temp 140°C. If the die temperature of the
AD5421 exceeds either 100°C or 140°C, the appropriate bit is
set. If the Temp 140°C bit is set in the fault register, the FAULT
pin is set to logic high.

Data Sheet AD5421

19MΩ

1MΩ

R

L

LOOP–

V

LOOP

COM

REG

IN

V

LOOP

AD5421

09128-048

R

L

LOOP–

DRIVE

COM

REG

IN

V

LOOP

AD5421

09128-050

R

L

200kΩ

LOOP–

DRIVE

COM

REG

IN

V

LOOP

AD5421

T1

DN2540

BSP129

09128-051

Loop Voltage Fault

There are two loop voltage alert bits in the fault register:
V

12V and V

LOOP

6V. If the voltage between the V

LOOP

LOOP

and
COM pins falls below 0.6 V (corresponding to a 12 V loop
supply value), the V

12V bit is set; this bit is cleared when

LOOP

the voltage returns above 0.7 V. Similarly, if the voltage between
the V
6 V loop supply value), the V
when the voltage returns above 0.4 V. If the V

and COM pins falls below 0.3 V (corresponding to a

LOOP

6V bit is set; this bit is cleared

LOOP

6V bit is set in

LOOP

the fault register, the FAULT pin is set to logic high.

Figure 41 illustrates how a resistor divider enables the monitor­ing of the loop supply with the V

input. The recommended

LOOP

resistor divider consists of a 1 MΩ and a 19 MΩ resistor that
provide a 20:1 ratio, allowing the 2.5 V input range of the V

LOOP

pin to monitor loop supplies up to 50 V. With a 20:1 divider ratio,
the preset V

6V and V

LOOP

12V alert bits of the fault register

LOOP

generate loop supply faults according to their stated values. If
another divider ratio is used, the fault bits generate faults at values
that are not equal to 6 V and 12 V.

LOOP CURRENT RANGE SELECTION

To select the loop current range, connect the RANGE0
and RANGE1 pins to the COM and DV

pins, as shown

DD

in Table 9.

Table 9. Selecting the Loop Current Range

RANGE1 Pin RANGE0 Pin Loop Current Range

COM COM 4 mA to 20 mA
COM DVDD 3.8 mA to 21 mA
DVDD COM 3.2 mA to 24 mA
DVDD DVDD 3.8 mA to 21 mA

CONNECTION TO LOOP POWER SUPPLY

The AD5421 is powered from the 4 mA to 20 mA current loop.
Typically, the power supply is located far from the transmitter
device and has a value of 24 V. The AD5421 can be connected
directly to the loop power supply and can tolerate a voltage up
to a maximum of 52 V (see Figure 42).

Figure 41. Resistor Divider Connection at V

LOOP

EXTERNAL CURRENT SETTING RESISTOR

The 24 kΩ resistor R
output voltage to a current, which is then mirrored with a gain
of 221 to the LOOP− pin. The stability of the loop current over
temperature is dependent on the temperature coefficient of R

Tabl e 1 and Table 2 outline the performance specifications of
the AD5421 with both the internal R
24 kΩ R

resistor. Using the internal R

SET

justed error of better than 0.126% FSR can be expected. Using
an external resistor gives improved performance of 0.048% FSR.
This specification assumes an ideal resistor; the actual performance
depends on the absolute value and temperature coefficient of
the resistor used. For more information, see the Determining
the Expected Total Error section.

, shown in Figure 1, converts the DAC

SET

resistor and an external,

SET

resistor, a total unad-

SET

Pin

SET

Rev. E | Page 21 of 36

Figure 42. Direct Connection of the AD5421 to Loop Power Supply

Figure 42 shows how the AD5421 is connected directly to the
loop power supply. An alternative power connection is shown
in Figure 43, which shows a depletion mode N-channel MOSFET
connected between the AD5421 and the loop power supply. The
use of this device keeps the voltage drop across the AD5421 at
approximately 12 V, limiting the worst-case on-chip power dissi­pation to 288 mW (12 V × 24 mA = 288 mW). If the AD5421 is

.

connected directly to the loop supply as shown in Figure 42, the
potential worst-case on-chip power dissipation for a 24 V loop
power supply is 576 mW (24 V × 24 mA = 576 mW). The power
dissipation changes in proportion to the loop power supply voltage.

Figure 43. MOSFET Connecting the AD5421 to Loop Power Supply

AD5421 Data Sheet

COM

DVDD

DVDD

3.3

LOOP–

R

DAC

V-TO-I

CIRCUITRY

C

IN

C

SLEW

09128-052

DAC

SLEW

R

t

C

×=5

nF68

220,155

ms5

≈

×

=

SLEW

C

nF133

220,155

ms10

≈

×

=

SLEW

C

6

5

4

3

2

1

0

–2 2218141062

VOLTAGE ACROSS 250Ω LOAD RESISTOR (V)

TIME (ms)

C

SLEW

= 267nF

C

SLEW

= 133nF

C

SLEW

= 68nF

09128-053

ON-CHIP ADC

The AD5421 contains an on-chip ADC used to measure and
feed back to the fault register either the temperature of the die
or the voltage between the V

and COM pins. The select ADC

LOOP

input bit (Bit D8) of the control register selects the parameter
to be converted. A conversion is initiated with command byte
00001000 (necessary only if auto fault readback is disabled). This
command byte powers on the ADC and performs the conversion.
A read of the fault register returns the conversion result. If auto
readback of the fault register is required, the ADC must first be
powered up by setting the on-chip ADC bit (Bit D7) of the
control register.

Because the FAULT pin can go high for as long as 30 μs, care is
required when performing a die temperature measurement after
a readback of the V

LOOP

voltage.

VOLTAGE REGULATOR

The on-chip voltage regulator provides a regulated voltage out­put to supply the AD5421 and the remainder of the transmitter
circuitry. The output voltage range is from 1.8 V to 12 V and is
selected by the states of three digital input pins (see Table 10).
The regulator output is accessed at the REG

Table 10. Setting the Voltage Regulator Output

REG_SEL2 REG_SEL1 REG_SEL0

COM COM COM 1.8
COM COM DVDD 2.5
COM DVDD COM 3.0

pin.

OUT

Regulated Output
Voltage (V)

The resistance of the DAC is typically 15.22 kΩ for the 4 mA
to 20 mA and 3.8 mA to 21 mA loop current ranges. The DAC
resistance changes to 16.11 kΩ when the 3.2 mA to 24 mA loop
current range is selected.

The time constant of the circuit is expressed as

τ = R

DAC

× C

SLEW

Taking five time constants as the required time to reach the final
value, C

can be determined for a desired response time, t,

SLEW

as follows:

where:
t is the desired time for the output current to reach its final
value.

R

is the resistance of the DAC core, either 15.22 kΩ or

DAC

16.11 kΩ, depending on the selected loop current range.

For a response time of 5 ms,

For a response time of 10 ms,

The responses for both of these configurations are shown
in Figure 45.

DVDD COM COM 5.0
DVDD COM DVDD 9.0
DVDD DVDD COM 12.0

LOOP CURRENT SLEW RATE CONTROL

The rate of change of the loop current can be controlled by
connecting an external capacitor between the C
COM. This reduces the rate of change of the loop current.
The output resistance of the DAC (R
C

capacitor generate a time constant that determines the

SLEW

response of the loop current (see Figure 44).

Figure 44. Slew Capacitor Circuit

) together with the

DAC

pin and

IN

Figure 45. 4 mA to 20 mA Step with Slew Rate Control

The CIN pin can also be used as a coupling input for HART
FSK signaling. The HART signal must be ac-coupled to the C

IN

input. The capacitor through which the HART signal is coupled
must be considered in the preceding calculations, where the
total capacitance is C

SLEW

+ C

. For more information, see

HART

the HART Communications section.

Rev. E | Page 22 of 36

Data Sheet AD5421

09128-054

R

L

200kΩ

LOOP–

DRIVE

COMC

IN

REG

IN

V

LOOP

AD5421

HART_OUT

HART_IN

HART

MODEM

C

HART

C

SLEW

HART

SLEW

HART

C

CC +

=5.4

( )

SLEW

HART

DAC

dB

CCR

f

+××π×=2

1

3

12

10

8

6

4

2

0

150

–150

–100

–50

0

50

100

–50 –30 –10 10 30 50

VOLTAGE ACROSS 500Ω LOAD RESISTOR (V)

OUTPUT OF HART DIGITAL FILTER (mV)

HCF_TOOL-31

TIME (ms)

09128-060

POWER-ON DEFAULT

The AD5421 powers on with all registers loaded with their default
values and with the loop current in the alarm state set to 3.2 mA
or 22.8 mA/24 mA (depending on the state of the ALARM_
CURRENT_DIRECTION pin and the selected range). The
AD5421 remains in this state until it is programmed with new
values. The SPI watchdog timer is enabled by default with a
timeout period of 1 sec. If there is no communication with the
AD5421 within 1 sec of power-on, the FAULT pin is set.

HART COMMUNICATIONS

The AD5421 can be interfaced to a Highway Addressable
Remote Transducer (HART) modem to enable HART digital
communications over the 2-wire loop connection. Figure 46
shows how the modem frequency shift keying (FSK) output is
connected to the AD5421.

Figure 46. Connecting a HART Modem to the AD5421

To achieve a 1 mA p-p FSK current signal on the loop, the voltage
at the C

pin must be 111 mV p-p. Assuming a 500 mV p-p

IN

output from the HART modem, this means that the signal must
be attenuated by a factor of 4.5. The following equation can be
used to calculate the values of the C

HART

and C

capacitors.

SLEW

To achieve a 500 Hz high-pass 3 dB frequency cutoff, the com­bined values of C

HART

and C

should be 21 nF. To ensure the

SLEW

correct HART signal amplitude on the current loop, the final
values for the capacitors are C

= 4.7 nF and C

HART

= 16.3 nF.

SLEW

Output Noise During Silence and Analog Rate of Change

The AD5421 has a direct influence on two important specifi­cations relating to the HART communications protocol: output
noise during silence and analog rate of change. Figure 24 shows
the measurement of the AD5421 output noise in the HART
extended bandwidth; the noise measurement is 0.2 mV rms,
within the required 2.2 mV rms value.

To meet the analog rate of change specification, the rate of
change of the 4 mA to 20 mA current must be slow enough so
that it does not interfere with the HART digital signaling. This
is determined by forcing a full-scale loop current change
through a 500 Ω load resistor and applying the resulting voltage
signal to the HART digital filter (HCF_TOOL-31). The peak
amplitude of the signal at the filter output must be less than
150 mV. To achieve this, the rate of change of the loop current
must be restricted to less than approximately 1.3 mA/ms.

The output of the AD5421 naturally slews at approximately
880 mA/ms, a rate that is far too great to comply with the
HART specifications. To reduce the slew rate, a capacitor can be
connected from the C

pin to COM, as described in the Loop

IN

Current Slew Rate Control section. To reduce the slew rate
enough so that the HART specification is met, a capacitor value
in the region of 4.7 µF is required, resulting in a full-scale transition
time of 500 ms. Many applications regard this time as too slow,
in which case the slew rate needs to be digitally controlled by
writing a sequence of codes to the DAC register so that the
output response follows the desired curve.

Figure 47 shows a digitally controlled full-scale step and the
resulting filter output. In Figure 47, it can be seen that the peak
amplitude of the filter output signal is less than the required
150 mV, and the transition time is approximately 30 ms.

From this equation, the ratio of C
ratio of the capacitor values sets the amplitude of the HART
FSK signal on the loop. The absolute values of the capacitors set
the response time of the loop current, as well as the bandwidth
presented to the HART signal connected at the C
bandwidth must pass frequencies from 500 Hz to 10 kHz. The
two capacitors and the internal impedance, R
pass filter. The 3 dB frequency of this high-pass filter should be
less than 500 Hz and can be calculated as follows:

HART

to C

is 1 to 3.5. This

SLEW

IN

, form a high-

DAC

pin. The

Figure 47. Digitally Controlled Full-Scale Step and Resulting HART Digital

Filter Output Signal

Rev. E | Page 23 of 36

AD5421 Data Sheet

09128-061

R

L

LOOP–

COM

C

IN

REG

IN

V

LOOP

AD5421

FROM HART MODEM

47nF

168nF

Figure 48 shows the circuit diagram for this measurement. The
47 nF and 168 nF capacitor values for C
adequate filtering of the digital steps, ensuring that they do not
cause interference.

HART

and C

SLEW

provide

Figure 48. Circuit Diagram for Figure 47

Rev. E | Page 24 of 36

Data Sheet AD5421

00000101

Load DAC

Address/command byte

Data-word

SERIAL INTERFACE

The AD5421 is controlled by a versatile, 3-wire serial interface
that operates at clock rates up to 30 MHz. It is compatible with
the SPI, QSPI™, MICROWIRE®, and DSP standards. Figure 2
shows the timing diagram. The interface operates with either
a continuous or noncontinuous gated burst clock.

The write sequence begins with a falling edge of the

SYNC
signal; data is clocked in on the SDIN data line on the falling
edge of SCLK. On the rising edge of

SYNC

, the 24 bits of data
are latched; the data is transferred to the addressed register and
the programmed function is executed (either a change in DAC
output or mode of operation).

If packet error checking on the SPI interface is required using
cyclic redundancy codes, an additional eight bits must be written
to the AD5421, creating a 32-bit serial interface. In this case,
32 bits are written to the AD5421 before

SYNC

is brought high.

INPUT SHIFT REGISTER

The input shift register is 24 bits wide (32 bits wide if CRC error
checking of the data is required). Data is loaded into the device
MSB first as a 24-/32-bit word under the control of a serial clock
input, SCLK. The input shift register consists of an 8-bit address/
command byte, a 16-bit data-word, and an optional 8-bit CRC,
as shown in Table 12 and Table 13.

The address/command byte decoding is described in Table 11.

Table 11. Address/Command Byte Functions

Address/Command Byte Function

00000001 Write to DAC register
00000010 Write to control register

Address/Command Byte Function

00000011 Write to offset adjust register
00000100 Write to gain adjust register

00000110 Force alarm current
00000111 Reset (it is recommended to wait

50 µs after a device reset before
writing the next command)

00001000 Initiate V

measurement
00001001 No operation
10000001 Read DAC register
10000010 Read control register
10000011 Read offset adjust register
10000100 Read gain adjust register
10000101 Read fault register

/temperature

LOOP

The 16 bits of the data-word written following a load DAC, force
alarm current, reset, initiate V

/temperature measurement,

LOOP

or no operation command byte are don’t cares (see Table 12 and
Tabl e 13).

REGISTER READBACK

To re a d back a register, Bit D11 of the control register must be set
to Logic 1 to disable the automatic readback of the fault register.
The 16 bits of the data-word written following a read command
are don’t cares (see Table 12 and Table 13).

The register data addressed by the read command is clocked out
of SDO on the subsequent write command (see Figure 3).

Table 12. Input Shift Register

MSB LSB

D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Table 13. Input Shift Register with CRC

MSB LSB

D31

D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Address/command byte Data-word CRC

Rev. E | Page 25 of 36

AD5421 Data Sheet

mA4

2

mA16

16

D I

LOOP

+×















=

mA8.3

2

mA2.17

16

D I

LOOP

+×















=

DAC REGISTER

The DAC register is a read/write register and is addressed
as described in Table 11. The data programmed to the DAC
register determines the loop current, as shown in the Ideal
Output Transfer Function section and in Tab l e 15.

Ideal Output Transfer Function

The transfer function describing the relationship between the
data programmed to the DAC register and the loop current is
expressed by the following three equations.

For the 4 mA to 20 mA output range, the loop current can be
expressed as follows:

Table 14. DAC Register Bit Map

MSB LSB

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

16-bit data

For the 3.8 mA to 21 mA output range, the loop current can be
expressed as follows:

For the 3.2 mA to 24 mA output range, the loop current can be
expressed as follows:

mA8.20

LOOP



=








D I

+×



16



2



mA2.3

where D is the decimal value of the DAC register.

Table 15. Relationship of DAC Register Code to Ideal Loop Current (Gain = 65,536; Offset = 0)

Ideal Loop Current (mA)

DAC Register Code

0x0000 4 3.8 3.2
0x0001 4.00024 3.80026 3.2003
… … … …
0x7FFF 11.9997 12.39974 13.5997
0x8000 12 12.4 13.6
… … … …
0xFFFE 19.9995 20.99947 23.9994
0xFFFF 19.9997 20.99974 23.9997

4 mA to 20 mA Range 3.8 mA to 21 mA Range 3.2 mA to 24 mA Range

Rev. E | Page 26 of 36

Data Sheet AD5421

0 1 1

1 sec (default)

CONTROL REGISTER

The control register is a read/write register and is addressed as described in Tab l e 11. The data programmed to the control register
determines the mode of operation of the AD5421.

Table 16. Control Register Bit Map

MSB LSB

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

SPI watchdog timeout

T0 T1 T2

SPI
watchdog
timer

Auto fault
readback

Alarm on
SPI fault

Table 17. Control Register Bit Descriptions

Control Bits Description

SPI watchdog
timeout

The T0, T1, and T2 bits allow the user to program the watchdog timeout period. The watchdog timer is reset when a valid
write to any AD5421 register occurs or when a NOP command is written.

T0 T1 T2 Timeout Period

0 0 0 50 ms
0 0 1 100 ms
0 1 0 500 ms

1 0 0 2 sec
1 0 1 3 sec
1 1 0 4 sec
1 1 1 5 sec

SPI watchdog
timer

Auto fault
readback

0 = SPI watchdog timer is enabled (default).
1 = SPI watchdog timer is disabled.

This bit specifies whether the fault register contents are automatically clocked out on the SDO pin on each write operation.
(The fault register can always be addressed for readback.)
0 = fault register contents are clocked out on the SDO pin (default).
1 = fault register contents are not clocked out on the SDO pin.

Alarm on SPI
fault

This bit specifies whether the loop current is forced to the alarm value when an SPI fault is detected (that is, the watchdog
timer times out). When an SPI fault is detected, the SPI fault bit of the fault register and the FAULT pin are always set.
0 = loop current is forced to the alarm value when an SPI fault is detected (default).
1 = loop current is not forced to the alarm value when an SPI fault is detected.

Set min loop
current

0 = normal operation (default).
1 = loop current is set to its minimum value so that the total current flowing in the loop consists only of the operating
current of the AD5421 and its associated circuitry.

Select ADC
input

0 = on-chip ADC measures the voltage between the V
1 = on-chip ADC measures the temperature of the AD5421 die.

On-chip ADC 0 = on-chip ADC is disabled (default).

1 = on-chip ADC is enabled.

Power down
internal

0 = internal voltage reference is powered up (default).
1 = internal voltage reference is powered down and an external voltage reference source is required.

reference
V

LOOP

alert

fault

This bit specifies whether the FAULT pin is set when the voltage between the V
(The V
0 = FAU LT pin is not set when the V
1 = FAULT pin is set when the V

6V bit of the fault register is always set.)

LOOP

LOOP

− COM voltage falls to approximately 0.3 V.

LOOP

Set min
loop
current

Select
ADC
input

On-chip
ADC

and COM pins (default).

LOOP

Power down
internal
reference

LOOP

− COM voltage falls to approximately 0.3 V.

V

LOOP

fault
alert

Reserved

and COM pins falls to approximately 0.3 V.

Rev. E | Page 27 of 36

AD5421 Data Sheet

11111111

2.49

−55

FAULT REGISTER

The read-only fault register is addressed as described in Tabl e 11. The bits in the fault register indicate a range of possible fault conditions.

Table 18. Fault Register Bit Map

MSB LSB

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

I

I

SPI PEC

LOOP

Over

LOOP

Under

Temp
140°C

Table 19. Fault Register Bit Descriptions

FA U LT

Fault Alert

Pin Set Description

SPI Yes This bit is set high to indicate the loss of the SPI interface signaling. This fault occurs if there is no valid

communication to the AD5421 over the SPI interface for more than the user-defined timeout period. The
occurrence of this fault also forces the loop current to the alarm value if Bit D10 of the control register is at
Logic 0. The alarm current direction is determined by the state of the ALARM_CURRENT_DIRECTION pin.

PEC (packet
error check)

I

Over Yes This bit is set high when the actual loop current is greater than the programmed loop current.

LOOP

I

Under Yes This bit is set high when the actual loop current is less than the programmed loop current.

LOOP

Yes This bit is set high when an error in the SPI communication is detected using cyclic redundancy check (CRC)

error detection. See the Packet Error Checking section for more information.

Temp 140°C Yes This bit is set high to indicate an overtemperature fault. This bit is set if the die temperature of the AD5421

exceeds approximately 140°C. This bit is cleared when the temperature returns below approximately 125°C.

Temp 100°C No This bit is set high to indicate an increasing temperature of the AD5421. This bit is set if the die temperature of the

AD5421 exceeds approximately 100°C. This bit is cleared when the temperature returns below approximately 85°C.

V

6V Yes This bit is set high when the voltage between the V

LOOP

a 6 V loop supply voltage with 20:1 resistor divider connected at V
above approximately 0.4 V.

V

12V No This bit is set high when the voltage between the V

LOOP

a 12 V loop supply voltage with 20:1 resistor divider connected at V
above approximately 0.7 V.

V

/temper-

LOOP

ature value

N/A These eight bits represent either the voltage between the V

depending on the setting of Bit D8 of the control register (see the On-Chip ADC Transfer Function Equations section).

8-Bit Value V

00000000 0 +300
… … …

Temp
100°C

V

V

LOOP

6V

− COM Voltage (V) Die Temperature (°C)

LOOP

LOOP

12V

and COM pins falls below approximately 0.3 V (representing

LOOP

LOOP

and COM pins falls below approximately 0.6 V (representing

LOOP

and COM pins or the AD5421 die temperature,

LOOP

/temperature value

V

LOOP

). This bit is cleared when the voltage returns

). This bit is cleared when the voltage returns

LOOP

On-Chip ADC Transfer Function Equations

The transfer function equation for the measurement of the
voltage between the V

where D is the 8-bit digital code returned by the on-chip ADC.

V

− COM = (2.5/256) × D

LOOP

and COM pins is as follows:

LOOP

The transfer function equation for the die temperature is
as follows:

Die Temperature = 125 − (1.771 × (D − 128))

where D is the 8-bit digital code returned by the on-chip ADC.

Rev. E | Page 28 of 36

Data Sheet AD5421

32769

+1

32768 (default)

0

65534

−1

…

…

OFFSET ADJUST REGISTER

The offset adjust register is a read/write register and is addressed as described in Table 11.

Table 20. Offset Adjust Register Bit Map

MSB LSB

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

16-bit offset adjust data

Table 21. Offset Adjust Register Adjustment Range

Offset Adjust Register Data Digital Offset Adjustment (LSBs)

65535 +32767
65534 +32766
… …

32767 −1
… …
1 −32767
0 −32768

GAIN ADJUST REGISTER

The gain adjust register is a read/write register and is addressed as described in Table 11.

Table 22. Gain Adjust Register Bit Map

MSB LSB

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

16-bit gain adjust data

Table 23. Gain Adjust Register Adjustment Range

Gain Adjust Register Data Digital Gain Adjustment at Full-Scale Output (LSBs)

65535 (default) 0

… …
32769 −32767
32768 −32768
32767 −32769

1 −65534
0 −65535

Rev. E | Page 29 of 36

AD5421 Data Sheet

( )
























−×















++ 768,32

2

mA16

mA4

16

Offset





























×

×















= D

Gain

I

LOOP

16

16

2

2

mA2.17

































×

×















= D

Gain

I

LOOP

16

16

2

2

mA8.20

( )
























−×















++ 768,32

2

mA8.20

mA2.3

16

Offset

Transfer Function Equations with Offset and Gain Adjust Values

When the offset adjust and gain adjust register values are taken
into account, the transfer equations can be expressed as follows.

For the 4 mA to 20 mA output range, the loop current can be
expressed as follows:

mA16








16



2





= D

I

LOOP








2



×

Gain






16





×








For the 3.8 mA to 21 mA output range, the loop current can be
expressed as follows:

For the 3.2 mA to 24 mA output range, the loop current can be
expressed as follows:

where:

D is the decimal value of the DAC register.
Gain is the decimal value of the gain adjust register.
Offset is the decimal value of the offset adjust register.

Note that the offset adjust register cannot adjust the zero-scale
output value downward.






++ 768,32

mA8.3

mA2.17















( )

−×





16

2



Offset













Rev. E | Page 30 of 36

Data Sheet AD5421

APPLICATIONS INFORMATION

Figure 49 shows a typical connection diagram for the AD5421
configured in a HART capable smart transmitter. Such a HART
enabled smart transmitter was developed by Analog Devices as
a reference demo circuit. This circuit, whose block diagram is
shown in Figure 50, was verified and registered as an approved
HART solution by the HART Communication Foundation.

To reduce power dissipation on the chip, a depletion mode
MOSFET (T1), such as a DN2540 or BSP129, can be connected
between the loop voltage and the AD5421, as shown in Figure 49.
If a low loop voltage is used, T1 does not need to be inserted,
and the loop voltage can connect directly to REG

(see Figure 42).

IN

In Figure 49, all interface signal lines are connected to the micro­controller. To reduce the number of interface signal lines, the
LDAC

signal can be connected to COM, and the SDO and FAULT
lines can be left unconnected. However, this configuration disables
the use of the fault alert features.

Under normal operating conditions, the voltage between COM
and LOOP− does not exceed 1.5 V, and the voltage at LOOP− is
negative with respect to COM. If it is possible that the voltage at
LOOP− may be forced positive with respect to COM, or if the
voltage difference between LOOP− and COM may be forced in

excess of 5 V, a 4.7 V low leakage Zener diode should be placed
between COM and the LOOP− pin, as shown in Figure 49, to
protect the AD5421 from potential damage.

DETERMINING THE EXPECTED TOTAL ERROR

The AD5421 can be set up in a number of different configu­rations, each of which achieves different levels of accuracy, as
described in Table 1 and Table 2. With the internal voltage
reference and internal R
of 0.157% of full-scale range can be expected for the C grade
device over the temperature range of −40°C to +105°C.

Other configurations specify an external voltage reference, an
external R
external R

resistor, or both an external voltage reference and

SET

resistor. In these configurations, the specifications

SET

assume that the external voltage reference and external R
resistor are ideal. Therefore, the errors associated with these
components must be added to the data sheet specifications to
determine the overall performance. The performance depends
on the specifications of these components.

enabled, a maximum total error

SET

SET

ADuCM360

OPTIONAL

EMC FILTER

R1
470Ω

4.7µF

0.1µF

1µF

AD5700/AD5700-1

TXD
RXD
RTS
CD

0.1µF

IODVDDDVDDREG

RANGE0

RANGE1

ALARM_CURRENT_DIRECT ION
R

INT/REXT

SYNC
SCLK
SDIN
SDO
FAU LT
LDAC

COM

REFOUT2

0.1µF

V

CC

HART_OUT

ADC_IP

DGNDAGND

10µF

REF

OPTIONAL

MOSFET

DN2540
BSP129

OUT

AD5421

REG_SEL0

REG_SEL1

REG_SEL2

SETS REGULATOR

VOLTAGE

47nF 168nF

1.2MΩ

1µF

1.2MΩ 150pF

REG

C

IN

300pF

T1

200kΩ

IN

DRIVE

V

LOOP

LOOP–

R

EXT1

R

EXT2

COMREFOUT1 REFIN

R1

OPTIONAL
RESISTOR

150kΩ

19MΩ

1MΩ

VZ = 4.7V

V

LOOP

R

L

Figure 49. AD5421 Application Diagram for HART Capable Smart Transmitter

Rev. E | Page 31 of 36

09128-055

AD5421 Data Sheet

09128-200

ADC 0

PRESSURE
SENSOR
SIMULATION

TEMPERATURE
SENSOR
PT100

3.3V

ADC 1

ADC

DAC

ADuCM360

SRAM

FLASH

CLOCK

RESET

WATCHDOG

T1: CD
T2: RTS
T3: COM
T4: TEST

SPI

UART

AD5700

AD5421

V

CC

HART_OUT

REF

ADC_IP

3.3V

3.3V

V

DD

C

IN

C_HART

C_SLEW

HART
INPUT
FILTER

COM

V-REGULATOR

TEMPERATURE

SENSOR

COM

REG

IN

V

LOOP

LOOP–

TEST CONNECTOR

+

–

50Ω

HART MODEM

MICRO-

CONTROLLER

WATCHDOG

TIMER

LEXC

DGNDAGND

Figure 50. Block Diagram—Analog Devices HART-Enabled Smart Transmitter Reference Demo Cir cuit

Rev. E | Page 32 of 36

Data Sheet AD5421

FSR%102.0%)029.0(%)0435.0(%0015.0%048.0

22

=+++

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

0 20 40 60 80 100

POWER DISSIPATION (W)

AMBIENT TE M P E RATURE (°C)

09128-103

TSSOP

LFCSP

60

50

40

30

20

10

0

40 50 60 70 80 90 100

SUPPLY VOLTAGE (V)

AMBIENT TE M P E RATURE (°C)

09128-102

LFCSP

TSSOP

−

TT

mW625

32

105125=−

=

−

JA

AJ MAX

θ

TT

=×−

JADMAXJ

PT

θ

( )( )

C77400228.052125 °=××−

C87)32)0228.052((125

)(

°=××−

=×−

JAD MAXJ

PT

θ

Maximum

Maximum permitted supply voltage

V21

400228.0

105125

=

×

−

=

×

−

JALOOP

AMAXJ

I

TT

θ

V27

320228.0

105125

=

×

−

=

×

−

JALOOP

A MAXJ

I

TT

θ

To determine the absolute worst-case overall error, the reference
and R

errors can be directly summed with the specified AD5421

SET

maximum error. For example, when using an external reference
and external R

resistor, the maximum AD5421 error is 0.048%

SET

of full-scale range. Assuming that the absolute errors for the
voltage reference and R

resistor are, respectively, 0.04% and

SET

0.05% with temperature coefficients of 3 ppm/°C and 2 ppm/°C,
respectively, the overall worst-case error is as follows:

Worst-Case Error =
AD5421 Error + V
R

Absolute Error + R

SET

Absolute Error + V

REF

TC

SET

REF

TC +

Worst-Case Error =

0.048% + 0.04% + [(3/10

0.05% + [(2/10

6

) × 100 × 145]% = 0.21% FSR

6

) × 100 × 145]% +

This is the absolute worst-case value when the AD5421 operates
over the temperature range of −40°C to +105°C. An error of this
value is very unlikely to occur because the temperature coeffi­cients of the individual components do not exhibit the same
drift polarity, and, therefore, an element of cancelation occurs.
For this reason, the TC values should be added in a root of
squares fashion.

A further improvement can be gained by performing a two-point
calibration at zero scale and full scale, thus reducing the absolute
errors of the voltage reference and R

resistor to a combined

SET

error of 1 LSB or 0.0015% FSR. After performing this calibration,
the total maximum error becomes

Total Error =

Excessive junction temperature can occur if the AD5421
experiences elevated voltages across its terminals while
regulating the loop current at a high value. The resulting
junction temperature depends on the ambient temperature.

Tabl e 24 provides the bounds of operation at maximum ambient
temperature and maximum supply voltage. This information is
displayed graphically in Figure 51 and Figure 52. These figures
assume that the exposed paddle is connected to a copper plane
of approximately 6 cm

Figure 51. Maximum Power Dissipation vs. Ambient Temperature

2

.

To reduce this error value further, a voltage reference and R
resistor with lower TC specifications must be chosen.

THERMAL AND SUPPLY CONSIDERATIONS

The AD5421 is designed to operate at a maximum junction temp­erature of 125°C. To ensure reliable and specified operation over
the lifetime of the product, it is important that the device not be
operated under conditions that cause the junction temperature
to exceed this value.

Table 24. Thermal and Supply Considerations (External MOSFET Not Connected)

Parameter Description 32-Lead LFCSP 28-Lead TSSOP

Maximum

Power
Dissipation

Maximum

Ambient
Temperature

Supply
Voltage

Maximum permitted power
dissipation when operating at an
ambient temperature of 105°C

Maximum permitted ambient
temperature when operating from a
supply of 52 V while regulating a loop
current of 22.8 mA

when operating at an ambient
temperature of 105°C while regulating
a loop current of 22.8 mA

SET

Figure 52. Maximum Supply Voltage vs. Ambient Temperature

40

105125=−

mW500

AMAXJ

θ

=

JA

Rev. E | Page 33 of 36

AD5421 Data Sheet

COMPLI ANT TO JEDEC STANDARDS MO-220-W HHD.

1

0.50

BSC

3.50 REF

BOTTOM VIEWTOP VIEW

PIN 1

INDICATOR

32

9

16

17

24

25

8

EXPOSED

PAD

PIN 1
INDICATOR

3.65

3.50 SQ

3.45

SEATING

PLANE

0.05 MAX

0.02 NOM

0.20 REF

COPLANARITY

0.08

0.30

0.25

0.18

5.10

5.00 SQ

4.90

0.80

0.75

0.70

FOR PROP E R CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CO NFIGURATI ON AND
FUNCTIO N DE S CRIPTIONS
SECTION OF THIS DATA SHEET.

0.50

0.40

0.30

0.25 MIN

04-02-2012-A

COMPLIANT TO JEDEC STANDARD

S MO-153-AET

05-08-2006-A

28

15

14

1

EXPOSED

PAD

(Pins Up)

9.80

9.70

9.

60

4.50

4.40

4.30

6.

40

BSC

3.05

3.00
2

.95

5.55

5.

50

5.45

FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.

PIN 1

INDICATOR

BOTTOMVIEW

TOP VIEW

1.20 MAX

SEATING

PLANE

0.65 BSC

0.30

0.19

0.15 MAX

0.05 MIN
COPLANARITY

0.10

1.05

1.00

0.80

0.20

0.09

0.25

8°
0°

0.75

0.60

0.45

OUTLINE DIMENSIONS

Figure 53. 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ]

5 mm × 5 mm Body, Very Very Thin Quad

(CP-32-11)

Dimensions shown in millimeters

Figure 54. 28-Lead Thin Shrink Small Outline Package, Exposed Pad [TSSOP_EP]

(RE-28-2)

Dimensions shown in millimeters

Rev. E | Page 34 of 36

Data Sheet AD5421

Model1

Temperature Range

Package Description

Package Option

ORDERING GUIDE

AD5421ACPZ-REEL7 −40°C to +105°C 32-Lead LFCSP_WQ CP-32-11
AD5421BCPZ-REEL7 −40°C to +105°C 32-Lead LFCSP_WQ CP-32-11
AD5421BREZ −40°C to +105°C 28-Lead TSSOP_EP RE-28-2
AD5421BREZ-REEL −40°C to +105°C 28-Lead TSSOP_EP RE-28-2
AD5421BREZ-REEL7 −40°C to +105°C 28-Lead TSSOP_EP RE-28-2
AD5421CREZ −40°C to +105°C 28-Lead TSSOP_EP RE-28-2
AD5421CREZ-RL −40°C to +105°C 28-Lead TSSOP_EP RE-28-2
AD5421CREZ-RL7 −40°C to +105°C 28-Lead TSSOP_EP RE-28-2
EVAL-AD5421SDZ Evaluation Board

1

Z = RoHS Compliant Part.

Rev. E | Page 35 of 36

AD5421 Data Sheet

©2011–2012 Analog Devices, Inc. All rights reserved. Trademarks and

NOTES

registered trademarks are the property of their respective owners.
D09128-0-7/12(E)

Rev. E | Page 36 of 36