ANALOG DEVICES AD5420 Service Manual

Single-Channel, 12-/16-Bit, Serial Input,

R

FEATURES

12-/16-bit resolution and monotonicity Current output ranges: 4 mA to 20 mA, 0 mA to 20 mA, or

0 mA to 24 mA ±0.01% FSR typical total unadjusted error (TUE)

±3 ppm/°C typical output drift Flexible serial digital interface On-chip output fault detection On-chip reference (10 ppm/°C maximum) Asynchronous clear function Power supply (AV

10.8 V to 40 V; AD5410AREZ/AD5420AREZ

10.8 V to 60 V; AD5410ACPZ/AD5420ACPZ Output loop compliance to AV Temperature range: −40°C to +85°C 24-lead TSSOP and 40-Lead LFCSP packages

APPLICATIONS

Process control Actuator control PLC

) range

DD

− 2.5 V

DD

4 mA to 20 mA, Current Source DAC

AD5410/AD5420

GENERAL DESCRIPTION

The AD5410/AD5420 are low cost, precision, fully integrated 12-/16-bit converters offering a programmable current source output designed to meet the requirements of industrial process control applications. The output current range is programmable at 4 mA to 20 mA, 0 mA to 20 mA, or an overrange function of 0 mA to 24 mA. The output is open-circuit protected. The device operates with a power supply (AV to 60 V. Output loop compliance is 0 V to AV

The flexible serial interface is SPI, MICROWIRE™, QSPI™, and DSP compatible and can be operated in 3-wire mode to minimize the digital isolation required in isolated applications.

The device also includes a power-on reset function, ensuring that the device powers up in a known state, and an asynchronous CLEAR pin that sets the output to the low end of the selected current range.

The total unadjusted error is typically ±0.01% FSR.

) range from 10.8 V

DD

− 2.5 V.

DD

FUNCTIONAL BLOCK DIAGRAM

DV

CC

SELECT

DV

CC

CAP1

CAP2

AD5410/AD5420

CLEA

LATCH

SCLK

SDIN

SDO

INPUT SHIFT

REGISTER

AND CONTROL

LOGIC

POWER-

ON

RESET

12/16

VREF

12-/16-BIT

DAC

REFIN

Figure 1.

R2 R3

R

SET

AV

DD

R3

SENSE

BOOST

I

OUT

FAULT

R

SET

GNDREFOUT

07027-001

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

AD5410/AD5420

REVISION HISTORY

2/10—Rev. A to Rev. B

Changes to Figure 46 ..................................................................... 23

8/09—Rev. 0 to Rev. A

Changes to Features and General Description ............................ 1

Changes to Table 1 ............................................................................ 3

Changes to Table 2 ............................................................................ 5

Changes to Introduction to Table 4 and to Table 4 ...................... 7

Added Figure 6, Changes to Figure 5 and Table 5 ........................ 8

Added Feedback/Monitoring of Output Current Section, Including Figure 45 to Figure 47; Renumbered Subsequent

Figures .............................................................................................. 23

Changes to Thermal and Supply Considerations Section and

Table 21 ............................................................................................ 26

Updated Outline Dimensions ....................................................... 28

Changes to Ordering Guide .......................................................... 28

3/09—Revision 0: Initial Version

Rev. B | Page 2 of 28

AD5410/AD5420

SPECIFICATIONS

AVDD = 10.8 V to 26.4 V, GND = 0 V, REFIN = 5 V external; DVCC = 2.7 V to 5.5 V, R unless otherwise noted.

Table 1.

Parameter1 Min Typ Max Unit Test Conditions/Comments

OUTPUT CURRENT RANGES 0 24 mA

0 20 mA 4 20 mA

ACCURACY, INTERNAL R

Resolution 16 Bits AD5420 12 Bits AD5410 Total Unadjusted Error (TUE) −0.3 +0.3 % FSR AD5420

−0.13 ±0.08 +0.13 % FSR AD5420, TA = 25°C

−0.5 +0.5 % FSR AD5410

−0.3 ±0.15 +0.3 % FSR AD5410, TA = 25°C

Relative Accuracy (INL)2 −0.024 +0.024 % FSR AD5420

−0.032 +0.032 % FSR AD5410

Differential Nonlinearity (DNL) −1 +1 LSB Guaranteed monotonic Offset Error −0.27 +0.27 % FSR

−0.12 ±0.08 +0.12 % FSR TA = 25°C

Offset Error Temperature Coefficient (TC)3 ±16 ppm FSR/°C Gain Error −0.18 +0.18 % FSR AD5420

−0.03 ±0.006 +0.03 % FSR AD5420, TA = 25°C

−0.22 +0.22 AD5410

−0.06 ±0.012 +0.06 AD5410, TA = 25°C

Gain Error Temperature Coefficient (TC)3 Full-Scale Error −0.2 +0.2 % FSR

−0.1 ±0.08 +0.1 % FSR TA = 25°C

Full-Scale Error Temperature Coefficient (TC)3

ACCURACY, EXTERNAL R

Resolution 16 Bits AD5420 12 Bits AD5410 Total Unadjusted Error (TUE) −0.15 +0.15 % FSR AD5420

−0.06 ±0.01 +0.06 % FSR AD5420, TA = 25°C

−0.3 +0.3 % FSR AD5410

−0.1 ±0.02 +0.1 % FSR

Relative Accuracy (INL)2

−0.032 +0.032 % FSR AD5410

Differential Nonlinearity (DNL) −1 +1 LSB Guaranteed monotonic Offset Error −0.1 +0.1 % FSR

−0.03 ±0.006 +0.03 % FSR TA = 25°C

Offset Error Temperature Coefficient (TC)3 Gain Error −0.08 +0.08 % FSR

−0.05 ±0.003 +0.05 % FSR TA = 25°C

Gain Error Temperature Coefficient (TC)3 Full-Scale Error −0.15 +0.15 % FSR

−0.06 ±0.01 +0.06 % FSR TA = 25°C

Full-Scale Error Temperature Coefficient (TC)3

OUTPUT CHARACTERISTICS3

Current Loop Compliance Voltage 0 AVDD − 2.5 V Output Current Drift vs. Time 50 ppm FSR Internal R 20 ppm FSR External R Resistive Load 1200 Ω Inductive Load 50 mH TA = 25°C DC Power Supply Rejection Ratio (PSRR) 1 μA/V

SET

±10 ppm FSR/°C

±12 ppm FSR/°C

Assumes an ideal 15 kΩ resistor

SET

−0.012 +0.012 % FSR AD5420

±3 ppm FSR/°C

±4 ppm FSR/°C

±7 ppm FSR/°C

Rev. B | Page 3 of 28

= 300 Ω; all specifications T

LOAD

AD5410, T

A

SET

MIN

to T

MAX

,

= 25°C

, drift after 1000 hours at 125°C

AD5410/AD5420

Parameter1 Min Typ Max Unit Test Conditions/Comments

Output Impedance 50 MΩ Output Current Leakage 60 pA Output disabled R3 Resistor Value 36 40 44 Ω TA = 25°C R3 Resistor Temperature Coefficient (TC) 30 ppm/°C I

Current 399 444 489 μA

BIAS

I

Current Temperature Coefficient (TC) 30 ppm/°C

BIAS

REFERENCE INPUT/OUTPUT

Reference Input3

Reference Input Voltage 4.95 5 5.05 V For specified performance DC Input Impedance 25 30 kΩ

Reference Output

Output Voltage 4.995 5.000 5.005 V TA = 25°C Reference TC

3, 4

Output Noise (0.1 Hz to 10 Hz)3 Noise Spectral Density3 Output Voltage Drift vs. Time3 Capacitive Load3 Load Current3 Short-Circuit Current3 Load Regulation3

DIGITAL INPUTS3

Input High Voltage, VIH 2 V Input Low Voltage, VIL 0.8 V Input Current −1 +1 μA Per pin Pin Capacitance 10 pF Per pin

DIGITAL OUTPUTS3

SDO

Output Low Voltage, VOL 0.4 V Sinking 200 μA Output High Voltage, VOH DVCC − 0.5 V Sourcing 200 μA High Impedance Leakage Current −1 +1 μA High Impedance Output Capacitance 5 pF

FAULT

Output Low Voltage, VOL 0.4 V 10 kΩ pull-up resistor to DVCC Output Low Voltage, VOL 0.6 V 2.5 mA load current Output High Voltage, VOH 3.6 V 10 kΩ pull-up resistor to DVCC

POWER REQUIREMENTS

AVDD 10.8 40 V TSSOP package

10.8 60 V LFCSP package DVCC

Input Voltage 2.7 5.5 V Internal supply disabled Output Voltage 4.5 V DVCC can be overdriven up to 5.5 V Output Load Current3 Short-Circuit Current3

AIDD 3 mA Output disabled 4 mA Output enabled DICC 1 mA VIH = DVCC, VIL = GND Power Dissipation 144 mW AVDD = 40 V, I 50 mW AVDD = 15 V, I

1

Temperature range: −40°C to +85°C; typical at +25°C.

2

For 0 mA to 20 mA and 0 mA to 24 mA ranges, INL is measured from Code 256 for the AD5420 and Code 16 for the AD5410.

3

Guaranteed by design and characterization but not production tested.

4

The on-chip reference is production trimmed and tested at 25°C and 85°C. It is characterized from −40°C to +85°C.

1.8 10 ppm/°C 18 μV p-p 100 nV/√Hz @ 10 kHz 50 ppm Drift after 1000 hours, T 600 nF 5 mA 7 mA 95 ppm/mA JEDEC compliant

5 mA 20 mA

= 0 mA

OUT

= 0 mA

OUT

= 125°C

A

Rev. B | Page 4 of 28

AD5410/AD5420

AC PERFORMANCE CHARACTERISTICS

AVDD = 10.8 V to 26.4 V, GND = 0 V, REFIN = 5 V external; DVCC = 2.7 V to 5.5 V, R otherwise noted.

Table 2.

Parameter1 Min Typ Max Unit Test Conditions/Comments

DYNAMIC PERFORMANCE

Output Current Settling Time2 10 μs 16 mA step, to 0.1% FSR

40 μs 16 mA step, to 0.1% FSR, L = 1 mH

AC PSRR −75 dB 200 mV, 50 Hz/60 Hz sine wave superimposed on power supply voltage

1

Guaranteed by design and characterization; not production tested.

2

Digital slew rate control feature disabled and CAP1 = CAP2 = open circuit.

TIMING CHARACTERISTICS

AVDD = 10.8 V to 26.4 V, GND = 0 V, REFIN = 5 V external; DVCC = 2.7 V to 5.5 V, R otherwise noted.

Table 3.

Parameter

WRITE MODE

t1 33 ns min SCLK cycle time t2 13 ns min SCLK low time t3 13 ns min SCLK high time t4 13 ns min LATCH delay time t5 40 ns min LATCH high time t5 5 μs min LATCH high time after a write to the control register t6 5 ns min Data setup time t7 5 ns min Data hold time t8 40 ns min LATCH low time t9 20 ns min CLEAR pulse width t10 5 μs max CLEAR activation time

READBACK MODE

t11 90 ns min SCLK cycle time t12 40 ns min SCLK low time t13 40 ns min SCLK high time t14 13 ns min LATCH delay time t15 40 ns min LATCH high time t16 5 ns min Data setup time t17 5 ns min Data hold time t18 40 ns min LATCH low time t19 35 ns max Serial output delay time (C t20 35 ns max LATCH rising edge to SDO tristate

DAISY-CHAIN MODE

t21 90 ns min SCLK cycle time t22 40 ns min SCLK low time t23 40 ns min SCLK high time t24 13 ns min LATCH delay time t25 40 ns min LATCH high time t26 5 ns min Data setup time t27 5 ns min Data hold time t28 40 ns min LATCH low time t29 35 ns max Serial output delay time (C

1

Guaranteed by characterization but not production tested.

2

All input signals are specified with tR = tF = 5 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V.

3

See Figure 2, Figure 3, and Figure 4.

4

C

LSDO

1, 2, 3

Limit at T

= capacitive load on SDO output.

, T

Unit Description

MIN

MAX

= 300 Ω; all specifications T

LOAD

= 300 Ω; all specifications T

LOAD

= 50 pF)4

L SDO

= 50 pF)4

L SDO

MIN

to T

MAX

, unless

Rev. B | Page 5 of 28

AD5410/AD5420

SCLK

t

2

LATCH

t

7

t

9

t

10

SDIN

CLEAR

I

OUT

t

DB23

6

t

1

2421

t

3

DB0

t

4

5

t

8

07027-002

Figure 2. Write Mode Timing Diagram

t

11

SCLK

2421

t

12

t

13

t

14

15

2

1

923

8

22

24

LATCH

t

18

DB0DB23

DB23

FIRST 8 BITS ARE DON’T CARE BITS

NOP CONDITION

DB15XXXX

t

19

SELECTED REGISTER DATA CLOCKED OUT

DB0

t

20

07027-003

SDIN

SDO

t

16

INPUT WORD SPECIFIES REGISTE R T O BE READ

UNDEFINED DATA

t

17

Figure 3. Readback Mode Timing Diagram

t

21

DB0

4826

t

24

25

t

28

07027-004

SCLK

LATCH

SDIN

SDO

DB23

INPUT WORD FOR DAC N

UNDEFINED

t

DB0

29

DB0

25

2421

t

26

DB23

INPUT W ORD FOR DAC N – 1

DB23

INPUT WORD FOR DAC N

22

t

23

t

27

Figure 4. Daisy-Chain Mode Timing Diagram

Rev. B | Page 6 of 28

AD5410/AD5420

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted. Transient currents of up to 80 mA do not cause SCR latch-up.

Table 4.

Parameter Rating

AVDD to GND −0.3 V to +60 V DVCC to GND −0.3 V to +7 V Digital Inputs to GND

Digital Outputs to GND

REFIN, REFOUT to GND −0.3 V to +7 V I

to GND −0.3 V to AVDD

OUT

Operating Temperature Range

Industrial −40°C to +85°C1 Storage Temperature Range −65°C to +150°C Junction Temperature (TJ max) 125°C 24-Lead TSSOP Package

Thermal Impedance, θJA 42°C/W

Thermal Impedance, θJC 9°C/W 40-Lead LFCSP Package

Thermal Impedance, θJA 28°C/W

Thermal Impedance, θJC 4°C/W Power Dissipation (TJ max − TA)/θJA Lead Temperature JEDEC industry standard

Soldering J-STD-020 ESD (Human Body Model) 2 kV

1

Power dissipated on chip must be derated to keep junction temperature

below 125°C. The assumption is that the maximum power dissipation condition is sourcing 24 mA into ground from AVDD with a 4 mA on-chip current.

−0.3 V to DV (whichever is less)

+ 0.3 V or +7 V

CC

+ 0.3 V or +7 V

CC

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

Rev. B | Page 7 of 28

AD5410/AD5420

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

GND

2

DV

CC

3

FAULT

4

GND

GND CLEAR LATCH

SCLK

SDIN

SDO GND GND

NOTES

1. NC = NO CONNEC T.

2. GROUND REF E RE NCE CONNECTION. IT IS RECOMMENDED THAT THE EXPOSED PAD BE THERMALLY CONNECTED TO A COPPER PLANE FOR ENHANCED THERMAL PERFORMANCE.

AD5410/

AD5420

5

TOP VIEW

6

(Not to Scale)

7 8

9

10 11

12

Figure 5. TSSOP Pin Configuration

24

23

22

21

20

19

18

17

16

15

14

13

AV

DD

NC CAP2 CAP1 BOOST I

OUT

R3

SENSE

NC DV

CC

REFIN REFOUT R

SET

SELECT

FAULT

NOTES

1. NC = NO CONNECT.

2. GROUND REFE RE NCE CONNECTION. IT IS RECO MMENDED THAT THE EXPOSED PAD BE THERMALLY CONNECTED TO A COPPER PLANE FOR

07027-005

ENHANCED THERMAL PE RFORMANCE.

CC

DD

NC 40

PIN 1

1NC

INDICATOR

2 3GND 4GND

AD5410/AD5420

5CLEAR 6LATCH 7SCLK 8SDIN 9SDO

10NC

1

1 NC

GND

NC

DV

37

38

39

TOP VIEW

(Not to Scale)

12

13

14

GND

C N

NC

AV

NC 32

31

33

34

35

36

18

19

20

15

17

16

C

NC

N

SET

GND

R

REFIN

REFOUT

Figure 6. LFCSP Pin Configuration

30 NC 29 CAP2 28 CAP1 27 BOOST

I

26

OUT

25

R3

SENSE

24

NC

23 DV

CC

22

NC

21 NC

SELECT

07027-053

Table 5. Pin Function Descriptions

TSSOP Pin No. LFCSP Pin No. Mnemonic Description

1, 4, 5, 12 3, 4, 14, 15, 37 GND These pins must be connected to ground. 2 39 DVCC Digital Supply Pin. Voltage ranges from 2.7 V to 5.5 V. 3 2

Fault Alert. This pin is asserted low when an open circuit is detected between I

FAU LT

GND or an overtemperature is detected. The FAULT pin is an open-drain output and must be connected to DV

6 5 CLEAR

Active High Input. Asserting this pin sets the output current to the zero-scale value,

through a pull-up resistor (typically 10 kΩ).

CC

which is either 0 mA or 4 mA, depending on the output range programmed, that is, 0 mA to 20 mA, 0 mA to 24 mA, or 4 mA to 20 mA.

7 6 LATCH

Positive Edge Sensitive Latch. A rising edge parallel loads the input shift register data into the relevant register. In the case of the data register, the output current is also updated.

8 7 SCLK

Serial Clock Input. Data is clocked into the input shift register on the rising edge of

SCLK. This operates at clock speeds of up to 30 MHz. 9 8 SDIN Serial Data Input. Data must be valid on the rising edge of SCLK. 10 9 SDO

Serial Data Output. This pin is used to clock data from the device in daisy-chain or

readback mode. Data is clocked out on the falling edge of SCLK. See Figure 3 and

Figure 4. 11 12, 13 GND Ground Reference Pin. 13 16 R

SET

An external, precision, low drift 15 kΩ current setting resistor can be connected to this

pin to improve the overall performance of the device. See the Specifications and

AD5410/AD5420 Features sections. 14 17 REFOUT

Internal Reference Voltage Output. V

= 5 V ± 5 mV at TA = 25°C. Typical temperature

REFOUT

drift is 1.8 ppm/°C. 15 18 REFIN External Reference Voltage Input. V 16 23

DV

CC

SELECT

This pin, when connected to GND, disables the internal supply, and an external supply

must be connected to the DV

CC

= 5 V ± 50 mV for specified performance.

REFIN

pin. Leave this pin unconnected to enable the internal

supply. See the AD5410/AD5420 Features section. 17, 23

1, 10, 11, 19, 20,

NC Do not connect to these pins. 21, 22, 24, 30, 31, 32, 33, 34, 35, 38, 40

OUT

and

Rev. B | Page 8 of 28

AD5410/AD5420

TSSOP Pin No. LFCSP Pin No. Mnemonic Description

18 25 R3

19 26 I 20 27 BOOST

21 28 CAP1

22 29 CAP2

24 36 AVDD Positive Analog Supply Pin. Voltage ranges from 10.8 V to 40 V. 25 (EPAD) 41 (EPAD)

SENSE

The voltage measured between this pin and the BOOST pin is directly proportional to the output current and can be used as a monitor/feedback feature. This should be used as a voltage sense output only; current should not be sourced from this pin. See the AD5410/AD5420 Features section.

Current Output Pin.

OUT

Optional External Transistor Connection. Connecting an external transistor reduces the power dissipated in the AD5410/AD5420. See the AD5410/AD5420 Features section.

Connection for Optional Output Filtering Capacitor. See the AD5410/AD5420 Features section.

Exposed pad

Ground Reference Connection. It is recommended that the exposed pad be thermally connected to a copper plane for enhanced thermal performance.

Rev. B | Page 9 of 28

ANALOG DEVICES AD5420 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

AC PERFORMANCE CHARACTERISTICS

TIMING CHARACTERISTICS

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS