ANALOG DEVICES AD5412 Service Manual

Single Channel, 12-Bit, Serial Input,

www.BDTIC.com/ADI

Preliminary Technical Data

FEATURES

12-Bit Resolution and Monotonicity
Current Output Ranges: 4–20mA, 0–20mA or 0–24mA

0.1% Total Unadjusted Error (TUE)

5ppm/°C Output Drift
Voltage Output Ranges: 0-5V, 0-10V, ±5V, ±10V,
10% over-range

0.05% Total Unadjusted Error (TUE)

3ppm/°C Output Drift
Flexible Serial Digital Interface
On-Chip Output Fault Detection
On-Chip Reference (10 ppm/°C Max)
Asynchronous CLEAR Function
Power Supply Range

AV

: 10.8V to 40 V

DD

AV

: -26.4V to -3V/0V

SS

Output Loop Compliance to AV
Temperature Range: -40°C to +85°C
TSSOP and LFCSP Packages

APPLICATIONS

Process Control
Actuator Control
PLC

– 2.5 V

DD

Current Source & Voltage Output DAC

AD5412

GENERAL DESCRIPTION

The AD5412 is a low-cost, precision, fully integrated 12-bit
converter offering a programmable current source and
programmable voltage output designed to meet the
requirements of industrial process control applications.
The output current range is programmable to 4mA to 20 mA,
0mA to 20mA or an overrange function of 0mA to 24mA.
Voltage output is provided from a separate pin that can be
configured to provide 0V to 5V, 0V to 10V, ±5V or ±10V
output ranges, an over-range of 10% is available on all ranges.
Analog outputs are short and open circuit protected and can
drive capacitive loads of 1uF and inductive loads of 1H.
The device is specified to operate with a power supply range
from 10.8 V to 40 V. Output loop compliance is 0 V to AV

2.5 V.
The flexible serial interface is SPI
compatible and can be operated in 3-wire mode to minimize the
digital isolation required in isolated applications.
The device also includes a power-on-reset function ensuring
that the device powers up in a known state and an
asynchronous CLEAR pin which sets the outputs to zero-scale /
mid-scale voltage output or the low end of the selected current
range.
The total output error is typically ±0.1% in current mode and
±0.05% in voltage mode.

Table 1. Related Devices

Part Number Description

AD5422

AD5420

AD5410

and MICROWIRE

Single Channel, 16-Bit, Serial
Input Current Source and
Voltage Output DAC

Single Channel, 16-Bit, Serial
Input Current Source DAC

Single Channel, 12-Bit, Serial
Input Current Source DAC

DD

–

Rev. PrC

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2007 Analog Devices, Inc. All rights reserved.

AD5412 Preliminary Technical Data

www.BDTIC.com/ADI

TABLE OF CONTENTS

Features.............................................................................................. 1

Applications....................................................................................... 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Functional Block Diagram .............................................................. 3

Specifications..................................................................................... 4

AC Performance Characteristics ................................................ 7

Timing Characteristics ................................................................ 8

Absolute Maximum Ratings.......................................................... 10

ESD Caution................................................................................ 10

Pin Configuration and Function Descriptions........................... 11

Typical Performance Characteristics Voltage output............... 13

Typical Performance Characteristics current output............... 17

Typical Performance Characteristics general ............................20

Terminology .................................................................................... 22

Theory of Operation ...................................................................... 24

Architecture................................................................................. 24

Serial Interface ............................................................................ 24

Default configuration................................................................. 28

Transfer Function....................................................................... 28

Data Register............................................................................... 29

Control Register.......................................................................... 29

RESET register............................................................................ 29

Status register.............................................................................. 30

Features............................................................................................ 31

fault alert...................................................................................... 31

voltage output short circuit protection.................................... 31

Asynchronous Clear (CLEAR)................................................. 31

Internal Reference...................................................................... 31

External current setting resistor............................................... 31

Voltage ouTput over-range........................................................ 31

Digital Power Supply.................................................................. 31

External boost function............................................................. 31

digital Slew rate control............................................................. 32

I

Filtering Capacitors............................................................ 32

OUT

Applications Information.............................................................. 33

driving inductive loads.............................................................. 33

Transient voltage protection ..................................................... 33

Layout Guidelines....................................................................... 33

Galvanically Isolated Interface ................................................. 33

Microprocessor Interfacing....................................................... 33

Thermal and supply considerations......................................... 34

Outline Dimensions....................................................................... 35

Ordering Guide .......................................................................... 35

REVISION HISTORY

PrC – Preliminary Version. October 9, 2007

Rev. PrC | Page 2 of 37

Preliminary Technical Data AD5412

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FUNCTIONAL BLOCK DIAGRAM

DV

CC

SELECT

DV

CC

CAP1

CAP2

AV

SS

AV

DD

CLEAR
SELECT

CLEAR

LATCH

SCLK

SDIN

SDO

AD5412

INPUT SHIFT

POWER

ON

RESET

DGND*

*LFCSP Package

REGISTER

AND

CONTROL

LOGIC

VREF

REFOUT

R2

12

12-BIT

/

DAC

R1

RANGE
SCALING

REFIN

Figure 1.

AGND

C

COMP2

C

COMP1

R3

BOOST

I

OUT

FAULT

R

SET

+V

SENSE

V

OUT

-V

SENSE

Rev. PrC | Page 3 of 37

AD5412 Preliminary Technical Data

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SPECIFICATIONS

AVDD = 10.8V to 40V, AVSS = -26.4V to -3V/0V, AVDD + |AVSS| < 52.8V, AGND = DGND = 0 V, REFIN= +5 V external;
DV

= 2.7 V to 5.5 V, V

CC

all specifications T

Table 2.

Parameter Value1 Unit Test Conditions/Comments
VOLTAGE OUTPUT

Output Voltage Ranges 0 to 5 V

0 to 10 V

-5 to +5 V

-10 to +10 V

ACCURACY Output unloaded

Bipolar Output

Resolution 12 Bits
Total Unadjusted Error (TUE) 0.1 % FSR max

TUE TC2 ±3 ppm typ

Relative Accuracy (INL) ±0.012 % FSR max
Differential Nonlinearity (DNL) ±1 LSB max Guaranteed monotonic
Bipolar Zero Error ±5 mV max

Bipolar Zero TC2 ±3 ppm FSR/°C max
Zero-Scale Error ±1 mV max

Zero-Scale TC2 ±3 ppm FSR/°C max
Gain Error ±0.05 % FSR max

Gain TC2 ±8 ppm FSR/°C max
Full-Scale Error 0.05 % FSR max

Full-Scale TC2 ±3 ppm FSR/°C max

Unipolar Output AVSS = 0 V

Resolution 12 Bits
Total Unadjusted Error (TUE) 0.1 % FSR max

Relative Accuracy (INL) ±0.012 % FSR max
Differential Nonlinearity (DNL) ±1 LSB max Guaranteed monotonic
Zero Scale Error +10 mV max

Zero Scale TC2 ±3 ppm FSR/°C max
Offset Error ±10 mV max
Gain Error ±0.05 % FSR max

Gain TC2 ±3 ppm FSR/°C max
Full-Scale Error 0.05 % FSR max

Full-Scale TC2 ±3 ppm FSR/°C max

OUTPUT CHARACTERISTICS2

Headroom 0.8 V max

0.5 V typ

Output Voltage TC ±3 ppm FSR/°C max

Output Voltage Drift vs. Time ±12 ppm FSR/500 hr typ Vout = ¾ of Full-Scale

±15 ppm FSR/1000 hr typ

Short-Circuit Current 12 mA typ

MIN

: RL = 2 kΩ, CL = 200 pF, I

OUT

to T

, ±10 V / 0 to 24 mA range unless otherwise noted.

MAX

: RL = 300Ω, HL = 50mH;

OUT

Rev. PrC | Page 4 of 37

Over temperature, supplies, and time, typically 0.05%
FSR

@ 25°C, error at other temperatures obtained using
bipolar zero TC

@ 25°C, error at other temperatures obtained using zero
scale TC

@ 25°C, error at other temperatures obtained using gain
TC

@ 25°C, error at other temperatures obtained using gain
TC

Over temperature, supplies, and time, typically 0.05%
FSR

@ 25°C, error at other temperatures obtained using gain
TC

@ 25°C, error at other temperatures obtained using gain
TC

@ 25°C, error at other temperatures obtained using gain
TC

Preliminary Technical Data AD5412

www.BDTIC.com/ADI

Parameter Value1 Unit Test Conditions/Comments

Load 2 kΩ min For specified performance
Capacitive Load Stability

RL = ∞ 20 nF max
RL = 2 kΩ TBD nF max

RL = ∞ 1 µF max External compensation capacitor of 4nF connected.
DC Output Impedance 0.3 Ω typ
Power-On Time 10 µs typ
DC PSRR TBD µV/V

CURRENT OUTPUT

Output Current Ranges 0 to 24 mA

0 to 20 mA

4 to 20 mA

ACCURACY

Resolution 12 Bits
Total Unadjusted Error (TUE) ±0.3 % FSR max Over temperature, supplies, and time, typically 0.1% FSR
TUE TC2 ±5 ppm/°C typ
Relative Accuracy (INL) ±0.012 % FSR max
Differential Nonlinearity (DNL) ±1 LSB max Guaranteed monotonic
Offset Error ±0.05 % FSR max
Offset Error Drift ±5 µv/°C typ
Gain Error ±0.02 % FSR max

Gain TC2 ±8 ppm FSR/°C max
Full-Scale Error 0.05 % FSR max

Full-Scale TC2 ±8 ppm FSR/°C

OUTPUT CHARACTERISTICS2

Current Loop Compliance Voltage AVDD - 2.5 V max
Output Current Drift vs. Time TBD ppm FSR/500 hr typ
TBD ppm FSR/1000 hr typ
Resistive Load TBD Ω max
Inductive Load 1 H max
DC PSRR 10 µA/V max
Output Impedance 50 MΩ typ

REFERENCE INPUT/OUTPUT

Reference Input2

Reference Input Voltage 5 V nom ±1% for specified performance

DC Input Impedance 30 kΩ min Typically 40 kΩ

Reference Range 4 to 5 V min to V max
Reference Output

Output Voltage 4.998 to 5.002 V min to V max @ 25°C

Reference TC ±10 ppm/°C max

Output Noise (0.1 Hz to 10 Hz)2 18 µV p-p typ

Noise Spectral Density2 120 nV/√Hz typ @ 10 kHz

Output Voltage Drift vs. Time2 ±40 ppm/500 hr typ

±50 ppm/1000 hr typ

Capacitive Load TBD nF max

Load Current 5 mA typ

Short Circuit Current 7 mA typ

Line Regulation2 10 ppm/V typ

Load Regulation2 TBD ppm/mA

Thermal Hysteresis2 TBD ppm

@ 25°C, error at other temperatures obtained using gain
TC

@ 25°C, error at other temperatures obtained using gain
TC

Rev. PrC | Page 5 of 37

AD5412 Preliminary Technical Data

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Parameter Value1 Unit Test Conditions/Comments
DIGITAL INPUTS2

VIH, Input High Voltage 2 V min
VIL, Input Low Voltage 0.8 V max
Input Current ±1 µA max Per pin
Pin Capacitance 10 pF typ Per pin

DIGITAL OUTPUTS 2

SDO

VOL, Output Low Voltage 0.4 V max sinking 200 µA
VOH, Output High Voltage DVCC − 0.5 V min sourcing 200 µA
High Impedance Leakage

Current
High Impedance Output

Capacitance

FAU LT

VOL, Output Low Voltage 0.4 V max
VOL, Output Low Voltage 0.6 V typ @ 2.5 mA

VOH, Output High Voltage 3.6 V min

POWER REQUIREMENTS

AVDD 10.8 to 40 V min to V max
AVSS -26.4 to 0 V min to V max
DVCC

Input Voltage 2.7 to 5.5 V min to V max Internal supply disabled
Output Voltage 4.5 V typ DVCC can be overdriven up to 5.5V
Output Load Current 5 mA typ

Short Circuit Current 20 mA typ
AIDD TBD mA Output unloaded
AISS TBD mA Output unloaded
DICC 1 mA max VIH = DVCC, VIL = GND, TBD mA typ
Power Dissipation TBD mW typ AVDD = 40V, AVSS = 0 V, V
TBD mW typ AVDD = 40V, AVSS = -15 V, V
TBD mW typ AVDD = 15V, AVSS = -15 V, V

1

Temperature range: -40°C to +85°C; typical at +25°C.

2

Guaranteed by characterization. Not production tested.

DVCC = 2.7 V to 5.5 V, JEDEC compliant

±1 µA max

5

pF typ

10kΩ pull-up resistor to DV

10kΩ pull-up resistor to DV

OUT

CC

CC

unloaded

unloaded

OUT

unloaded

OUT

Rev. PrC | Page 6 of 37

Preliminary Technical Data AD5412

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AC PERFORMANCE CHARACTERISTICS

AVDD = 10.8V to 40V, AVSS = -26.4V to -3V/0V, AVDD + |AVSS| < 52.8V, AGND = DGND = 0 V, REFIN= +5 V external;
DV

= 2.7 V to 5.5 V, V

CC

all specifications T

Table 3.

Parameter1 Unit Test Conditions/Comments

DYNAMIC PERFORMANCE

VOLTAGE OUTPUT

Output Voltage Settling Time 8 µs typ Full-scale step (10 V) to ±0.03% FSR
10 µs max
5 µs max 512 LSB step settling

Output Current Settling Time 10 µs max To 0.1% FSR

Slew Rate 1 V/µs typ
Power-On Glitch Energy 10 nV-sec typ
Digital-to-Analog Glitch Energy 10 nV-sec typ
Glitch Impulse Peak Amplitude 20 mV typ
Digital Feedthrough 1 nV-sec typ
Output Noise (0.1 Hz to 10 Hz Bandwidth) 0.1 LSB p-p typ
Output Noise (100 kHz Bandwidth) 80 µV rms max
1/f Corner Frequency 1 kHz typ
Output Noise Spectral Density 100 nV/√Hz typ Measured at 10 kHz
AC PSRR TBD dB

CURRENT OUTPUT

Output Current Settling Time TBD µs typ To 0.1% FSR , L = 1H

TBD µs typ To 0.1% FSR , L < 1mH

1

Guaranteed by characterization, not production tested.

MIN

: RL = 2 kΩ, CL = 200 pF, I

OUT

to T

, ±10 V / 0 to 24 mA range unless otherwise noted.

MAX

: RL = 300Ω, HL = 50mH;

OUT

200mV 50/60Hz Sinewave
superimposed on power supply voltage.

Rev. PrC | Page 7 of 37

AD5412 Preliminary Technical Data

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TIMING CHARACTERISTICS

AVDD = 10.8V to 40V, AVSS = -26.4V to -3V/0V, AVDD + |AVSS| < 52.8V, AGND = DGND = 0 V, REFIN= +5 V external;
DV

= 2.7 V to 5.5 V, V

CC

all specifications T

MIN

: RL = 2 kΩ, CL = 200 pF, I

OUT

to T

, ±10 V / 0 to 24 mA range unless otherwise noted.

MAX

: RL = 300Ω, HL = 50mH;

OUT

Table 4.

Parameter
Write Mode

1, 2, 3

Limit at T

, T

MIN

Unit Description

MAX

t1 33 ns min SCLK cycle time
t2 13 ns min SCLK low time
t3 13 ns min SCLK high time
t4 13 ns min LATCH delay time
t5 40 ns min LATCH high time
t5 5 µs min LATCH high time (After a write to the CONTROL register)
t6 5 ns min Data setup time
t7 5 ns min Data hold time
t8 40 ns min LATCH low time
t9 20 ns min CLEAR pulsewidth
t10 5 µs max CLEAR activation time

Readback Mode

t11 82 ns min SCLK cycle time
t12 33 ns min SCLK low time
t13 33 ns min SCLK high time
t14 13 ns min LATCH delay time
t15 40 ns min LATCH high time
t16 5 ns min Data setup time
t17 5 ns min Data hold time
t18 40 ns min LATCH low time
t19 40 ns max Serial output delay time (C

L SDO

4

= 15pF)

t20 33 ns max LATCH rising edge to SDO tri-state

Daisychain Mode

t21 82 ns min SCLK cycle time
t22 33 ns min SCLK low time
t23 33 ns min SCLK high time
t24 13 ns min LATCH delay time
t25 40 ns min LATCH high time
t26 5 ns min Data setup time
t27 5 ns min Data hold time
t28 40 ns min LATCH low time
t29 40 ns max Serial output delay time (C

L SDO

4

= 15pF)

1

Guaranteed by characterization. Not production tested.

2

All input signals are specified with tR = tF = 5 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V.

3

See Figure 2, Figure 3, and Figure 4.

4

C

= Capacitive load on SDO output.

L SDO

Rev. PrC | Page 8 of 37

Preliminary Technical Data AD5412

www.BDTIC.com/ADI

t

1

SCLK

SCLK

LATCH

SDIN

CLEAR

OUTPUT

t

12

2421

t

3

DB0

t

t

8

t

4

5

t

6

DB23

t

2

t

7

t

9

t

10

Figure 2. Write Mode Timing Diagram

t

11

2

2421

t

13

t

t

14

15

1

923

8

22

24

LATCH

SDIN

SDO

LATCH

SCLK

SDIN

t

16

DB23

t

17

INPUT WORD SPECIFIES
REGISTER TO BE READ

UNDEFINED DATA

DB23

INPUT WORD F OR DAC N

t

18

DB0

DB23

FIRST 8 BITS ARE
DON’T CARE B ITS

Figure 3. Readback Mode Timing Diagram

25

2421

t

26

DB0

DB23

t

29

NOP CONDITIO N

X

XXX

DB15

SELECTED REGISTER
DATA CLOCKED OUT

t

t

22

t

27

INPUT WO RD F O R DAC N-1

t

23

DB0

t

t

19

DB0

20

21

4826

DB0

t

24

t

28

t

25

SDO

DB23 DB0

UNDEFINED

DB23 DB0

INPUT WO RD FOR DAC N

Figure 4. Daisychain Mode Timing Diagram

Rev. PrC | Page 9 of 37

AD5412 Preliminary Technical Data

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ABSOLUTE MAXIMUM RATINGS

TA = 25°C unless otherwise noted.
Transient currents of up to 100 mA do not cause SCR latch-up.

Table 5.

Parameter Rating

AVDD to AGND, DGND −0.3V to 48V
AVSS to AGND, DGND +0.3 V to −48 V
AVDD to AVSS -0.3V to 60V
DVCC to AGND, DGND −0.3 V to +7 V
Digital Inputs to AGND, DGND

Digital Outputs to AGND, DGND

REFIN/REFOUT to AGND, DGND −0.3 V to +7 V
V

to AGND, DGND AVSS to AVDD

OUT

I

to AGND, DGND −0.3V to AVDD

OUT

AGND to DGND -0.3V to +0.3V
Operating Temperature Range

Industrial −40°C to +851°C
Storage Temperature Range −65°C to +150°C
Junction Temperature (TJ max) 125°C
24-Lead TSSOP Package

θJA Thermal Impedance 42°C/W
40-Lead LFCSP Package

θJA Thermal Impedance 28°C/W
Power Dissipation (TJ max – TA)/ θJA
Lead Temperature JEDEC Industry Standard

Soldering J-STD-020

−0.3 V to DV
(whichever is less)

−0.3 V to DV
(whichever is less)

+ 0.3 V or 7 V

CC

+ 0.3 V or 7V

CC

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

1

Power dissipated on chip must be de-rated to keep junction temperature

below 125°C. Assumption is max power dissipation condition is sourcing
24mA into Ground from AVDD with a 3mA on-chip current.

Rev. PrC | Page 10 of 37

Preliminary Technical Data AD5412

T

E

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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

AV
DV

FAULT

GND

CLEAR SELE CT

CLEAR

LATCH

SCLK

SDIN

SDO

AGND

GND

SS
CC

1
2

AD5422

3
4
5

TOP VIEW

6

(Not to Scale)

7
8

9
10
11
12

24
23
22
21
20
19
18
17
16
15
14
13

AV

DD

-V

SENSE

+V

SENSE

V

OUT

BOOST
I

OUT

C

COMP2

C

COMP1

DV

CC

REFIN
REFOUT
R

SET

SELEC

CLEAR SELECT

CC

NC

DV

NC

40 39 38 37 36 35 34 33 32 31

NC

1
2

FAULT

3

GND

4
5

CLEAR

6

LATCH

SCLK

7

SDIN

8
9

SDO

NC

10

11 12 13 14 15 16 17 18 19 20

NC

DGND

AGND

AVSSAVDDNC

AD5422

TOP VIEW

(Not to Scale)

SS

AV

SENS

SENSE

OUT

-V

NC

+V

V

30

NC

29

CAP2

28

CAP1

27

BOOST

26

I

OUT

25

C

COMP2

24

C

COMP1

23

CC

SELECT

DV

22

NC

21

NC

SET

R

GND

NC

NC

REFIN

REFOUT

Figure 5. TSSOP Pin Configuration Figure 6. LFCSP Pin Configuration

Table 6. Pin Function Descriptions

TSSOP Pin No. LFCSP Pin No. Mnemonic Description

1 14,37 AVSS

Negative Analog Supply Pin. Voltage ranges from –3 V to –24 V. This pin can be

connected to 0V if output voltage range is unipolar.
2 39 DVCC Digital Supply Pin. Voltage ranges from 2.7 V to 5.5 V.
3 2

FAU LT

Fault alert, This pin is asserted low when an open circuit is detected in current mode or

an over temperature is detected. Open drain output, must be connected to a pull-up

resistor.
4,12 3,15 GND These pins must be connected to 0V.
1,10,11,19,

NC No Connection.
20,21,22,30,
31,35,38,40

5 4

CLEAR

Selects the voltage output clear value, either zero-scale or mid-scale code. See Table 20

SELECT

6 5 CLEAR

Active High Input. Asserting this pin will set the current output to the bottom of the
selected range or will set the voltage output to the user selected value (zero-scale or
mid-scale).

7 6 LATCH

Positive edge sensitive latch, a rising edge will parallel load the input shift register data
into the DAC register, also updating the output.

8 7 SCLK

Serial Clock Input. Data is clocked into the shift register on the rising edge of SCLK. This

operates at clock speeds up to 30 MHz.
9 8 SDIN Serial Data Input. Data must be valid on the rising edge of SCLK.
10 9 SDO

Serial Data Output. Used to clock data from the serial register in daisy-chain or readback

mode. Data is clocked out on the falling edge of SCLK and is valid on the falling edge of

SCLK.
11 12 AGND Ground reference pin for analog circuitry.
N/A 13 DGND

Ground reference pin for digital circuitry. (AGND and DGND are internally connected in

TSSOP package).
13 16 R

SET

An external, precision, low drift 15kΩ current setting resistor can be connected to this

pin to improve the I

temperature drift performance. Refer to Features section.

OUT

14 17 REFOUT Internal Reference Voltage Output. REFOUT = 5 V ± 2 mV.
15 18 REFIN

External Reference Voltage Input. Reference input range is 4 V to 5 V. REFIN = 5 V for

specified performance.
16 23

DV

CC

SELECT

This pin when connected to GND disables the internal supply and an external supply

must be connected to the DV

pin. Leave this pin unconnected to enable the internal

CC

supply. Refer to features section.
17 24 C
18 25 C

COMP1

COMP2

Optional compensation capacitor connection for the voltage output buffer. Connecting

a 4nF capacitor between these pins will allow the voltage output to drive up to 1µF.

Rev. PrC | Page 11 of 37

AD5412 Preliminary Technical Data

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TSSOP Pin No. LFCSP Pin No. Mnemonic Description

19 26 I
20 27 BOOST

N/A 28 CAP1 Connection for optional output filtering capacitor. Refer to Features section.
N/A 29 CAP2 Connection for optional output filtering capacitor. Refer to Features section.
21 32 V

22 33 +V
23 34 -V
24 36 AVDD Positive Analog Supply Pin. Voltage ranges from 10.8V to 60V.
Paddle Paddle AVSS

Current output pin.

OUT

Optional external transistor connection. Connecting an external transistor will reduce
the power dissipated in the AD5412. Refer to the features section.

OUT

Sense connection for the positive voltage output load connection.

SENSE

Sense connection for the negative voltage output load connection.

SENSE

Buffered Analog Output Voltage. The output amplifier is capable of directly driving a 2
kΩ, 2000 pF load.

Negative Analog Supply Pin. Voltage ranges from –3 V to –24 V. This pin can be
connected to 0V if output voltage range is unipolar.

Rev. PrC | Page 12 of 37

Preliminary Technical Data AD5412

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TYPICAL PERFORMANCE CHARACTERISTICS

VOLTAGE OUTPUT

Figure 7. Integral Non Linearity Error vs DAC Code (Four Traces)

Figure 8. Differential Non Linearity Error vs. DAC Code (Four Traces)

Figure 10. Integral Non Linearity vs. Temperature (Four Traces)

Figure 11. Differential Non Linearity vs. Temperature (Four Traces)

Figure 9. Total Unadjusted Error vs. DAC Code (Four Traces)

Rev. PrC | Page 13 of 37

Figure 12. Integral Non Linearity vs. Supply Voltage (Four Traces)

AD5412 Preliminary Technical Data

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Figure 13.Differential Non Linearity Error vs. Supply Voltage (Four Traces)

Figure 14. Integral Non Linearity Error vs. Reference Voltage (Four traces)

Figure 16. Total Unadjusted Error vs.Reference Voltage (Four Traces)

Figure 17. Total Unadjusted Error vs. Supply Voltage (Four Traces)

Figure 15. Differential Non Linearity Error vs. Reference Voltage (Four Traces)

Figure 18. Offset Error vs.Temperature

Rev. PrC | Page 14 of 37

Preliminary Technical Data AD5412

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Figure 19. Bipolar Zero Error vs. Temperature

Figure 20. Gain Error vs. Temperature

Figure 22. Source and Sink Capability of Output Amplifier

Zero-Scale Loaded

Figure 23.Full-Scale Positive Step

Figure 21. Source and Sink Capability of Output Amplifier

Full-Scale Code Loaded

Figure 24. Full-Scale Negative Step

Rev. PrC | Page 15 of 37

AD5412 Preliminary Technical Data

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Figure 25. Digital-to-Analog Glitch Energy

Figure 26. Peak-to-Peak Noise (0.1Hz to 10Hz Bandwidth)

Figure 28. V

Figure 29. V

vs. Time on Power-up

OUT

vs, Time on Output Enabled

OUT

Figure 27. Peak-to-Peak Noise (100kHz Bandwidth)

Rev. PrC | Page 16 of 37

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TYPICAL PERFORMANCE CHARACTERISTICS

CURRENT OUTPUT

Figure 30. Integral Non Linearity vs. Code

Figure 31.Differential Non Linearity vs. Code

Figure 33. Integral Non Linearity vs. Temperature

Figure 34. Differential Non Linearity vs. Temperature

Figure 32. Total Unadjusted Error vs. Code

Rev. PrC | Page 17 of 37

Figure 35. Integral Non Linearity vs. Supply

AD5412 Preliminary Technical Data

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Figure 36. Differential Non Linearity vs. Supply Voltage

Figure 37. Integral Non Linearity vs. Reference Voltage

Figure 39. Total Unadjusted Error vs. Reference Voltage

Figure 40. Total Unadjusted Error vs. Supply Voltage

Figure 38. Differential Non Linearity vs. Reference Voltage

Figure 41. Offset Error vs. Temperature

Rev. PrC | Page 18 of 37

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Figure 42. Gain Error vs. Temperature

Figure 43. Voltage Compliance vs. Temperature

Figure 44. I

Figure 45. I

vs. Time on Power-up

OUT

vs. Time on Output Enabled

OUT

Rev. PrC | Page 19 of 37

AD5412 Preliminary Technical Data

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TYPICAL PERFORMANCE CHARACTERISTICS

GENERAL

Figure 46. DI

Figure 47. AI

vs.Logic Input Voltage

CC

/AISS vs AVDD/AVSS

DD

Figure 49. DV

Output Voltage vs. DICC Load Current

CC

Figure 50. Refout Turn-on Transient

Figure 48. AI

vs AVDD

DD

Figure 51. Refout Output Noise (0.1Hz to 10Hz Bandwidth)

Rev. PrC | Page 20 of 37

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Figure 52. Refout Output Noise (100kHz Bandwidth)

Figure 53. Refout Line Transient

Figure 55. Refout Histogram of Thermal Hysteresis

Figure 56. Refout Voltage vs. Load Current

Figure 54. Refout Load Transient

Rev. PrC | Page 21 of 37

AD5412 Preliminary Technical Data

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TERMINOLOGY

Relative Accuracy or Integral Nonlinearity (INL)

For the DAC, relative accuracy, or integral nonlinearity (INL), is
a measure of the maximum deviation, in LSBs, from a straight
line passing through the endpoints of the DAC transfer
function. A typical INL vs. code plot can be seen in Figure 7.

Differential Nonlinearity (DNL)

Differential nonlinearity (DNL) is the difference between the
measured change and the ideal 1 LSB change between any two
adjacent codes. A specified differential nonlinearity of ±1 LSB
maximum ensures monotonicity. This DAC is guaranteed
monotonic by design. A typical DNL vs. code plot can be seen
in Figure 10.

Monotonicity

A DAC is monotonic if the output either increases or remains
constant for increasing digital input code. The AD5724R/
AD5734R/AD5754R are monotonic over their full operating
temperature range.

Bipolar Zero Error

Bipolar zero error is the deviation of the analog output from the
ideal half-scale output of 0 V when the DAC register is loaded
with 0x8000 (straight binary coding) or 0x0000 (twos complement
coding). A plot of bipolar zero error vs. temperature can be seen
in Table TBD.

Bipolar Zero TC

Bipolar zero TC is a measure of the change in the bipolar zero
error with a change in temperature. It is expressed in ppm
FSR/°C.

Full-Scale Error

Full-Scale error is a measure of the output error when full-scale
code is loaded to the DAC register. Ideally, the output should be
full-scale − 1 LSB. Full-scale error is expressed in percent of
full-scale range (% FSR).

Negative Full-Scale Error/Zero-Scale Error

Negative full-scale error is the error in the DAC output voltage
when 0x0000 (straight binary coding) or 0x8000 (twos
complement coding) is loaded to the DAC register. Ideally, the
output voltage should be negative full-scale
zero-scale error vs. temperature can be seen in Table TBD

Zero-Scale TC

This is a measure of the change in zero-scale error with a change in
temperature. Zero-scale error TC is expressed in ppm FSR/°C.

Output Voltage Settling Time

Output voltage settling time is the amount of time it takes for
the output to settle to a specified level for a full-scale input
change. A plot of settling time can be seen in Table TBD

− 1 LSB. A plot of

Rev. PrC | Page 22 of 37

Slew Rate

The slew rate of a device is a limitation in the rate of change of
the output voltage. The output slewing speed of a voltage­output D/A converter is usually limited by the slew rate of the
amplifier used at its output. Slew rate is measured from 10% to
90% of the output signal and is given in V/µs.

Gain Error

This is a measure of the span error of the DAC. It is the
deviation in slope of the DAC transfer characteristic from ideal
expressed in % FSR. A plot of gain error vs. temperature can be
seen in Table TBD

Gain TC

This is a measure of the change in gain error with changes in
temperature. Gain Error TC is expressed in ppm FSR/°C.

Tot a l U n ad ju s te d E rr o r

Total unadjusted error (TUE) is a measure of the output error
taking all the various errors into account, namely INL error,
offset error, gain error, and output drift over supplies,
temperature, and time. TUE is expressed in % FSR.

Current Loop Voltage Compliance

The maximum voltage at the I
currnet will be equal to the programmed value.

Power-On Glitch Energy

Power-on glitch energy is the impulse injected into the analog
output when the AD5412 is powered-on. It is specified as the area
of the glitch in nV-sec. See Table TBD

Digital-to-Analog Glitch Impulse

Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state, but the output voltage remains constant. It is normally
specified as the area of the glitch in nV-sec and is measured
when the digital input code is changed by 1 LSB at the major
carry transition (0x7FFF to 0x8000). See Table TBD

Glitch Impulse Peak Amplitude

Glitch impulse peak amplitude is the peak amplitude of the
impulse injected into the analog output when the input code in
the DAC register changes state. It is specified as the amplitude
of the glitch in mV and is measured when the digital input code
is changed by 1 LSB at the major carry transition (0x7FFF to
0x8000). See Table TBD.

Digital Feedthrough

Digital feedthrough is a measure of the impulse injected into
the analog output of the DAC from the digital inputs of the
DAC, but is measured when the DAC output is not updated. It
is specified in nV-sec and measured with a full-scale code
change on the data bus.

Power Supply Rejection Ratio (PSRR)

PSRR indicates how the output of the DAC is affected by
changes in the power supply voltage.

Reference TC

pin for which the output

OUT

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Reference TC is a measure of the change in the reference output
voltage with a change in temperature. It is expressed in ppm/°C.

Line Regulation

Line regulation is the change in reference output voltage due to
a specified change in supply voltage. It is expressed in ppm/V.

Load Regulation

Load regulation is the change in reference output voltage due to
a specified change in load current. It is expressed in ppm/mA.

Thermal Hysteresis

Thermal hysteresis is the change of reference output voltage
after the device is cycled through temperatures from +25°C to

−40°C to +85°C and back to +25°C. This is a typical value from
a sample of parts put through such a cycle. See Table TBDfor a
histogram of thermal hysteresis.

VVV

C)25(−°

_

_

OHYSO

O

)( ×

=

ppmV

HYSO

TCO

_

C)25(

−°

VV

TCO

_

6

C)25(

°

V

O

10

where:

V

(25°C) = VO at 25°C

O

V

= VO at 25°C after temperature cycle

O_TC

Rev. PrC | Page 23 of 37

AD5412 Preliminary Technical Data

V

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THEORY OF OPERATION

+V

V

-V

and C

SENSE

OUT

SENSE

COMP2

±3V

pins.

R

1

R

L

The AD5412 is a precision digital to current loop and voltage
output converter designed to meet the requirements of
industrial process control applications. It provides a high
precision, fully integrated, low cost single-chip solution for
generating current loop and unipolar/bipolar voltage outputs.
The current ranges available are; 0 to 20mA, 0 to 24mA and 4 to
20mA, the voltage ranges available are; 0 to 5V, ±5V, 0 to 10V
and ±10V, the current and voltage outputs are available on
separate pins and only one is active at any one time. The desired
output configuration is user selectable via the CONTROL
register.

ARCHITECTURE

The DAC core architecture of the AD5412 consists of two
matched DAC sections. A simplified circuit diagram is shown
in Figure 57. The 4 MSBs of the 12-bit data word are decoded to
drive 15 switches, E1 to E15. Each of these switches connects 1
of 15 matched resistors to either ground or the reference buffer
output. The remaining 12 bits of the data-word drive switches
S0 to S7 of an 8-bit voltage mode R-2R ladder network.

OUT

2R

2R

2R

2R

S1

S0

V

REF

8-BIT R-2R L ADDE R FOUR MSBs DECODED INTO

Figure 57. DAC Ladder Structure

2R

S7

15 EQUAL SEGMENTS

2R
E2

E1

The voltage output from the DAC core is either converted to a
current (see diagram, Figure 58) which is then mirrored to the
supply rail so that the application simply sees a current source
output with respect to ground or it is buffered and scaled to
output a software selectable unipolar or bipolar voltage range
(See diagram, Figure 59). The current and voltage are output on
separate pins and cannot be output simultaneously.

AV

DD

2R
E15

12-BIT
DAC

REFIN

RANGE
SCALING

Figure 59. Voltage Output

Voltage Output Amplifier

The voltage output amplifier is capable of generating both
unipolar and bipolar output voltages. It is capable of driving a
load of 2 kΩ in parallel with 1 µF to AGND. The source and
sink capabilities of the output amplifier can be seen in Figure
TBD. The slew rate is 1 V/µs with a full-scale settling time of 10
µs, (10V step). Figure 59 shows the voltage output drving a load,

on top of a common mode voltage of up to ±3V.

R

L

In output module applications where a cable could possibly
become disconnected from +V

resulting in the amplifier

SENSE

loop being broken and most probably resulting in large
destructive voltages on V

, a resistor, R1, of value 2kΩ to 5kΩ

OUT

should be included as shown to ensure the amplifier loop is kept
closed.

Driving Large Capacitive Loads

The voltage output amplifier is capable of driving capacitive
loads of up to 1uF with the addition of a non-polarised 4nF
compensation capacitor between the C

COMP1

Without the compensation capacitor, up to 20nF capacitive
loads can be driven.

Reference Buffers

The AD5412 can operate with either an external or internal
reference. The reference input has an input range of 4 V to 5 V,
5 V for specified performance. This input voltage is then buffered
before it is applied to the DAC.

R2

R3

SERIAL INTERFACE

The AD5412 is controlled over a versatile 3-wire serial interface
that operates at clock rates up to 30 MHz. It is compatible with
SPI®, QSPI™, MICROWIRE™, and DSP standards.

Input Shift Register

The input shift register is 24 bits wide. Data is loaded into the

12-BIT
DAC

A1

T1

A2

T2

I

OUT

device MSB first as a 24-bit word under the control of a serial

R1

Figure 58. Voltage to Current conversion circuitry

clock input, SCLK. Data is clocked in on the rising edge of
SCLK. The input register consists of 8 control bits and 16 data
bits as shown in Table 7. The 24 bit word is unconditionally
latched on the rising edge of LATCH. Data will continue to be
clocked in irrespective of the state of LATCH, on the rising edge
of LATCH the data that is present in the input register will be
latched, in other words the last 24 bits to be clocked in before

Rev. PrC | Page 24 of 37

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the rising edge of LATCH will be the data that is latched. The
timing diagram for this operation is shown in Figure 2.

Rev. PrC | Page 25 of 37

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Table 7. Input Shift Register Format

MSB LSB

D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

ADDRESS WORD DATA WORD

Table 8. Control Word Functions

Address
Word

00000000 No Operation (NOP)
00000001 DATA Register
00000010

01010101 CONTROL Register
01010110 RESET Register

Functio n

Readback register value as per Read Address
(See Table 10)

Standalone Operation

The serial interface works with both a continuous and noncon­tinuous serial clock. A continuous SCLK source can only be
used if LATCH is taken high after the correct number of data
bits have been clocked in. In gated clock mode, a burst clock
containing the exact number of clock cycles must be used, and
LATCH must be taken high after the final clock to latch the
data. The first rising edge of SCLK that clocks in the MSB of the
dataword marks the beginning ot the write cycle. Exactly 24
rising clock edges must be applied to SCLK before LATCH is

th

brought high. If LATCH is brought high before the 24

rising

SCLK edge, the data written will be invalid. If more than 24
rising SCLK edges are applied before LATCH is brought high,
the input data will also be invalid.

CONTROLLER

DATA OUT

SERIAL CLOCK

CONTROL OUT

DATA IN

AD5412*

SDIN
SCLK
LATCH

SDO

SDIN

AD5412*

SCLK
LATCH

SDO

SDIN

AD5412*

SCLK
LATCH

Rev. PrC | Page 26 of 37

SDO

*ADDITIONA L PINS OM ITTE D F OR CLARI TY

Figure 60. Daisy Chaining the AD5412

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Daisy-Chain Operation

For systems that contain several devices, the SDO pin can be
used to daisy chain several devices together as shown in Figure

60. This daisy-chain mode can be useful in system diagnostics
and in reducing the number of serial interface lines. Daisychain
mode is enabled by setting the DCEN bit of the CONTROL
register. The first rising edge of SCLK that clocks in the MSB of
the dataword marks the beginning of the write cycle. SCLK is
continuously applied to the input shift register. If more than 24
clock pulses are applied, the data ripples out of the shift register
and appears on the SDO line. This data is clocked out on the
falling edge of SCLK and is valid on the next rising edge. By
connecting the SDO of the first device to the SDIN input of the
next device in the chain, a multidevice interface is constructed.
Each device in the system requires 24 clock pulses. Therefore,
the total number of clock cycles must equal 24 ×
the total number of AD5412 devices in the chain. When the
serial transfer to all devices is complete, LATCH is taken high.
This latches the input data in each device in the daisy chain.
The serial clock can be a continuous or a gated clock.

A continuous SCLK source can only be used if LATCH is taken
high after the correct number of clock cycles. In gated clock

N, where N is

mode, a burst clock containing the exact number of clock cycles
must be used, and LATCH must be taken high after the final
clock to latch the data. See Figure 4 for a timing diagram.

Readback Operation

Readback mode is invoked by setting the control word and read
address as shown in Table 9 and Table 10 when writing to the
input register. The next write to the AD5412 should be a NOP
command which will clock out the data from the previously
addressed register as shown in Figure 3.
By default the SDO pin is disabled, after having addressed the
AD5412 for a read operation, a rising edge on LATCH will
enable the SDO pin in anticipation of data being clocked out,
after the data has been clocked out on SDO, a rising edge on
LATCH will disable (tri-state) the SDO pin once again.
To read back the data register for example, the following
sequence should be implemented:

Write 0x020001 to the AD5412 input register. This

1.
configures the part for read mode with the data register
selected.

Follow this with a second write, a NOP condition, 0x000000

2.
During this write, the data from the register is clocked out
on the SDO line.

Table 9. Input Shift Register Contents for a read operation

MSB LSB

D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

0 0 0 0 0 0 1 0 X X X X X X X X X X X X X X

Table 10. Read Address Decoding

Read Address Function

00 Read Status Register
01 Read Data Register
10 Read Control Register

Read
Address

Rev. PrC | Page 27 of 37

AD5412 Preliminary Technical Data

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V

is the reference voltage applied at the REFIN pin.

DEFAULT CONFIGURATION

On initial power-up of the AD5412 the power-on-reset circuit
ensures that all registers are loaded with zero-code, as such the
default output is the current output with the 4mA to 20mA
range selected, the current output until a value is programmed
is 0mA. The voltage output pin will be in three-state. An
alternative current range or a voltage output range may be
selected via the CONTROL register.

TRANSFER FUNCTION

Voltage Output

For a unipolar voltage output range, the output voltage
expression is given by

D

⎤

⎡

×=

GainVV

REFIN

OUT

For a bipolar voltage output range, the output voltage
expression is given by

GainVV

×=

REFIN

OUT

where:

D is the decimal equivalent of the code loaded to the DAC.
N is the bit resolution of the DAC.

N

⎥

⎢

2

⎦

⎣

VGain

D

⎤

⎡

N

⎥

⎢

⎦

⎣

×

−

REFIN

22

REFIN

Gain is an internal gain whose value depends on the output

range selected by the user as shown in Table 11.

Table 11.

Output Range Gain Value

+5 V 1
+10 V 2
±5 V 2
±10 V 4

Current Output

For the 0 to 20mA, 0 to 24mA and 4 to 20mA current output
ranges the output current expressions are respectively given by

20

mA

24

2

2

N

mA

N

⎤
⎥

⎦

⎤

D

×

⎥
⎦

⎤

D

×

⎥
⎦

mAD

4

+×

OUT

OUT

=

⎡

=

⎢
⎣

⎡

=

⎢
⎣

mA

16

⎡

N

⎢

2

⎣

I

I

I

OUT

where:

D is the decimal equivalent of the code loaded to the DAC.
N is the bit resolution of the DAC.

Rev. PrC | Page 28 of 37

Preliminary Technical Data AD5412

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DATA REGISTER

The DATA register is addressed by setting the control word of the input shift register to 0x01. The data to be written to the DATA registe r
is entered in positions D15 to D0 as shown in Table 12,

Table 12. Programming the Data Register

MSB LSB
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

DATA WORD X X X X

CONTROL REGISTER

The CONTROL register is addressed by setting the control word of the input shift register to 0x55. The data to be written to the
CONTROL register is entered in positions D15 to D0 as shown in Table 13. The CONTROL register functions are shown in Table 14.

Table 13. Programming the CONTROL Register

MSB LSB
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

CLRSEL OVRRNG REXT OUTEN SR CLOCK SR STEP SREN DCEN R2 R1 R0

Table 14. Control Register Functions

Option Description

CRSEL

OVRRNG

REXT

OUTEN

SR CLOCK See Features Section. Digital Slew Rate Control
SR STEP See Features Section. Digital Slew Rate Control
SREN Digital Slew Rate Control enable
DCEN Daisychain enable
R2,R1,R0 Output range select. See Table 15

See Table 20 for a description of the CLRSEL
operation

Setting this bit increases the voltage output
range by 10%. Further details in Features
section

Setting this bit selects the external current
setting resistor, Further details in Features
section

Output enable. This bit must be set to enable
the outputs, The range bits select which output
will be functional.

RESET REGISTER

The RESET register is addressed by setting the control word of the input shift register to 0x56. The data to be written to the RESET
register is entered in positions D15 to D0 as shown in Table 16. The RESET register options are shown in Table 16 and Table 17.

Table 15. Output Range Options

R2 R1 R0 Output Range Selected

0 0 0 0 to +5V Voltage Range
0 0 1 0 to 10V Voltage Range
0 1 0 ±5V Voltage Range
0 1 1 ±10V Voltage Range
1 0 1 4 to 20 mA Current Range
1 1 0 0 to 20 mA Current Range
1 1 1 0 to 24 mA Current Range

Table 16. Programming the RESET Register

MSB LSB
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

RESET

Table 17. RESET register Functions

Option Description

RESET Setting this bit performs a reset operation, restoring the AD5412 to its initial power on state

Rev. PrC | Page 29 of 37

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STATUS REGISTER

The STATUS register is a read only register. The STATUS register functionality is shown in Table 18 and Table 19.

Table 18. Decoding the STATUS Register

MSB LSB

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

I

Table 19. STATUS Register Functions

Option Description

I

FAULT This bit will be set if a fault is detected on the I

OUT

SLEW ACTIVE This bit will be set while the output value is slewing (slew rate control enabled)
OVER TEMP This bit will be set if the AD5412 core temperature exceeds approx. 150°C.

OUT

pin.

FAULT SLEW ACTIVE OVER TEMP

OUT

Rev. PrC | Page 30 of 37

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FEATURES

FAULT ALERT

The AD5412 is equipped with a FAULT pin, this is an open­drain output allowing several AD5412 devices to be connected
together to one pull-up resistor for global fault detection. The
FAULT pin is forced active by any one of the following fault
scenarios;

The Voltage at I

1)
compliance range, due to an open-loop circuit or
insufficient power supply voltage. The I
controlled by a PMOS transistor and internal
amplifier as shown in Figure 58. The internal circuitry
that develops the fault output avoids using a
comparator with “window limits” since this would
require an actual output error before the FAULT
output becomes active. Instead, the signal is generated
when the internal amplifier in the output stage has less
than approxiamately one volt of remaining drive
capability (when the gate of the output PMOS
transistor nearly reaches ground). Thus the FAULT
output activates slightly before the compliance limit is
reached. Since the comparison is made within the
feedback loop of the output amplifier, the output
accuracy is maintained by its open-loop gain and an
output error does not occur before the FAULT output
becomes active.

If the core temperature of the AD5412 exceeds approx.

2)
150°C.

The OPEN CCT and OVER TEMP bits of the STATUS register
are used in conjunction with the FAULT pin to inform the user
which one of the fault conditions caused the FAULT pin to be
asserted. See Table 18 and Table 19.

attempts to rise above the

OUT

current is

OUT

VOLTAGE OUTPUT SHORT CIRCUIT PROTECTION

Under normal operation the voltage output will sink/source
5mA and maintain specified operation. The maximum current
that the voltage output will deliver is 10mA, this is the short
circuit current.

ASYNCHRONOUS CLEAR (CLEAR)

CLEAR is an active high clear that allows the voltage output to
be cleared to either zero-scale code or mid-scale code, user­selectable via the CLEAR SELECT pin or the CLRSEL bit of the
CONTROL register as described in Table 20. (The Clear select
feature is a logical OR function of the CLEAR SELECT pin and
the CLRSEL bit). The Current output will clear to the bottom of
its programmed range. It is necessary to maintain CLEAR high
for a minimum amount of time (see Figure 2) to complete the
operation. When the CLEAR signal is returned low, the output
remains at the cleared value until a new value is programmed. A
clear operation can also be performed via the CLEAR
command in the control register.

Rev. PrC | Page 31 of 37

Table 20. CLEAR SELECT Options

CLR SELECT Output CLR Value
Unipolar Output Range Bipolar Output Range

0 0 V 0 V
1 Mid-Scale Negative Full-Scale

INTERNAL REFERENCE

The AD5412 contains an integrated +5V voltage reference with
initial accuracy of ±2mV max and a temperature drift
coefficient of ±10 ppm max. The reference voltage is buffered
and externally available for use elsewhere within the system. See
Figure 56 for a load regulation graph of the Integrated reference.

EXTERNAL CURRENT SETTING RESISTOR

Referring to Figure 58, R1 is an internal sense resistor as part of
the voltage to current conversion circuitry. The stability of the
output current over temperature is dependent on the stability of
the value of R1. As a method of improving the stability of the
output current over temperature an external precision 15kΩ low
drift resistor can be connected to the R
be used instead of the internal resistor R1. The external resistor
is selected via the CONTROL register. See Table 13.

pin of the AD5412 to

SET

VOLTAGE OUTPUT OVER-RANGE

An over-range facility is provided on the voltage output. When
enabled via the CONTROL register, the selected output range
will be over-ranged by 10%.

DIGITAL POWER SUPPLY

By default the DVCC pin accepts a power supply of 2.7V to 5.5V,
alternatively, via the DV
supply may be output on the DV
supply for other devices in the system or as a termination for
pull-up resistors. This facility offers the advantage of not having
to bring a digital supply across an isolation barrier. The internal
power supply is enabled by leaving the DV
unconnected. To disable the internal supply DV
should be tied to 0V.

SELECT pin an internal 4.5V power

CC

pin for use as a digital power

CC

SELECT pin

CC

SELECT

CC

EXTERNAL BOOST FUNCTION

The addition of an external boost transistor as shown in Figure
61 will reduce the power dissipated in the AD5412 by reducing
the current flowing in the on-chip output transistor (dividing it
by the current gain of the external circuit). A discrete NPN
transistor with a breakdown voltage, BV
can be used.
The external boost capability has been developed for those
users who may wish to use the AD5412 at the extremes of the
supply voltage, load current and temperature range. The boost
transistor can also be used to reduce the amount of temperature
induced drift in the part. This will minimise the temperature
induced drift of the on-chip voltage reference, which improves
drift and linearity.

, greater than 60V

CEO

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BOOST

MJD31C

OR

PBSS8110Z

AD5412

I

OUT

0.022 F

1k

R

LOAD

Figure 61. External Boost Configuration

DIGITAL SLEW RATE CONTROL

The Slew Rate Control feature of the AD5412 allows the user to
control the rate at which the output value changes. This feature
is available on both the current and voltage outputs. With the
slew rate control feature disabled the output value will change at
a rate limited by the output drive circuitry and the attached
load. If the user wishes to reduce the slew rate this can be
achieved by enabling the slew rate control feature.With the
feature enabled via the SREN bit of the CONTROL register, (See
Table 13) the output, instead of slewing directly between two
values, will step digitally at a rate defined by two parameters
accessible via the CONTROL register as shown in Table 13. The
parameters are SR CLOCK and SR STEP. SR CLOCK defines
the rate at which the digital slew will be updated, e.g. if the
selected update rate is 1MHz the output will update every 1µs,
SR STEP defines by how much the output value will change at
each update. Together both parameters define the rate of change
of the output value.Table 21 and Table 22 outline the range of
values for both the SR CLOCK and SR STEP parameters.

Table 21. Slew Rate Update Clock Options

SR CLOCK Update Clock Frequency (Hz)

0000 1000000
0001 500000
0010 333333
0011 250000
0100 200000
0101 100000
0110 50000
0111 33333
1000 25000
1001 20000
1010 12500
1011 10000
1100 8333
1101 6666
1110 5000
1111 3921

Table 22. Slew Rate Step Size Options

SR STEP Step Size (LSBs)

000 1
001 2
010 4
011 8
100 16
101 32
110 64
111 128

The following equation describes the slew rate as a function of
the step size, the update clock frequency and the LSB size.

SlewRate

=

6

101×

LSBSizekFrequencyUpdateClocStepSize

Where:

Slew Rate is expressed in A/µs For I

or V/µs for V

OUT

OUT

LSBSize = Fullscale Range / 65536

When the slew rate control feature is enabled, all output
changes will change at the programmed slew rate, i.e. if the
CLEAR pin is asserted the output will slew to the clear value at
the programmed slew rate. The output can be halted at its
current value with a write to the CONTROL register. To avoid
halting the output slew, the SLEW ACTIVE bit can be used to
check that the slew has completed before writing to the AD5412
registers. See Table 18.

I

FILTERING CAPACITORS

OUT

Two capacitors may be placed between the pins CAP1, CAP2
and AV

as shown in Figure 62. The capacitors form a filter on

DD

the current output circuitry reducing the bandwidth and the
rate of change of the output current.

AV

DD

C1C

2

AV

DD

CAP1

AGND

CAP2

I

OUT

AD5412

Figure 62. I

Filtering Capacitors

OUT

Rev. PrC | Page 32 of 37

Preliminary Technical Data AD5412

www.BDTIC.com/ADI

APPLICATIONS INFORMATION

DRIVING INDUCTIVE LOADS

When driving inductive or poorly defined loads connect a

0.01µF capacitor between I

and GND. This will ensure

OUT

stability with loads beyond 50mH. There is no maximum
capacitance limit. The capacitive component of the load may
cause slower settling, though this may be masked by the settling
time of the AD5412.

TRANSIENT VOLTAGE PROTECTION

The AD5412 contains ESD protection diodes which prevent
damage from normal handling. The industrial control
environment can, however, subject I/O circuits to much higher
transients. In order to protect the AD5412 from excessively high
voltage transients , external power diodes and a surge current
limiting resistor may be required, as shown in Figure 63. The
constraint on the resistor value is that during normal operation
the output level at IOUT must remain within its voltage
compliance limit of
and resistor must have appropriate power ratings.

AVDD – 2.5V and the two protection diodes

AV

DD

AV

DD

AD5412

Figure 63. Output Transient Voltage Protection

AGND

I

OUT

R

P

R

LOAD

avoid radiating noise to other parts of the board and should
never be run near the reference inputs. A ground line routed
between the SDIN and SCLK lines helps reduce crosstalk
between them (not required on a multilayer board that has a
separate ground plane, but separating the lines helps). It is
essential to minimize noise on the REFIN line because it
couples through to the DAC output.

Avoid crossover of digital and analog signals. Traces on
opposite sides of the board should run at right angles to each
other. This reduces the effects of feed through the board. A
microstrip technique is by far the best, but not always possible
with a double-sided board. In this technique, the component
side of the board is dedicated to ground plane, while signal
traces are placed on the solder side.

GALVANICALLY ISOLATED INTERFACE

In many process control applications, it is necessary to provide
an isolation barrier between the controller and the unit being
controlled to protect and isolate the controlling circuitry from
any hazardous common-mode voltages that might occur. The

iCoupler® family of products from Analog Devices provides

voltage isolation in excess of 2.5 kV. The serial loading structure
of the AD5412 make it ideal for isolated interfaces because the
number of interface lines is kept to a minimum. Figure 64 shows
a 4-channel isolated interface to the AD5412 using an

ADuM1400. For further information, visit
http://www.analog.com/icouplers.

LAYOUT GUIDELINES

In any circuit where accuracy is important, careful consideration
of the power supply and ground return layout helps to ensure
the rated performance. The printed circuit board on which the
AD5412 is mounted should be designed so that the analog and
digital sections are separated and confined to certain areas of the
board. If the AD5412 is in a system where multiple devices
require an AGND-to-DGND connection, the connection
should be made at one point only. The star ground point should
be established as close as possible to the device.

The AD5412 should have ample supply bypassing of 10 µF in
parallel with 0.1 µF on each supply located as close to the
package as possible, ideally right up against the device. The 10
µF capacitors are the tantalum bead type. The 0.1 µF capacitor
should have low effective series resistance (ESR) and low
effective series inductance (ESI) such as the common ceramic
types, which provide a low impedance path to ground at high
frequencies to handle transient currents due to internal logic
switching.

The power supply lines of the AD5412 should use as large a
trace as possible to provide low impedance paths and reduce the
effects of glitches on the power supply line. Fast switching
signals such as clocks should be shielded with digital ground to

Controller

Serial Clock Out

Serial Data Out

SYNC Out

Control out

*ADDITIONAL PI NS O M ITTED FOR CLARITY

ADuM1400 *

V

IA

ENCODE DECODE

V

IB

ENCODE DECODE

V

IC

ENCODE DECODE

V

ID

ENCODE DECODE

Figure 64. Isolated Interface

V

OA

V

OB

V

OC

V

OD

To SCLK

To S DI N

To LAT C H

To CLEA R

MICROPROCESSOR INTERFACING

Microprocessor interfacing to the AD5412 is via a serial bus that
uses protocol compatible with microcontrollers and DSP
processors. The communications channel is a 3-wire
(minimum) interface consisting of a clock signal, a data signal,
and a latch signal. The AD5412 require a 24-bit data-word with
data valid on the rising edge of SCLK.

For all interfaces, the DAC output update is initiated on the
rising edge of LATCH. The contents of the registers can be read
using the readback function.

Rev. PrC | Page 33 of 37

AD5412 Preliminary Technical Data

(

www.BDTIC.com/ADI

THERMAL AND SUPPLY CONSIDERATIONS

The AD5412 is designed to operate at a maximum junction
temperature of 125°C. It is important that the device is not
operated under conditions that will cause the junction
temperature to exceed this value . Excessive junction
temperature can occur if the AD5412 is operated from the
maximum AV
directly to ground. In this case the ambient temperature should
be controlled or AV
depend on the device package.

and driving the maximum current (24mA)

DD

should be reduced. The conditions will

DD

At maximum ambient temperature of 85°C the 24-lead TSSOP
package can dissipate 950mW and the 40-lead LFCSP package
can dissipate 1.42W.
To ensure the junction temperature does not exceed 125°C
while driving the maximum current of 24mA directly into
ground (also adding an on-chip current of 3mA), AV

should

DD

be reduced from the maximum rating to ensure the package is
not required to dissipate more power than stated above. See
Table 23, Figure 65 and Figure 66.

2.5

2

1.5

1

Power Dissipation (W)

0.5

0

40 45 50 55 60 65 70 75 80 85

Figure 65. Maximum Power Dissipation Vs Ambient Temperature Figure 66. Maximum Supply Voltage Vs Ambient Temperature

Ambient Temperature (°C)

TSSOP
LFCSP

45

43

41

39

37

35

33

Supply Voltage (V)

31

29

27

25

25 35 45 55 65 75 85

Ambient Temperature (°C)

TSSOP
LFCSP

Table 23. Thermal and Supply considerations for each package

TSSOP LFCSP

Maximum allowed power dissipation
when operating at an ambient
temperature of 85°C

Maximum allowed ambient
temperature when operating from a
supply of 60V and driving 24mA
directly to ground.

Maximum allowed supply voltage
when operating at an ambient
temperature of 85°C and driving 24mA
directly to ground.

−

max

T

AI

T

J

Θ

max

JA

A

−

TT

AJ

Θ×

JADD

85125

−

=

=

mW

950

W

42

JADJ

85125

−

=

35

=

42027.0

×

)

V

V

CPT

°=××−=Θ×− 7942027.040125max

−

max

T

AI

T

J

Θ

max

JA

A

−

TT

AJ

Θ×

JADD

85125

−

=

=

42.1

28

JADJ

=

()

85125

−

53

=

28027.0

×

CPT

°>××−=Θ×− 8528027.040125max

Rev. PrC | Page 34 of 37

Preliminary Technical Data AD5412

www.BDTIC.com/ADI

OUTLINE DIMENSIONS

7.90

7.80

7.70

5.02

5.00

4.95

24

1.20 MAX

0.15

0.05

0.10 COPLANARI TY

INDICATOR

1.00

0.85

0.80

PIN 1

SEATING
PLANE

12° MAX

SEATING
PLANE

13

TOP VIEW

0.65
BSC

4.50

4.40

4.30

1.05

1.00

0.80

6.40 BSC

8°
0°

121

0.30

0.19

COMPLI ANT TO JE DE C S TANDARDS MO-153-ADT

BOTTOM VIEW

0.20

0.09

EXPOSED

PAD

(Pins Up)

0.75

0.60

0.45

Figure 67. 24-Lead Thin Shrink Small Outline Package, Exposed Pad [TSSOP_EP]

(RE-24)

Dimensions shown in millimeters

6.00

BSC SQ

TOP

VIEW

0.80 MAX

0.65 TYP

0.30

0.23

0.18

5.75

BCS SQ

0.20 REF

0.05 MAX

0.02 NOM

COPLANARITY

0.60 MAX

0.50
BSC

0.50

0.40

0.30

0.08

0.60 MAX

31

30

EXPOSED

(BOTTOM VIEW)

21

20

PAD

4.50
REF

40

1

10

11

3.25

3.20

3.15

PIN 1
INDICATOR

4.25

4.10 SQ

3.95

0.25 MIN

050806-A

COMPLI ANT TO JE DE C S TANDARDS MO-220-V JJD- 2

Figure 68. 40-Lead Lead Frame Chip Scale Package

(CP-40)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD5412BREZ -40°C to 85°C 24 Lead TSSOP_EP RE-24
AD5412BCPZ -40°C to 85°C 40 Lead LFCSP CP-40

Rev. PrC | Page 35 of 37

101306-A

AD5412 Preliminary Technical Data

www.BDTIC.com/ADI

NOTES

Rev. PrC | Page 36 of 37

Preliminary Technical Data AD5412

www.BDTIC.com/ADI

NOTES

©2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
PR07028-0-11/07(PrC)

Rev. PrC | Page 37 of 37