ANALOG DEVICES AD5412 Service Manual

Single Channel, 12-Bit, Serial Input,

www.BDTIC.com/ADI

Preliminary Technical Data

FEATURES

12-Bit Resolution and Monotonicity
Current Output Ranges: 4–20mA, 0–20mA or 0–24mA

0.1% Total Unadjusted Error (TUE)

5ppm/°C Output Drift
Voltage Output Ranges: 0-5V, 0-10V, ±5V, ±10V,
10% over-range

0.05% Total Unadjusted Error (TUE)

3ppm/°C Output Drift
Flexible Serial Digital Interface
On-Chip Output Fault Detection
On-Chip Reference (10 ppm/°C Max)
Asynchronous CLEAR Function
Power Supply Range

AV

: 10.8V to 40 V

DD

AV

: -26.4V to -3V/0V

SS

Output Loop Compliance to AV
Temperature Range: -40°C to +85°C
TSSOP and LFCSP Packages

APPLICATIONS

Process Control
Actuator Control
PLC

– 2.5 V

DD

Current Source & Voltage Output DAC

AD5412

GENERAL DESCRIPTION

The AD5412 is a low-cost, precision, fully integrated 12-bit
converter offering a programmable current source and
programmable voltage output designed to meet the
requirements of industrial process control applications.
The output current range is programmable to 4mA to 20 mA,
0mA to 20mA or an overrange function of 0mA to 24mA.
Voltage output is provided from a separate pin that can be
configured to provide 0V to 5V, 0V to 10V, ±5V or ±10V
output ranges, an over-range of 10% is available on all ranges.
Analog outputs are short and open circuit protected and can
drive capacitive loads of 1uF and inductive loads of 1H.
The device is specified to operate with a power supply range
from 10.8 V to 40 V. Output loop compliance is 0 V to AV

2.5 V.
The flexible serial interface is SPI
compatible and can be operated in 3-wire mode to minimize the
digital isolation required in isolated applications.
The device also includes a power-on-reset function ensuring
that the device powers up in a known state and an
asynchronous CLEAR pin which sets the outputs to zero-scale /
mid-scale voltage output or the low end of the selected current
range.
The total output error is typically ±0.1% in current mode and
±0.05% in voltage mode.

Table 1. Related Devices

Part Number Description

AD5422

AD5420

AD5410

and MICROWIRE

Single Channel, 16-Bit, Serial
Input Current Source and
Voltage Output DAC

Single Channel, 16-Bit, Serial
Input Current Source DAC

Single Channel, 12-Bit, Serial
Input Current Source DAC

DD

–

Rev. PrC

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2007 Analog Devices, Inc. All rights reserved.

AD5412 Preliminary Technical Data

www.BDTIC.com/ADI

TABLE OF CONTENTS

Features.............................................................................................. 1

Applications....................................................................................... 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Functional Block Diagram .............................................................. 3

Specifications..................................................................................... 4

AC Performance Characteristics ................................................ 7

Timing Characteristics ................................................................ 8

Absolute Maximum Ratings.......................................................... 10

ESD Caution................................................................................ 10

Pin Configuration and Function Descriptions........................... 11

Typical Performance Characteristics Voltage output............... 13

Typical Performance Characteristics current output............... 17

Typical Performance Characteristics general ............................20

Terminology .................................................................................... 22

Theory of Operation ...................................................................... 24

Architecture................................................................................. 24

Serial Interface ............................................................................ 24

Default configuration................................................................. 28

Transfer Function....................................................................... 28

Data Register............................................................................... 29

Control Register.......................................................................... 29

RESET register............................................................................ 29

Status register.............................................................................. 30

Features............................................................................................ 31

fault alert...................................................................................... 31

voltage output short circuit protection.................................... 31

Asynchronous Clear (CLEAR)................................................. 31

Internal Reference...................................................................... 31

External current setting resistor............................................... 31

Voltage ouTput over-range........................................................ 31

Digital Power Supply.................................................................. 31

External boost function............................................................. 31

digital Slew rate control............................................................. 32

I

Filtering Capacitors............................................................ 32

OUT

Applications Information.............................................................. 33

driving inductive loads.............................................................. 33

Transient voltage protection ..................................................... 33

Layout Guidelines....................................................................... 33

Galvanically Isolated Interface ................................................. 33

Microprocessor Interfacing....................................................... 33

Thermal and supply considerations......................................... 34

Outline Dimensions....................................................................... 35

Ordering Guide .......................................................................... 35

REVISION HISTORY

PrC – Preliminary Version. October 9, 2007

Rev. PrC | Page 2 of 37

Preliminary Technical Data AD5412

www.BDTIC.com/ADI

FUNCTIONAL BLOCK DIAGRAM

DV

CC

SELECT

DV

CC

CAP1

CAP2

AV

SS

AV

DD

CLEAR
SELECT

CLEAR

LATCH

SCLK

SDIN

SDO

AD5412

INPUT SHIFT

POWER

ON

RESET

DGND*

*LFCSP Package

REGISTER

AND

CONTROL

LOGIC

VREF

REFOUT

R2

12

12-BIT

/

DAC

R1

RANGE
SCALING

REFIN

Figure 1.

AGND

C

COMP2

C

COMP1

R3

BOOST

I

OUT

FAULT

R

SET

+V

SENSE

V

OUT

-V

SENSE

Rev. PrC | Page 3 of 37

AD5412 Preliminary Technical Data

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SPECIFICATIONS

AVDD = 10.8V to 40V, AVSS = -26.4V to -3V/0V, AVDD + |AVSS| < 52.8V, AGND = DGND = 0 V, REFIN= +5 V external;
DV

= 2.7 V to 5.5 V, V

CC

all specifications T

Table 2.

Parameter Value1 Unit Test Conditions/Comments
VOLTAGE OUTPUT

Output Voltage Ranges 0 to 5 V

0 to 10 V

-5 to +5 V

-10 to +10 V

ACCURACY Output unloaded

Bipolar Output

Resolution 12 Bits
Total Unadjusted Error (TUE) 0.1 % FSR max

TUE TC2 ±3 ppm typ

Relative Accuracy (INL) ±0.012 % FSR max
Differential Nonlinearity (DNL) ±1 LSB max Guaranteed monotonic
Bipolar Zero Error ±5 mV max

Bipolar Zero TC2 ±3 ppm FSR/°C max
Zero-Scale Error ±1 mV max

Zero-Scale TC2 ±3 ppm FSR/°C max
Gain Error ±0.05 % FSR max

Gain TC2 ±8 ppm FSR/°C max
Full-Scale Error 0.05 % FSR max

Full-Scale TC2 ±3 ppm FSR/°C max

Unipolar Output AVSS = 0 V

Resolution 12 Bits
Total Unadjusted Error (TUE) 0.1 % FSR max

Relative Accuracy (INL) ±0.012 % FSR max
Differential Nonlinearity (DNL) ±1 LSB max Guaranteed monotonic
Zero Scale Error +10 mV max

Zero Scale TC2 ±3 ppm FSR/°C max
Offset Error ±10 mV max
Gain Error ±0.05 % FSR max

Gain TC2 ±3 ppm FSR/°C max
Full-Scale Error 0.05 % FSR max

Full-Scale TC2 ±3 ppm FSR/°C max

OUTPUT CHARACTERISTICS2

Headroom 0.8 V max

0.5 V typ

Output Voltage TC ±3 ppm FSR/°C max

Output Voltage Drift vs. Time ±12 ppm FSR/500 hr typ Vout = ¾ of Full-Scale

±15 ppm FSR/1000 hr typ

Short-Circuit Current 12 mA typ

MIN

: RL = 2 kΩ, CL = 200 pF, I

OUT

to T

, ±10 V / 0 to 24 mA range unless otherwise noted.

MAX

: RL = 300Ω, HL = 50mH;

OUT

Rev. PrC | Page 4 of 37

Over temperature, supplies, and time, typically 0.05%
FSR

@ 25°C, error at other temperatures obtained using
bipolar zero TC

@ 25°C, error at other temperatures obtained using zero
scale TC

@ 25°C, error at other temperatures obtained using gain
TC

@ 25°C, error at other temperatures obtained using gain
TC

Over temperature, supplies, and time, typically 0.05%
FSR

@ 25°C, error at other temperatures obtained using gain
TC

@ 25°C, error at other temperatures obtained using gain
TC

@ 25°C, error at other temperatures obtained using gain
TC

Preliminary Technical Data AD5412

www.BDTIC.com/ADI

Parameter Value1 Unit Test Conditions/Comments

Load 2 kΩ min For specified performance
Capacitive Load Stability

RL = ∞ 20 nF max
RL = 2 kΩ TBD nF max

RL = ∞ 1 µF max External compensation capacitor of 4nF connected.
DC Output Impedance 0.3 Ω typ
Power-On Time 10 µs typ
DC PSRR TBD µV/V

CURRENT OUTPUT

Output Current Ranges 0 to 24 mA

0 to 20 mA

4 to 20 mA

ACCURACY

Resolution 12 Bits
Total Unadjusted Error (TUE) ±0.3 % FSR max Over temperature, supplies, and time, typically 0.1% FSR
TUE TC2 ±5 ppm/°C typ
Relative Accuracy (INL) ±0.012 % FSR max
Differential Nonlinearity (DNL) ±1 LSB max Guaranteed monotonic
Offset Error ±0.05 % FSR max
Offset Error Drift ±5 µv/°C typ
Gain Error ±0.02 % FSR max

Gain TC2 ±8 ppm FSR/°C max
Full-Scale Error 0.05 % FSR max

Full-Scale TC2 ±8 ppm FSR/°C

OUTPUT CHARACTERISTICS2

Current Loop Compliance Voltage AVDD - 2.5 V max
Output Current Drift vs. Time TBD ppm FSR/500 hr typ
TBD ppm FSR/1000 hr typ
Resistive Load TBD Ω max
Inductive Load 1 H max
DC PSRR 10 µA/V max
Output Impedance 50 MΩ typ

REFERENCE INPUT/OUTPUT

Reference Input2

Reference Input Voltage 5 V nom ±1% for specified performance

DC Input Impedance 30 kΩ min Typically 40 kΩ

Reference Range 4 to 5 V min to V max
Reference Output

Output Voltage 4.998 to 5.002 V min to V max @ 25°C

Reference TC ±10 ppm/°C max

Output Noise (0.1 Hz to 10 Hz)2 18 µV p-p typ

Noise Spectral Density2 120 nV/√Hz typ @ 10 kHz

Output Voltage Drift vs. Time2 ±40 ppm/500 hr typ

±50 ppm/1000 hr typ

Capacitive Load TBD nF max

Load Current 5 mA typ

Short Circuit Current 7 mA typ

Line Regulation2 10 ppm/V typ

Load Regulation2 TBD ppm/mA

Thermal Hysteresis2 TBD ppm

@ 25°C, error at other temperatures obtained using gain
TC

@ 25°C, error at other temperatures obtained using gain
TC

Rev. PrC | Page 5 of 37

AD5412 Preliminary Technical Data

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Parameter Value1 Unit Test Conditions/Comments
DIGITAL INPUTS2

VIH, Input High Voltage 2 V min
VIL, Input Low Voltage 0.8 V max
Input Current ±1 µA max Per pin
Pin Capacitance 10 pF typ Per pin

DIGITAL OUTPUTS 2

SDO

VOL, Output Low Voltage 0.4 V max sinking 200 µA
VOH, Output High Voltage DVCC − 0.5 V min sourcing 200 µA
High Impedance Leakage

Current
High Impedance Output

Capacitance

FAU LT

VOL, Output Low Voltage 0.4 V max
VOL, Output Low Voltage 0.6 V typ @ 2.5 mA

VOH, Output High Voltage 3.6 V min

POWER REQUIREMENTS

AVDD 10.8 to 40 V min to V max
AVSS -26.4 to 0 V min to V max
DVCC

Input Voltage 2.7 to 5.5 V min to V max Internal supply disabled
Output Voltage 4.5 V typ DVCC can be overdriven up to 5.5V
Output Load Current 5 mA typ

Short Circuit Current 20 mA typ
AIDD TBD mA Output unloaded
AISS TBD mA Output unloaded
DICC 1 mA max VIH = DVCC, VIL = GND, TBD mA typ
Power Dissipation TBD mW typ AVDD = 40V, AVSS = 0 V, V
TBD mW typ AVDD = 40V, AVSS = -15 V, V
TBD mW typ AVDD = 15V, AVSS = -15 V, V

1

Temperature range: -40°C to +85°C; typical at +25°C.

2

Guaranteed by characterization. Not production tested.

DVCC = 2.7 V to 5.5 V, JEDEC compliant

±1 µA max

5

pF typ

10kΩ pull-up resistor to DV

10kΩ pull-up resistor to DV

OUT

CC

CC

unloaded

unloaded

OUT

unloaded

OUT

Rev. PrC | Page 6 of 37

Preliminary Technical Data AD5412

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AC PERFORMANCE CHARACTERISTICS

AVDD = 10.8V to 40V, AVSS = -26.4V to -3V/0V, AVDD + |AVSS| < 52.8V, AGND = DGND = 0 V, REFIN= +5 V external;
DV

= 2.7 V to 5.5 V, V

CC

all specifications T

Table 3.

Parameter1 Unit Test Conditions/Comments

DYNAMIC PERFORMANCE

VOLTAGE OUTPUT

Output Voltage Settling Time 8 µs typ Full-scale step (10 V) to ±0.03% FSR
10 µs max
5 µs max 512 LSB step settling

Output Current Settling Time 10 µs max To 0.1% FSR

Slew Rate 1 V/µs typ
Power-On Glitch Energy 10 nV-sec typ
Digital-to-Analog Glitch Energy 10 nV-sec typ
Glitch Impulse Peak Amplitude 20 mV typ
Digital Feedthrough 1 nV-sec typ
Output Noise (0.1 Hz to 10 Hz Bandwidth) 0.1 LSB p-p typ
Output Noise (100 kHz Bandwidth) 80 µV rms max
1/f Corner Frequency 1 kHz typ
Output Noise Spectral Density 100 nV/√Hz typ Measured at 10 kHz
AC PSRR TBD dB

CURRENT OUTPUT

Output Current Settling Time TBD µs typ To 0.1% FSR , L = 1H

TBD µs typ To 0.1% FSR , L < 1mH

1

Guaranteed by characterization, not production tested.

MIN

: RL = 2 kΩ, CL = 200 pF, I

OUT

to T

, ±10 V / 0 to 24 mA range unless otherwise noted.

MAX

: RL = 300Ω, HL = 50mH;

OUT

200mV 50/60Hz Sinewave
superimposed on power supply voltage.

Rev. PrC | Page 7 of 37

AD5412 Preliminary Technical Data

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TIMING CHARACTERISTICS

AVDD = 10.8V to 40V, AVSS = -26.4V to -3V/0V, AVDD + |AVSS| < 52.8V, AGND = DGND = 0 V, REFIN= +5 V external;
DV

= 2.7 V to 5.5 V, V

CC

all specifications T

MIN

: RL = 2 kΩ, CL = 200 pF, I

OUT

to T

, ±10 V / 0 to 24 mA range unless otherwise noted.

MAX

: RL = 300Ω, HL = 50mH;

OUT

Table 4.

Parameter
Write Mode

1, 2, 3

Limit at T

, T

MIN

Unit Description

MAX

t1 33 ns min SCLK cycle time
t2 13 ns min SCLK low time
t3 13 ns min SCLK high time
t4 13 ns min LATCH delay time
t5 40 ns min LATCH high time
t5 5 µs min LATCH high time (After a write to the CONTROL register)
t6 5 ns min Data setup time
t7 5 ns min Data hold time
t8 40 ns min LATCH low time
t9 20 ns min CLEAR pulsewidth
t10 5 µs max CLEAR activation time

Readback Mode

t11 82 ns min SCLK cycle time
t12 33 ns min SCLK low time
t13 33 ns min SCLK high time
t14 13 ns min LATCH delay time
t15 40 ns min LATCH high time
t16 5 ns min Data setup time
t17 5 ns min Data hold time
t18 40 ns min LATCH low time
t19 40 ns max Serial output delay time (C

L SDO

4

= 15pF)

t20 33 ns max LATCH rising edge to SDO tri-state

Daisychain Mode

t21 82 ns min SCLK cycle time
t22 33 ns min SCLK low time
t23 33 ns min SCLK high time
t24 13 ns min LATCH delay time
t25 40 ns min LATCH high time
t26 5 ns min Data setup time
t27 5 ns min Data hold time
t28 40 ns min LATCH low time
t29 40 ns max Serial output delay time (C

L SDO

4

= 15pF)

1

Guaranteed by characterization. Not production tested.

2

All input signals are specified with tR = tF = 5 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V.

3

See Figure 2, Figure 3, and Figure 4.

4

C

= Capacitive load on SDO output.

L SDO

Rev. PrC | Page 8 of 37

Preliminary Technical Data AD5412

www.BDTIC.com/ADI

t

1

SCLK

SCLK

LATCH

SDIN

CLEAR

OUTPUT

t

12

2421

t

3

DB0

t

t

8

t

4

5

t

6

DB23

t

2

t

7

t

9

t

10

Figure 2. Write Mode Timing Diagram

t

11

2

2421

t

13

t

t

14

15

1

923

8

22

24

LATCH

SDIN

SDO

LATCH

SCLK

SDIN

t

16

DB23

t

17

INPUT WORD SPECIFIES
REGISTER TO BE READ

UNDEFINED DATA

DB23

INPUT WORD F OR DAC N

t

18

DB0

DB23

FIRST 8 BITS ARE
DON’T CARE B ITS

Figure 3. Readback Mode Timing Diagram

25

2421

t

26

DB0

DB23

t

29

NOP CONDITIO N

X

XXX

DB15

SELECTED REGISTER
DATA CLOCKED OUT

t

t

22

t

27

INPUT WO RD F O R DAC N-1

t

23

DB0

t

t

19

DB0

20

21

4826

DB0

t

24

t

28

t

25

SDO

DB23 DB0

UNDEFINED

DB23 DB0

INPUT WO RD FOR DAC N

Figure 4. Daisychain Mode Timing Diagram

Rev. PrC | Page 9 of 37

AD5412 Preliminary Technical Data

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ABSOLUTE MAXIMUM RATINGS

TA = 25°C unless otherwise noted.
Transient currents of up to 100 mA do not cause SCR latch-up.

Table 5.

Parameter Rating

AVDD to AGND, DGND −0.3V to 48V
AVSS to AGND, DGND +0.3 V to −48 V
AVDD to AVSS -0.3V to 60V
DVCC to AGND, DGND −0.3 V to +7 V
Digital Inputs to AGND, DGND

Digital Outputs to AGND, DGND

REFIN/REFOUT to AGND, DGND −0.3 V to +7 V
V

to AGND, DGND AVSS to AVDD

OUT

I

to AGND, DGND −0.3V to AVDD

OUT

AGND to DGND -0.3V to +0.3V
Operating Temperature Range

Industrial −40°C to +851°C
Storage Temperature Range −65°C to +150°C
Junction Temperature (TJ max) 125°C
24-Lead TSSOP Package

θJA Thermal Impedance 42°C/W
40-Lead LFCSP Package

θJA Thermal Impedance 28°C/W
Power Dissipation (TJ max – TA)/ θJA
Lead Temperature JEDEC Industry Standard

Soldering J-STD-020

−0.3 V to DV
(whichever is less)

−0.3 V to DV
(whichever is less)

+ 0.3 V or 7 V

CC

+ 0.3 V or 7V

CC

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

1

Power dissipated on chip must be de-rated to keep junction temperature

below 125°C. Assumption is max power dissipation condition is sourcing
24mA into Ground from AVDD with a 3mA on-chip current.

Rev. PrC | Page 10 of 37

Preliminary Technical Data AD5412

T

E

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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

AV
DV

FAULT

GND

CLEAR SELE CT

CLEAR

LATCH

SCLK

SDIN

SDO

AGND

GND

SS
CC

1
2

AD5422

3
4
5

TOP VIEW

6

(Not to Scale)

7
8

9
10
11
12

24
23
22
21
20
19
18
17
16
15
14
13

AV

DD

-V

SENSE

+V

SENSE

V

OUT

BOOST
I

OUT

C

COMP2

C

COMP1

DV

CC

REFIN
REFOUT
R

SET

SELEC

CLEAR SELECT

CC

NC

DV

NC

40 39 38 37 36 35 34 33 32 31

NC

1
2

FAULT

3

GND

4
5

CLEAR

6

LATCH

SCLK

7

SDIN

8
9

SDO

NC

10

11 12 13 14 15 16 17 18 19 20

NC

DGND

AGND

AVSSAVDDNC

AD5422

TOP VIEW

(Not to Scale)

SS

AV

SENS

SENSE

OUT

-V

NC

+V

V

30

NC

29

CAP2

28

CAP1

27

BOOST

26

I

OUT

25

C

COMP2

24

C

COMP1

23

CC

SELECT

DV

22

NC

21

NC

SET

R

GND

NC

NC

REFIN

REFOUT

Figure 5. TSSOP Pin Configuration Figure 6. LFCSP Pin Configuration

Table 6. Pin Function Descriptions

TSSOP Pin No. LFCSP Pin No. Mnemonic Description

1 14,37 AVSS

Negative Analog Supply Pin. Voltage ranges from –3 V to –24 V. This pin can be

connected to 0V if output voltage range is unipolar.
2 39 DVCC Digital Supply Pin. Voltage ranges from 2.7 V to 5.5 V.
3 2

FAU LT

Fault alert, This pin is asserted low when an open circuit is detected in current mode or

an over temperature is detected. Open drain output, must be connected to a pull-up

resistor.
4,12 3,15 GND These pins must be connected to 0V.
1,10,11,19,

NC No Connection.
20,21,22,30,
31,35,38,40

5 4

CLEAR

Selects the voltage output clear value, either zero-scale or mid-scale code. See Table 20

SELECT

6 5 CLEAR

Active High Input. Asserting this pin will set the current output to the bottom of the
selected range or will set the voltage output to the user selected value (zero-scale or
mid-scale).

7 6 LATCH

Positive edge sensitive latch, a rising edge will parallel load the input shift register data
into the DAC register, also updating the output.

8 7 SCLK

Serial Clock Input. Data is clocked into the shift register on the rising edge of SCLK. This

operates at clock speeds up to 30 MHz.
9 8 SDIN Serial Data Input. Data must be valid on the rising edge of SCLK.
10 9 SDO

Serial Data Output. Used to clock data from the serial register in daisy-chain or readback

mode. Data is clocked out on the falling edge of SCLK and is valid on the falling edge of

SCLK.
11 12 AGND Ground reference pin for analog circuitry.
N/A 13 DGND

Ground reference pin for digital circuitry. (AGND and DGND are internally connected in

TSSOP package).
13 16 R

SET

An external, precision, low drift 15kΩ current setting resistor can be connected to this

pin to improve the I

temperature drift performance. Refer to Features section.

OUT

14 17 REFOUT Internal Reference Voltage Output. REFOUT = 5 V ± 2 mV.
15 18 REFIN

External Reference Voltage Input. Reference input range is 4 V to 5 V. REFIN = 5 V for

specified performance.
16 23

DV

CC

SELECT

This pin when connected to GND disables the internal supply and an external supply

must be connected to the DV

pin. Leave this pin unconnected to enable the internal

CC

supply. Refer to features section.
17 24 C
18 25 C

COMP1

COMP2

Optional compensation capacitor connection for the voltage output buffer. Connecting

a 4nF capacitor between these pins will allow the voltage output to drive up to 1µF.

Rev. PrC | Page 11 of 37

AD5412 Preliminary Technical Data

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TSSOP Pin No. LFCSP Pin No. Mnemonic Description

19 26 I
20 27 BOOST

N/A 28 CAP1 Connection for optional output filtering capacitor. Refer to Features section.
N/A 29 CAP2 Connection for optional output filtering capacitor. Refer to Features section.
21 32 V

22 33 +V
23 34 -V
24 36 AVDD Positive Analog Supply Pin. Voltage ranges from 10.8V to 60V.
Paddle Paddle AVSS

Current output pin.

OUT

Optional external transistor connection. Connecting an external transistor will reduce
the power dissipated in the AD5412. Refer to the features section.

OUT

Sense connection for the positive voltage output load connection.

SENSE

Sense connection for the negative voltage output load connection.

SENSE

Buffered Analog Output Voltage. The output amplifier is capable of directly driving a 2
kΩ, 2000 pF load.

Negative Analog Supply Pin. Voltage ranges from –3 V to –24 V. This pin can be
connected to 0V if output voltage range is unipolar.

Rev. PrC | Page 12 of 37