2-channel 12-bit DAC
Twos complement facilitates bipolar applications
Bipolar zero with 2 V dc offset
Built-in 2.000 V precision reference with 10 ppm/°C typ TC
Buffered voltage output: 0 V to 4 V
Single-supply operation: 4.5 V to 5.5 V
Fast 0.8 µs settling time typ
Ultracompact MSOP-10 package
Monotonic DNL < ±1 LSB
Optimized accuracy at zero scale
Power-on reset to V
3-wire serial data input
Extended temperature range: –40°C to +105°C
APPLICATIONS
Single-supply bipolar converter operations
General-purpose DSP applications
Digital gain and offset controls
Instrumentation level settings
Disk drive control
Precision motor control
GENERAL DESCRIPTION
The AD5399 is the industry-first dual 12-bit digital-to-analog
converter that accepts twos complement digital coding with 2 V
dc offset for single-supply operation. Augmented with a built-in
precision reference and a solid buffer amplifier, the AD5399 is
the smallest self-contained 12-bit precision DAC that fits many
general-purpose as well as DSP specific applications. The twos
complement programming facilitates the natural coding
implementation commonly found in DSP applications, and
allows operation in single supply. The AD5399 provides a 2 V
reference output, V
be used for other on-board components that require a precision
reference. The device is specified for operation from 5 V ± 10%
single supply with bipolar output swing from 0 V to 4 V
centered at 2 V.
REF
, for bipolar zero monitoring. It can also
REF
AD5399
FUNCTIONAL BLOCK DIAGRAM
V
TP
V
AGND
CS
CLK
SDI
DGND
DD
V
2V
REF
DECODER SW
DRIVER A
12
A0
16-BIT
DAC A
REGISTER
ADDR
DECODE
EN
D15...D0
AD5399
X2×2
DECODER SW
DRIVER B
DAC B
REGISTER
12
POWER-ON
RESET
Figure 1.
V
= ((D – 2048)/4096 × 4 V) + 2 V for 0 ≤ D ≤ 4095, where D
The AD5399 is available in the compact 1.1 mm low profile
MSOP-10 package. All parts are guaranteed to operate over the
extended industrial temperature range of –40°C to +105°C.
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
Codes 2048 to 2052, due to int. op amp offset –1.2 ±0.5 +1.2 LSB
Integral Nonlinearity Error INL –0.4 ±0.02 +0.4 %FS
Positive Full-Scale Error V
Bipolar Zero-Scale Error V
Negative Full-Scale Error V
ANALOG OUTPUTS
Nominal Positive Full-Scale V
Positive Full-Scale Tempco2 TCV
Code = 0xFF, TA = –40°C to +105°C –60 ±10 +60 ppm/°C
Nominal VBZ Output Voltage VBZ 1.995 2.000 2.004 V
Bipolar Zero Output Resistance2
VBZ Output Voltage Tempco TCVBZ T
T
Nominal Peak-to-Peak Output Swing |V
DIGITAL INPUTS
Input Logic High VIH V
Input Logic Low VIL V
Input Current IIL V
Input Capacitance2
POWER SUPPLIES
Power Supply Range V
Supply Current IDD V
Supply Current in Shutdown I
V
Power Dissipation3 P
Power Supply Sensitivity PSS ∆VDD = 5 V ± 10% –0.006 +0.003 +0.006 %/%
DYNAMIC CHARACTERISTICS2
Settling Time tS 0.1% error band 0.8 µs
Digital Feedthrough Q 10 nV-s
Bipolar Zero-Scale Glitch G 10 nV-s
Capacitive Load Driving Capability CL No oscillation 1000 pF
INTERFACE TIMING CHARACTERISTICS
2, 4
SCLK Cycle Frequency t
SCLK Clock Cycle Time t1 30 ns
Input Clock Pulse Width t2, t3 Clock level low or high 15 ns
Data Setup Time t4 5 ns
Data Hold Time t5 0 ns
CS
to SCLK Active Edge Setup Time
SCLK to CS Hold Time
Repeat Programming, CS High Time
1
Typical values represent average readings at 25°C and VDD = 5 V.
2
Guaranteed by design and not subject to production test.
3
P
is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
DISS
4
See timing diagram (Figure 5) for location of measured values. All input control voltages are specified with tR = tF = 2 ns (10% to 90% of 3 V) and timed from a voltage
level of 1.5 V. Switching characteristics are measured using V
Code = 0xF –0.75 –0.15 +0.75 %FS
+FSE
Code = 0x000 –0.75 –0.15 +0.75 %FS
BZSE
Code = 0x800 –0.75 –0.15 +0.75 %FS
–FSE
Code = 0x7FF 4 V
OUTA/B
Code = 0x7FF, TA = 0°C to 70°C –40 ±10 +40 ppm/°C
OUTA/B
R
BZ
| + |V
+FS
C
5 pF
IL
DD RANGE
DD_SHDN
V
DISS
1 Ω
= 0°C to 70°C –40 ±10 +40 ppm/°C
A
= –40°C to +105°C –60 ±10 +60 ppm/°C
A
| Code 0x7FF to Code 0x800 4 V
–FS
= 5 V 2.4 V
DD
= 5 V 0.8 V
DD
= 0 V or 5 V, VDD = 5 V ±1 µA
IN
4.5 5.5 V
= VDD or VIL = 0 V 1.8 2.6 mA
IH
V
= VDD or VIL = 0 V, B14 = 0, TA = 0°C to 105°C 10 100 µA
IH
= VDD or VIL = 0 V, B14 = 0, TA = –40°C to 0°C 100 500 µA
IH
= VDD or VIL = 0 V, VDD = 5.5 V 9 13 mW
IH
33 MHz
CYC
5 ns
t
6
0 ns
t
7
30 ns
t
8
= 5 V. Input logic should have a 1 V/µs minimum slew rate.
DD
Rev. D | Page 3 of 12
AD5399
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter Rating
VDD to GND –0.3 V, +7.5 V
V
, V
OUTA
Digital Input Voltages to GND 0 V, VDD + 0.3 V
Operating Temperature Range –40°C to +105°C
Maximum Junction Temperature (TJ
Storage Temperature –65°C to +150°C
Lead Temperature (Soldering, 10 sec) 300°C
Package Power Dissipation (T
Thermal Resistance, θJA, MSOP-10 206°C/W
, VBZ to GND 0 V, VDD
OUTB
) 150°C
MAX
J MAX
– TA)/θJA
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. D | Page 4 of 12
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