ANALOG DEVICES AD5398A Service Manual

120 mA, Current Sinking,

V

FEATURES

Current sink: 120 mA
2-wire, (I
10-bit resolution
Integrated current sense resistor
Power supply: 2.7 V to 5.5 V
Guaranteed monotonic over all codes
Power down to: 0.5 μA typical
Internal reference
Ultralow noise preamplifier
Power-down function
Power-on reset
Available in 3 × 3 array WLCSP package

APPLICATIONS

Consumer

2

C-compatible) 1.8 V serial interface

Lens autofocus
Image stabilization
Optical zoom
Shutters
Iris/exposure
Neutral density (ND) filters
Lens covers
Camera phones
Digital still cameras
Camera modules
Digital video cameras/camcorders
Camera-enabled devices
Security cameras
Web/PC cameras

10-Bit, I2C DAC

AD5398A

Industrial

Heater control
Fan control
Cooler (Peltier) control
Solenoid control
Valve control
Linear actuator control
Light control
Current loop control

GENERAL DESCRIPTION

The AD5398A is a single, 10-bit digital-to-analog converter
(DAC) with a current sink output capability of 120 mA. This
device features an internal reference and operates from a
single 2.7 V to 5.5 V supply. The DAC is controlled via a
2-wire (1.8 V, I
at clock rates up to 400 kHz.

The AD5398A incorporates a power-on reset circuit, which
ensures the DAC output powers up to 0 V and remains there
until a valid write takes place. It has a power-down feature
that reduces the current consumption of the device to 0.5 µA
typically.

The AD5398A is designed for autofocus, image stabilization,
and optical zoom applications in camera phones, digital still
cameras, and camcorders. The AD5398A is also suitable for
many industrial applications, such as controlling temperature,
light, and movement without derating, over temperatures
ranging from −30°C to +85°C. The I
AD5398A is 0x18 to 0x1F inclusive.

2

C®-compatible) serial interface that operates

2

C address range for the

FUNCTIONAL BLOCK DIAGRAM

DD

REFERENCE

10-BIT

CURRENT

OUTPUT DAC

Figure 1.

SDA

SCL

PD

AD5398A

I2C SERIAL

INTERFACE

DGND

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

POWER-ON

RESET

V

DD

D1

R

R

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2008 Analog Devices, Inc. All rights reserved.

SENSE

3.3Ω

AGNDDGND

I

SINK

07795-001

AD5398A

TABLE OF CONTENTS

Features .............................................................................................. 1

Pin Configuration and Function Descriptions ..............................6

Consumer Applications ................................................................... 1

Industrial Applications .................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

AC Specifications .......................................................................... 4

Timing Specifications .................................................................. 4

Absolute Maximum Ratings ............................................................ 5

ESD Caution .................................................................................. 5

REVISION HISTORY

10/08—Revision 0: Initial Version

Typical Performance Characteristics ..............................................7

Terminology .......................................................................................9

Theory of Operation ...................................................................... 10

Serial Interface ............................................................................ 10

2

I

C Bus Operation ...................................................................... 10

Data Format ................................................................................ 11

Power Supply Bypassing and Grounding ................................ 12

Applications Information .............................................................. 13

Outline Dimensions ....................................................................... 14

Ordering Guide .......................................................................... 14

Rev. 0 | Page 2 of 16

AD5398A

SPECIFICATIONS

VDD = 2.7 V to 5.5 V, AGND = DGND = 0 V, load resistance (RL) = 25 Ω connected to VDD; all specifications T
unless otherwise noted.

MIN

to T

MAX

,

Table 1.

B Version

1

Parameter Min Typ Max Unit Test Conditions/Comments

DC PERFORMANCE

= 3.6 V to 4.5 V; device operates over 2.7 V to 5.5 V

V

DD

with reduced performance
Resolution 10 Bits 117 μA/LSB
Relative Accuracy
Differential Nonlinearity
Zero Code Error

2

2, 3

2, 4

0 0.5 1 mA All 0s loaded to DAC

±1.5 ±4 LSB

±1 LSB Guaranteed monotonic over all codes

Offset Error @ Code 162 0.5 mA
Gain Error2 ±0.6 % of FSR at 25°C
Offset Error Drift
Gain Error Drift

2, 4, 5

10 μA/°C

2, 5

±0.2 ±0.5 LSB/°C

OUTPUT CHARACTERISTICS

Minimum Sink Current4 3 mA
Maximum Sink Current 120 mA

= 3.6 V to 4.5 V; device operates over 2.7 V to 5.5 V;

V

DD

specified maximum sink current may not be achieved
Output Current During PD
Output Compliance5 0.6 VDD V

5

80 nA PD = 1

Output voltage range over which maximum 120 mA
sink current is available

Output Compliance

5

0.48 V

V

DD

Output voltage range over which 90 mA sink current
is available

Power-Up Time

LOGIC INPUT (PD)

5

20 μs To 10% of FS, coming out of power-down mode; V

5

DD

Input Current ±1 μA
Input Low Voltage, V
Input High Voltage, V

0.54 V VDD = 2.7 V to 5.5 V

INL

1.26 V VDD = 2.7 V to 5.5 V

INH

Pin Capacitance 3 pF

LOGIC INPUTS (SCL, SDA)5

Input Low Voltage, V
Input High Voltage, V
Input Low Voltage, V
Input High Voltage, V

−0.3 +0.54 V VDD = 2.7 V to 3.6 V

INL

1.26 VDD + 0.3 V VDD = 2.7 V to 3.6 V

INH

−0.3 +0.54 V VDD = 3.6 V to 5.5 V

INL

1.4 VDD + 0.3 V VDD = 3.6 V to 5.5 V

INH

Input Leakage Current, IIN ±1 μA VIN = 0 V to VDD
Input Hysteresis, V

0.05 VDD V

HYST

Digital Input Capacitance, CIN 6 pF
Glitch Rejection

6

50 ns Pulse width of spike suppressed

POWER REQUIREMENTS

VDD 2.7 5.5 V
IDD (Normal Mode) 0.5 1 mA

IDD (Power-Down Mode)

1

Temperature range for the B version is −30°C to +85°C.

2

See the Terminology section.

3

Linearity is tested using a reduced code range: Code 32 to Code 1023.

4

To achieve near zero output current, use the power-down feature.

5

Guaranteed by design and characterization; not production tested. PD is active high. SDA and SCL pull-up resistors are tied to 1.8 V.

6

Input filtering on both the SCL and SDA inputs suppresses noise spikes that are less than 50 ns.

7

PD is active high. When PD is taken high, the AD5389A enters power-down mode.

7

0.5 μA VIH = VDD, VIL = GND, VDD = 3 V

specification is valid for all DAC codes;

I

DD

= VDD, VIL = GND, VDD = 5.5 V

V

IH

= 5 V

Rev. 0 | Page 3 of 16

AD5398A

AC SPECIFICATIONS

VDD = 2.7 V to 5.5 V, AGND = DGND = 0 V, RL = 25 Ω connected to VDD, unless otherwise noted.

Table 2.

1, 2

B Version
Parameter Min Typ Max Unit Test Conditions/Comments

Output Current Settling Time 250 μs

= 5 V, RL = 25 Ω, LL = 680 μH

V

DD

¼ scale to ¾ scale change (0x100 to 0x300)
Slew Rate 0.3 mA/μs
Major Code Change Glitch Impulse 0.15 nA-sec 1 LSB change around major carry
Digital Feedthrough

1

Temperature range for the B version is –30°C to +85°C.

2

Guaranteed by design and characterization; not production tested.

3

See the Terminology section.

3

0.06 nA-sec

TIMING SPECIFICATIONS

VDD = 2.7 V to 5.5 V. All specifications T

Table 3.

Parameter

f

400 kHz max SCL clock frequency

SCL

1

B Version

Limit at T

MIN

, T

MAX

t1 2.5 μs min SCL cycle time
t2 0.6 μs min t
t3 1.3 μs min t
t4 0.6 μs min t
t5 100 ns min t

2

t

6

0.9 μs max t
0 μs min
t7 0.6 μs min t
t8 0.6 μs min t
t9 1.3 μs min t
t10 300 ns max tR, rise time of both SCL and SDA when receiving
0 ns min Can be CMOS driven
t11 250 ns max tF, fall time of SDA when receiving
300 ns max tF, fall time of both SCL and SDA when transmitting
20 + 0.1 C

3

b

Cb 400 pF max Capacitive load for each bus line

1

Guaranteed by design and characterization; not production tested.

2

A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH MIN of the SCL signal) to bridge the undefined region of the SCL

falling edge.

3

Cb is the total capacitance of one bus line in pF. tR and tF are measured between 0.3 VDD and 0.7 VDD.

Timing Diagram

to T

MIN

MAX

Unit

ns min

, unless otherwise noted.

Description

, SCL high time

HIGH

, SCL low time

LOW

, start/repeated start condition hold time

HD, STA

, data setup time

SU, DAT

, data hold time

HD, DAT

, setup time for repeated start

SU, STA

, stop condition setup time

SU, STO

, bus free time between a stop condition and a start condition

BUF

SDA

t

3

t

4

t

10

t

6

t

t

11

2

t

5

REPEATED

CONDITIO N

SCL

t

9

START

CONDITIO N

Figure 2. 2-Wire Serial Interface Timing Diagram

t

7

START

t

4

t

1

t

8

STOP

CONDITION

07795-002

Rev. 0 | Page 4 of 16

AD5398A

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.1

Table 4.

Parameter Rating

VDD to AGND −0.3 V to +7 V
VDD to DGND −0.3 V to VDD + 0.3 V
AGND to DGND −0.3 V to +0.3 V
SCL, SDA to DGND −0.3 V to VDD + 0.3 V
PD to DGND −0.3 V to VDD + 0.3 V
I

to AGND −0.3 V to VDD + 0.3 V

SINK

Operating Temperature Range

Industrial (B Version) −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Junction Temperature (TJ max) 150°C
θJA Thermal Impedance2

Mounted on 2-Layer Board 84°C/W

Mounted on 4-Layer Board 48°C/W
Lead Temperature, Soldering

Maximum Peak Reflow Temperature3 260°C (±5°C)

1

Transient currents of up to 100 mA do not cause SCR latch-up.

2

To achieve the optimum θJA, it is recommended that the AD5398A be

soldered onto a 4-layer board.

3

As per Jedec J-STD-020C.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability. Only one absolute maximum rating may be
applied at any one time.

ESD CAUTION

Rev. 0 | Page 5 of 16