Analog Devices AD5384 a Datasheet

40-Channel, 3 V/5 V, Single-Supply,

FEATURES

Guaranteed monotonic
INL error: ±4 LSB max
On-chip 1.25 V/2.5 V, 10 ppm/°C reference
Temperature range: –40°C to +85°C
Rail-to-rail output amplifier
Power-down
Package type: 100-lead CSPBGA (10 mm × 10 mm)
User Interfaces:

Serial (SPI-®/QSPI-™/MICROWIRE-™/DSP-compatible,

featuring data readback)

2

C-®compatible

I

FUNCTIONAL BLOCK DIAGRAM

DVDD (×3) DGND (×4) AVDD (×5) AGND (×5) DAC GND (×5) REFGND REFOUT/REFIN SIGNAL GND (×5)

PD
SYNC/AD 0
DCEN/AD 1

AD5384

Serial, 14-Bit Voltage Output DAC

AD5384

INTEGRATED FUNCTIONS

Channel monitor
Simultaneous output update via

Clear function to user-programmable code
Amplifier boost mode to optimize slew rate
User-programmable offset and gain adjust
Toggle mode enables square wave generation
Thermal monitor

APPLICATIONS

Variable optical attenuators (VOA)
Level setting (ATE)
Optical micro-electro-mechanical systems (MEMS)
Control systems
Instrumentation

1.25V/2.5V

REFERENCE

LDAC

INPUT
REG 0

SDO

DIN/SDA

SCLK/SCL

SPI/I2C

RESET

BUSY

CLR

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

INTERFACE

CONTROL

LOGIC

POWER-ON

RESET

VOUT0……VOUT38

39-TO-1

MUX

VOUT39/MON_OUT LDAC

STATE

MACHINE

+

CONTROL

LOGIC

14
14

INPUT
REG 1

14
14

INPUT
REG 6

14
14

INPUT
REG 7

14
14

m REG 0

c REG 0

m REG 1

c REG 1

m REG 6

c REG 6

m REG 7

c REG 7

Figure 1.

1414 1414

×5

DAC

REG 0

DAC

REG 1

DAC

REG 6

DAC

REG 7

DAC 0

R

R

1414 1414

DAC 1

R

R

1414 1414

DAC 6

R

R

1414 1414

DAC 7

R

R

VOUT0

VOUT1
VOUT2
VOUT3
VOUT4
VOUT5
VOUT6

VOUT7
VOUT8

VOUT38

04652-0-001

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]

www.analog.com

Fax: [phone] © 2004 Analog Devices, Inc. All rights reserved.

AD5384

TABLE OF CONTENTS

General Description......................................................................... 3

Reset Function............................................................................ 25

Specifications..................................................................................... 4

AD5384-5 Specifications............................................................. 4

AC Characteristics........................................................................ 6

AD5384-3 Specifications............................................................. 7

AC Characteristics........................................................................ 9

Timing Characteristics................................................................... 10

Serial Interface............................................................................ 10

2

I

C Serial Interface......................................................................12

Absolute Maximum Ratings.......................................................... 13

Pin Configuration and Function Descriptions........................... 14

Te r mi n ol o g y .................................................................................... 17

Typical Performance Characteristics........................................... 18

Functional Description .................................................................. 21

DAC Architecture—General..................................................... 21

Data Decoding............................................................................ 21

Asynchronous Clear Function.................................................. 25

BUSY

Power-On Reset .......................................................................... 25

Power-Down ............................................................................... 25

Interfaces.......................................................................................... 26

DSP-, SPI-, Microwire-Compatible Serial Interfaces ............ 26

2

I

C Serial Interface..................................................................... 28

Microprocessor Interfacing....................................................... 31

Application Information................................................................ 32

Power Supply Decoupling .........................................................32

Monitor Function....................................................................... 32

Toggle Mode Function............................................................... 32

Thermal Monitor Function....................................................... 33

AD5384 in a MEMS-Based Optical Switch ............................33

Optical Attenuators.................................................................... 34

and

LDAC

Functions...................................................... 25

On-Chip Special Function Registers (SFR) ............................22

SFR Commands.......................................................................... 22

Hardware Functions .......................................................................25

REVISION HISTORY

10/04—Changed from Rev. 0 to Rev. A

Changes to Table 19........................................................................ 24

Changes to Ordering Guide.......................................................... 35

7/04—Revision 0: Initial Version

Outline Dimensions .......................................................................35

Ordering Guide .......................................................................... 35

Rev. A | Page 2 of 36

AD5384

GENERAL DESCRIPTION

The AD5384 is a complete single-supply, 40-channel, 14-bit
DAC available in a 100-lead CSPBGA package. All 40 channels
have an on-chip output amplifier with rail-to-rail operation.
The AD5384 includes an internal 1.25 V/2.5 V, 10 ppm/°C
reference, an on-chip channel monitor function that multiplexes
the analog outputs to a common MON_OUT pin for external
monitoring, and an output amplifier boost mode that allows the
amplifier slew rate to be optimized. The AD5384 contains a
serial interface compatible with SPI, QSPI, MICROWIRE, and

Table 1. Complete Family of High Channel Count, Low Voltage, Single-Supply DACs in Portfolio

Model Resolution AVDD Range Output Channels Linearity Error (LSB) Package Description Package Option

AD5380BST-5 14 Bits 4.5 V to 5.5 V 40 ±4 100-Lead LQFP ST-100
AD5380BST-3 14 Bits 2.7 V to 3.6 V 40 ±4 100-Lead LQFP ST-100
AD5381BST-5 12 Bits 4.5 V to 5.5 V 40 ±1 100-Lead LQFP ST-100
AD5381BST-3 12 Bits 2.7 V to 3.6 V 40 ±1 100-Lead LQFP ST-100
AD5384BBC-5 14 Bits 4.5 V to 5.5 V 40 ±4 100-Lead CSPBGA BC-100
AD5384BBC-3 14 Bits 2.7 V to 3.6 V 40 ±4 100-Lead CSPBGA BC-100
AD5382BST-5 14 Bits 4.5 V to 5.5 V 32 ±4 100-Lead LQFP ST-100
AD5382BST-3 14 Bits 2.7 V to 3.6 V 32 ±4 100-Lead LQFP ST-100
AD5383BST-5 12 Bits 4.5 V to 5.5 V 32 ±1 100-Lead LQFP ST-100
AD5383BST-3 12 Bits 2.7 V to 3.6 V 32 ±1 100-Lead LQFP ST-100
AD5390BST-5 14 Bits 4.5 V to 5.5 V 16 ±3 52-Lead LQFP ST-52
AD5390BCP-5 14 Bits 4.5 V to 5.5 V 16 ±3 64-Lead LFCSP CP-64
AD5390BST-3 14 Bits 2.7 V to 3.6 V 16 ±4 52-Lead LQFP ST-52
AD5390BCP-3 14 Bits 2.7 V to 3.6 V 16 ±4 64-Lead LFCSP CP-64
AD5391BST-5 12 Bits 4.5 V to 5.5 V 16 ±1 52-Lead LQFP ST-52
AD5391BCP-5 12 Bits 4.5 V to 5.5 V 16 ±1 64-Lead LFCSP CP-64
AD5391BST-3 12 Bits 2.7 V to 3.6 V 16 ±1 52-Lead LQFP ST-52
AD5391BCP-3 12 Bits 2.7 V to 3.6 V 16 ±1 64-Lead LFCSP CP-64
AD5392BST-5 14 Bits 4.5 V to 5.5 V 8 ±3 52-Lead LQFP ST-52
AD5392BCP-5 14 Bits 4.5 V to 5.5 V 8 ±3 64-Lead LFCSP CP-64
AD5392BST-3 14 Bits 2.7 V to 3.6 V 8 ±4 52-Lead LQFP ST-52
AD5392BCP-3 14 Bits 2.7 V to 3.6 V 8 ±4 64-Lead LFCSP CP-64

DSP interface standards with interface speeds in excess of

2

30 MHz and an I

C-compatible interface supporting 400 kHz
data transfer rate. An input register followed by a DAC register
provides double buffering, allowing the DAC outputs to be
updated independently or simultaneously. using the

LDAC
input. Each channel has a programmable gain and offset adjust
register letting the user fully calibrate any DAC channel. Power

consumption is typically 0.25 mA/channel with boost mode off.

Table 2. 40-Channel, Bipolar Voltage Output DAC

Model Resolution Analog Supplies Output Channels Linearity Error (LSB) Package Package Option

AD5379ABC 14 Bits ±11.4 V to ±16.5 V 40 ±3 108-Lead CSPBGA BC-108

Rev. A | Page 3 of 36

AD5384

SPECIFICATIONS

AD5384-5 SPECIFICATIONS

AVDD = 4.5 V to 5.5 V; DVDD = 2.7 V to 5.5 V, AGND = DGND = 0 V; external REFIN = 2.5 V; all specifications T
otherwise noted.

Table 3.

Parameter AD5384-51 Unit Test Conditions/Comments

ACCURACY

Resolution 14 Bits
Relative Accuracy2 (INL) ±4 LSB max ±1 LSB typical
Differential Nonlinearity (DNL) –1/+2 LSB max Guaranteed monotonic by design over temperature
Zero-Scale Error 4 mV max

Offset Error ±4 mV max Measured at code 32 in the linear region

Offset Error TC ±5 µV/°C typ
Gain Error ±0.024 % FSR max At 25°C
±0.06 % FSR max T
Gain Temperature Coefficient
DC Crosstalk

3

3

2 ppm FSR/°C typ

0.5 LSB max

MIN

to T

MAX

REFERENCE INPUT/OUTPUT

Reference Input

3

Reference Input Voltage 2.5 V ±1% for specified performance, AVDD = 2 × REFIN + 50 mV
DC Input Impedance 1 MΩ min Typically 100 MΩ
Input Current ±1 µA max Typically ±30 nA
Reference Range 1 to VDD/2 V min/max

Reference Output

4

Enabled via CR10 in the AD5384 control register, CR12,
selects the output voltage.

Output Voltage 2.495/2.505 V min/max At ambient; CR12 = 1; optimized for 2.5 V operation

1.22/1.28 V min/max CR12 = 0
Reference TC ±10 ppm/°C max Temperature range: +25°C to +85°C
±15 ppm/°C max Temperature range: −40°C to +85°C

OUTPUT CHARACTERISTICS

Output Voltage Range

3

2

0/AV

DD

V min/max
Short-Circuit Current 40 mA max
Load Current ±1 mA max
Capacitive Load Stability

RL = ∞ 200 pF max
RL = 5 kΩ 1000 pF max

DC Output Impedance 0.5 Ω max

MONITOR PIN

Output Impedance 500 Ω typ
Three-State Leakage Current 100 nA typ

LOGIC INPUTS (EXCEPT SDA/SCL)

3

DVDD = 2.7 V to 5.5 V
VIH, Input High Voltage 2 V min
VIL, Input Low Voltage 0.8 V max
Input Current ±10 µA max Total for all pins. TA = T

MIN

to T

Pin Capacitance 10 pF max

LOGIC INPUTS (SDA, SCL ONLY)

VIH, Input High Voltage 0.7 DVDD V min SMBus-compatible at DVDD < 3.6 V
VIL, Input Low Voltage 0.3 DVDD V max SMBus-compatible at DVDD < 3.6 V
IIN, Input Leakage Current ±1 µA max
V

, Input Hysteresis 0.05 DVDD V min

HYST

CIN, Input Capacitance 8 pF typ
Glitch Rejection 50 ns max Input filtering suppresses noise spikes of less than 50 ns

MAX

MIN

to T

MAX

, unless

Rev. A | Page 4 of 36

AD5384

Parameter AD5384-51 Unit Test Conditions/Comments

LOGIC OUTPUTS (BUSY, SDO)3

VOL, Output Low Voltage 0.4 V max DVDD = 5 V ± 10%, sinking 200 µA
VOH, Output High Voltage DVDD – 1 V min DVDD = 5 V ± 10%, sourcing 200 µA
VOL, Output Low Voltage 0.4 V max DVDD = 2.7 V to 3.6 V, sinking 200 µA
VOH, Output High Voltage DVDD – 0.5 V min DVDD = 2.7 V to 3.6 V, sourcing 200 µA
High Impedance Leakage Current ±1 µA max SDO only
High Impedance Output Capacitance 5 pF typ SDO only

LOGIC OUTPUT (SDA)3

VOL, Output Low Voltage 0.4 V max I

0.6 V max I
Three-State Leakage Current ±1 µA max
Three-State Output Capacitance 8 pF typ

POWER REQUIREMENTS

AVDD 4.5/5.5 V min/max
DVDD 2.7/5.5 V min/max
Power Supply Sensitivity3

∆Midscale/∆ΑVDD –85 dB typ

AIDD 0.375 mA/channel max Outputs unloaded, boost off; 0.25 mA/channel typ

0.475 mA/channel max Outputs unloaded, boost on; 0.32 5mA/channel typ
DIDD 1 mA max VIH = DVDD, VIL = DGND
AIDD (Power-Down) 2 µA max Typically 200 nA
DIDD (Power-Down) 20 µA max Typically 3 µA
Power Dissipation 80 mW max Outputs unloaded, boost off, AVDD = DVDD = 5 V

1

AD5384-5 is calibrated using an external 2.5 V reference. Temperature range for all versions: –40°C to +85°C.

2

Accuracy guaranteed from V

3

Guaranteed by characterization, not production tested.

4

Default on the AD5384-5 is 2.5 V. Programmable to 1.25 V via CR12 in the AD5384 control register; operating the AD5384-5 with a 1.25 V reference will lead to

degraded accuracy specifications.

= 10 mV to AVDD – 50 mV.

OUT

= 3 mA

SINK

= 6 mA

SINK

Rev. A | Page 5 of 36

AD5384

AC CHARACTERISTICS

AVDD = 2.7 V to 3.6 V; DVDD = 2.7 V to 5.5 V, AGND = DGND = 0 V.

Table 4.

Parameter AD5384-5 Unit Test Conditions/Comments

DYNAMIC PERFORMANCE

Output Voltage Settling Time

8 µs typ

10 µs max

Slew Rate

3 V/µs typ Boost mode on, CR11 = 1

Digital-to-Analog Glitch Energy 12 nV-s typ
Glitch Impulse Peak Amplitude 15 mV typ
Channel-to-Channel Isolation 100 dB typ See the Terminology section
DAC-to-DAC Crosstalk 1 nV-s typ See the Terminology section
Digital Crosstalk 0.8 nV-s typ
Digital Feedthrough 0.1 nV-s typ Effect of input bus activity on DAC output under test
Output Noise 0.1 Hz to 10 Hz 15 µV p-p typ External reference, midscale loaded to DAC
40 µV p-p typ Internal reference, midscale loaded to DAC
Output Noise Spectral Density

1

Guaranteed by design and characterization, not production tested.

2

The slew rate can be programmed via the current boost control bit (CR11) in the AD5384 control register.

2

@ 1 kHz 150 nV/√Hz typ
@ 10 kHz 100 nV/√Hz typ

1

Boost mode off, CR11 = 0
1/4 scale to 3/4 scale change settling to ±1 LSB

2 V/µs typ Boost mode off, CR11 = 0

Rev. A | Page 6 of 36

AD5384

AD5384-3 SPECIFICATIONS

AVDD = 2.7 V to 3.6 V; DVDD = 2.7 V to 5.5 V, AGND = DGND = 0 V; external REFIN = 1.25 V; all specifications T
unless otherwise noted.

Table 5.

Parameter AD5384-31Unit Test Conditions/Comments

ACCURACY

Resolution 14 Bits
Relative Accuracy2 ±4 LSB max
Differential Nonlinearity –1/+2 LSB max Guaranteed monotonic over temperature
Zero-Scale Error 4 mV max
Offset Error ±4 mV max Measured at Code 64 in the linear region
Offset Error TC ±5 µV/°C typ
Gain Error ±0.024 % FSR max At 25°C
±0.1 % FSR max T
Gain Temperature Coefficient
DC Crosstalk

3

3

2 ppm FSR/°C typ

0.5 LSB max

MIN

to T

MAX

REFERENCE INPUT/OUTPUT

Reference Input

3

Reference Input Voltage 1.25 V ±1% for specified performance
DC Input Impedance 1 MΩ min Typically 100 MΩ
Input Current ±1 µA max Typically ±30 nA
Reference Range 1 to AVDD/2 V min/max

Reference Output

4

Output Voltage 1.245/1.255 V min/max At ambient; CR12 = 0; optimized for 1.25 V operation

2.47/2.53 V min/max CR12 = 1

Reference TC ±10 ppm/°C max Temperature range: +25°C to +85°C

OUTPUT CHARACTERISTICS

Output Voltage Range

2

±15 ppm/°C max

3

0/AV

DD

V min/max

Temperature range: −40°C to +85°C

Short-Circuit Current 40 mA max
Load Current ±1 mA max
Capacitive Load Stability

RL = ∞ 200 pF max
RL = 5 kΩ 1000 pF max

DC Output Impedance 0.5 Ω max

MONITOR PIN

Output Impedance 500 Ω typ
Three-State Leakage Current 100 nA typ

LOGIC INPUTS (EXCEPT SDA/SCL)3 DVDD = 2.7 V to 3.6 V

VIH, Input High Voltage 2 V min
V

Input Low Voltage 0.8 V max

IL,

Input Current ±10 µA max Total for all pins; TA = T

MIN

to T

MAX

Pin Capacitance 10 pF max

LOGIC INPUTS (SDA, SCL ONLY)

VIH, Input High Voltage 0.7 DV
VIL, Input Low Voltage 0.3 DV

DD

DD

V min SMBus-compatible at DVDD < 3.6 V

V max SMBus-compatible at DVDD < 3.6 V
IIN, Input Leakage Current ±1 µA max
V

, Input Hysteresis 0.05 DV

HYST

V min

DD

CIN, Input Capacitance 8 pF typ
Glitch Rejection 50 ns max Input filtering suppresses noise spikes of less than 50 ns

MIN

to T

MAX

,

Rev. A | Page 7 of 36

AD5384

Parameter AD5384-31Unit Test Conditions/Comments

LOGIC OUTPUTS (BUSY, SDO)3

VOL, Output Low Voltage 0.4 V max Sinking 200 µA
VOH, Output High Voltage DVDD – 0.5 V min Sourcing 200 µA
High Impedance Leakage Current ±1 µA max SDO only
High Impedance Output Capacitance 5 pF typ SDO only

LOGIC OUTPUT (SDA)

3

VOL, Output Low Voltage 0.4 V max I

0.6 V max I
Three-State Leakage Current ±1 µA max
Three-State Output Capacitance 8 pF typ

POWER REQUIREMENTS

AV

DD

DV

DD

Power Supply Sensitivity

∆Midscale/∆ΑV

AI

DD

3

DD

0.475 mA/channel max Outputs unloaded, boost on; 0.325 mA/channel typ
DI

DD

AIDD (Power-Down) 2 µA max Typically 200 nA
DIDD (Power-Down) 20 µA max Typically 1 µA
Power Dissipation 48 mW max Outputs unloaded, boost off, AVDD = DVDD = 3 V

1

AD5384-3 is calibrated using an external 1.25 V reference. Temperature range is –40°C to +85°C.

2

Accuracy guaranteed from V

3

Guaranteed by characterization, not production tested.

4

Default on the AD5384-3 is 1.25 V. Programmable to 2.5 V via CR12 in the AD5384 control register; operating the AD5384-3 with a 2.5 V reference will lead to degraded

accuracy specifications and limited input code range.

= 10 mV to AVDD – 50 mV.

OUT

= 3 mA

SINK

= 6 mA

SINK

2.7/3.6 V min/max

2.7/3.6 V min/max

–85 dB typ

0.375 mA/channel max Outputs unloaded, boost off; 0.25 mA/channel typ

1 mA max VIH = DVDD, VIL = DGND

Rev. A | Page 8 of 36

AD5384

AC CHARACTERISTICS

AVDD = 2.7 V to 3.6 V and 4.5 V to 5.5 V; DVDD = 2.7 V to 5.5 V; AGND = DGND = 0 V.

Table 6.

Parameter AD5384-3 Unit Test Conditions/Comments

DYNAMIC PERFORMANCE

Output Voltage Settling Time

8 µs typ

10 µs max

Slew Rate

3 V/µs typ Boost mode on, CR11 = 1

Digital-to-Analog Glitch Energy 12 nV-s typ
Glitch Impulse Peak Amplitude 15 mV typ
Channel-to-Channel Isolation 100 dB typ See the Terminology section
DAC-to-DAC Crosstalk 1 nV-s typ See the Terminology section
Digital Crosstalk 0.8 nV-s typ
Digital Feedthrough 0.1 nV-s typ Effect of input bus activity on DAC output under test
Output Noise 0.1 Hz to 10 Hz 15 µV p-p typ External reference, midscale loaded to DAC
40 µV p-p typ Internal reference, midscale loaded to DAC
Output Noise Spectral Density

1

Guaranteed by design and characterization, not production tested.

2

The slew rate can be programmed via the current boost control bit (CR11 ) in the AD5384 control register.

2

@ 1 kHz 150 nV/√Hz typ
@ 10 kHz 100 nV/√Hz typ

1

Boost mode off, CR11 = 0
1/4 scale to 3/4 scale change settling to ±1 LSB

2 V/µs typ Boost mode off, CR11 = 0

Rev. A | Page 9 of 36

AD5384

T

TIMING CHARACTERISTICS

SERIAL INTERFACE

DVDD = 2.7 V to 5.5 V; AVDD = 4.5 V to 5.5 V or 2.7 V to 3.6 V; AGND = DGND = 0 V; all specifications T
unless otherwise noted.

MIN

to T

MAX

,

Table 7.

Parameter

1, 2, 3

Limit at T

MIN

, T

MAX

Unit Description

t1 33 ns min SCLK cycle time
t

2

13 ns min SCLK high time
t3 13 ns min SCLK low time
t4 13 ns min
t5 4 13 ns min

4

t

6

33 ns min
t7 10 ns min
t7A 50 ns min

SYNC falling edge to SCLK falling edge setup time

th

SCLK falling edge to SYNC falling edge

24
Minimum
Minimum
Minimum

SYNC low time
SYNC high time

SYNC high time in readback mode
t8 5 ns min Data setup time
t9 4.5 ns min Data hold time

4

t

30 ns max

10

t11 670 ns max

4

t

12

20 ns min
t13 20 ns min
t14 100 ns max
t15 0 ns min
t16 100 ns min

24th SCLK falling edge to
BUSY pulse width low (single channel update)
24th SCLK falling edge to
LDAC pulse width low
BUSY rising edge to DAC output response time
BUSY rising edge to LDAC falling edge
LDAC falling edge to DAC output response time

BUSY falling edge

LDAC falling edge

t17 8 µs typ DAC output settling time boost mode off
t18 20 ns min

t

19

5

t

20

5

t

21

5

t

22

t

23

12 µs max

20 ns max SCLK rising edge to SDO valid

5 ns min

8 ns min

20 ns min

CLR pulse width low
CLR pulse activation time

SCLK falling edge to

SYNC rising edge
SYNC rising edge to SCLK rising edge
SYNC rising edge to LDAC falling edge

1

Guaranteed by design and characterization, not production tested.

2

All input signals are specified with t

3

See , F , and . Figure 2 igure 3 Figure 5, Figure 6

4

Standalone mode only.

5

Daisy-chain mode only.

= t

= 5 ns (10% to 90% of DVDD), and are timed from a voltage level of 1.2 V.

r

f

O OUTPUT PIN

Figure 2. Load Circuit for Digital Output Timing

200µA

C

L

50pF

200µA

Rev. A | Page 10 of 36

I

OL

I

OH

V

OH

V

OL

(MIN) OR

(MAX)

04652-0-003

AD5384

t

1

SCLK

SYNC

t

DIN

BUSY

1

LDAC

1

V

OUT

2

LDAC

2

V

OUT

CLR

V

OUT

1

LDAC ACTIVE DURING BUSY

2

LDAC ACTIVE AFTER BUSY

7

t

4

DB23

t8t

t

3

t

6

9

t

2

t

5

DB0

t

10

t

11

t

12

t

18

t

19

t

13

t

15

242412

t

17

t

14

t

13

t

17

t

16

04652-0-004

Figure 3. Serial Interface Timing Diagram (Standalone Mode)

24 48SCLK

t

7A

SYNC

DIN

SDO

SCLK

SYNC

DIN

SDO

DB23 DB0 DB23 DB0

INPUT WORD SPECIFIES

REGISTER TO BE READ

NOP CONDITION

DB23 DB0

UNDEFINED

SELECTED REGISTER

DATA CLOCKED OUT

Figure 4. Serial Interface Timing Diagram (Data Readback Mode)

t

1

t

t

7

t

4

t8t

3

9

DB23 DB0 DB23 DB0

INPUT WORD FOR DAC N

24 48

t

2

INPUT WORD FOR DAC N + 1

t

20

DB23 DB0

03731-0-005

t

t

22

21

UNDEFINED

INPUT WORD FOR DAC N

LDAC

Figure 5. Serial Interface Timing Diagram (Daisy-Chain Mode)

t

13

t

23

04652-0-005

Rev. A | Page 11 of 36