Datasheet AD5384 Datasheet (Analog Devices)

40-Channel, 3 V/5 V, Single-Supply,

FEATURES

Guaranteed monotonic
INL error: ±4 LSB max
On-chip 1.25 V/2.5 V, 10 ppm/°C reference
Temperature range: –40°C to +85°C
Rail-to-rail output amplifier
Power-down
Package type: 100-lead CSPBGA (10 mm × 10 mm)
User Interfaces:

Serial (SPI-®/QSPI-™/MICROWIRE-™/DSP-compatible,

featuring data readback)

2

C-®compatible

I

FUNCTIONAL BLOCK DIAGRAM

DVDD (×3) DGND (×4) AVDD (×5) AGND (×5) DAC GND (×5) REFGND REFOUT/REFIN SIGNAL GND (×5)

PD
SYNC/AD 0
DCEN/AD 1

AD5384

Serial, 14-Bit Voltage Output DAC

AD5384

INTEGRATED FUNCTIONS

Channel monitor
Simultaneous output update via

Clear function to user-programmable code
Amplifier boost mode to optimize slew rate
User-programmable offset and gain adjust
Toggle mode enables square wave generation
Thermal monitor

APPLICATIONS

Variable optical attenuators (VOA)
Level setting (ATE)
Optical micro-electro-mechanical systems (MEMS)
Control systems
Instrumentation

1.25V/2.5V

REFERENCE

LDAC

INPUT
REG 0

SDO

DIN/SDA

SCLK/SCL

SPI/I2C

RESET

BUSY

CLR

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

INTERFACE

CONTROL

LOGIC

POWER-ON

RESET

VOUT0……VOUT38

39-TO-1

MUX

VOUT39/MON_OUT LDAC

STATE

MACHINE

+

CONTROL

LOGIC

14
14

INPUT
REG 1

14
14

INPUT
REG 6

14
14

INPUT
REG 7

14
14

m REG 0

c REG 0

m REG 1

c REG 1

m REG 6

c REG 6

m REG 7

c REG 7

Figure 1.

1414 1414

×5

DAC

REG 0

DAC

REG 1

DAC

REG 6

DAC

REG 7

DAC 0

R

R

1414 1414

DAC 1

R

R

1414 1414

DAC 6

R

R

1414 1414

DAC 7

R

R

VOUT0

VOUT1
VOUT2
VOUT3
VOUT4
VOUT5
VOUT6

VOUT7
VOUT8

VOUT38

04652-0-001

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]

www.analog.com

Fax: [phone] © 2004 Analog Devices, Inc. All rights reserved.

AD5384

TABLE OF CONTENTS

General Description......................................................................... 3

Reset Function............................................................................ 25

Specifications..................................................................................... 4

AD5384-5 Specifications............................................................. 4

AC Characteristics........................................................................ 6

AD5384-3 Specifications............................................................. 7

AC Characteristics........................................................................ 9

Timing Characteristics................................................................... 10

Serial Interface............................................................................ 10

2

I

C Serial Interface......................................................................12

Absolute Maximum Ratings.......................................................... 13

Pin Configuration and Function Descriptions........................... 14

Te r mi n ol o g y .................................................................................... 17

Typical Performance Characteristics........................................... 18

Functional Description .................................................................. 21

DAC Architecture—General..................................................... 21

Data Decoding............................................................................ 21

Asynchronous Clear Function.................................................. 25

BUSY

Power-On Reset .......................................................................... 25

Power-Down ............................................................................... 25

Interfaces.......................................................................................... 26

DSP-, SPI-, Microwire-Compatible Serial Interfaces ............ 26

2

I

C Serial Interface..................................................................... 28

Microprocessor Interfacing....................................................... 31

Application Information................................................................ 32

Power Supply Decoupling .........................................................32

Monitor Function....................................................................... 32

Toggle Mode Function............................................................... 32

Thermal Monitor Function....................................................... 33

AD5384 in a MEMS-Based Optical Switch ............................33

Optical Attenuators.................................................................... 34

and

LDAC

Functions...................................................... 25

On-Chip Special Function Registers (SFR) ............................22

SFR Commands.......................................................................... 22

Hardware Functions .......................................................................25

REVISION HISTORY

10/04—Changed from Rev. 0 to Rev. A

Changes to Table 19........................................................................ 24

Changes to Ordering Guide.......................................................... 35

7/04—Revision 0: Initial Version

Outline Dimensions .......................................................................35

Ordering Guide .......................................................................... 35

Rev. A | Page 2 of 36

AD5384

GENERAL DESCRIPTION

The AD5384 is a complete single-supply, 40-channel, 14-bit
DAC available in a 100-lead CSPBGA package. All 40 channels
have an on-chip output amplifier with rail-to-rail operation.
The AD5384 includes an internal 1.25 V/2.5 V, 10 ppm/°C
reference, an on-chip channel monitor function that multiplexes
the analog outputs to a common MON_OUT pin for external
monitoring, and an output amplifier boost mode that allows the
amplifier slew rate to be optimized. The AD5384 contains a
serial interface compatible with SPI, QSPI, MICROWIRE, and

Table 1. Complete Family of High Channel Count, Low Voltage, Single-Supply DACs in Portfolio

Model Resolution AVDD Range Output Channels Linearity Error (LSB) Package Description Package Option

AD5380BST-5 14 Bits 4.5 V to 5.5 V 40 ±4 100-Lead LQFP ST-100
AD5380BST-3 14 Bits 2.7 V to 3.6 V 40 ±4 100-Lead LQFP ST-100
AD5381BST-5 12 Bits 4.5 V to 5.5 V 40 ±1 100-Lead LQFP ST-100
AD5381BST-3 12 Bits 2.7 V to 3.6 V 40 ±1 100-Lead LQFP ST-100
AD5384BBC-5 14 Bits 4.5 V to 5.5 V 40 ±4 100-Lead CSPBGA BC-100
AD5384BBC-3 14 Bits 2.7 V to 3.6 V 40 ±4 100-Lead CSPBGA BC-100
AD5382BST-5 14 Bits 4.5 V to 5.5 V 32 ±4 100-Lead LQFP ST-100
AD5382BST-3 14 Bits 2.7 V to 3.6 V 32 ±4 100-Lead LQFP ST-100
AD5383BST-5 12 Bits 4.5 V to 5.5 V 32 ±1 100-Lead LQFP ST-100
AD5383BST-3 12 Bits 2.7 V to 3.6 V 32 ±1 100-Lead LQFP ST-100
AD5390BST-5 14 Bits 4.5 V to 5.5 V 16 ±3 52-Lead LQFP ST-52
AD5390BCP-5 14 Bits 4.5 V to 5.5 V 16 ±3 64-Lead LFCSP CP-64
AD5390BST-3 14 Bits 2.7 V to 3.6 V 16 ±4 52-Lead LQFP ST-52
AD5390BCP-3 14 Bits 2.7 V to 3.6 V 16 ±4 64-Lead LFCSP CP-64
AD5391BST-5 12 Bits 4.5 V to 5.5 V 16 ±1 52-Lead LQFP ST-52
AD5391BCP-5 12 Bits 4.5 V to 5.5 V 16 ±1 64-Lead LFCSP CP-64
AD5391BST-3 12 Bits 2.7 V to 3.6 V 16 ±1 52-Lead LQFP ST-52
AD5391BCP-3 12 Bits 2.7 V to 3.6 V 16 ±1 64-Lead LFCSP CP-64
AD5392BST-5 14 Bits 4.5 V to 5.5 V 8 ±3 52-Lead LQFP ST-52
AD5392BCP-5 14 Bits 4.5 V to 5.5 V 8 ±3 64-Lead LFCSP CP-64
AD5392BST-3 14 Bits 2.7 V to 3.6 V 8 ±4 52-Lead LQFP ST-52
AD5392BCP-3 14 Bits 2.7 V to 3.6 V 8 ±4 64-Lead LFCSP CP-64

DSP interface standards with interface speeds in excess of

2

30 MHz and an I

C-compatible interface supporting 400 kHz
data transfer rate. An input register followed by a DAC register
provides double buffering, allowing the DAC outputs to be
updated independently or simultaneously. using the

LDAC
input. Each channel has a programmable gain and offset adjust
register letting the user fully calibrate any DAC channel. Power

consumption is typically 0.25 mA/channel with boost mode off.

Table 2. 40-Channel, Bipolar Voltage Output DAC

Model Resolution Analog Supplies Output Channels Linearity Error (LSB) Package Package Option

AD5379ABC 14 Bits ±11.4 V to ±16.5 V 40 ±3 108-Lead CSPBGA BC-108

Rev. A | Page 3 of 36

AD5384

SPECIFICATIONS

AD5384-5 SPECIFICATIONS

AVDD = 4.5 V to 5.5 V; DVDD = 2.7 V to 5.5 V, AGND = DGND = 0 V; external REFIN = 2.5 V; all specifications T
otherwise noted.

Table 3.

Parameter AD5384-51 Unit Test Conditions/Comments

ACCURACY

Resolution 14 Bits
Relative Accuracy2 (INL) ±4 LSB max ±1 LSB typical
Differential Nonlinearity (DNL) –1/+2 LSB max Guaranteed monotonic by design over temperature
Zero-Scale Error 4 mV max

Offset Error ±4 mV max Measured at code 32 in the linear region

Offset Error TC ±5 µV/°C typ
Gain Error ±0.024 % FSR max At 25°C
±0.06 % FSR max T
Gain Temperature Coefficient
DC Crosstalk

3

3

2 ppm FSR/°C typ

0.5 LSB max

MIN

to T

MAX

REFERENCE INPUT/OUTPUT

Reference Input

3

Reference Input Voltage 2.5 V ±1% for specified performance, AVDD = 2 × REFIN + 50 mV
DC Input Impedance 1 MΩ min Typically 100 MΩ
Input Current ±1 µA max Typically ±30 nA
Reference Range 1 to VDD/2 V min/max

Reference Output

4

Enabled via CR10 in the AD5384 control register, CR12,
selects the output voltage.

Output Voltage 2.495/2.505 V min/max At ambient; CR12 = 1; optimized for 2.5 V operation

1.22/1.28 V min/max CR12 = 0
Reference TC ±10 ppm/°C max Temperature range: +25°C to +85°C
±15 ppm/°C max Temperature range: −40°C to +85°C

OUTPUT CHARACTERISTICS

Output Voltage Range

3

2

0/AV

DD

V min/max
Short-Circuit Current 40 mA max
Load Current ±1 mA max
Capacitive Load Stability

RL = ∞ 200 pF max
RL = 5 kΩ 1000 pF max

DC Output Impedance 0.5 Ω max

MONITOR PIN

Output Impedance 500 Ω typ
Three-State Leakage Current 100 nA typ

LOGIC INPUTS (EXCEPT SDA/SCL)

3

DVDD = 2.7 V to 5.5 V
VIH, Input High Voltage 2 V min
VIL, Input Low Voltage 0.8 V max
Input Current ±10 µA max Total for all pins. TA = T

MIN

to T

Pin Capacitance 10 pF max

LOGIC INPUTS (SDA, SCL ONLY)

VIH, Input High Voltage 0.7 DVDD V min SMBus-compatible at DVDD < 3.6 V
VIL, Input Low Voltage 0.3 DVDD V max SMBus-compatible at DVDD < 3.6 V
IIN, Input Leakage Current ±1 µA max
V

, Input Hysteresis 0.05 DVDD V min

HYST

CIN, Input Capacitance 8 pF typ
Glitch Rejection 50 ns max Input filtering suppresses noise spikes of less than 50 ns

MAX

MIN

to T

MAX

, unless

Rev. A | Page 4 of 36

AD5384

Parameter AD5384-51 Unit Test Conditions/Comments

LOGIC OUTPUTS (BUSY, SDO)3

VOL, Output Low Voltage 0.4 V max DVDD = 5 V ± 10%, sinking 200 µA
VOH, Output High Voltage DVDD – 1 V min DVDD = 5 V ± 10%, sourcing 200 µA
VOL, Output Low Voltage 0.4 V max DVDD = 2.7 V to 3.6 V, sinking 200 µA
VOH, Output High Voltage DVDD – 0.5 V min DVDD = 2.7 V to 3.6 V, sourcing 200 µA
High Impedance Leakage Current ±1 µA max SDO only
High Impedance Output Capacitance 5 pF typ SDO only

LOGIC OUTPUT (SDA)3

VOL, Output Low Voltage 0.4 V max I

0.6 V max I
Three-State Leakage Current ±1 µA max
Three-State Output Capacitance 8 pF typ

POWER REQUIREMENTS

AVDD 4.5/5.5 V min/max
DVDD 2.7/5.5 V min/max
Power Supply Sensitivity3

∆Midscale/∆ΑVDD –85 dB typ

AIDD 0.375 mA/channel max Outputs unloaded, boost off; 0.25 mA/channel typ

0.475 mA/channel max Outputs unloaded, boost on; 0.32 5mA/channel typ
DIDD 1 mA max VIH = DVDD, VIL = DGND
AIDD (Power-Down) 2 µA max Typically 200 nA
DIDD (Power-Down) 20 µA max Typically 3 µA
Power Dissipation 80 mW max Outputs unloaded, boost off, AVDD = DVDD = 5 V

1

AD5384-5 is calibrated using an external 2.5 V reference. Temperature range for all versions: –40°C to +85°C.

2

Accuracy guaranteed from V

3

Guaranteed by characterization, not production tested.

4

Default on the AD5384-5 is 2.5 V. Programmable to 1.25 V via CR12 in the AD5384 control register; operating the AD5384-5 with a 1.25 V reference will lead to

degraded accuracy specifications.

= 10 mV to AVDD – 50 mV.

OUT

= 3 mA

SINK

= 6 mA

SINK

Rev. A | Page 5 of 36

AD5384

AC CHARACTERISTICS

AVDD = 2.7 V to 3.6 V; DVDD = 2.7 V to 5.5 V, AGND = DGND = 0 V.

Table 4.

Parameter AD5384-5 Unit Test Conditions/Comments

DYNAMIC PERFORMANCE

Output Voltage Settling Time

8 µs typ

10 µs max

Slew Rate

3 V/µs typ Boost mode on, CR11 = 1

Digital-to-Analog Glitch Energy 12 nV-s typ
Glitch Impulse Peak Amplitude 15 mV typ
Channel-to-Channel Isolation 100 dB typ See the Terminology section
DAC-to-DAC Crosstalk 1 nV-s typ See the Terminology section
Digital Crosstalk 0.8 nV-s typ
Digital Feedthrough 0.1 nV-s typ Effect of input bus activity on DAC output under test
Output Noise 0.1 Hz to 10 Hz 15 µV p-p typ External reference, midscale loaded to DAC
40 µV p-p typ Internal reference, midscale loaded to DAC
Output Noise Spectral Density

1

Guaranteed by design and characterization, not production tested.

2

The slew rate can be programmed via the current boost control bit (CR11) in the AD5384 control register.

2

@ 1 kHz 150 nV/√Hz typ
@ 10 kHz 100 nV/√Hz typ

1

Boost mode off, CR11 = 0
1/4 scale to 3/4 scale change settling to ±1 LSB

2 V/µs typ Boost mode off, CR11 = 0

Rev. A | Page 6 of 36

AD5384

AD5384-3 SPECIFICATIONS

AVDD = 2.7 V to 3.6 V; DVDD = 2.7 V to 5.5 V, AGND = DGND = 0 V; external REFIN = 1.25 V; all specifications T
unless otherwise noted.

Table 5.

Parameter AD5384-31Unit Test Conditions/Comments

ACCURACY

Resolution 14 Bits
Relative Accuracy2 ±4 LSB max
Differential Nonlinearity –1/+2 LSB max Guaranteed monotonic over temperature
Zero-Scale Error 4 mV max
Offset Error ±4 mV max Measured at Code 64 in the linear region
Offset Error TC ±5 µV/°C typ
Gain Error ±0.024 % FSR max At 25°C
±0.1 % FSR max T
Gain Temperature Coefficient
DC Crosstalk

3

3

2 ppm FSR/°C typ

0.5 LSB max

MIN

to T

MAX

REFERENCE INPUT/OUTPUT

Reference Input

3

Reference Input Voltage 1.25 V ±1% for specified performance
DC Input Impedance 1 MΩ min Typically 100 MΩ
Input Current ±1 µA max Typically ±30 nA
Reference Range 1 to AVDD/2 V min/max

Reference Output

4

Output Voltage 1.245/1.255 V min/max At ambient; CR12 = 0; optimized for 1.25 V operation

2.47/2.53 V min/max CR12 = 1

Reference TC ±10 ppm/°C max Temperature range: +25°C to +85°C

OUTPUT CHARACTERISTICS

Output Voltage Range

2

±15 ppm/°C max

3

0/AV

DD

V min/max

Temperature range: −40°C to +85°C

Short-Circuit Current 40 mA max
Load Current ±1 mA max
Capacitive Load Stability

RL = ∞ 200 pF max
RL = 5 kΩ 1000 pF max

DC Output Impedance 0.5 Ω max

MONITOR PIN

Output Impedance 500 Ω typ
Three-State Leakage Current 100 nA typ

LOGIC INPUTS (EXCEPT SDA/SCL)3 DVDD = 2.7 V to 3.6 V

VIH, Input High Voltage 2 V min
V

Input Low Voltage 0.8 V max

IL,

Input Current ±10 µA max Total for all pins; TA = T

MIN

to T

MAX

Pin Capacitance 10 pF max

LOGIC INPUTS (SDA, SCL ONLY)

VIH, Input High Voltage 0.7 DV
VIL, Input Low Voltage 0.3 DV

DD

DD

V min SMBus-compatible at DVDD < 3.6 V

V max SMBus-compatible at DVDD < 3.6 V
IIN, Input Leakage Current ±1 µA max
V

, Input Hysteresis 0.05 DV

HYST

V min

DD

CIN, Input Capacitance 8 pF typ
Glitch Rejection 50 ns max Input filtering suppresses noise spikes of less than 50 ns

MIN

to T

MAX

,

Rev. A | Page 7 of 36

AD5384

Parameter AD5384-31Unit Test Conditions/Comments

LOGIC OUTPUTS (BUSY, SDO)3

VOL, Output Low Voltage 0.4 V max Sinking 200 µA
VOH, Output High Voltage DVDD – 0.5 V min Sourcing 200 µA
High Impedance Leakage Current ±1 µA max SDO only
High Impedance Output Capacitance 5 pF typ SDO only

LOGIC OUTPUT (SDA)

3

VOL, Output Low Voltage 0.4 V max I

0.6 V max I
Three-State Leakage Current ±1 µA max
Three-State Output Capacitance 8 pF typ

POWER REQUIREMENTS

AV

DD

DV

DD

Power Supply Sensitivity

∆Midscale/∆ΑV

AI

DD

3

DD

0.475 mA/channel max Outputs unloaded, boost on; 0.325 mA/channel typ
DI

DD

AIDD (Power-Down) 2 µA max Typically 200 nA
DIDD (Power-Down) 20 µA max Typically 1 µA
Power Dissipation 48 mW max Outputs unloaded, boost off, AVDD = DVDD = 3 V

1

AD5384-3 is calibrated using an external 1.25 V reference. Temperature range is –40°C to +85°C.

2

Accuracy guaranteed from V

3

Guaranteed by characterization, not production tested.

4

Default on the AD5384-3 is 1.25 V. Programmable to 2.5 V via CR12 in the AD5384 control register; operating the AD5384-3 with a 2.5 V reference will lead to degraded

accuracy specifications and limited input code range.

= 10 mV to AVDD – 50 mV.

OUT

= 3 mA

SINK

= 6 mA

SINK

2.7/3.6 V min/max

2.7/3.6 V min/max

–85 dB typ

0.375 mA/channel max Outputs unloaded, boost off; 0.25 mA/channel typ

1 mA max VIH = DVDD, VIL = DGND

Rev. A | Page 8 of 36

AD5384

AC CHARACTERISTICS

AVDD = 2.7 V to 3.6 V and 4.5 V to 5.5 V; DVDD = 2.7 V to 5.5 V; AGND = DGND = 0 V.

Table 6.

Parameter AD5384-3 Unit Test Conditions/Comments

DYNAMIC PERFORMANCE

Output Voltage Settling Time

8 µs typ

10 µs max

Slew Rate

3 V/µs typ Boost mode on, CR11 = 1

Digital-to-Analog Glitch Energy 12 nV-s typ
Glitch Impulse Peak Amplitude 15 mV typ
Channel-to-Channel Isolation 100 dB typ See the Terminology section
DAC-to-DAC Crosstalk 1 nV-s typ See the Terminology section
Digital Crosstalk 0.8 nV-s typ
Digital Feedthrough 0.1 nV-s typ Effect of input bus activity on DAC output under test
Output Noise 0.1 Hz to 10 Hz 15 µV p-p typ External reference, midscale loaded to DAC
40 µV p-p typ Internal reference, midscale loaded to DAC
Output Noise Spectral Density

1

Guaranteed by design and characterization, not production tested.

2

The slew rate can be programmed via the current boost control bit (CR11 ) in the AD5384 control register.

2

@ 1 kHz 150 nV/√Hz typ
@ 10 kHz 100 nV/√Hz typ

1

Boost mode off, CR11 = 0
1/4 scale to 3/4 scale change settling to ±1 LSB

2 V/µs typ Boost mode off, CR11 = 0

Rev. A | Page 9 of 36

AD5384

T

TIMING CHARACTERISTICS

SERIAL INTERFACE

DVDD = 2.7 V to 5.5 V; AVDD = 4.5 V to 5.5 V or 2.7 V to 3.6 V; AGND = DGND = 0 V; all specifications T
unless otherwise noted.

MIN

to T

MAX

,

Table 7.

Parameter

1, 2, 3

Limit at T

MIN

, T

MAX

Unit Description

t1 33 ns min SCLK cycle time
t

2

13 ns min SCLK high time
t3 13 ns min SCLK low time
t4 13 ns min
t5 4 13 ns min

4

t

6

33 ns min
t7 10 ns min
t7A 50 ns min

SYNC falling edge to SCLK falling edge setup time

th

SCLK falling edge to SYNC falling edge

24
Minimum
Minimum
Minimum

SYNC low time
SYNC high time

SYNC high time in readback mode
t8 5 ns min Data setup time
t9 4.5 ns min Data hold time

4

t

30 ns max

10

t11 670 ns max

4

t

12

20 ns min
t13 20 ns min
t14 100 ns max
t15 0 ns min
t16 100 ns min

24th SCLK falling edge to
BUSY pulse width low (single channel update)
24th SCLK falling edge to
LDAC pulse width low
BUSY rising edge to DAC output response time
BUSY rising edge to LDAC falling edge
LDAC falling edge to DAC output response time

BUSY falling edge

LDAC falling edge

t17 8 µs typ DAC output settling time boost mode off
t18 20 ns min

t

19

5

t

20

5

t

21

5

t

22

t

23

12 µs max

20 ns max SCLK rising edge to SDO valid

5 ns min

8 ns min

20 ns min

CLR pulse width low
CLR pulse activation time

SCLK falling edge to

SYNC rising edge
SYNC rising edge to SCLK rising edge
SYNC rising edge to LDAC falling edge

1

Guaranteed by design and characterization, not production tested.

2

All input signals are specified with t

3

See , F , and . Figure 2 igure 3 Figure 5, Figure 6

4

Standalone mode only.

5

Daisy-chain mode only.

= t

= 5 ns (10% to 90% of DVDD), and are timed from a voltage level of 1.2 V.

r

f

O OUTPUT PIN

Figure 2. Load Circuit for Digital Output Timing

200µA

C

L

50pF

200µA

Rev. A | Page 10 of 36

I

OL

I

OH

V

OH

V

OL

(MIN) OR

(MAX)

04652-0-003

AD5384

t

1

SCLK

SYNC

t

DIN

BUSY

1

LDAC

1

V

OUT

2

LDAC

2

V

OUT

CLR

V

OUT

1

LDAC ACTIVE DURING BUSY

2

LDAC ACTIVE AFTER BUSY

7

t

4

DB23

t8t

t

3

t

6

9

t

2

t

5

DB0

t

10

t

11

t

12

t

18

t

19

t

13

t

15

242412

t

17

t

14

t

13

t

17

t

16

04652-0-004

Figure 3. Serial Interface Timing Diagram (Standalone Mode)

24 48SCLK

t

7A

SYNC

DIN

SDO

SCLK

SYNC

DIN

SDO

DB23 DB0 DB23 DB0

INPUT WORD SPECIFIES

REGISTER TO BE READ

NOP CONDITION

DB23 DB0

UNDEFINED

SELECTED REGISTER

DATA CLOCKED OUT

Figure 4. Serial Interface Timing Diagram (Data Readback Mode)

t

1

t

t

7

t

4

t8t

3

9

DB23 DB0 DB23 DB0

INPUT WORD FOR DAC N

24 48

t

2

INPUT WORD FOR DAC N + 1

t

20

DB23 DB0

03731-0-005

t

t

22

21

UNDEFINED

INPUT WORD FOR DAC N

LDAC

Figure 5. Serial Interface Timing Diagram (Daisy-Chain Mode)

t

13

t

23

04652-0-005

Rev. A | Page 11 of 36

AD5384

I2C SERIAL INTERFACE

DVDD = 2.7 V to 5.5 V; AVDD = 4.5 V to 5.5 V or 2.7 V to 3.6 V; AGND = DGND = 0 V; all specifications T
unless otherwise noted.

MIN

to T

MAX

,

Table 8.

Parameter

F

SCL

t

1

t

2

t

3

t

4

t

5

2

t

6

0 µs min t
t7 0.6 µs min t
t8 0.6 µs m0in t
t9 1.3 µs min t

1

Limit at T

MIN

, T

Unit Description

MAX

400 kHz max SCL clock frequency

2.5 µs min SCL cycle time

0.6 µs min t

1.3 µs min t

0.6 µs min t
100 ns min t

0.9 µs max t

, SCL high time

HIGH

, SCL low time

LOW

, start/repeated start condition hold time

HD,STA

, data setup time

SU,DAT

, data hold time

HD,DAT

, data hold time

HD,DAT

, setup time for repeated start

SU,STA

, stop condition setup time

SU,STO

, bus free time between a STOP and a START condition

BUF

t10 300 ns max tR, rise time of SCL and SDA when receiving
0 ns min tR, rise time of SCL and SDA when receiving (CMOS-compatible)
t11 300 ns max tF, fall time of SDA when transmitting
0 ns min tF, fall time of SDA when receiving (CMOS-compatible)
300 ns max tF, fall time of SCL and SDA when receiving
20 + 0.1Cb

3

ns min tF, fall time of SCL and SDA when transmitting

Cb 400 pF max Capacitive load for each bus line

1

See . Figure 6

2

A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the V

falling edge.

3

Cb is the total capacitance, in pF, of one bus line. tR and tF are measured between 0.3 DVDD and 0.7 DVDD.

min of the SCL signal) in order to bridge the undefined region of SCL’s

IH

SDA

SCL

t

9

START

CONDITION

t

3

t

4

t

10

t

6

Figure 6. I

t

2

C-Compatible Serial Interface Timing Diagram

t

11

t

2

5

REPEATED
CONDITION

t

7

START

t

4

t

1

t

8

STOP

CONDITION

04652-0-006

Rev. A | Page 12 of 36

AD5384

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.1

Table 9.

Parameter Rating
AVDD to AGND –0.3 V to +7 V
DVDD to DGND –0.3 V to +7 V
Digital Inputs to DGND –0.3 V to DVDD + 0.3 V
SDA/SCL to DGND –0.3 V to + 7 V
Digital Outputs to DGND –0.3 V to DVDD + 0.3 V
REFIN/REFOUT to AGND –0.3 V to AVDD + 0.3 V
AGND to DGND –0.3 V to +0.3 V
VOUTx to AGND –0.3 V to AVDD + 0.3 V
Analog Inputs to AGND –0.3 V to AVDD + 0.3 V
Operating Temperature Range

Commercial (B Version) –40°C to +85°C
Storage Temperature Range –65°C to +150°C
JunctionTemperature (TJ max) 150°C
100-lead CSPBGA Package

θJAThermal Impedance 40°C/W
Reflow Soldering

Peak Temperature 230°C

1

Transient currents of up to 100 mA do not cause SCR latch-up.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
this product features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.

Rev. A | Page 13 of 36

AD5384

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

123456789101112

A
B
C
D

E

F
G
H

J

K

L
M

123456789101112

Figure 7. 100-Lead CSPBGA Pin Configuration

TOP VIEW

A
B
C
D
E
F
G
H
J
K
L
M

04652-0-007

Table 10. Pin Number and Name

CSPBGA
Number

Ball
Name

A1 NC B9
A2 VOUT24 B10 VOUT22 E9 DACGND3 H12 VOUT14
A3
A4

CLR
SYNC

CSPBGA
Number

Ball
Name

RESET

CSPBGA

Number

Ball
Name

CSPBGA

Number

Ball
Name

E4 DACGND4 H11 VOUT13

B11 NC E11 VOUT17 J1 AVDD1
B12 VOUT23 E12 VOUT19 J2 VOUT30

CSPBGA

Number

L5 AGND5
L6 VOUT6
L7 VOUT32
L8 VOUT34

Ball
Name

A5 SCLK C1 VOUT26 F1 REFGND J4 DACGND5 L9 VOUT36

A6 DVDD1 C2

SIGNAL
GND4

F2

SIGNAL
GND1

J5 AGND1 L10 VOUT38

A7 DGND C11 NC F4 DACGND1 J6 DACGND2 L11 NC
A8 PD C12 VOUT21 F9

SIGNAL

J7 DACGND2 L12 VOUT9

GND3

A9 DCEN D1 VOUT27 F11 VOUT16 J8 AGND2 M1 NC

A10

A11

LDAC

BUSY

D2

SIGNAL
GND4

F12 VOUT18 J9

SIGNAL
GND2

M2 VOUT3

D4 DACGND4 G1 VOUT28 J11 VOUT12 M3 VOUT4

A12 NC D5 AGND4 G2 VOUT29 J12 VOUT11 M4 VOUT5

B1 VOUT25 D6 DVDD2 G4 DACGND1 K1 VOUT0 M5 AVDD5
B2 NC D7 DGND G9 SIGNAL GND3 K2 VOUT1 M6 VOUT7
B3 DGND D8 AGND3 G11 VOUT15 K11 NC M7 VOUT33
B4 DIN D9 DACGND3 G12 AVDD2 K12 VOUT10 M8 VOUT35
B5 SDO D11 VOUT20 H1 REFOUT/REFIN L1 VOUT2 M9 VOUT37
B6 DVDD3 D12 AVDD3 H2 VOUT31 L2 NC M10 VOUT39/

MON_OUT

B7 DGND E1 AVDD4 H4 DACGND5 L3

SIGNAL

M11 VOUT8

GND5

B8

SPI/

I2C

E2

SIGNAL
GND1

H9

SIGNAL
GND2

L4

SIGNAL
GND5

M12 NC

Rev. A | Page 14 of 36

AD5384

Table 11. Pin Function Descriptions

Mnemonic Function

VOUTx

SIGNAL GND(1–5)

DAC GND(1–5)

AGND(1–5)

AVDD(1–5)

DGND Ground for All Digital Circuitry.
DVDD

REF GND Ground Reference Point for the Internal Reference.
REFOUT/REFIN

VOUT39/MON_OUT

SYNC/AD0 Serial Interface Mode. This is the frame synchronization input signal for the serial clocks before the addressed register

DCEN/ AD1

SDO

LDAC Load DAC Logic Input (Active Low). If LDAC is taken low while BUSY is inactive (high), the contents of the input

CLR Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is activated, all channels are updated

RESET Asynchronous Digital Reset Input (Falling Edge Sensitive). The function of this pin is equivalent to that of the power-

Buffered Analog Outputs for Channel x. Each analog output is driven by a rail-to-rail output amplifier operating at a
gain of 2. Each output is capable of driving an output load of 5 kΩ to ground. Typical output impedance is 0.5 Ω.

Analog Ground Reference Points for Each Group of Eight Output Channels. All SIGNAL_GND pins are tied together
internally and should be connected to the AGND plane as close as possible to the AD5384.

Each group of eight channels contains a DAC_GND pin. This is the ground reference point for the internal 14-bit DAC.
These pins shound be connected to the AGND plane.

Analog Ground Reference Point. Each group of eight channels contains an AGND pin. All AGND pins should be
connected externally to the AGND plane.

Analog Supply Pins. Each group of eight channels has a separate AVDD pin. These pins are shorted internally and
should be decoupled with a 0.1 µF ceramic capacitor and a 10 µF tantalum capacitor. Operating range for the
AD5384-5 is 4.5 V to 5.5 V; operating range for the AD5384-3 is 2.7 V to 3.6 V.

Logic Power Supply. Guaranteed operating range is 2.7 V to 5.5 V. It is recommended that these pins be decoupled
with 0.1 µF ceramic and 10 µF tantalum capacitors to DGND.

The AD5384 contains a common REFOUT/REFIN pin. The default for this pin is a reference input. When the internal
reference is selected, this pin is the reference output. If the application requires an external reference, it can be
applied to this pin. The internal reference is enabled/disabled via the control register.

This pin has a dual function. It acts a a buffered output for Channel 39 in default mode. But when the monitor
function is enabled, this pin acts as the output of a 39-to-1 channel multiplexer that can be programmed to multiplex
one of Channels 0 to 38 to the MON_OUT pin. The MON_OUT pin output impedance typically is 500 Ω and is
intended to drive a high input impedance like that exhibited by SAR ADC inputs.

is updated.

2

I

C Mode. This pin acts as a hardware address pin used in conjunction with AD1 to determine the software address

for the device on the I
Multifunction Pin. In serial interface mode, this pin acts as a daisy-chain enable in SPI mode and as a hardware

address pin in I

2

C mode.

2

C bus.

Serial Interface. Daisy-chain select input (level sensitive, active high). When high, this signal is used in conjunction
with SPI/

2

I
for this device on the I

I2C high to enable the SPI serial interface daisy-chain mode.

C Mode. This pin acts as a hardware address pin used in conjunction with AD0 to determine the software address

2

C bus.

Serial Data Output in Serial Interface Mode. Three-stateable CMOS output. SDO can be used for daisy-chaining a
number of devices together. Data is clocked out on SDO on the rising edge of SCLK, and is valid on the falling edge of
SCLK.

Digital CMOS Output.

BUSY goes low during internal calculations of the data (x2) loaded to the DAC data register.
During this time, the user can continue writing new data to the x1, c, and m registers, but no further updates to the
DAC registers and DAC outputs can take place. If
goes low during power-on reset, and when the
events on

LDAC are ignored. A CLR operation also brings BUSY low.

registers are transferred to the DAC registers, and the DAC outputs are updated. If
active and internal calculations are taking place, the

LDAC is taken low while BUSY is low, this event is stored. BUSY also

BUSY pin is low. During this time, the interface is disabled and any

LDAC is taken low while BUSY is

LDAC event is stored and the DAC registers are updated when

BUSY goes inactive. However, any events on LDAC during power-on reset or on RESET are ignored.

with the data in the
the

CLR code.

CLR code register. BUSY is low for a duration of 35 µs while all channels are being updated with

on reset generator. When this pin is taken low, the state machine initiates a reset sequence to digitally reset the x1, m,
c, and x2 registers to their default power-on values. This sequence typically takes 270 µs. The falling edge of
initiates the
is low, all interfaces are disabled and all
operation and the status of the

RESET process and BUSY goes low for the duration, returning high when RESET is complete. While BUSY

LDAC pulses are ignored. When BUSY returns high, the part resumes normal

RESET pin is ignored until the next falling edge is detected.

RESET

Rev. A | Page 15 of 36

AD5384

Mnemonic Function

PD

NC No Connect. The user is advised not to connect any signals to these pins.
SPI/ I2C
SCLK/SCL

DIN/SDA

Power Down (Level Sensitive, Active High). PD is used to place the device in low power mode, where AI
2 µA and DI

to 20 µA. In power-down mode, all internal analog circuitry is placed in low power mode, and the

DD

analog output is configured as a high impedance output or provides a 100 kΩ load to ground, depending on how
the power-down mode is configured. The serial interface remains active during power-down.

This pin acts as serial interface mode select. When this input is high SPI mode is selected. When low, I2C is selected.
Serial Interface Mode. In serial interface mode, data is clocked into the shift register on the falling edge of SCLK. This

operates at clock speeds up to 30 MHz.

2

I

C Mode. In I2C mode, this pin performs the SCL function, clocking data into the device. The data transfer rate in I2C

mode is compatible with both 100 kHz and 400 kHz operating modes.
Serial Interface Mode. In serial interface mode, this pin acts as the serial data input. Data must be valid on the falling

edge of SCLK.

2

C Mode. In I2C mode, this pin is the serial data pin (SDA) operating as an open-drain input/output.

I

reduces to

DD

Rev. A | Page 16 of 36

AD5384

TERMINOLOGY

Relative Accuracy

DC Output Impedance

Relative accuracy or endpoint linearity is a measure of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after
adjusting for zero-scale error and full-scale error, and is
expressed in LSB.

Differential Nonlinearity

Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of 1 LSB maximum
ensures monotonicity.

Zero-Scale Error

Zero-scale error is the error in the DAC output voltage when all
0s are loaded into the DAC register. Ideally, with all 0s loaded to
the DAC and m = all 1s, c = 2

VOUT

(Zero-Scale)

= 0 V

n – 1

Zero-scale error is a measure of the difference between VOUT
(actual) and VOUT (ideal), expressed in mV. It is mainly due to
offsets in the output amplifier.

Offset Error

Offset error is a measure of the difference between VOUT
(actual) and VOUT (ideal) in the linear region of the transfer
function, expressed in mV. Offset error is measured on the
AD5384-5 with Code 32 loaded into the DAC register, and on
the AD5384-3 with Code 64.

Gain Error

Gain Error is specified in the linear region of the output range
between V

= 10 mV and V

OUT

= AVDD – 50 mV. It is the

OUT

deviation in slope of the DAC transfer characteristic from the
ideal and is expressed in %FSR with the DAC output unloaded.

DC Crosstalk

This is the dc change in the output level of one DAC at midscale
in response to a full-scale code (all 0s to all 1s, and vice versa)
and output change of all other DACs. It is expressed in LSB.

This is the effective output source resistance. It is dominated by
package lead resistance.

Output Voltage Settling Time

This is the amount of time it takes for the output of a DAC to
settle to a specified level for a ¼ to ¾ full-scale input change,
and is measured from the

BUSY

rising edge.

Digital-to-Analog Glitch Energy

This is the amount of energy injected into the analog output at
the major code transition. It is specified as the area of the glitch
in nV-s. It is measured by toggling the DAC register data
between 0x1FFF and 0x2000.

DAC-to-DAC Crosstalk

DAC-to-DAC crosstalk is the glitch impulse that appears at the
output of one DAC due to both the digital change and the sub­sequent analog output change at another DAC. The victim
channel is loaded with midscale. DAC-to-DAC crosstalk is
specified in nV-s.

Digital Crosstalk

Digital crosstalk is the glitch impulse transferred to the output
of one converter due to a change in the DAC register code of
another converter. It is specified is specified in nV-s.

Digital Feedthrough

When the device is not selected, high frequency logic activity
on the device’s digital inputs can be capacitively coupled both
across and through the device to show up as noise on the VOUT
pins. It can also be coupled along the supply and ground lines.
This noise is digital feedthrough.

Output Noise Spectral Density

This is a measure of internally generated random noise. Random
noise is characterized as a spectral density (voltage per √Hertz).
It is measured by loading all DACs to midscale and measuring
noise at the output. It is measured in nV/√Hz in a 1 Hz band­width at 10 kHz.

Rev. A | Page 17 of 36

AD5384

TYPICAL PERFORMANCE CHARACTERISTICS

2.0

1.5

1.0

AVDD = DVDD = 5.5V
V

= 2.5V

REF

= 25°C

T

A

2.0

1.5

1.0

AVDD = DVDD = 3V
V

= 1.25V

REF

= 25°C

T

A

INL ERROR (LSB)

2.539

2.538

2.537

2.536

2.535

2.534

2.533

2.532

2.531

2.530

2.529

AMPLITUDE (V)

2.528

2.527

2.526

2.525

2.524

2.523

0.5

–0.5

–1.0

–1.5

–2.0

0.5

0

INPUT CODE

163840 4096 8192 12288

03731-0-033

Figure 8. Typical AD5384-5 INL Plot

AVDD = DVDD = 5V

= 2.5V

V

REF

T

= 25°C

A

14ns/SAMPLE NUMBER
1 LSB CHANGE AROUND MIDSCALE
GLITCH IMPULSE = 10nV-s

SAMPLE NUMBER

5500 100 150 200 250 30050 350 400 500450

03731-0-034

Figure 9. AD5384-5 Glitch Impulse

0

–0.5

INL ERROR (LSB)

–1.0

–1.5

–2.0

INPUT CODE

Figure 11. Typical AD5384-3 INL Plot

40

35

30

25

20

15

FREQUENCY

10

5

0
–5.0

–4.0

–1.0 3.0–3.0 1.00 4.0 5.0

–2.0 2.0

–1.5 2.5–3.5–4.5

REFERENCE DRIFT (ppm/°C)

0.5–0.5 3.5–2.5 1.5

Figure 12. AD5384-REFOUT Temperature Coefficient

4.5

163840 4096 8192 12288

03731-0-035

03731-0-048

AVDD = DVDD = 5V

= 2.5V

V

REF

= 25°C

T

A

V

OUT

Figure 10. Slew Rate with Boost Off

03731-0-012

Rev. A | Page 18 of 36

AVDD = DVDD = 5V
V

= 2.5V

REF

= 25°C

T

A

Figure 13. Slew Rate with Boost On

V

OUT

03731-0-015

AD5384

14

12

10

8

6

AVDD = 5.5V

= 2.5V

V

REF

= 25°C

T

A

AVDD = DVDD = 5V
V

= 2.5V

REF

T

= 25°C

A

POWER SUPPLY RAMP RATE = 10ms

V

OUT

4

PERCENTAGE OF UNITS (%)

2

10

8

6

4

NUMBER OF UNITS

2

0

AIDD (mA)

Figure 14. Histogram with Boost Off

DIDD (mA)

Figure 15. DI

Histogram

DD

DVDD = 5.5V
V

IH

VIL = DGND
T

A

0.8 0.90.4 0.5 0.6 0.7

118910

= DV

= 25°C

AV

DD

04598-0-049

03731-0-011

Figure 17. AD5384 Power-Up Transient

DD

04598-0-050

14

12

10

8

6

NUMBER OF UNITS

4

2

0

INL ERROR DISTRIBUTION (LSB)

AVDD = 5.5V
REFIN = 2.5V
T

= 25°C

A

2–2 –1 0 1

04652-0-039

Figure 18. INL Distribution

WR

BUSY

AVDD = DVDD = 5V

= 2.5V

V

REF

T

= 25°C

A

EXITS SOFT PD
TO MIDSCALE

Figure 16. Exiting Soft Power Down

PD

V

OUT

03731-0-045

V

OUT

AVDD = DVDD = 5V

V

= 2.5V

REF

T

= 25°C

EXITS HARDWARE PD

A

TO MIDSCALE

03731-0-038

Figure 19. Exiting Hardware Power Down

Rev. A | Page 19 of 36

AD5384

6

FULL-SCALE

5

4

3

(V)

OUT

2

V

1

0

–1

–40 –20 –10 –5 –2 0 2 5 10 20 40

3/4 SCALE

MIDSCALE

1/4 SCALE

ZERO-SCALE

CURRENT (mA)

Figure 20. AD5384-5 Output Amplifier Source and Sink Capability

0.20

0.15

–0.05

ERROR VOLTAGE (V)

–0.10

–0.15

0.10

0.05

0

ERROR AT ZERO SINKING CURRENT

(VDD–V

) AT FULL-SCALE SOURCING CURRENT

OUT

AVDD = DVDD= 5V

V

= 2.5V

REF

= 25°C

T

A

AVDD = 5V
V
T

REF

= 25°C

A

= 2.5V

04652-0-030

6

AVDD = DVDD= 3V

= 1.25V

V

REF

= 25°C

T

A

5

4

3

MIDSCALE

(V)

OUT

2

V

1

0

–1

–40 –20 –10 –5 –2 0 2 5 10 20 –40

3/4 SCALE

ZERO-SCALE

FULL-SCALE

1/4 SCALE

CURRENT (mA)

Figure 23. AD5384-3 Output Amplifier Source and Sink Capability

AMPLITUDE (V)

2.456

2.455

2.454

2.453

2.452

2.451

2.450

AVDD = DVDD = 5V
V

= 2.5V

REF

= 25°C

T

A

14ns/SAMPLE NUMBER

04652-0-031

–0.20

I

SOURCE/ISINK

(mA)

Figure 21. Headroom at Rail vs. Source/Sink Current

OUTPUT NOISE (nV/ Hz)

600

500

400

300

200

100

0

REFOUT = 1.25V

FREQUENCY (Hz)

AVDD = 5V
T

A

REFOUT DECOUPLED
WITH 100nF CAPACITOR

REFOUT = 2.5V

Figure 22. REFOUT Noise Spectral Density

= 25°C

2.000 0.25 0.50 0.75 1.00 1.25 1.50 1.75

04652-0-040

100k100 1k 10k

04652-0-035

2.449

SAMPLE NUMBER

Figure 24. Adjacent Channel DAC to DAC Crosstalk

AVDD = DVDD = 5V
T

= 25°C

A

DAC LOADED WITH MIDSCALE
EXTERNAL REFERENCE
Y AXIS = 5µV/DIV
X AXIS = 100ms/DIV

Figure 25. 0.1 Hz to 10 Hz Noise Plot

AVDD = DVDD = 5V

= 2.5V

V

REF

T

= 25°C

A

EXITS SOFT PD

TO MIDSCALE

5500 100 150 200 250 30050 350 400 500450

04652-0-034

04652-0-032

Rev. A | Page 20 of 36

AD5384

FUNCTIONAL DESCRIPTION

DAC ARCHITECTURE—GENERAL

The AD5384 is a complete single-supply, 40-channel, voltage
output DAC offering 14-bit resolution, available in a 100-lead
CSPBGA package. It features two serial interfaces, SPI and I
This family includes an internal1.25/2.5 V, 10 ppm/°C
reference that can be used to drive the buffered reference
inputs. Alternatively, an external reference can be used to drive
these inputs. Reference selection is via a bit in the control
register. Internal/external reference selection is via the CR10 bit
in the control register; CR12 selects the reference magnitude if
the internal reference is selected. All channels have an on-chip
output amplifier with rail-to-rail output capable of driving 5 kΩ
in parallel with a 200 pF load.

V

(+) AVDD

REF

×1 INPUT

REG

m REG

c REG

14-BIT

×2INPUT DATA

DAC

AGND

Figure 26. Single-Channel Architecture

V

OUT

R

R

04652-0-014

The architecture of a single DAC channel consists of a14-bit
resistor-string DAC followed by an output buffer amplifier
operating at a gain of 2. This resistor-string architecture
guarantees DAC monotonicity. The 14-bitbinary digital code
loaded to the DAC register determines at which node on the
string the voltage is tapped off before being fed to the output
amplifier.

Each channel on these devices contains independent offset and
gain control registers allowing the user to digitally trim offset
and gain. These registers let the user calibrate out errors in the
complete signal chain including the DAC using the internal m
and c registers which hold the correction factors. All channels
are double buffered allowing synchronous updating of all
channels using the

pin. Figure 26 shows a block diagram

LDAC

of a single channel on the AD5384. The digital input transfer
function for each DAC can be represented as

x2 = [(m + 2)/ 2

n

× x1] + (c – 2

n – 1

)

where:

x2 is the data-word loaded to the resistor string DAC.
x1 is the 14-bit data-word written to the DAC input register.
m is the gain coefficient (default is 0x3FFE on the AD5384).

The gain coefficient is written to the 13 most significant bits
(DB13 to DB1) and the LSB (DB0) is 0.

n is the DAC resolution (n = 14 for AD5384).
c is the14-bit offset coefficient (default is 0x2000).

2

C.

The complete transfer function for these devices can be
represented as

V

= 2 × V

OUT

REF

× x2/2

n

where:
x2 is the data-word loaded to the resistor string DAC.
V

is the internal reference voltage or the reference voltage

REF

externally applied to the DAC REFOUT/REFIN pin. For
specified performance, an external reference voltage of 2.5 V is
recommended for the AD5384-5, and 1.25 V for the AD5384-3.

DATA DECODING

The AD5384 contains a 14-bit data bus, DB13-DB0. Depending
on the value of REG1 and REG0 outlined in Table 12, this data
is loaded into the addressed DAC input register(s), offset (c)
register(s), or gain (m) register(s). The format data, offset (c)
and gain (m) register contents are outlined in Table 13, Table 14,
and Table 15.

Table 12. Register Selection

REG1 REG0 Register Selected

1 1 Input Data Register (x1)
1 0 Offset Register (c)
0 1 Gain Register (m)
0 0 Special Function Registers (SFRs)

Table 13. DAC Data Format (REG1 = 1, REG0 = 1)

DB13 to DB0 DAC Output (V)

11 1111 1111 1111 2 V
11 1111 1111 1110 2 V
10 0000 0000 0001 2 V
10 0000 0000 0000 2 V
01 1111 1111 1111 2 V
00 0000 0000 0001 2 V
00 0000 0000 0000 0

Table 14. Offset Data Format (REG1 = 1, REG0 = 0)

DB13 to DB0 Offset (LSB)

11 1111 1111 1111 +8191
11 1111 1111 1110 +8190
10 0000 0000 0001 +1
10 0000 0000 0000 0
01 1111 1111 1111 –1
00 0000 0000 0001 –8191
00 0000 0000 0000 –8192

× (16383/16384)

REF

× (16382/16384)

REF

× (8193/16384)

REF

× (8192/16384)

REF

× (8191/16384)

REF

× (1/16384)

REF

Rev. A | Page 21 of 36

AD5384

Table 15. Gain Data Format (REG1 = 0, REG0 = 1)

DB13 to DB0 Gain Factor

11 1111 1111 1110 1
10 1111 1111 1110 0.75
01 1111 1111 1110 0.5
00 1111 1111 1110 0.25
00 0000 0000 0000 0

ON-CHIP SPECIAL FUNCTION REGISTERS (SFR)

The AD5384 contains a number of special function registers
(SFRs), as outlined in Table 16. SFRs are addressed with
REG1 = REG0 = 0 and are decoded using Address Bits A5 to A0.

Table 16. SFR Register Functions (REG1 = 0, REG0 = 0)

R/WA5 A4 A3 A2 A1 A0 Function

X 0 0 0 0 0 0 NOP (No Operation)
0 0 0 0 0 0 1 Write CLR Code
0 0 0 0 0 1 0 Soft CLR
0 0 0 1 0 0 0 Soft Power-Down
0 0 0 1 0 0 1 Soft Power-Up
0 0 0 1 1 0 0 Control Register Write
1 0 0 1 1 0 0 Control Register Read
0 0 0 1 0 1 0 Monitor Channel
0 0 0 1 1 1 1 Soft Reset

SFR COMMANDS

NOP (No Operation)

REG1 = REG0 = 0, A5–A0 = 000000

Performs no operation but is useful in serial readback mode to
clock out data on D

for diagnostic purposes.

OUT

low during a NOP operation.

Write CLR Code

REG1 = REG0 = 0, A5–A0 = 000001
DB13–DB0 = Contain the CLR data

Bringing the

line low or exercising the soft clear function

CLR

loads the contents of the DAC registers with the data contained
in the user-configurable CLR register, and sets VOUT0 to
VOUT39, accordingly. This can be very useful for setting up a
specific output voltage in a clear condition. It is also beneficial
for calibration purposes; the user can load full scale or zero
scale to the clear code register and then issue a hardware or
software clear to load this code to all DACs, removing the need
for individual writes to each DAC. Default on power-up is all 0s.

BUSY

pulses

Soft CLR

REG1 = REG0 = 0, A5–A0 = 000010
DB13–DB0 = Don’t Care

Executing this instruction performs the CLR, which is
functionally the same as that provided by the external

CLR

pin.

The DAC outputs are loaded with the data in the CLR code
register. It takes 35 µs to fully execute the SOFT CLR, as
indicated by the

BUSY

low time.

Soft Power-Down

REG1 = REG0 = 0, A5–A0 = 001000
DB13–DB0 = Don’t Care

Executing this instruction performs a global power-down that
puts all channels into a low power mode that reduces the analog
supply current to 2 µA maximum and the digital current to
20 µA maximum. In power-down mode, the output amplifier
can be configured as a high impedance output or can provide a
100 kΩ load to ground. The contents of all internal registers are
retained in power-down mode. No register can be written to
while in power-down.

Soft Power-Up

REG1 = REG0 = 0, A5–A0 = 001001
DB13–DB0 = Don’t Care

This instruction is used to power up the output amplifiers and
the internal reference. The time to exit power-down is 8 µs. The
hardware power-down and software function are internally
combined in a digital OR function.

Soft RESET

REG1 = REG0 = 0, A5–A0 = 001111
DB13–DB0 = Don’t Care

This instruction is used to implement a software reset. All
internal registers are reset to their default values, which
correspond to m at full scale and c at zero. The contents of the
DAC registers are cleared, setting all analog outputs to 0 V. The
soft reset activation time is 135 µs.

Rev. A | Page 22 of 36

AD5384

Table 17. Control Register Contents

MSB LSB

CR13 CR12 CR11 CR10 CR9 CR8 CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0

Control Register Write/Read

REG1 = REG0 = 0, A5–A0 = 001100, R/
the operation is a write (R/

= 0) or a read (R/W = 1). DB13 to

W

DB0 contain the control register data.

status determines if

W

CR8: Thermal Monitor Function. This function is used to
monitor the AD5384 internal die temperature, when enabled.
The thermal monitor powers down the output amplifiers when
the temperature exceeds 130°C. This function can be used to

Control Register Contents

CR13: Power-Down Status. This bit is used to configure the
output amplifier state in power-down.

CR13 = 1: Amplifier output is high impedance (default on
power-up).

CR13 = 0: Amplifier output is 100 kΩ to ground.

CR12: REF Select. This bit selects the operating internal
reference for the AD5384. CR12 is programmed as follows:

CR12 = 1: Internal reference is 2.5 V (AD5384-5 default), the
recommended operating reference for AD5384-5.

CR12 = 0: Internal reference is 1.25 V (AD5384-3 default),
the recommended operating reference for AD5384-3.

protect the device when power dissipation might be exceeded if
a number of output channels are simultaneously short-circuited.
A soft power-up re-enables the output amplifiers if the die
temperature drops below 130°C.

CR8 = 1: Thermal Monitor Enabled.

CR8 = 0: Thermal Monitor Disabled (default on power-up).

CR7: Don’t Care.

CR6 to CR2: Toggle Function Enable. This function allows the

user to toggle the output between two codes loaded to the A
and B register for each DAC. Control register bits CR6 to CR2
are used to enable individual groups of eight channels for
operation in toggle mode. A Logic 1 written to any bit enables a
group of channels; a Logic 0 disables a group.

LDAC

is used to

toggle between the two registers. Table 18 shows the decoding

CR11: Current Boost Control. This bit is used to boost the
current in the output amplifier, thereby altering its slew rate.
This bit is configured as follows:

for toggle mode operation. For example, CR6 controls group w,
which contains Channels 32 to 39, CR6 = 1 enables these
channels.

CR11 = 1: Boost Mode On. This maximizes the bias current
in the output amplifier, optimizing its slew rate but increasing
the power dissipation.

CR11 = 0: Boost Mode Off (default on power-up). This
reduces the bias current in the output amplifier and reduces
the overall power consumption.

CR10: Internal/External Reference. This bit determines if the
DAC uses its internal reference or an externally applied
reference.

CR10 = 1: Internal Reference Enabled. The reference output
depends on data loaded to CR12.

CR10 = 0: External Reference Selected (default on power-up).

CR9: Channel Monitor Enable (see Channel Monitor Function).

CR9 = 1: Monitor Enabled. This enables the channel monitor
function. After a write to the monitor channel in the SFR
register, the selected channel output is routed to the
MON_OUT pin. VOUT39 operates as the MON_OUT pin.

CR9 = 0: Monitor Disabled (default on power-up). When the
monitor is disabled, the MON_OUT pin assumes its normal
DAC output function.

CR1 and CR0: Don’t Care.

Table 18.

CR Bit Group Channels

CR6 4 32–39
CR5 3 24–31
CR4 2 16–23
CR3 1 8–15
CR2 0 0–7

Channel Monitor Function

REG1 = REG0 = 0, A5–A0 = 001010

DB13–DB8 = Contain data to address the monitored channel.

A channel monitor function is provided on the AD5384. This
feature, which consists of a multiplexer addressed via the
interface, allows any channel output to be routed to the
MON_OUT pin for monitoring using an external ADC. In
channel monitor mode, VOUT39 becomes the MON_OUT pin,
to which all monitored pins are routed. The channel monitor
function must be enabled in the control register before any
channels are routed to MON_OUT. On the AD5384, DB13 to
DB8 contain the channel address for the monitored channel.
Selecting Channel Address 63 three-states MON_OUT.

Rev. A | Page 23 of 36

AD5384

Table 19. AD5384 Channel Monitor Decoding

REG1 REG0 A5 A4 A3 A2 A1 A0 DB13 DB12 DB11 DB10 DB9 DB8 DB7–DB0 MON_OUT
0 0 0 0 1 0 1 0 0 0 0 0 0 0 X VOUT0
0 0 0 0 1 0 1 0 0 0 0 0 0 1 X VOUT1
0 0 0 0 1 0 1 0 0 0 0 0 1 0 X VOUT2
0 0 0 0 1 0 1 0 0 0 0 0 1 1 X VOUT3
0 0 0 0 1 0 1 0 0 0 0 1 0 0 X VOUT4
0 0 0 0 1 0 1 0 0 0 0 1 0 1 X VOUT5
0 0 0 0 1 0 1 0 0 0 0 1 1 0 X VOUT6
0 0 0 0 1 0 1 0 0 0 0 1 1 1 X VOUT7
0 0 0 0 1 0 1 0 0 0 1 0 0 0 X VOUT8
0 0 0 0 1 0 1 0 0 0 1 0 0 1 X VOUT9
0 0 0 0 1 0 1 0 0 0 1 0 1 0 X VOUT10
0 0 0 0 1 0 1 0 0 0 1 0 1 1 X VOUT11
0 0 0 0 1 0 1 0 0 0 1 1 0 0 X VOUT12
0 0 0 0 1 0 1 0 0 0 1 1 0 1 X VOUT13
0 0 0 0 1 0 1 0 0 0 1 1 1 0 X VOUT14
0 0 0 0 1 0 1 0 0 0 1 1 1 1 X VOUT15
0 0 0 0 1 0 1 0 0 1 0 0 0 0 X VOUT16
0 0 0 0 1 0 1 0 0 1 0 0 0 1 X VOUT17
0 0 0 0 1 0 1 0 0 1 0 0 1 0 X VOUT18
0 0 0 0 1 0 1 0 0 1 0 0 1 1 X VOUT19
0 0 0 0 1 0 1 0 0 1 0 1 0 0 X VOUT20
0 0 0 0 1 0 1 0 0 1 0 1 0 1 X VOUT21
0 0 0 0 1 0 1 0 0 1 0 1 1 0 X VOUT22
0 0 0 0 1 0 1 0 0 1 0 1 1 1 X VOUT23
0 0 0 0 1 0 1 0 0 1 1 0 0 0 X VOUT24
0 0 0 0 1 0 1 0 0 1 1 0 0 1 X VOUT25
0 0 0 0 1 0 1 0 0 1 1 0 1 0 X VOUT26
0 0 0 0 1 0 1 0 0 1 1 0 1 1 X VOUT27
0 0 0 0 1 0 1 0 0 1 1 1 0 0 X VOUT28
0 0 0 0 1 0 1 0 0 1 1 1 0 1 X VOUT29
0 0 0 0 1 0 1 0 0 1 1 1 1 0 X VOUT30
0 0 0 0 1 0 1 0 0 1 1 1 1 1 X VOUT31
0 0 0 0 1 0 1 0 1 0 0 0 0 0 X VOUT32
0 0 0 0 1 0 1 0 1 0 0 0 0 1 X VOUT33
0 0 0 0 1 0 1 0 1 0 0 0 1 0 X VOUT34
0 0 0 0 1 0 1 0 1 0 0 0 1 1 X VOUT35
0 0 0 0 1 0 1 0 1 0 0 1 0 0 X VOUT36
0 0 0 0 1 0 1 0 1 0 1 1 0 1 X VOUT37
0 0 0 0 1 0 1 0 1 0 0 1 1 0 X VOUT38
0 0 0 0 1 0 1 0 1 0 0 1 1 1 X VOUT39
0 0 0 0 1 0 1 0 1 0 1 0 0 0 X Undefined

• • • • • • • • • • • • • • • •
0 0 0 0 1 0 1 0 1 1 1 1 1 0 X Undefined
0 0 0 0 1 0 1 0 1 1 1 1 1 1 X Three-State

REG1 REG0A5 A4 A3 A2 A1 A0

VOUT0
VOUT1

VOUT37
VOUT38

00001010

AD5384

CHANNEL

MONITOR

DECODING

CHANNEL ADDRESS

DB13–DB8

Figure 27. Channel Monitor Decoding

Rev. A | Page 24 of 36

VOUT39/MON_OUT

04652-0-015

AD5384

HARDWARE FUNCTIONS

RESET FUNCTION

Bringing the
registers to their power-on reset state. Reset is a negative edge-

sensitive input. The default corresponds to m at full scale and to
c at zero. The contents of the DAC registers are cleared, setting
VOUT0 to VOUT39 to 0 V. The hardware reset activation time
takes 270 µs. The falling edge of

process;
RESET
disabled and all
high, the part resumes normal operation and the status of the

RESET

BUSY

is complete. While

pin is ignored until the next falling edge is detected.

line low resets the contents of all internal

RESET

initiates the reset

RESET

goes low for the duration, returning high when

is low, all interfaces are

BUSY

pulses are ignored. When

LDAC

BUSY

returns

ASYNCHRONOUS CLEAR FUNCTION

Bringing the
registers to the data contained in the user configurable CLR

register and sets VOUT0 to VOUT39 accordingly. This function
can be used in system calibration to load zero scale and full
scale to all channels. The execution time for a CLR is 35 µs.

line low clears the contents of the DAC

CLR

BUSY AND LDAC FUNCTIONS

is a digital CMOS output that indicates the status of the

BUSY
AD5384. The value of x2, the internal data loaded to the DAC

data register, is calculated each time the user writes new data to
the corresponding x1, c ,or m registers. During the calculation
of x2, the

can continue writing new data to the x1, m, or c registers, but
no DAC output updates can take place. The DAC outputs are
updated by taking the

is active, the

BUSY
update immediately after
the

LDAC

output goes low. While

BUSY

input low. If

LDAC

event is stored and the DAC outputs

LDAC

goes high. The user can hold

BUSY

input permanently low, in which case the DAC

is low, the user

BUSY

LDAC

goes low while

outputs update immediately after
goes low during power-on reset and when a falling edge is

detected on the
disabled and any events on
contains an extra feature whereby a DAC register is not updated

unless its x2 register has been written to since the last time

was brought low. Normally, when

LDAC
the DAC registers are filled with the contents of the x2 registers.

However, the AD5384 updates the DAC register only if the x2
data has changed, thereby removing unnecessary digital
crosstalk.

pin. During this time, all interfaces are

RESET

LDAC

POWER-ON RESET

The AD5384 contains a power-on reset generator and state
machine. The power-on reset resets all registers to a predefined
state and configures the analog outputs as high impedance. The

pin goes low during the power-on reset sequencing,

BUSY
preventing data writes to the device.

POWER-DOWN

The AD5384 contains a global power-down feature that puts all
channels into a low power mode and reduces the analog power
consumption to 2 µA maximum and digital power consumption
to 20 µA maximum. In power-down mode, the output amplifier
can be configured as a high impedance output or it can provide
a 100 kΩ load to ground. The contents of all internal registers
are retained in power-down mode. When exiting power-down,
the settling time of the amplifier elapses before the outputs
settles to their correct values.

goes high.

BUSY

are ignored. The AD5384

is brought low,

LDAC

BUSY

also

Rev. A | Page 25 of 36

AD5384

INTERFACES

The AD5384 contains a serial interface that can be
programmed either as DSP-, SPI-, MICROWIRE-, or I
compatible. The SPI/

MICROWIRE, or I

pin is used to select DSP, SPI,

I2C

2

C interface mode. To minimize both the
power consumption of the device and the on-chip digital noise,
the active interface powers up fully only when the device is
being written to, i.e., on the falling edge of

SYNC

DSP-, SPI-, MICROWIRE-COMPATIBLE SERIAL INTERFACES

The serial interface can be operated with a minimum of three
wires in standalone mode or five wires in daisy-chain mode.
Daisy chaining allows many devices to be cascaded together to
increase system channel count. The SPI/

tied high to enable the DSP-, SPI-, MICROWIRE-compatible
serial interface. The serial interface control pins are

, DIN, SCLK—Standard 3-Wire Interface Pins.

SYNC
DCEN—Selects Standalone Mode or Daisy-Chain Mode.

SDO—Data Out Pin for Daisy-Chain Mode.

Figure 3 and Figure 5 show the timing diagrams for a serial
write to the AD5384 in standalone and in daisy-chain modes.
The 24-bit data-word format for the serial interface is shown in
Table 20.

(Ball B8) should be

I2C

2

C-

.

/B. When toggle mode is enabled, this selects whether the

A

data write is to the A or B register, with Toggle disabled this bit
should be set to zero to select the A data register.

R/

is the read or write control bit.

W

A5–A0 are used to address the input channels.

REG1 and REG0 select the register to which data is written, as

shown in Table 12.

DB13–DB0 contain the input data-word.

X is a don’t care condition.

Standalone Mode

By connecting DCEN (daisy-chain enable) pin low, standalone
mode is enabled. The serial interface works with both a
continuous and a noncontinuous serial clock. The first falling
edge of

starts the write cycle and resets a counter that

SYNC

counts the number of serial clocks to ensure that the correct
number of bits are shifted into the serial shift register. Any
further edges on

, except for a falling edge, are ignored

SYNC

until 24 bits are clocked in. Once 24 bits are shifted in, the
SCLK is ignored. For another serial transfer to take place, the
counter must be reset by the falling edge of

SYNC

.

Table 20. 40-Channel, 14-Bit DAC Serial Input Register Configuration

MSB LSB
A

W A5 A4 A3 A2 A1 A0 REG1 REG0 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

/B R/

Rev. A | Page 26 of 36

AD5384

Daisy-Chain Mode

For systems that contain several devices, the SDO pin can be
used to daisy-chain several devices together. This daisy-chain
mode can be useful in system diagnostics and in reducing the
number of serial interface lines.

By connecting DCEN (daisy-chain enable) pin high, the daisy­chain mode is enabled. The first falling edge of

SYNC

starts the

write cycle. The SCLK is applied continuously to the input shift
register when

is low. If more than 24 clock pulses are

SYNC

applied, the data ripples out of the shift register and appears on
the SDO line. This data is clocked out on the rising edge of
SCLK and is valid on the falling edge. By connecting the SDO
of the first device to the DIN input on the next device in the
chain, a multidevice interface is constructed. 24 clock pulses are
required for each device in the system. Therefore, the total
number of clock cycles must equal 24N where N is the total
number of AD5384 devices in the chain.

When the serial transfer to all devices is complete,

SYNC

is

taken high. This latches the input data in each device in the
daisy-chain and prevents any further data being clocked into
the input shift register.

If the

is taken high before 24 clocks are clocked into the

SYNC

part, this is considered a bad frame and the data is discarded.

The serial clock may be either a continuous or a gated clock. A
continuous SCLK source can be used only if it can be arranged
that

is held low for the correct number of clock cycles. In

SYNC

gated clock mode a burst clock containing the exact number of
clock cycles must be used and

taken high after the final

SYNC

clock to latch the data.

Readback Mode

Readback mode is invoked by setting the R/
serial input register write. With R/

= 1, Bits A5 to A0, in

W

bit = 1 in the

W

association with Bits REG1 and REG0, select the register to be
read. The remaining data bits in the write sequence are don’t
cares. During the next SPI write, the data appearing on the SDO
output contains the data from the previously addressed register.
For a read of a single register, the NOP command can be used
in clocking out the data from the selected register on SDO.
Figure 28 shows the readback sequence.

For example, to read back the m register of Channel 0 on the
AD5384, the following sequence should be followed. First, write
0x404XXX to the AD5384 input register. This configures the
AD5384 for read mode with the m register of Channel 0
selected. Note that Data Bits DB13 to DB0 are don’t cares.
Follow this with a second write, a NOP condition, 0x000000.
During this write, the data from the m register is clocked out on
the SDO line, i.e., data clocked out contains the data from the m
register in Bits DB13 to DB0, and the top 10 bits contain the
address information as previously written. In readback mode,
the

signal must frame the data. Data is clocked out on

SYNC

the rising edge of SCLK and is valid on the falling edge of the
SCLK signal. If the SCLK idles high between the write and read
operations of a readback operation, the first bit of data is
clocked out on the falling edge of

SYNC

.

SCLK

SYNC

DIN

SDO

DB23 DB0 DB0DB23

UNDEFINED SELECTED REGISTER DATA CLOCKED OUT

24 48

NOP CONDITIONINPUT WORD SPECIFIES REGISTER TO BE READ

Figure 28. Serial Readback Operation

DB0DB23

04652-0-016

Rev. A | Page 27 of 36

AD5384

I2C SERIAL INTERFACE

The AD5384 features an I2C-compatible 2-wire interface
consisting of a serial data line (SDA) and a serial clock line
(SCL). SDA and SCL facilitate communication between the
AD5384 and the master at rates up to 400 kHz. Figure 6 shows
the 2-wire interface timing diagrams that incorporate three
different modes of operation.

2

C mode by configuring the SPI/

Select I
The device is connected to this bus as slave devices, i.e., no

clock is generated by the AD5384. The AD5384 has a 7-bit slave
address 1010 1(AD1)(AD0). The 5 MSBs are hard coded, and
the two LSBs are determined by the state of the AD1 AD0 pins.
The ability to hardware-configure AD1 and AD0 allows four of
these devices to be configured on the bus.

2

C Data Transfer

I

One data bit is transferred during each SCL clock cycle. The
data on SDA must remain stable during the high period of the
SCL clock pulse. Changes in SDA while SCL is high are control
signals, which configure start and stop conditions. Both SDA
and SCL are pulled high by the external pull-up resistors when

2

C bus is not busy.

the I

Start and Stop Conditions

A master device initiates communication by issuing a start
condition. A start condition is a high-to-low transition on SDA
with SCL high. A stop condition is a low-to-high transition on
SDA while SCL is high. A start condition from the master
signals the beginning of a transmission to the AD5384. The stop
condition frees the bus. If a repeated start condition (Sr) is
generated instead of a stop condition, the bus remains active.

Repeated START Conditions

A repeated start (Sr) condition may indicate a change of data
direction on the bus. Sr may be used when the bus master is

2

writing to several I

C devices and wants to maintain control of

the bus.

Acknowledge Bit (ACK)

The acknowledge bit (ACK) is the ninth bit attached to any
8-bit data-word. ACK is always generated by the receiving
device. The AD5384 devices generate an ACK when receiving
an address or data by pulling SDA low during the ninth clock
period. Monitoring ACK allows detection of unsuccessful data
transfers. An unsuccessful data transfer occurs if a receiving
device is busy or if a system fault occurs. In the event of an
unsuccessful data transfer, the bus master should re-attempt
communication.

pin to a Logic 0.

I2C

Slave Addresses

A bus master initiates communication with a slave device by
issuing a start condition followed by the 7-bit slave address.
When idle, the AD5384 waits for a start condition followed by
its slave address. The LSB of the address word is the Read/Write

) bit. The AD5384 devices are receive-only devices; when

(R/

W

communicating with these, R/

= 0. After receiving the proper

W
address 1010 1(AD1)(AD0), the AD5384 issues an ACK by
pulling SDA low for one clock cycle.

The AD5384 has four different user programmable addresses
determined by the AD1 and AD0 bits.

Write Operation

There are three specific modes in which data can be written to
the AD5384 family of DACs.

4-Byte Mode

When writing to the AD5384 DACs, the user must begin with
an address byte (R/

= 0), after which the DAC acknowledges

W

that it is prepared to receive data by pulling SDA low. The
address byte is followed by the pointer byte; this addresses the
specific channel in the DAC to be addressed and also is
acknowledged by the DAC. Two bytes of data are then written
to the DAC, as shown in Figure 29. A stop condition follows.
This lets the user update a single channel within the AD5384 at
any time and requires four bytes of data to be transferred from
the master.

3-Byte Mode

In 3-byte mode, the user can update more than one channel in a
write sequence without having to write the device address byte
each time. The device address byte is required only once; sub­sequent channel updates require the pointer byte and the data
bytes. In 3-byte mode, the user begins with an address byte

= 0), after which the DAC acknowledges that it is prepared

(R/

W

to receive data by pulling SDA low. The address byte is followed
by the pointer byte. This addresses the specific channel in the
DAC to be addressed and also is acknowledged by the DAC.
This is then followed by the two data bytes, REG1 and REG0,
which determine the register to be updated.

If a stop condition does not follow the data bytes, another
channel can be updated by sending a new pointer byte followed
by the data bytes. This mode requires only three bytes to be sent
to update any channel once the device is initially addressed, and
reduces the software overhead in updating the AD5384 channels.
A stop condition at any time exits this mode. Figure 30 shows a
typical configuration.

Rev. A | Page 28 of 36

AD5384

A

A

SDA

SDA

SDA

SDA

SCL

SD

START COND

BY MASTER

SCL

SD

SCL

START COND

BY MASTER

1 0 1 0 1 AD1 AD0 R/W 0 0 A5 A4 A3 A2 A1 A0

ACK BY

ADDRESS BYTE

REG1 REG0 MSB LSB MSB LSB

MOST SIGNIFICANT BYTE LEAST SIGNIFICANT BYTE

AD538x

Figure 29. 4-Byte AD5384, I

MSB ACK BY

POINTER BYTE

ACK BY

AD538x

2

C Write Operation

AD538x

1

0 1 0 0 0 A5 A4 A3 A2 A1 A01 AD1 AD0 R/W

ACK BY

ADDRESS BYTE POINTER BYTE FOR CHANNEL "N"

AD538x

MSB

ACK BY
AD538x

ACK BY

AD538x

STOP
COND

BY

MASTER

04652-0-017

SCL

REG1 REG0 MSB LSB MSB LSB

SCL

SCL

ACK BY

MOST SIGNIFICANT DATA BYTE

0 0 A5 A4 A3 A2 A1 A0

MSB ACK BY

POINTER BYTE FOR CHANNEL "NEXT CHANNEL"

REG1 REG0 MSB LSB MSB LSB

MOST SIGNIFICANT DATA BYTE LEAST SIGNIFICANT DATA BYTE

DATA FOR CHANNEL "NEXT CHANNEL"

Figure 30. 3-Byte AD5384, I

AD538x

DATA FOR CHANNEL "N"

AD538x

ACK BY

AD538x

2

C Write Operation

LEAST SIGNIFICANT DATA BYTE

ACK BY

AD538x

ACK BY
AD538x

STOP COND
BY MASTER

04652-0-018

Rev. A | Page 29 of 36

AD5384

2-Byte Mode

Following initialization of 2-byte mode, the user can update
channels sequentially. The device address byte is required only
once, and the pointer address pointer is configured for auto­increment or burst mode.

The user must begin with an address byte (R/
which the DAC acknowledges that it is prepared to receive data

by pulling SDA low. The address byte is followed by a specific
pointer byte (0xFF) that initiates the burst mode of operation.
The address pointer initializes to Channel 0,and, upon receiving
the two data bytes for the present address, automatically
increments to the next address.

SCL

= 0), after

W

The REG0 and REG1 bits in the data byte determine which
register is updated. In this mode, following the initialization,
only the two data bytes are required to update a channel. The
channel address automatically increments from Address 0. This
mode allows transmission of data to all channels in one block
and reduces the software overhead in configuring all channels.
A stop condition at any time exits this mode. Toggle mode is
not supported in 2-byte mode. Figure 31 shows a typical
configuration.

SDA

START COND

BY MASTER

SCL

SDA

SCL

SDA

SCL

SDA

1 0 1 0 1 AD1 AD0 R/W 0 0 A5 = 1 A4 = 1 A3 = 1 A2 = 1 A1 = 1 A0 = 1

ACK BY

ADDRESS BYTE POINTER BYTE

REG1 REG0 MSB LSB MSB LSB

MOST SIGNIFICANT DATA BYTE

REG1 REG0 MSB LSB MSB LSB

MOST SIGNIFICANT DATA BYTE

REG1 REG0 MSB LSB MSB LSB

MOST SIGNIFICANT DATA BYTE

AD538x

CHANNEL N DATA FOLLOWED BY STOP

MSB ACK BY

ACK BY

AD538x

CHANNEL 0 DATA

ACK BY
AD538x

CHANNEL 1 DATA

ACK BY

AD538x

LEAST SIGNIFICANT DATA BYTE

LEAST SIGNIFICANT DATA BYTE

LEAST SIGNIFICANT DATA BYTE

CONVERTER

Figure 31. 2-Byte, 12C Write Operation

AD538x

ACK BY
AD538x

ACK BY

ACK BY

CONVERTER

STOP

COND

BY

MASTER

04652-0-019

Rev. A | Page 30 of 36

AD5384

MICROPROCESSOR INTERFACING

AD5384 to MC68HC11

The serial peripheral interface (SPI) on the MC68HC11 is
configured for master mode (MSTR = 1), the Clock Polarity bit
(CPOL) = 0, and the Clock Phase bit (CPHA) = 1. The SPI is
configured by writing to the SPI control register (SPCR)—see
the 68HC11 User Manual. SCK of the 68HC11 drives the SCLK
of the AD5384, the MOSI output drives the serial data line (D
of the AD5384, and the MISO input is driven from D

The

signal is derived from a port line (PC7). When data

SYNC

OUT

IN

.

is being transmitted to the AD5384, the SYNC line is taken low
(PC7). Data appearing on the MOSI output is valid on the
falling edge of SCK. Serial data from the 68HC11 is transmitted
in 8-bit bytes with only eight falling clock edges occurring in
the transmit cycle.

MC68HC11

MISO
MOSI

SCK
PC7

Figure 32. AD5384-toMC68HC11 Interface

DVDD

SPI/I
RESET
SDO
DIN
SCLK
SYNC

AD5384

2

C

AD5384 to PIC16C6x/7x

The PIC16C6x/7x synchronous serial port (SSP) is configured
as an SPI master with the Clock Polarity bit = 0. This is done by
writing to the synchronous serial port control register
(SSPCON). See the PIC16/17 Microcontroller User Manual. In
this example I/O, port RA1 is being used to pulse

SYNC

and

enable the serial port of the AD5384. This microcontroller
transfers only eight bits of data during each serial transfer
operation; therefore, three consecutive read/write operations
could be needed, depending on the mode. Figure 33 shows the
connection diagram.

PIC16C6X/7X

SDI/RC4
SDO/RC5
SCK/RC3

RA1

DVDD

SPI/I
RESET
SDO
DIN
SCLK
SYNC

AD5384

2

C

)

04652-0-020

AD5384 to 8051

The AD5384 requires a clock synchronized to the serial data.
The 8051 serial interface must therefore be operated in Mode 0.
In this mode, serial data enters and exits through RxD, and a
shift clock is output on TxD. Figure 34 shows how the 8051 is
connected to the AD5384. Because the AD5384 shifts data out
on the rising edge of the shift clock and latches data in on the
falling edge, the shift clock must be inverted. The AD5384
requires its data to be MSB first. Since the 8051 outputs the LSB
first, the transmit routine must take this into account.

8XC51

DVDD

RxD

TxD
P1.1

Figure 34. AD5384-to-8051 Interface

DVDD

SPI/I
RESET

SDO
DIN
SCLK
SYNC

AD5384

2

C

AD5384 to ADSP-2101/ADSP-2103

Figure 35 shows a serial interface between the AD5384 and the
ADSP-2101/ADSP-2103. The ADSP-2101/ADSP-2103 should
be set up to operate in SPORT transmit alternate framing mode.
The ADSP-2101/ADSP-2103 SPORT is programmed through
the SPORT control register and should be configured as follows:
internal clock operation, active low framing, and 16-bit word
length. Transmission is initiated by writing a word to the Tx
register after the SPORT has been enabled.

ADSP-2101/

ADSP-2103

DR

DT

SCK

TFS

RFS

Figure 35. AD5384-to-ADSP-2101/ADSP-2103 Interface

DVDD

SPI/I
RESET
SDO
DIN
SCLK

SYNC

AD5384

2

C

04652-0-022

04652-0-023

04652-0-021

Figure 33. AD5384-to-PIC16C6x/7x Interface

Rev. A | Page 31 of 36

AD5384

APPLICATION INFORMATION

POWER SUPPLY DECOUPLING

In any circuit where accuracy is important, careful considera­tion of the power supply and ground return layout helps to
ensure the rated performance. The printed circuit board on
which the AD5384 is mounted should be designed so that the
analog and digital sections are separated and confined to
certain areas of the board. If the AD5384 is in a system where
multiple devices require an AGND-to-DGND connection, the
connection should be made at one point only, a star ground
point established as close to the device as possible.

For supplies with multiple pins (AV
be tied together. The AD5384 should have ample supply bypass­ing of 10 µF in parallel with 0.1 µF on each supply, located as
close to the package as possible and ideally right up against the
device. The 10 µF capacitors are the tantalum bead type. The

0.1 µF capacitor should have low effective series resistance
(ESR) and effective series inductance (ESI), like the common
ceramic types that provide a low impedance path to ground at
high frequencies, to handle transient currents due to internal
logic switching.

The power supply lines of the AD5384 should use as large a
trace as possible to provide low impedance paths and reduce the
effects of glitches on the power supply line. Fast switching
signals, such as clocks, should be shielded with digital ground
to avoid radiating noise to other parts of the board, and should
never be run near the reference inputs. A ground line routed
between the D

and SCLK lines helps to reduce crosstalk

IN

between them (this is not required on a multilayer board
because there is a separate ground plane, but separating the
lines helps). It is essential to minimize noise on the V
REFIN lines.

Avoid crossover of digital and analog signals. Traces on
opposite sides of the board should run at right angles to each
other. This reduces the effects of feedthrough through the
board. A microstrip technique is by far the best, but is not
always possible with a double-sided board. In this technique,
the component side of the board is dedicated to the ground
plane while signal traces are placed on the solder side.

, AVCC), these pins should

DD

and

IN

MONITOR FUNCTION

The AD5384 contains a channel monitor function that consists
of a multiplexer addressed via the interface, allowing any
channel output to be routed to this pin for monitoring using an
external ADC. In channel monitor mode, VOUT39 becomes
the MON_OUT pin, to which all monitored signals are routed.
The channel monitor function must be enabled in the control
register before any channels are routed to MON_OUT. contains
the decoding information required to route any channel to
MON_OUT. Selecting Channel Address 63 three-states
MON_OUT. Figure 36 shows a typical monitoring circuit
implemented using a 12-bit SAR ADC in a 6-lead SOT package.
The controller output port selects the channel to be monitored,
and the input port reads the converted data from the ADC.

VOUT0

VOUT38

DAC_GND SIGNAL_GND

AVCC

AD5384

VOUT39/MON_OUT

Figure 36. Typical Channel Monitoring Circuit

DIN

SYNC

SCLK

AGND

AD7476

V

IN

AVCC

SCLK

SDATA

GND

OUTPUT PORT

CS

INPUT PORT

CONTROLLER

TOGGLE MODE FUNCTION

The toggle mode function allows an output signal to be gener­ated using the

two DAC data registers. This function is configured using the
SFR control register as follows. A write with REG1 = REG0 = 0
and A5–A0 = 001100 specifies a control register write. The
toggle mode function is enabled in groups of eight channels
using Bits CR6 to CR2 in the control register (see Table 17).
Figure 37 shows a block diagram of toggle mode
implementation.

control signal, which switches between

LDAC

04652-0-024

DATA

REGISTER

A

INPUT

INPUT

DATA

REGISTER

A/B

DATA

REGISTER

B

Figure 37. Toggle Mode Function

DAC

REGISTER

Rev. A | Page 32 of 36

14-BIT DAC

V

OUT

LDAC
CONTROL INPUT

04652-0-025

AD5384

Each of the 40 DAC channels on the AD5384 contains an A and
B data register. Note that the B registers can be loaded only
when toggle mode is enabled. The sequence of events when
configuring the AD5384 for toggle mode is

1. Enable toggle mode for the required channels via the

control register.

2. Load data to A registers.

THERMAL MONITOR FUNCTION

The AD5384 contains a temperature shutdown function to
protect the chip if multiple outputs are shorted. The short­circuit current of each output amplifier is typically 40 mA.
Operating the AD5384 at 5 V leads to a power dissipation of
200 mW per shorted amplifier. With five channels shorted, this
leads to an extra watt of power dissipation. For the 100-lead
CSPBGA, the θ

is typically 44°C/W.

JA

3. Load data to B registers.

4. Apply

The

LDAC

determining the analog output. The first

.

LDAC

is used to switch between the A and B registers in

configures the

LDAC
output to reflect the data in the A registers. This mode offers
significant advantages if the user wants to generate a square
wave at the output of all 40 channels, as might be required to
drive a liquid crystal-based variable optical attenuator. In this
case, the user writes to the control register and enables the
toggle function by setting CR6 to CR2 = 1, thus enabling the
five groups of eight for toggle mode operation. The user must
then load data to all 40 A and B registers. Toggling

LDAC

sets

the output values to reflect the data in the A and B registers.
The frequency of the

determines the frequency of the

LDAC

square wave output.

Toggle mode is disabled via the control register. The first

LDAC

following the disabling of the toggle mode updates the outputs
with the data contained in the A registers.

5V

0.01µF

OUTPUT RANGE

0V–200V

The thermal monitor is enabled by the user via CR8 in the
control register. The output amplifiers on the AD5384 are
automatically powered down if the die temperature exceeds
approximately 130°C. After a thermal shutdown has occurred,
the user can re-enable the part by executing a soft power-up if
the temperature drops below 130°C, or by turning off the
thermal monitor function via the control register.

AD5384 IN A MEMS-BASED OPTICAL SWITCH

In their feed-forward control paths, MEMS based optical
switches require high resolution DACs that offer high channel
density with 14-bit monotonic behavior. The 40-channel, 14-bit
AD5384 DAC satisfies these requirements. In the circuit in
Figure 38, the 0 V to 5 V outputs of the AD5384 are amplified
to achieve an output range of 0 V to 200 V, which is used to
control actuators that determine the position of MEMS mirrors
in an optical switch. The exact position of each mirror is
measured using sensors. The sensor outputs are multiplexed
into a high resolution ADC in determining the mirror position.
The control loop is closed and driven by an ADSP-21065L, a
32-bit SHARC® DSP with an SPI-compatible SPORT interface.
The ADSP-21065L writes data to the DAC, controls the multi­plexer, and reads data from the ADC via the serial interface.

REFOUT REFINA AVDD

14-BIT DAC

14-BIT DAC

AD5384

VOUT1

VOUT40

Figure 38. AD5384 in a MEMS-Based Optical Switch

ACTUATORS

G = 50

FOR MEMS

MIRROR

ARRAY

G = 50

Rev. A | Page 33 of 36

ADSP-21065L

SENSOR

AND

MULTIPLEXER

8-CHANNEL ADC

(AD7856)

OR

SINGLE-CHANNEL

ADC (AD7671)

04652-0-026

AD5384

OPT I CAL AT T ENUATOR S

Based on its high channel count, high resolution, monotonic
behavior, and high level of integration, the AD5384 is ideally
targeted at optical attenuation applications used in dynamic
gain equalizers, variable optical attenuators (VOA), and optical
add-drop multiplexers (OADMs). In these applications, each
wavelength is individually extracted using an arrayed wave
guide; its power is monitored using a photodiode, transimped­ance amplifier, and an ADC in a closed-loop control system.

DWDM

IN

AWG

11

12

1n–1

1n

ADD

PORTS

OPTICAL

SWITCH

DROP

PORTS

ATTENUATOR

ATTENUATOR

ATTENUATOR

ATTENUATOR

The AD5384 controls the optical attenuator for each
wavelength, ensuring that the power is equalized in all
wavelengths before being multiplexed onto the fiber. This
prevents information loss and saturation from occurring at
amplification stages further along the fiber.

PHOTODIODES

DWDM

AWG

OUT

FIBREFIBRE

TIA/LOG AMP
(AD8304/AD8305)

AD5384,

N:1 MULTIPLEXER

ADG731
(40:1 MUX)

40-CHANNEL,

14-BIT DAC

16-BIT ADCCONTROLLER

AD7671
(0-5V, 1MSPS)

04652-0-027

Figure 39. OADM Using the AD5384 as Part of an Optical Attenuator

Rev. A | Page 34 of 36

AD5384

OUTLINE DIMENSIONS

A1 CORNER

BOTTOM

VIEW

0.80 BSC

DETAILA

INDEX AREA

SEATING
PLANE

A
B
C
D
E
F
G
H

J
K
L
M

1.11

1.01

0.91

0.12 MAX
COPLANARITY

2.50 SQ

1.40

1.35

1.20

10.00

BSC SQ

BALL A1
PAD CORNER

TOP VIEW

DETAIL A

8.80

BSC

0.65 REF

0.34 NOM

0.29 MIN

*COMPLIANT TO JEDEC STANDARDS MO-205AC

WITH THE EXCEPTION OF BALL DIAMETER.

109 87654321

12 11

0.50*

0.45

0.40
BALL DIAMETER

Figure 40. 100-Lead Chip Scale Package Ball Grid Array [CSP_BGA]

(BC-100-2)

Dimensions shown in millimeters

ORDERING GUIDE

AV

DD

Model Resolution Temperature Range

Range

AD5384BBC-5 14 Bits –40°C to +85°C 4.5 V to 5.5 V 40 ±4 100-Lead CSPBGA BC-100-2
AD5384BBC-5REEL7 14 Bits –40°C to +85°C 4.5 V to 5.5 V 40 ±4 100-Lead CSPBGA BC-100-2
AD5384BBC-3 14 Bits –40°C to +85°C 2.7 V to 3.6 V 40 ±4 100-Lead CSPBGA BC-100-2
AD5384BBC-3REEL7 14 Bits –40°C to +85°C 2.7 V to 3.6 V 40 ±4 100-Lead CSPBGA BC-100-2

Output
Channels

Linearity
Error (LSB)

Package
Description

Package
Option

Rev. A | Page 35 of 36

AD5384

NOTES

Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent
Rights to use these components in an I

© 2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.

D04652–0–10/04(A)

2

C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.

Rev. A | Page 36 of 36