ANALOG DEVICES AD5373 Service Manual

32-Channel, 16/14, Serial Input,

Preliminary Technical Data

FEATURES

32-channel DAC in 56-LFCSP and 64-LQFP AD5372 Guaranteed monotonic to 16 bits AD5373 Guaranteed monotonic to 14 bits Maximum output voltage span of 4 × V Nominal output voltage range of -4 V to +8 V Multiple, independent output spans available System calibration function allowing user-programmable

offset and gain Channel grouping and addressing features Thermal Monitoring Function DSP/microcontroller-compatible serial interface

2.5 V to 5.5 V JEDEC-compliant digital levels

DV

VDDV

CC

CONTROL REGISTER

5372-0001B

SERIAL

INTERFACE

STATE

MACHINE

POWER-ON

RESET

AD5372/

AD5373

n

SYNC

SDI

SCLK

SDO

BUSY

RESET

CLR

AD5372/AD5373—Protected by U.S. Patent No. 5,969,657; other patents pending

n =16 FOR AD5372

n

n =14 FOR AD5373

8

n

n n

n

n n

8

n

n n

n

n n

SS

A/B SELECT

REGISTER

X1 REGISTER

MREGISTER CREGISTER

X1 REGISTER

MREGISTER CREGISTER

A/B SELECT

REGISTER

X1 REGISTER

MREGISTER CREGISTER

X1 REGISTER

MREGISTER CREGISTER

REF

AGND DNGD

·

(20 V)

FUNCTIONAL BLOCK DIAGRAM

8

n

8

n

TO

MUX 2's

n

X2A REGISTER

A/B

MUX

X2BREGISTER

n

·

n

·

n

TO

MUX 2's

n

·

n

A/B

MUX

A/B

MUX

A/B

MUX

·

n

·

n

·

X2A REGISTER X2B REGISTER

·

X2A REGISTER X2B REGISTER

Power-on reset Digital reset (

Clear function to user-defined SIGGND (

Simultaneous update of DAC outputs (

APPLICATIONS

Level setting in automatic test equipment (ATE) Variable optical attenuators (VOA) Optical switches Industrial control systems Instrumentation

LDAC

14

OFS0

REGISTER

n

MUX

GROUP2 TO GROUP 3

ARE IDENTICALTO GROUP 1

Figure 1.

DAC 0

REGISTER

2

·

2

·

2

n

14

n

·

DAC 7

REGISTER

OFS1

REGISTER

DAC 0

REGISTER

·

DAC 7

REGISTER

RESET

n

OFFSET

DAC 0

n

DAC 0

·

n

DAC 7

n

OFFSET

DAC 1

n

DAC 0

·

n

DAC 7

VREF1 SUPPLIES GROUP 1 TO3

SIGGND2

Voltage-Output DACs

AD5372/AD5373

)

pin)

CLR

pin)

LDAC

VREF0

VOUT0 VOUT1 VOUT2 VOUT3 VOUT4 VOUT5 VOUT6 VOUT7

SIGGND0

VREF1

VOUT8 VOUT9 VOUT10 VOUT11 VOUT12 VOUT13 VOUT14 VOUT15

SIGGND1

VOUT16 TO VOUT31

BUFFER

SIGGND3

BUFFER

GROUP0

OUTPUT BUFFER

AND POWER

DOWN CONTROL

·

OUTPUT BUFFER

AND POWER

DOWN CONTROL

GROUP 1

OUTPUT BUFFER

AND POWER

DOWN CONTROL

·

OUTPUT BUFFER

AND POWER

DOWN CONTROL

Rev. PrF

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Anal og Devices. Trademarks and registered trademarks are the property of their respective companies.

www.analog.com

AD5372/AD5373 Preliminary Technical Data

TABLE OF CONTENTS

Specifications......................................................................................4

Clear Function............................................................................ 16

AC Characteristics.........................................................................5

Timing Characteristics .................................................................6

Absolute Maximum Ratings.............................................................8

ESD Caution...................................................................................8

Terminology .................................................................................... 11

Functional Description.................................................................. 12

DAC Architecture—General..................................................... 12

Channel Groups.......................................................................... 12

A/ B Reigsters And Gain/Offset Adjustment.......................... 13

Load DAC.................................................................................... 13

Offset DACs ................................................................................13

Output Amplifier........................................................................ 14

Transfer Function....................................................................... 14

Reference Selection .................................................................... 14

Calibration................................................................................... 15

BUSY and LDAC Functions...................................................... 16

Power-Down Mode.................................................................... 16

Thermal Monitor Function....................................................... 16

Toggle Mode................................................................................ 17

Serial Interface ................................................................................ 18

SPI Write Mode........................................................................... 18

SPI Readback Mode ...................................................................19

Register Update Rates................................................................ 19

Channel Addressing And Special Modes................................ 19

Special Function Mode.............................................................. 20

Power Supply Decoupling ......................................................... 22

Power Supply Sequencing ......................................................... 22

Interfacing Examples...................................................................... 23

Outline Dimensions....................................................................... 24

Ordering Guide........................................................................... 24

AD5372 Calibration Example................................................... 15

Reset Function ............................................................................16

REVISION HISTORY

Pr B1 Modified SPI timing diagrams

Added Reference Selection and Calibration text

Pr. B2 Added Reset Function text

Pr. B3 Added Power Down Mode text

Pr. B4 Added Terminology and Power Supply Sequencing sections

Pr D Rewrote calibration section Changed SPI read diagram

Pr F. Changed LFCSP Vout8 and Vout9 positions

Rev. PrF| Page 2 of 25

Preliminary Technical Data AD5372/AD5373

General Description

The AD5372 and AD5373 contain 32, 16-bit or 14-bit DACs in a single, 56-lead, LFCSP or 64-lead LQFP package. The AD5372/AD5373 provides buffered voltage outputs with a span 4 times the reference voltage. The gain and offset of each DAC can be independently trimmed to remove errors. For even greater flexibility, the device is divided into 4 groups of 8 DACs. Two offset DACs allow the output range of the groups to be altered. Group 0 can be adjusted by Offset DAC 0, and group 1 to group 3 can be adjusted by Offset DAC 2.

The ADAD5372/AD5373 offers guaranteed operation over a wide supply range with V

from -4.5 V to -16.5 V and VDD

SS

from+8 V to +16.5 V. The output amplifier headroom requirement is 1.4 V operating with a load current of 1 mA.

Table 1. High Channel Count Bipolar DACs

Model Resolution Nominal Output

Span

AD5360BCPZ 16 Bits AD5360BSTZ 16 Bits AD5361BCPZ 14 Bits AD5361BSTZ 14 Bits AD5362BCPZ 16 Bits AD5362BSTZ 16 Bits AD5363BCPZ 14 Bits AD5363BSTZ 14 Bits AD5370BCPZ 16 Bits AD5370BSTZ 16 Bits AD5371BCPZ 14 Bits AD5371BSTZ 14 Bits AD5372BCPZ 16 Bits AD5372BSTZ 16 Bits AD5373BCPZ 14 Bits AD5373BSTZ 14 Bits

4 × V 4 × V 4 × V 4 × V 4 × V 4 × V 4 × V 4 × V 4 × V 4 × V 4 × V 4 × V 4 × V 4 × V 4 × V 4 × V

(20 V)

REF

(20 V)

REF

(20 V)

REF

(20 V)

REF

(20 V)

REF

(20 V)

REF

(20 V)

REF

(20 V)

REF

(12 V)

REF

(12 V)

REF

(12 V)

REF

(12 V)

REF

(12 V)

REF

(12 V)

REF

(12 V)

REF

(12 V)

REF

Output Channels

16 ±4 56-Lead LFCSP CP-56 16 ±4 52-Lead LQFP ST-52 16 ±1 56-Lead LFCSP CP-56 16 ±1 52-Lead LQFP ST-52 8 ±4 56-Lead LFCSP CP-56 8 ±4 52-Lead LQFP ST-52 8 ±1 56-Lead LFCSP CP-56 8 ±1 52-Lead LQFP ST-52 40 ±4 64-Lead LFCSP CP-64 40 ±4 64-Lead LQFP ST-64 40 ±1 100-Ball CSPBGA BC-100-2 40 ±1 80-Lead LQFP ST-80 32 ±4 56-Lead LFCSP CP-56 32 ±4 64-Lead LQFP ST-64 32 ±1 56-Lead LFCSP CP-56 32 ±1 64-Lead LQFP ST-64

The ADAD5372/AD5373 has a high-speed serial interface, which is compatible with SPI®, QSPI™, MICROWIRE™, and DSP interface standards and can handle clock speeds of up to 50 MHz.

The DAC outputs are updated on reception of new data into the DAC registers. All the outputs can be updated simultaneously by taking the

LDAC

input low. Each channel has a program-

mable gain and an offset adjust register.

Each DAC output is gained and buffered on-chip with respect to an external SIGGND input. The DAC outputs can also be

CLR

switched to SIGGND via the

pin.

Linearity Error (LSB) Package Description Package Option

Rev. PrF | Page 3 of 25

AD5372/AD5373 Preliminary Technical Data

SPECIFICATIONS

DVCC = 2.3 V to 5.5 V; VDD = 8 V to 16.5 V; VSS = −4.5 V to −16.5 V; V Gain (m), Offset(c) and DAC Offset registers at default value; all specifications T

Table 2. Performance Specifications

Parameter AD53721

B Version

AD5373 B Version

ACCURACY

Resolution 16 14 Bits Relative Accuracy ±4 ±1 LSB max Differential Nonlinearity ±1 ±1 LSB max Guaranteed monotonic by design over temperature. Offset Error ±20 ±20 mV max Before Calibration Gain Error ±20 ±20 mV max Before Calibration Offset Error2 100 100 µV max After Calibration Gain Error2 100 100 µV max After Calibration Gain Error of Offset DAC ±35 ±35 mV

VOUT Temperature Coefficient 5 5

DC Crosstalk2 0.5 0.5 mV max

REFERENCE INPUTS (VREF1, VREF2)2

V

DC Input Impedance 1 1 MΩ min Typically 100 MΩ.

REF

V

Input Current 60 60 nA max Per input. Typically ±30 nA.

REF

V

Range 2/5 2/5 V min/max ±2% for specified operation.

REF

SIGGND INPUT (SIGGND0 TO SIGGND4)2

DC Input Impedance 55 55 kΩ min Typically 60 kΩ. Input Range ±0.5 ±0.5 V min/max

OUTPUT CHARACTERISTICS2

Output Voltage Range VSS + 1.4 VSS + 1.4 V min I V

− 1.4 VDD − `.4 V max I

DD

Short Circuit Current 5 5 mA max Load Current ±1 ±1 mA max Capacitive Load 2200 2200 pF max DC Output Impedance 1 1 Ω max

DIGITAL INPUTS JEDEC compliant.

Input High Voltage 1.7 1.7 V min IOVCC = 2.5 V to 3.6 V.

2.0 2.0 V min IOV Input Low Voltage 0.8 0.8 V max IOVCC = 2.5 V to 5.5 V. Input Current (with pull-up/pull-

±8 ±8 µA max CLR and RESET pin only.

down) Input Current (no pull-up/pull-down) ±1 ±1 µA max All other digital input pins. Input Capacitance2 10 10 pF max

DIGITAL OUTPUTS (SDO)

Output Low Voltage 0.5 0.5 V max Sinking 200 µA. Output High Voltage (SDO) DVCC − 0.5 DVCC − 0.5 V min Sourcing 200 µA. High Impedance Leakage Current −5 −5 µA max SDO only. High Impedance Output Capacitance2 10 10 pF typ

= 3 V; AGND = DGND = SIGGND = 0 V; RL = Open Circuit;

REF

to T

MIN

1

Unit Test Conditions/Comments2

, unless otherwise noted.

MAX

Positive or Negative Full Scale. See Offset DACs section for details

ppm FSR/°C

Includes linearity, offset, and gain drift.

typ

Typically 100 µV. Measured channel at mid-scale, fullscale change on any other channel

= 1 mA.

LOAD

= 1 mA.

LOAD

= 3.6 V to 5.5 V.

CC

Rev. PrF| Page 4 of 25

Preliminary Technical Data AD5372/AD5373

Parameter AD53721

B Version

AD5373 B Version

1

Unit Test Conditions/Comments

2

POWER REQUIREMENTS

DVCC 2.3/5.5 2.3/5.5 V min/max

VDD 8/16.5 8/16.5 V min/max

VSS −4.5/−16.5 −4.5/−16.5 V min/max

Power Supply Sensitivity2

∆ Full Scale/∆ VDD −75 −75 dB typ ∆ Full Scale/∆ VSS −75 −75 dB typ

∆ Full Scale/∆ VCC −90 −90 dB typ DICC 2 2 mA max VCC = 5.5 V, VIH = VCC, VIL = GND. IDD 14 14 mA max Outputs unloaded. ISS 14 14 mA max Outputs unloaded. Power Dissipation

Power Dissipation Unloaded (P) 350 350 mW

Junction Temperature3 130 130 °C max TJ = TA + P

TOTAL

× θJ.

1

Temperature range for B Version: −40°C to +85°C. Typical specifications are at 25°C.

2

Guaranteed by design and characterization, not production tested.

3

Where θJ represents the package thermal impedance.

AC CHARACTERISTICS

DVCC = 2.5 V; VDD = 15 V; VSS = −15 V; V Gain (m), Offset(c) and DAC Offset registers at default value; all specifications T

Table 3. AC Characteristics

Parameter AD5372/

DYNAMIC PERFORMANCE1

Output Voltage Settling Time 20 µs typ Full-scale change 30 µs max DAC latch contents alternately loaded with all 0s and all 1s. Slew Rate 1 V/µs typ Digital-to-Analog Glitch Energy 20 nV-s typ Glitch Impulse Peak Amplitude 10 mV max Channel-to-Channel Isolation 100 dB typ V DAC-to-DAC Crosstalk 40 nV-s typ Between DACs in the same group. 10 nV-s typ Between DACs from different groups. Digital Crosstalk 0.1 nV-s typ Digital Feedthrough 1 nV-s typ Effect of input bus activity on DAC output under test. Output Noise Spectral Density @ 10 kHz 250 nV/(Hz)

1

Guaranteed by design and characterization. Not production tested

= 3 V; AGND = DGND = SIGGND = 0 V; CL = 200pF; RL = 10 kΩ;

REF

MIN

to T

, unless otherwise noted.

MAX

Unit Test Conditions/Comments

AD5373

(+) = 2 V p-p, 1 kHz.

REF

1/2

typ V

REF

= 0 V.

Rev. PrF | Page 5 of 25

AD5372/AD5373 Preliminary Technical Data

TIMING CHARACTERISTICS

DVCC = 2.3 V to 5.5 V; VDD = 8 V to 16.5 V; VSS = −4.5 V to −16.5 V; V R

= Open Circuit; Gain (m), Offset(c) and DAC Offset registers at default value; all specifications T

L

SPI INTERFACE (Figure 4 and Figure 5)

Parameter1, 2, 3 Limit at TMIN, TMAX Unit Description

t

1

20 ns min SCLK Cycle Time.

t2 8 ns min SCLK High Time. t3 8 ns min SCLK Low Time. t4 11 ns min

t

5

20 ns min

t6 10 ns min t

7

5 ns min Data Setup Time.

SYNC Falling Edge to SCLK Falling Edge Setup Time. Minimum SYNC High Time. 24th SCLK Falling Edge to SYNC Rising Edge.

t8 5 ns min Data Hold Time.

3

t

42 ns max

9

t

1.25 µs max

10

SYNC Rising Edge to BUSY Falling Edge.

Pulse Width Low (Single-Channel Update.) See Table 7.

BUSY

t11 500 ns max Single-Channel Update Cycle Time t

20 ns min

12

t13 10 ns min t14 3

µs max

t15 0 ns min t16 3

µs max

24th SCLK Falling Edge to LDAC Falling Edge. LDAC Pulse Width Low. BUSY Rising Edge to DAC Output Response Time. BUSY Rising Edge to LDAC Falling Edge. LDAC Falling Edge to DAC Output Response Time.

t17 20/30 µs typ/max DAC Output Settling Time. t18 125 ns max

t19 330 ns min t20 400 µs max

t21 270 ns min

5

t

25 ns max SCLK Rising Edge to SDO Valid.

22

1

Guaranteed by design and characterization, not production tested.

2

All input signals are specified with tr = tf = 2 ns (10% to 90% of VCC) and timed from a voltage level of 1.2 V.

3

See Figure 4 and Figure 5.

4

This is measured with the load circuit of Figure 2.

5

This is measured with the load circuit of Figure 3.

TO

OUTPUT

C

L

Figure 2. Load Circuit for

50pF

BUSY

V

CC

RL2.2kΩ

Timing Diagram

V

OL

/RESET Pulse Activation Time.

CLR

Pulse Width Low.

RESET RESET Time Indicated by BUSY Low. Minimum SYNC

= 3 V; AGND = DGND = SIGGND = 0 V;

REF

to T

MIN

MAX

High Time in Readback Mode.

200µA

TO

OUTPUT

C

50pF

L

200µA

Figure 3. Load Circuit for SDO Timing Diagram

I

OL

I

OL

, unless otherwise noted.

VOH(min)-VOL(max)

2

Rev. PrF| Page 6 of 25

Preliminary Technical Data AD5372/AD5373

SCLK

SYNC

BUSY

LDAC

VOUT

LDAC

VOUT

CLR

VOUT

SDI

1

2

1

2

t

4

t

5

t

7

t

8

DB23

t

1

24

t

3

t

2

t

6

DB0

t

9

t

18

1

t

10

t

12

t

24

11

13

t

17

t

14

t

15

t

13

t

17

t

16

t

19

RESET

VOUT

BUSY

1

LDAC ACTIVE DURING BUSY.

2

LDAC ACTIVE AFTER BUSY.

t

18

t

20

05814-004A

Figure 4.

SPI Write Timing

t

22

SCLK

SYNC

SDI

SDO

5371-0005D

24

DB23 DB0

INPUTWORD SPECIFIES

REGISTERTO BE READ

LSB FROMPREVIOUS WRITE

SPI Read Timing

Figure 5.

t

21

DB23

NOP CONDITION

DB0

DB23

SELECTED REGISTER DATA

CLOCKED OUT

48

DB0

Rev. PrF | Page 7 of 25

AD5372/AD5373 Preliminary Technical Data

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted. Transient currents of up to 100 mA do not cause SCR latch-up.

Table 4. Absolute Maximum Ratings

Parameter Rating

VDD to AGND −0.3 V to +17 V VSS to AGND −17 V to +0.3 V DVCC to DGND −0.3 V to +7 V Digital Inputs to DGND −0.3 V to VCC + 0.3 V Digital Outputs to DGND −0.3 V to VCC + 0.3 V V

1, V

2 to AGND −0.3 V to +7 V

REF

VOUT0–VOUT39 to AGND VSS − 0.3 V to VDD + 0.3 V SIGGND to AGND VSS − 0.3 V to VDD + 0.3 V AGND to DGND −0.3 V to +0.3 V Operating Temperature Range (TA)

Industrial (B Version) −40°C to +85°C Storage Temperature Range −65°C to +150°C Junction Temperature ( TJ max) 130°C θJA Thermal Impedance

56-LFCSP 24°C/w

64-LQFP 45.5°C/w Reflow Soldering

Peak Temperature 230°C

Time at Peak Temperature 10 s to 40 s

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Rev. PrF| Page 8 of 25

ANALOG DEVICES AD5373 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual