Datasheet AD5373 Datasheet (ANALOG DEVICES)

32-Channel, 16/14, Serial Input,

Preliminary Technical Data

FEATURES

32-channel DAC in 56-LFCSP and 64-LQFP
AD5372 Guaranteed monotonic to 16 bits
AD5373 Guaranteed monotonic to 14 bits
Maximum output voltage span of 4 × V
Nominal output voltage range of -4 V to +8 V
Multiple, independent output spans available
System calibration function allowing user-programmable

offset and gain
Channel grouping and addressing features
Thermal Monitoring Function
DSP/microcontroller-compatible serial interface

2.5 V to 5.5 V JEDEC-compliant digital levels

DV

VDDV

CC

CONTROL
REGISTER

5372-0001B

SERIAL

INTERFACE

STATE

MACHINE

POWER-ON

RESET

AD5372/

AD5373

n

SYNC

SDI

SCLK

SDO

BUSY

RESET

CLR

AD5372/AD5373—Protected by U.S. Patent No. 5,969,657; other patents pending

n =16 FOR AD5372

n

n =14 FOR AD5373

8

n

n
n

n

n
n

8

n

n
n

n

n
n

SS

A/B SELECT

REGISTER

X1 REGISTER

MREGISTER
CREGISTER

X1 REGISTER

MREGISTER
CREGISTER

A/B SELECT

REGISTER

X1 REGISTER

MREGISTER
CREGISTER

X1 REGISTER

MREGISTER
CREGISTER

REF

AGND DNGD

·

·

·

·

·

·

·

·

·

·

·

·

(20 V)

FUNCTIONAL BLOCK DIAGRAM

8

n

n

8

n

n

TO

MUX 2's

n

n

X2A REGISTER

A/B

MUX

X2BREGISTER

n

·

n

n

n

·

·

·

·

·

n

TO

MUX 2's

n

·

·

·

·

·

·

n

A/B

MUX

A/B

MUX

A/B

MUX

·

·

·

·

·

·

·

·

·

·

·

·

·

·

·

·

·

·

n

n

·

·

·

·

·

·

n

·

·

·

·

·

·

X2A REGISTER
X2B REGISTER

X2A REGISTER
X2B REGISTER

·

·

·

·

·

·

X2A REGISTER
X2B REGISTER

Power-on reset
Digital reset (

Clear function to user-defined SIGGND (

Simultaneous update of DAC outputs (

APPLICATIONS

Level setting in automatic test equipment (ATE)
Variable optical attenuators (VOA)
Optical switches
Industrial control systems
Instrumentation

LDAC

14

OFS0

REGISTER

n

MUX

MUX

MUX

MUX

GROUP2 TO GROUP 3

ARE IDENTICALTO GROUP 1

Figure 1.

DAC 0

REGISTER

2

·

·

·

·

·

·

2

2

·

·

·

·

·

·

2

n

14

n

n

·

·

·

·

·

·

DAC 7

REGISTER

OFS1

REGISTER

DAC 0

REGISTER

·

·

·

·

·

·

DAC 7

REGISTER

RESET

n

OFFSET

DAC 0

n

DAC 0

·

·

·

·

·

·

n

DAC 7

n

OFFSET

DAC 1

n

DAC 0

·

·

·

·

·

·

n

DAC 7

VREF1 SUPPLIES
GROUP 1 TO3

SIGGND2

Voltage-Output DACs

AD5372/AD5373

)

pin)

CLR

pin)

LDAC

VREF0

VOUT0
VOUT1
VOUT2
VOUT3
VOUT4
VOUT5
VOUT6
VOUT7

SIGGND0

VREF1

VOUT8
VOUT9
VOUT10
VOUT11
VOUT12
VOUT13
VOUT14
VOUT15

SIGGND1

VOUT16
TO
VOUT31

BUFFER

BUFFER

SIGGND3

BUFFER

GROUP0

OUTPUT BUFFER

AND POWER

DOWN CONTROL

·

·

·

·

·

·

OUTPUT BUFFER

AND POWER

DOWN CONTROL

GROUP 1

OUTPUT BUFFER

AND POWER

DOWN CONTROL

·

·

·

·

·

·

OUTPUT BUFFER

AND POWER

DOWN CONTROL

Rev. PrF

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Anal og Devices. Trademarks and
registered trademarks are the property of their respective companies.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]
Fax: [phone] © 2006 Analog Devices, Inc. All rights reserved.

www.analog.com

AD5372/AD5373 Preliminary Technical Data

TABLE OF CONTENTS

Specifications......................................................................................4

Clear Function............................................................................ 16

AC Characteristics.........................................................................5

Timing Characteristics .................................................................6

Absolute Maximum Ratings.............................................................8

ESD Caution...................................................................................8

Terminology .................................................................................... 11

Functional Description.................................................................. 12

DAC Architecture—General..................................................... 12

Channel Groups.......................................................................... 12

A/ B Reigsters And Gain/Offset Adjustment.......................... 13

Load DAC.................................................................................... 13

Offset DACs ................................................................................13

Output Amplifier........................................................................ 14

Transfer Function....................................................................... 14

Reference Selection .................................................................... 14

Calibration................................................................................... 15

BUSY and LDAC Functions...................................................... 16

Power-Down Mode.................................................................... 16

Thermal Monitor Function....................................................... 16

Toggle Mode................................................................................ 17

Serial Interface ................................................................................ 18

SPI Write Mode........................................................................... 18

SPI Readback Mode ...................................................................19

Register Update Rates................................................................ 19

Channel Addressing And Special Modes................................ 19

Special Function Mode.............................................................. 20

Power Supply Decoupling ......................................................... 22

Power Supply Sequencing ......................................................... 22

Interfacing Examples...................................................................... 23

Outline Dimensions....................................................................... 24

Ordering Guide........................................................................... 24

AD5372 Calibration Example................................................... 15

Reset Function ............................................................................16

REVISION HISTORY

Pr B1 Modified SPI timing diagrams

Added Reference Selection and Calibration text

Pr. B2 Added Reset Function text

Pr. B3 Added Power Down Mode text

Pr. B4 Added Terminology and Power Supply Sequencing sections

Pr D Rewrote calibration section
Changed SPI read diagram

Pr F. Changed LFCSP Vout8 and Vout9 positions

Rev. PrF| Page 2 of 25

Preliminary Technical Data AD5372/AD5373

General Description

The AD5372 and AD5373 contain 32, 16-bit or 14-bit DACs in
a single, 56-lead, LFCSP or 64-lead LQFP package. The
AD5372/AD5373 provides buffered voltage outputs with a span
4 times the reference voltage. The gain and offset of each DAC
can be independently trimmed to remove errors. For even
greater flexibility, the device is divided into 4 groups of 8 DACs.
Two offset DACs allow the output range of the groups to be
altered. Group 0 can be adjusted by Offset DAC 0, and group 1
to group 3 can be adjusted by Offset DAC 2.

The ADAD5372/AD5373 offers guaranteed operation over a
wide supply range with V

from -4.5 V to -16.5 V and VDD

SS

from+8 V to +16.5 V. The output amplifier headroom
requirement is 1.4 V operating with a load current of 1 mA.

Table 1. High Channel Count Bipolar DACs

Model Resolution Nominal Output

Span

AD5360BCPZ 16 Bits
AD5360BSTZ 16 Bits
AD5361BCPZ 14 Bits
AD5361BSTZ 14 Bits
AD5362BCPZ 16 Bits
AD5362BSTZ 16 Bits
AD5363BCPZ 14 Bits
AD5363BSTZ 14 Bits
AD5370BCPZ 16 Bits
AD5370BSTZ 16 Bits
AD5371BCPZ 14 Bits
AD5371BSTZ 14 Bits
AD5372BCPZ 16 Bits
AD5372BSTZ 16 Bits
AD5373BCPZ 14 Bits
AD5373BSTZ 14 Bits

4 × V
4 × V
4 × V
4 × V
4 × V
4 × V
4 × V
4 × V
4 × V
4 × V
4 × V
4 × V
4 × V
4 × V
4 × V
4 × V

(20 V)

REF

(20 V)

REF

(20 V)

REF

(20 V)

REF

(20 V)

REF

(20 V)

REF

(20 V)

REF

(20 V)

REF

(12 V)

REF

(12 V)

REF

(12 V)

REF

(12 V)

REF

(12 V)

REF

(12 V)

REF

(12 V)

REF

(12 V)

REF

Output
Channels

16 ±4 56-Lead LFCSP CP-56
16 ±4 52-Lead LQFP ST-52
16 ±1 56-Lead LFCSP CP-56
16 ±1 52-Lead LQFP ST-52
8 ±4 56-Lead LFCSP CP-56
8 ±4 52-Lead LQFP ST-52
8 ±1 56-Lead LFCSP CP-56
8 ±1 52-Lead LQFP ST-52
40 ±4 64-Lead LFCSP CP-64
40 ±4 64-Lead LQFP ST-64
40 ±1 100-Ball CSPBGA BC-100-2
40 ±1 80-Lead LQFP ST-80
32 ±4 56-Lead LFCSP CP-56
32 ±4 64-Lead LQFP ST-64
32 ±1 56-Lead LFCSP CP-56
32 ±1 64-Lead LQFP ST-64

The ADAD5372/AD5373 has a high-speed serial interface,
which is compatible with SPI®, QSPI™, MICROWIRE™, and DSP
interface standards and can handle clock speeds of up to 50
MHz.

The DAC outputs are updated on reception of new data into the
DAC registers. All the outputs can be updated simultaneously
by taking the

LDAC

input low. Each channel has a program-

mable gain and an offset adjust register.

Each DAC output is gained and buffered on-chip with respect
to an external SIGGND input. The DAC outputs can also be

CLR

switched to SIGGND via the

pin.

Linearity Error
(LSB) Package Description Package Option

Rev. PrF | Page 3 of 25

AD5372/AD5373 Preliminary Technical Data

SPECIFICATIONS

DVCC = 2.3 V to 5.5 V; VDD = 8 V to 16.5 V; VSS = −4.5 V to −16.5 V; V
Gain (m), Offset(c) and DAC Offset registers at default value; all specifications T

Table 2. Performance Specifications

Parameter AD53721

B Version

AD5373
B Version

ACCURACY

Resolution 16 14 Bits
Relative Accuracy ±4 ±1 LSB max
Differential Nonlinearity ±1 ±1 LSB max Guaranteed monotonic by design over temperature.
Offset Error ±20 ±20 mV max Before Calibration
Gain Error ±20 ±20 mV max Before Calibration
Offset Error2 100 100 µV max After Calibration
Gain Error2 100 100 µV max After Calibration
Gain Error of Offset DAC ±35 ±35 mV

VOUT Temperature Coefficient 5 5

DC Crosstalk2 0.5 0.5 mV max

REFERENCE INPUTS (VREF1, VREF2)2

V

DC Input Impedance 1 1 MΩ min Typically 100 MΩ.

REF

V

Input Current 60 60 nA max Per input. Typically ±30 nA.

REF

V

Range 2/5 2/5 V min/max ±2% for specified operation.

REF

SIGGND INPUT (SIGGND0 TO SIGGND4)2

DC Input Impedance 55 55 kΩ min Typically 60 kΩ.
Input Range ±0.5 ±0.5 V min/max

OUTPUT CHARACTERISTICS2

Output Voltage Range VSS + 1.4 VSS + 1.4 V min I
V

− 1.4 VDD − `.4 V max I

DD

Short Circuit Current 5 5 mA max
Load Current ±1 ±1 mA max
Capacitive Load 2200 2200 pF max
DC Output Impedance 1 1 Ω max

DIGITAL INPUTS JEDEC compliant.

Input High Voltage 1.7 1.7 V min IOVCC = 2.5 V to 3.6 V.

2.0 2.0 V min IOV
Input Low Voltage 0.8 0.8 V max IOVCC = 2.5 V to 5.5 V.
Input Current (with pull-up/pull-

±8 ±8 µA max CLR and RESET pin only.

down)
Input Current (no pull-up/pull-down) ±1 ±1 µA max All other digital input pins.
Input Capacitance2 10 10 pF max

DIGITAL OUTPUTS (SDO)

Output Low Voltage 0.5 0.5 V max Sinking 200 µA.
Output High Voltage (SDO) DVCC − 0.5 DVCC − 0.5 V min Sourcing 200 µA.
High Impedance Leakage Current −5 −5 µA max SDO only.
High Impedance Output Capacitance2 10 10 pF typ

= 3 V; AGND = DGND = SIGGND = 0 V; RL = Open Circuit;

REF

to T

MIN

1

Unit Test Conditions/Comments2

, unless otherwise noted.

MAX

Positive or Negative Full Scale. See Offset DACs
section for details

ppm FSR/°C

Includes linearity, offset, and gain drift.

typ

Typically 100 µV. Measured channel at mid-scale, full­scale change on any other channel

= 1 mA.

LOAD

= 1 mA.

LOAD

= 3.6 V to 5.5 V.

CC

Rev. PrF| Page 4 of 25

Preliminary Technical Data AD5372/AD5373

Parameter AD53721

B Version

AD5373
B Version

1

Unit Test Conditions/Comments

2

POWER REQUIREMENTS

DVCC 2.3/5.5 2.3/5.5 V min/max

VDD 8/16.5 8/16.5 V min/max

VSS −4.5/−16.5 −4.5/−16.5 V min/max

Power Supply Sensitivity2

∆ Full Scale/∆ VDD −75 −75 dB typ
∆ Full Scale/∆ VSS −75 −75 dB typ

∆ Full Scale/∆ VCC −90 −90 dB typ
DICC 2 2 mA max VCC = 5.5 V, VIH = VCC, VIL = GND.
IDD 14 14 mA max Outputs unloaded.
ISS 14 14 mA max Outputs unloaded.
Power Dissipation

Power Dissipation Unloaded (P) 350 350 mW

Junction Temperature3 130 130 °C max TJ = TA + P

TOTAL

× θJ.

1

Temperature range for B Version: −40°C to +85°C. Typical specifications are at 25°C.

2

Guaranteed by design and characterization, not production tested.

3

Where θJ represents the package thermal impedance.

AC CHARACTERISTICS

DVCC = 2.5 V; VDD = 15 V; VSS = −15 V; V
Gain (m), Offset(c) and DAC Offset registers at default value; all specifications T

Table 3. AC Characteristics

Parameter AD5372/

DYNAMIC PERFORMANCE1

Output Voltage Settling Time 20 µs typ Full-scale change
30 µs max DAC latch contents alternately loaded with all 0s and all 1s.
Slew Rate 1 V/µs typ
Digital-to-Analog Glitch Energy 20 nV-s typ
Glitch Impulse Peak Amplitude 10 mV max
Channel-to-Channel Isolation 100 dB typ V
DAC-to-DAC Crosstalk 40 nV-s typ Between DACs in the same group.
10 nV-s typ Between DACs from different groups.
Digital Crosstalk 0.1 nV-s typ
Digital Feedthrough 1 nV-s typ Effect of input bus activity on DAC output under test.
Output Noise Spectral Density @ 10 kHz 250 nV/(Hz)

1

Guaranteed by design and characterization. Not production tested

= 3 V; AGND = DGND = SIGGND = 0 V; CL = 200pF; RL = 10 kΩ;

REF

MIN

to T

, unless otherwise noted.

MAX

Unit Test Conditions/Comments

AD5373

(+) = 2 V p-p, 1 kHz.

REF

1/2

typ V

REF

= 0 V.

Rev. PrF | Page 5 of 25

AD5372/AD5373 Preliminary Technical Data

TIMING CHARACTERISTICS

DVCC = 2.3 V to 5.5 V; VDD = 8 V to 16.5 V; VSS = −4.5 V to −16.5 V; V
R

= Open Circuit; Gain (m), Offset(c) and DAC Offset registers at default value; all specifications T

L

SPI INTERFACE (Figure 4 and Figure 5)

Parameter1, 2, 3 Limit at TMIN, TMAX Unit Description

t

1

20 ns min SCLK Cycle Time.

t2 8 ns min SCLK High Time.
t3 8 ns min SCLK Low Time.
t4 11 ns min

t

5

20 ns min

t6 10 ns min
t

7

5 ns min Data Setup Time.

SYNC Falling Edge to SCLK Falling Edge Setup Time.
Minimum SYNC High Time.
24th SCLK Falling Edge to SYNC Rising Edge.

t8 5 ns min Data Hold Time.

3

t

42 ns max

9

t

1.25 µs max

10

SYNC Rising Edge to BUSY Falling Edge.

Pulse Width Low (Single-Channel Update.) See Table 7.

BUSY

t11 500 ns max Single-Channel Update Cycle Time
t

20 ns min

12

t13 10 ns min
t14 3

µs max

t15 0 ns min
t16 3

µs max

24th SCLK Falling Edge to LDAC Falling Edge.
LDAC Pulse Width Low.
BUSY Rising Edge to DAC Output Response Time.
BUSY Rising Edge to LDAC Falling Edge.
LDAC Falling Edge to DAC Output Response Time.

t17 20/30 µs typ/max DAC Output Settling Time.
t18 125 ns max

t19 330 ns min
t20 400 µs max

t21 270 ns min

5

t

25 ns max SCLK Rising Edge to SDO Valid.

22

1

Guaranteed by design and characterization, not production tested.

2

All input signals are specified with tr = tf = 2 ns (10% to 90% of VCC) and timed from a voltage level of 1.2 V.

3

See Figure 4 and Figure 5.

4

This is measured with the load circuit of Figure 2.

5

This is measured with the load circuit of Figure 3.

TO

OUTPUT

PIN

C

L

Figure 2. Load Circuit for

50pF

BUSY

V

CC

RL2.2kΩ

Timing Diagram

V

OL

/RESET Pulse Activation Time.

CLR

Pulse Width Low.

RESET
RESET Time Indicated by BUSY Low.
Minimum SYNC

= 3 V; AGND = DGND = SIGGND = 0 V;

REF

to T

MIN

MAX

High Time in Readback Mode.

200µA

TO

OUTPUT

PIN

C

50pF

L

200µA

Figure 3. Load Circuit for SDO Timing Diagram

I

OL

I

OL

, unless otherwise noted.

VOH(min)-VOL(max)

2

Rev. PrF| Page 6 of 25

Preliminary Technical Data AD5372/AD5373

SCLK

SYNC

BUSY

LDAC

VOUT

LDAC

VOUT

CLR

VOUT

SDI

1

1

2

2

1

2

t

4

t

5

t

7

t

8

DB23

t

1

24

t

3

t

2

t

6

DB0

t

9

t

18

1

t

t

10

t

12

t

24

11

13

t

17

t

14

t

15

t

13

t

17

t

16

t

19

RESET

VOUT

BUSY

1

LDAC ACTIVE DURING BUSY.

2

LDAC ACTIVE AFTER BUSY.

t

18

t

20

05814-004A

Figure 4.

SPI Write Timing

t

22

SCLK

SYNC

SDI

SDO

5371-0005D

24

DB23 DB0

INPUTWORD SPECIFIES

REGISTERTO BE READ

LSB FROMPREVIOUS WRITE

SPI Read Timing

Figure 5.

t

21

DB23

NOP CONDITION

DB0

DB23

SELECTED REGISTER DATA

CLOCKED OUT

48

DB0

DB0

Rev. PrF | Page 7 of 25

AD5372/AD5373 Preliminary Technical Data

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.
Transient currents of up to 100 mA do not cause SCR latch-up.

Table 4. Absolute Maximum Ratings

Parameter Rating

VDD to AGND −0.3 V to +17 V
VSS to AGND −17 V to +0.3 V
DVCC to DGND −0.3 V to +7 V
Digital Inputs to DGND −0.3 V to VCC + 0.3 V
Digital Outputs to DGND −0.3 V to VCC + 0.3 V
V

1, V

2 to AGND −0.3 V to +7 V

REF

REF

VOUT0–VOUT39 to AGND VSS − 0.3 V to VDD + 0.3 V
SIGGND to AGND VSS − 0.3 V to VDD + 0.3 V
AGND to DGND −0.3 V to +0.3 V
Operating Temperature Range (TA)

Industrial (B Version) −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Junction Temperature ( TJ max) 130°C
θJA Thermal Impedance

56-LFCSP 24°C/w

64-LQFP 45.5°C/w
Reflow Soldering

Peak Temperature 230°C

Time at Peak Temperature 10 s to 40 s

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only, and functional operation of the device at these or
any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may
affect device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. PrF| Page 8 of 25

Preliminary Technical Data AD5372/AD5373

6

5

RESET

BUSY

VOUT27

SIGGND3

VOUT28
VOUT29
VOUT30
VOUT31

NC
NC
NC
NC
NC
NC
NC

VDD

2

2

T

T

C

U

U

R

A

L

O

O

D

C

L

V

V

64 63 62 61 60 59 58

1

PIN1

2

IDENTIFIER
3
4

5
6
7
8
9

10
11
12

13

14
15
16

17 18 19 20 21 22 23 24

1

S

C

C

F

S

N

N

E

V

R
V

4

2

D

D

T

C

N

N

U

C

I

O

V

G

G

O
V

A

(Not to Scale)

8

9

T

T

U

U

O

O

V

V

D

D

D

S

D

S

57 56 55 54 53 52 51 50 49

AD5372
AD5373

TOP VIEW

25 26

2

1

1

0

1

1

1

D

T

T

T

N

U

U

U

G

O

O

O

G

I

V

V

V

S

K
L
C
S

27

28

3

1
T
U
O
V

7

6

D

T

T

C

C

N

U

U

C

N

V

G

O

Y
S

29

4

1
T
U
O
V

O

D

V

D

V

48

VOUT5

47

VOUT4

46

SIGGND0

45

VOUT3

44

VOUT2

43

VOUT1

42

VOUT0

41

VREF0

40

VOUT23

39

VOUT22

38

VOUT21

37

VOUT20

36

VSS

35

VDD

34

SIGGND2

33

VOUT19

100605

32

30

31

8

7

6

5

1

1

1

1

T

T

T

T

U

U

U

U

O

O

O

O

V

V

V

V

LDAC

CLR

RESET

BUSY

VOUT27

SIGGND3

VOUT28
VOUT29
VOUT30
VOUT31

NC

VDD

VSS

VREF1

NC = NO CONNECT

6
2
T
U

O
V

6
5

1
2
3
4
5
6
7
8

9
10
11
12
13
14

5
1

9
T
U

O
V

Figure 7. 56-Lead LFCSP

Figure 6.64-Lead LQFP

Pin Configuration

Table 5. Pin Function Descriptions

Pin Function

DVCC

Logic Power Supply; 2.5 V to 5.5 V. These pins should be decoupled with 0.1 µF ceramic capacitors and 10 µF
capacitors.

VSS

Negative Analog Power Supply; −11.4 V to −16.5 V for specified performance. These pins should be decoupled with

0.1 µF ceramic capacitors and 10 µF capacitors.

VDD

Positive Analog Power Supply; +11.4 V to +16.5 V for specified performance. These pins should be decoupled with

0.1 µF ceramic capacitors and 10 µF capacitors.
AGND Ground for All Analog Circuitry. All AGND pins should be connected to the AGND plane.
DGND Ground for All Digital Circuitry. All DGND pins should be connected to the DGND plane.
V

0 Reference Input for DACs 0 to 7. This reference voltage is referred to AGND.

REF

V

1 Reference Input for DACs 8 to 31. This reference voltage is referred to AGND.

REF

VOUT0 to VOUT31

DAC Outputs. Buffered analog outputs for each of the 40 DAC channels. Each analog output is capable of driving an

output load of 10 kΩ to ground. Typical output impedance of these amplifiers is 1 Ω.
SYNC1
SCLK1

Active Low Input. This is the frame synchronization signal for the serial interface.

Serial Clock Input. Data is clocked into the shift register on the falling edge of SCLK. This pin operates at clock speeds

up to 50 MHz.
SDI1 Serial Data Input. Data must be valid on the falling edge of SCLK.
SDO1

Serial Data Output. CMOS output. SDO can be used for readback. Data is clocked out on SDO on the rising edge of

SCLK and is valid on the falling edge of SCLK.
CLR
LDAC

RESET

Asynchronous Clear Input (level sensitive, active low). See the Clear Function section for more information

Load DAC Logic Input (Active Low).See the

BUSY

AND

LDAC

FUNCTIONS section for more information.

Asynchronous Digital Reset Input.

5

4

2

2

D

D

T

T

C

N

N

U
O
V

5
5

U

C

G

V

G

O

D

D

A

V

1

2

3

4

5

5

5

5

PIN 1
INDICATOR

O
D
S
0
5

AD5372/

AD5373

TOP VIEW

(Not to scale)

6
1

8
T
U

O
V

2

2

1

1

1

3

2

1

1

0

1

1

1

1

D

T

T

T

T

N

U

U

U

U

G

O

O

O

O

V

V

IG

V

V

S

1

0

9

8

7

6

7

D

T

T

C

C

K

N

U

U

L

I

C

N

G

V

Y

C

D

S

S

8

9

4

4

3

2

2

2

5

4

1

1

T

T

U

U

O

O

V

V

O

O

V

V

D

D

S

3

4

5

6

7

4

4

4

4

4

8

7

6

5

4

2

2

2

2

2

2

9

8

7

6

1

1

1

T

D

1

T

T

T

N

U

U

U

U

G

O

O

O

O

G

I

V

V

V

V

S

Pin Configuration

42

VOUT5
VOUT4

41
40

SIGGND0

39

VOUT3

38

VOUT2

37

VOUT1
VOUT0

36
35

VREF0

34

VOUT23

33

VOUT22

32

VOUT21

31

VOUT20

30

VSS

29

VDD

5372-0060

Rev. PrF | Page 9 of 25

AD5372/AD5373 Preliminary Technical Data

Pin Function

BUSY

SIGGND0 Reference Ground for DACs 0 to 7. VOUT0 to VOUT7 are referenced to this voltage.
SIGGND1 Reference Ground for DACs 8 to 15. VOUT7 to VOUT15 are referenced to this voltage.
SIGGND1 Reference Ground for DACs 16 to 23. VOUT16 to VOUT23 are referenced to this voltage.
SIGGND3 Reference Ground for DACs 24 and 31. VOUT24 to VOUT31 are referenced to this voltage.
EXPOSED PADDLE The Lead Free Chip Scale Package (LFCSP) has an exposed paddle on the underside. This should be connected to VSS

Digital Input/Open-Drain Output. BUSY
for more information.

is open-drain when an output. See the

BUSY

AND

LDAC

FUNCTIONS section

Rev. PrF| Page 10 of 25

Preliminary Technical Data AD5372/AD5373

TERMINOLOGY

Relative Accuracy

Relative accuracy, or endpoint linearity, is a measure of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after
adjusting for zero-scale error and full-scale error and is
expressed in least significant bits (LSB).

Differential Nonlinearity

Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of 1 LSB maximum
ensures monotonicity.

Zero-Scale Error

Zero-scale error is the error in the DAC output voltage when all
0s are loaded into the DAC register.
Zero-scale error is a measure of the difference between VOUT
(actual) and VOUT (ideal) expressed in mV. Zero-scale error is
mainly due to offsets in the output amplifier.

Full-Scale Error

Full-scale error is the error in DAC output voltage when all 1s
are loaded into the DAC register.
Full-scale error is a measure of the difference between VOUT
(actual) and VOUT (ideal) expressed in mV. It does not include
zero-scale error.

Gain Error Gain error is the difference between full-scale error
and zero-scale error. It is expressed in mV.

Gain Error = Full-Scale Error − Zero-Scale Error

VOUT Temperature Coefficient

This includes output error contributions from linearity, offset,
and gain drift.

DC Output Impedance

DC output impedance is the effective output source resistance.
It is dominated by package lead resistance.

DC Crosstalk

The DAC outputs are buffered by op amps that share common

and VSS power supplies. If the dc load current changes in

V

DD

one channel (due to an update), this can result in a further dc
change in one or more channel outputs. This effect is more
significant at high load currents and reduces as the load
currents are reduced. With high impedance loads, the effect is
virtually immeasurable. Multiple V

and VSS terminals are

DD

provided to minimize dc crosstalk.

Output Voltage Settling Time

The amount of time it takes for the output of a DAC to settle to
a specified level for a full-scale input change.

Digital-to-Analog Glitch Energy

The amount of energy injected into the analog output at the
major code transition. It is specified as the area of the glitch in
nV-s. It is measured by toggling the DAC register data between
0x1FFF and 0x2000.

Channel-to-Channel Isolation

Channel-to-channel isolation refers to the proportion of input
signal from one DAC’s reference input that appears at the
output of another DAC operating from another reference. It is
expressed in dB and measured at midscale.

DAC-to-DAC Cross talk

DAC-to-DAC crosstalk is the glitch impulse that appears at the
output of one converter due to both the digital change and
subsequent analog output change at another converter. It is
specified in nV-s.

Digital Crosstalk

The glitch impulse transferred to the output of one converter
due to a change in the DAC register code of another converter is
defined as the digital crosstalk and is specified in nV-s.

Digital Feedthrough

When the device is not selected, high frequency logic activity on
the device’s digital inputs can be capacitively coupled both
across and through the device to show up as noise on the
VOUT pins. It can also be coupled along the supply and ground
lines. This noise is digital feedthrough.

Output Noise Spectral Density

Output noise spectral density is a measure of internally
generated random noise. Random noise is characterized as a
spectral density (voltage per √Hz). It is measured by loading all
DACs to midscale and measuring noise at the output. It is

1/2

measured in nV/(Hz)

Rev. PrF | Page 11 of 25

AD5372/AD5373 Preliminary Technical Data

FUNCTIONAL DESCRIPTION

DAC ARCHITECTURE—GENERAL

The ADAD5372/AD5373 contains 32 DAC channels and 32
output amplifiers in a single package. The architecture of a
single DAC channel consists of a 16-bit (AD5372) or 14-bit
(AD5373) resistor-string DAC followed by an output buffer
amplifier. The resistor-string section is simply a string of
resistors, each of value R, from V
architecture guarantees DAC monotonicity. The 16-bit
(AD5372) or 14-bit (AD5373) binary digital code loaded to the
DAC register determines at which node on the string the

Table 6. AD5372(AD5373) Registers

Register Name Word Length (Bits) Description

X1A (group)(channel) 16(14) Input data register A, one for each DAC channel.
X1B (group) (channel) 16(14) Input data register B, one for each DAC channel.
M (group) (channel) 16(14) Gain trim registers, one for each DAC channel.
C (group) (channel) 16(14) Offset trim registers, one for each DAC channel.
X2A (group)(channel) 16(14)

X2B (group) (channel) 16(14)

DAC (group) (channel)

OFS0 14 Offset DAC 0 data register, sets offset for Group 0.
OFS1 14 Offset DAC 1 data register, sets offset for Groups 1 to 3.
Control 3

A/B Select 0 8

A/B Select 1 8 Each bit in this register determines if a DAC in Group 1 takes its data from register

A/B Select 2 8 Each bit in this register determines if a DAC in Group 2 takes its data from register

A/B Select 3 8 Each bit in this register determines if a DAC in Group 3 takes its data from register

to AGND. This type of

REF

Output data register A, one for each DAC channel. These registers store the final,
calibrated DAC data after gain and offset trimming. They are not readable, nor directly
writable.

Output data register B, one for each DAC channel. These registers store the final,
calibrated DAC data after gain and offset trimming. They are not readable, nor directly
writable.

Data registers from which the DACs take their final input data. The DAC registers are
updated from the X2A or X2B registers. They are not readable, nor directly writable.

A

Bit 2 =
Bit 1 = Enable Temp Shutdown. 0 = disable temp shutdown. 1 = enable.
Bit 0 = Soft Power Down. 0 = soft power up. 1 = soft power down.
Each bit in this register determines if a DAC in Group 0 takes its data from register

X2A or X2B (0 = X2A, 1 = X2B)

/B. 0 = global selection of X1A input data registers. 1 = X1B registers.

X2A or X2B (0 = X2A, 1 = X2B)

X2A or X2B (0 = X2A, 1 = X2B)

X2A or X2B (0 = X2A, 1 = X2B)

voltage is tapped off before being fed into the output amplifier.
The output amplifier multiplies the DAC out voltage by 4. The
output span is 12 V with a 3 V reference and 20 V with a 5 V
reference.

CHANNEL GROUPS

The 32 DAC channels of the AD5372/AD5373 are arranged
into four groups of 8 channels. The eight DACs of Group 0
derive their reference voltage from VREF0. Group 1 to Group 3
derive their reference voltage from VREF1. Each group has its
own signal ground pin

.

Rev. PrF| Page 12 of 25

Preliminary Technical Data AD5372/AD5373

A/ B REIGSTERS AND GAIN/OFFSET ADJUSTMENT

Each DAC channel has seven data registers. The actual DAC
data word can be written to either the X1A or X1B input
register, depending on the setting of the
Register. If the
register. If the

A

/B bit is 0, data will be written to the X1A

A

/B bit is 1, data will be written to the X1B
register. Note that this single bit is a global control and affects
every DAC channel in the device. It is not possible to set up the
device on a per-channel basis so that some writes are to X1A
registers and some writes are to X1B registers.

X1A

REGISTER

X1B

REGISTER

REGISTER

REGISTER

MUX

M

C

Figure 8. Data Registers Associated With Each DAC Channel

X2A

REGISTER

X2B

REGISTER

Each DAC channel also has a gain (M) and offset (C) register,
which allow trimming out of the gain and offset errors of the
entire signal chain. Data from the X1A register is operated on
by a digital multiplier and adder controlled by the contents of
the M and C registers. The calibrated DAC data is then stored in
the X2A register. Similarly, data from the X1B register is
operated on by the multiplier and adder and stored in the X2B
register.

Although a multiplier and adder symbol are shown for each
channel, there is only one multiplier and one adder in the
device, which are shared between all channels. This has
implications for the update speed when several channels are
updated at once, as described later.

Each time data is written to the X1A register, or to the M or C

A

register with the

/B control bit set to 0, the X2A data is
recalculated and the X2A register is automatically updated.
Similarly, X2B is updated each time data is written to X1B, or to
M or C with

A

/B set to 1. The X2A and X2B registers are not

readable, nor directly writable by the user.

Data output from the X2A and X2B registers is routed to the
final DAC register by a multiplexer. Whether each individual
DAC takes its data from the X2A or X2B register is controlled
by an 8-bit A/B Select Register associated with each group of 8
DACs. If a bit in this register is 0, the DAC takes its data from
the X2A register; if 1 the DAC takes its data from the X2B
register (bit 0 controls DAC 0 through bit 7 controls DAC 7).

Note that, since there are 32 bits in 4 registers, it is possible to
set up, on a per-channel basis, whether each DAC takes its data
from the X2A or X2B register. A global command is also
provided that sets all bits in the A/B Select Registers to 0 or to 1.

A

/B bit in the Control

MUX

DAC

REGISTER

DAC

LOAD DAC

All DACs in the AD5372/AD5373 can be updated

LDAC

simultaneously by taking

low, when each DAC register
will be updated from either its X2A or X2B register, depending
on the setting of the A/B select registers. The DAC register is
not readable, nor directly writable by the user.

OFFSET DACS

In addition to the gain and offset trim for each DAC, there are
two 14-bit Offset DACs, one for Group 0, and one for Group 1
to Group 3. These allow the output range of all DACs connected
to them to be offset within a defined range. Thus, subject to the
limitations of headroom, it is possible to set the output range of
Group 0 or Group 1 to Group3 to be unipolar positive, unipolar
negative, or bipolar, either symmetrical or asymmetrical about
zero volts. The DACs in the AD5372/AD5373 are factory
trimmed with the Offset DACs set at their default values. This
gives the best offset and gain performance for the default
output range and span.
When the output range is adjusted by changing the value of the
Offset DAC an extra offset is introduced due to the gain error
of the Offset DAC. The amount of offset is dependent on the
magnitude of the reference and how much the Offset DAC
moves from its default value. This offset is quoted on the
specification page. The worst case offset occurs when the Offset
DAC is at positive or negative full-scale. This value can be
added to the offset present in the main DAC of a channel to
give an indication of the overall offset for that channel. In most
cases the offset can be removed by programming the channels
C register with an appropriate value. The extra offset cause by
the Offset DACs only needs to be taken into account when the
Offset DAC is changed from its default value. Figure 9 shows
the allowable code range which may be loaded to the Offset
DAC and this is dependant on the reference value used. Thus,
for a 5V reference, the Offset DAC should not be programmed
with a value greater than 8192 (0x2000).

5

4

3

)
V

(
F

E
R
V

2

1

0

0 4096 8192 12288 16383

OFFSET DAC CODE

Figure 9. Offset DAC Code Range

RESERVED

0

0

2

0

-

0

7

3

5

Rev. PrF | Page 13 of 25

AD5372/AD5373 Preliminary Technical Data

OUTPUT AMPLIFIER

As the output amplifiers can swing to 1.4 V below the positive
supply and 1.4 V above the negative supply, this limits how
much the output can be offset for a given reference voltage. For
example, it is not possible to have a unipolar output range of
20V, since the maximum supply voltage is ±16.5 V.

S1

S2

CLR

SIGGND

R6

10kΩ

S3

OUTPUT

CLR

SIGGND

OFFSET

DAC

2049-0008

DAC

CHANNEL

R5
R1

CLR

R2

R4

R3

CHECK VALUE OF R1 &R5

R1,R2,R3 = 20kΩ
R4,R5 = 60kΩ
R6 = 10kΩ

Figure 10. Output Amplifier and Offset DAC

Figure 10 shows details of a DAC output amplifier and its
connections to the Offset DAC. On power up, S1 is open,
disconnecting the amplifier from the output. S3 is closed, so the
output is pulled to SIGGND (R1 and R2 are very much greater
than R6). S2 is also closed to prevent the output amplifier being
open-loop. If
this condition until

CLR

is low at power-up, the output will remain in

CLR

is taken high. The DAC registers can
be programmed, and the outputs will assume the programmed
values when

CLR

is taken high. Even if

CLR

is high at power­up, the output will remain in the above condition until
V

> 6 V and VSS < -4 V and the initialization sequence has

DD

finished. The outputs will then go to their power-on default
value.

TRANSFER FUNCTION

The output voltage of a DAC in the AD5372/AD5373 is
dependent on the value in the input register, the value of the M
and C registers, and the offset from the Offset DAC. The
transfer functions for the AD5372 and AD5373 are shown
below.

AD5372 Transfer Function

Code applied to DAC from X1A or X1B register:­DAC_CODE = INPUT_CODE × (m+1)/2
DAC output voltage:­V

OUT

= 4 × V

× (DAC_CODE – OFFSET_CODE )/2

REF

Notes
DAC_CODE should be within the range of 0 to 65535.
For 12 V span V
For 20 V span V

= 3.0 V.

REF

= 5.0 V.

REF

X1A, X1B default code = 21844
m = code in gain register - default code = 2

16

+ c - 215

16

– 1.

16

+V

SIGGND

c = code in offset register - default code = 2

14

.
OFFSET_CODE is the code loaded to the offset DAC. It is
multiplied by 4 in the transfer function as this DAC is a 14 bit
device. On power up the default code loaded to the offset DAC
is 5461 (0x1555). With a 3V reference this gives a span of -4 V
to +8 V.

AD5373 Transfer Function

Code applied to DAC from X1A or X1B register:-

14

DAC_CODE = INPUT_CODE × (m+1)/2

+ c - 213
DAC output voltage:­V

OUT

= 4 × V

× (DAC_CODE – OFFSET_CODE )/2

REF

14

+V

SIGGND

Notes
DAC_CODE should be within the range of 0 to 16383.
For 12 V span V
For 20 V span V

= 3.0 V.

REF

= 5.0 V.

REF

X1A, X1B default code = 5461
m = code in gain register - default code = 2
c = code in offset register - default code = 2

14

13

– 1.

.

OFFSET_CODE is the code loaded to the offset DAC. It is
multiplied by 4 in the transfer function as this DAC is a 14 bit
device. On power up the default code loaded to the offset DAC
is 5461 (0x1555). With a 3V reference this gives a span of -4 V
to +8 V.

REFERENCE SELECTION

The AD5372/AD5373 has two reference input pins. The voltage
applied to the reference pins determines the output voltage span
on VOUT0 to VOUT31. VREF0 determines the voltage span for
VOUT0 to VOUT7 (Group 0) and VREF1 determines the
voltage span for VOUT8 to VOUT31 (Group 1 to Group 3).
The reference voltage applied to each VREF pin can be
different, if required, allowing the groups to have a different
voltage spans. The output voltage range can be adjusted further
by programming the offset and gain registers for each channel
as well as programming the offset DACs. If the offset and gain
features are not used (i.e. the m and c registers are left at their
default values) the required reference levels can be calculated as
follows:

VREF = (VOUT

If the offset and gain features of the AD5372/AD5373 are used,
then the required output range is slightly different. The chosen
output range should take into account the system offset and
gain errors that need to be trimmed out. Therefore, the chosen
output range should be larger than the actual, required range.

The required reference levels can be calculated as follows:

1. Identify the nominal output range on VOUT.

2. Identify the maximum offset span and the maximum

– VOUT

max

min

)/4

Rev. PrF | Page 14 of 25

Preliminary Technical Data AD5372/AD5373

gain required on the full output signal range.

3. Calculate the new maximum output range on VOUT

including the expected maximum offset and gain
errors.

4. Choose the new required VOUT

keeping the VOUT limits centered on the nominal
values. Note that V
headroom.

5. Calculate the value of VREF as follows:

VREF = (VOUTMAX – VOUTMIN)/4

and VSS must provide sufficient

DD

and VOUT

max

min

,

Reference Selection Example

Nominal Output Range = 12V (-4V to +8V)
Offset Error = ±70mV
Gain Error = ±3%
SIGGND = AGND = 0V

1) Gain Error = ±3%

=> Maximum Positive Gain Error = +3%
=> Output Range incl. Gain Error = 12 + 0.03(12)=12.36V

2) Offset Error = ±70mV

=> Maximum Offset Error Span = 2(70mV)=0.14V
=> Output Range including Gain Error and Offset Error =

12.36V + 0.14V = 12.5V

3) VREF Calculation

Actual Output Range = 12.5V, that is -4.25V to +8.25V
(centered);
VREF = (8.25V + 4.25V)/4 = 3.125V

If the solution yields an inconvenient reference level, the user
can adopt one of the following approaches:

Reducing Zero-scale and Full-scale Error

Zero-scale error can be reduced as follows:

1. Set the output to the lowest possible value.

2. Measure the actual output voltage and compare it with the

required value. This gives the zero-scale error.

3. Calculate the number of LSBs equivalent to the

error and subtract this from the default value of
the C register. Note that only negative zero-scale error can
be reduced.

Full-scale error can be reduced as follows:

1. Measure the zero-scale error.

2. Set the output to the highest possible value.

3. Measure the actual output voltage and compare it with the

required value. Add this error to the zero-scale error. This
is the full-scale error.

4. Calculate the number of LSBs equivalent to the full-scale

error and subtract it from the default value of the M
register. Note that only positive full-scale error can be
reduced.

5. The M and C registers should not be programmed until

both zero-scale and full-scale errors have been calculated.

AD5372 CALIBRATION EXAMPLE

This example assumes that a −4 V to +8 V output is required.
The DAC output is set to −4 V but measured at −4.03 V. This
gives an zero-scale error of −30 mV.

1. Use a resistor divider to divide down a convenient,

higher reference level to the required level.

2. Select a convenient reference level above VREF and

modify the Gain and Offset registers to digitally
downsize the reference. In this way the user can use
almost any convenient reference level but may reduce
the performance by overcompaction of the transfer
function.

3. Use a combination of these two approaches

CALIBRATION

The user can perform a system calibration on the AD5372 and
AD5373 to reduce gain and offset errors to below 1 LSB. This is
achieved by calculating new values for the M and C registers and
reprogramming them.

Rev. PrF | Page 15 of 25

1. 1 LSB = 12 V/65536 = 183.105 µV

2. 30 mV = 164 LSB

3. 164 LSB should be added to the default C register value:

(32768 + 164) = 32932

4. 32932 should be programmed to the C register

The full-scale error can now be removed. The output is set to +8
V and a value of +8.02 V is measured. The full-scale error is
+20 mV – (–30 mV) = +50 mV
This is a full-scale error of +50 mV.

1. 50 mV = 273 LSBs

2. 273 LSB should be subtracted from the default M register

value: (65535 − 273) = 65262

3. 65262 should be programmed to the M register

AD5372/AD5373 Preliminary Technical Data

RESET FUNCTION

When the
disconnected and the DAC outputs VOUT0 to VOUT31 are

tied to their associated SIGGND signals via a 10 kΩ resistor. On
the rising edge of

initiates a reset sequence to reset the X, M and C registers to
their default values. This sequence typically takes 300µs and the
user should not write to the part during this time. When the
reset sequence is complete, and provided that

DAC output will be at a potential specified by the default
register settings which will be equivalent to SIGGGND. The
DAC outputs will remain at SIGGND until the X, M or C
registers are updated and

pin is taken low, the DAC buffers are

RESET

the AD5372/AD5373 state machine

RESET

LDAC

is taken low.

is high, the

CLR

CLEAR FUNCTION

is an active low input which should be high for normal

CLR
operation. The
resistor. When
buffer stages, VOUT0 to VOUT31, is switched to the externally
set potential on the relevant SIGGND pin. While

pulses are ignored. When

LDAC
DAC outputs remain cleared until
contents of input registers and DAC registers 0 to 31 are not

affected by taking
the outputs
span is adjusted by writing to the offset DAC.

CLR

pin has in internal 500kΩ pull-down

CLR

is low, the input to each of the DAC output

CLR

is low, all

CLR

is taken high again, the

CLR

is taken low. The

LDAC

low. To prevent glitches appearing on

CLR

should be brought low whenever the output

BUSY AND LDAC FUNCTIONS

The value of an X2 (A or B) register is calculated each time the
user writes new data to the corresponding X1, C, or M registers.
During the calculation of X2, the
BUSY

is low, the user can continue writing new data to the X1,
M, or C registers (see the Register Update Rates section for
more details), but no DAC output updates can take place.

BUSY

The
resistor. Where multiple AD5372 or AD5373 devices may be
used in one system the
useful where it is required that no DAC in any device is updated
until all other DACs are ready. When each device has finished
updating the X2 (A or B) registers it will release the
If another device hasn’t finished updating its X2 registers it will
hold

The DAC outputs are updated by taking the
LDAC

and the DAC outputs update immediately after
high. A user can also hold the
this case, the DAC outputs update immediately after
goes high.
whenever the A/B Select Registers are written to.

pin is bidirectional and has a 50 kΩ internal pullup

BUSY

BUSY

low, thus delaying the effect of

goes low while

BUSY

BUSY

also goes low, for approximately 500ns,

BUSY

output goes low. While

pins can be tied together. This is

BUSY

pin.

LDAC

going low.

LDAC

input low. If

is active, the

LDAC

LDAC

event is stored
BUSY

goes

input permanently low. In

BUSY

As described later, the ADAD5372/AD5373 has flexible
addressing that allows writing of data to a single channel, all
channels in a group, the same channel in groups 0 to 3 or
groups 1 to 4, or all channels in the device. This means that 1, 4,
8 or 32 DAC register values may need to be calculated and
updated. As there is only one multiplier shared between 32
channels, this task must be done sequentially, so the length of

BUSY

the
being updated.

Table 7.

Action BUSY Pulse Width

Loading Input, C, or M to 1 channel 1.25
Loading Input, C, or M to 4 channels 2.75
Loading Input, C, or M to 8 channels 4.75
Loading Input, C, or M to 32 channels 16.75

BUSY

The AD5372/AD5373 contains an extra feature whereby a DAC
register is not updated unless its X2A or X2B register has been
written to since the last time

when
the contents of the X2A or X2B registers, depending on the
setting of the A/B Select Registers. However the
AD5372/AD5373 updates the DAC register only if the X2 data
has changed, thereby removing unnecessary digital crosstalk.

pulse will vary according to the number of channels

BUSY

Pulse Widths

(µs max)

Pulse Width = ((Number of Channels +1) × 500ns) +250ns

LDAC

was brought low. Normally,

LDAC

is brought low, the DAC registers are filled with

POWER-DOWN MODE

The AD5372/AD5373 can be powered down by setting Bit 0 in
the control register. This will turn off the DACs thus reducing
the current consumption. The DAC outputs will be connected
to their respective SIGGND potentials. The power-down mode
doesn’t change the contents of the registers and the DACs will
return to their previous voltage when the power-down bit is
cleared.

THERMAL MONITOR FUNCTION

The AD5372/AD5373 can be programmed to power down the
DACs if the temperature on the die exceeds 130°C. Setting Bit 1
in the control register (see Table 15) will enable this function. If
the die temperature exceeds 130°C the AD5372/AD5373 will
enter a temperature power-down mode, which is equivalent to
setting the power-down bit in the control register. To indicate
that the AD5372/AD5373 has entered temperature power-down
mode Bit 4 of the control register is set. The AD5372/AD5373
will remain in temperature shutdown mode, even if the die
temperature falls, until Bit 1 in the control register is cleared.

Rev. PrF | Page 16 of 25

Preliminary Technical Data AD5372/AD5373

TOGGLE MODE

The AD5372/AD5373 has two X2 registers per channel, X2A
and X2B, which can be used to switch the DAC output between
two levels with ease. This approach greatly reduces the overhead
required by a micro-processor which would otherwise have to
write to each channel individually. When the user writes to
either the X1A ,X2A, M or C registers the calculation engine
will take a certain amount of time to calculate the appropriate
X2A or X2B values. If the application only requires that the
DAC output switch between two levels, such as a data generator,
any method which reduces the amount of calculation time
encountered is advantageous. For the data generator example
the user need only set the high and low levels for each channel
once, by writing to the X1A and X1B registers. The values of
X2A and X2B will be calculated and stored in their respective
registers. The calculation delay therefore only happens during
the setup phase, i.e. when programming the initial values. To
toggle a DAC output between the two levels it is only required
to write to the relevant A/B Select Register to set the MUX2
register bit. Furthermore, since there are 8 MUX2 control bits
per register it is possible to update eight channels with a single
write. Table 17 shows the bits that correspond to each DAC
output.

Rev. PrF | Page 17 of 25

AD5372/AD5373 Preliminary Technical Data

SERIAL INTERFACE

The AD5372/AD5373 contains a high-speed SPI serial interface
operating at clock frequencies up to 50 MHz (20MHz for read
operations). To minimize both the power consumption of the
device and on-chip digital noise, the interface powers up fully
only when the device is being written to, that is, on the falling

SYNC

edge of
when operating from a 2.7 V to 3.6 V DV
controlled by four pins, as follows.

SYNC

Frame synchronization input.

SDI

Serial data input pin.

SCLK

Clocks data in and out of the device.

SDO

Serial data output pin for data readback.

SPI WRITE MODE

The AD5372AD5373 allows writing of data via the serial
interface to every register directly accessible to the serial
interface, which is all registers except the X2A and X2B
registers and the DAC registers. The X2A and X2B registers are
updated when writing to the X1A, X1B, M and C registers, and
the DAC registers are updated by
Table 8 or Table 9) is 24 bits long. 16 or 14 of these bits are data
bits, six bits are address bits, and two bits are mode bits that

Table 8. AD5372 Serial Word Bit Assignation

I23 I22 I21 I20 I19 I18 I17 I16 I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 I0
M1 M0 A5 A4 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Table 9. AD5373 Serial Word Bit Assignation

I23 I22 I21 I20 I19 I18 I17 I16 I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1* I0*
M1 M0 A5 A4 A3 A2 A1 A0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0

*

Reserved bits. Set to 0 when writing. Bits are read back as 0

. The serial interface is 2.5 V LVTTL compatible

supply. It is

CC

LDAC

. The serial word (see

determine what is done with the data. Two bits are reserved on
the AD5373.

The serial interface works with both a continuous and a burst
(gated) serial clock. Serial data applied to SDI is clocked into
the AD5372AD5373 by clock pulses applied to SCLK. The first

SYNC

falling edge of

starts the write cycle. At least 24 falling
clock edges must be applied to SCLK to clock in 24 bits of data,
before

SYNC

is taken high again. If

SYNC

is taken high before

the 24th falling clock edge, the write operation will be aborted.

SYNC

If a continuous clock is used,

must be taken high before
the 25th falling clock edge. This inhibits the clock within the
AD5372/AD5373. If more than 24 falling clock edges are
applied before

SYNC

is taken high again, the input data will be

corrupted. If an externally gated clock of exactly 24 pulses is

SYNC

used,

may be taken high any time after the 24th falling

clock edge.

The input register addressed is updated on the rising edge of
SYNC

. In order for another serial transfer to take place,

SYNC

must be taken low again

Rev. PrF | Page 18 of 25

Preliminary Technical Data AD5372/AD5373

SPI READBACK MODE

The ADAD5372/AD5373 allows data readback via the serial
interface from every register directly accessible to the serial
interface, which is all registers except the DAC data registers. In
order to read back a register, it is first necessary to tell the
ADAD5372/AD5373 which register is to be read. This is
achieved by writing to the device a word whose first two bits are
the special function code 00. The remaining bits then
determine if the operation is a readback, and the register which
is to be read back, or if it is a write to of the special function
registers such as the control register.
After the special function write has been performed, if it is a
readback command then data from the selected register will be
clocked out of the SDO pin during the next SPI operation. The
SDO pin is normally three-state but becomes driven as soon as
a read command has been issued. The pin will remain driven
until the registers data has been clocked out. See Figure 5 for
the read timing diagram. Note that due to the timing
requirements of t

(25ns) the maximum speed of the SPI

5

interface during a read operation should not exceed 20MHz.

REGISTER UPDATE RATES

As mentioned previously the value of the X2 (A or B) register is
calculated each time the user writes new data to the
corresponding X1, C or M registers. The calculation is
performed by a three stage process. The first two stages take
500ns each and the third stage takes 250ns. When the write to
one of the X1, C or M registers is complete the calculation
process begins. If the write operation involves the update of a
single DAC channel the user is free to write to another register
provided that the write operation doesn’t finish until the first
stage calculation is complete, i.e. 500ns after the completion of
the first write operation. If a group of channels is being updated
by a single write operation the first stage calculation will be
repeated for each channel, taking 500ns per channel. In this
case the user should not complete the next write operation until
this time has elapsed.

Table 10. Group Addressing

A5 A4 A3 Group Selected

0 0 0 All groups, all DACs
0 0 1 0
0 1 0 1
0 1 1 2
1 0 0 3
1 0 1 4
1 1 0 1, 2, 3, 4, 5
1 1 1 2, 3, 4, 5

Table 11. Channel Addressing

A2 A1 A0 Channel Selected

0 0 0 0
0 0 1 1
0 1 0 2
0 1 1 3
1 0 0 4
1 0 1 5
1 1 0 6
1 1 1 7

Table 12. Mode Bits

M1 M0 Action

1 1 Write DAC data (x) register
1 0 Write DAC offset (m) register
0 1 Write DAC gain (m) register
0 0

Special function, used in combination with other
bits of word

The AD5372/AD5373 has very flexible addressing that allows
writing of data to a single channel, all channels in a group, the
same channel in groups 0 to 3 or groups 1 to 3, or all channels
in the device Table 10 shows all these address modes.

CHANNEL ADDRESSING AND SPECIAL MODES

If the mode bits are not 00, then the data word D13 to D0 is
written to the device. Address bits A5 to A0 determine which
channel or channels is/are written to, while the mode bits
determine to which register (X1A, X1B, C or M) the data is
written, as shown in Table 8 and Table 9. If data is to be written

A

to the X1A or X1B register, the setting of the
Control Register determines which (0 Æ X1A, 1 Æ X1B).

/B bit in the

Rev. PrF | Page 19 of 25

AD5372/AD5373 Preliminary Technical Data

Table 13. Group and Channel Addressing

This table shows which group(s) and which channel(s) is/are addressed for every combination of address bits A5 to A0.

ADDRESS

BITS A2 TO

A0

000 001 010 011 100 101 110 111

All groups,

000

all channels

Group 0, all

001

channels

Group 1, all

010

channels

Group 2, all

011

channels

Group 3, all

100

channels

Reserved Group 0,

101

Reserved Group 0,

110

Reserved Group 0,

111

Group 0,
channel 0

Group 0,
channel 1

Group 0,
channel 2

Group 0,
channel 3

Group 0,
channel 4

channel 5

channel 6

channel 7

Group 1,
channel 0

Group 1,
channel 1

Group 1,
channel 2

Group 1,
channel 3

Group 1,
channel 4

Group 1,
channel 5

Group 1,
channel 6

Group 1,
channel 7

ADDRESS BITS A5 TO A3

Group 2,
channel 0

Group 2,
channel 1

Group 2,
channel 2

Group 2,
channel 3

Group 2,
channel 4

Group 2,
channel 5

Group 2,
channel 6

Group 2,
channel 7

Group 3,
channel 0

Group 3,
channel 1

Group 3,
channel 2

Group 3,
channel 3

Group 3,
channel 4

Group 3,
channel 5

Group 3,
channel 6

Group 3,
channel 7

Reserved Groups 0,1,2,3

channel 0

Reserved Groups 0,1,2,3

channel 1

Reserved Groups 0,1,2,3

channel 2

Reserved Groups 0,1,2,3

channel 3

Reserved Groups 0,1,2,3

channel 4

Reserved Groups 0,1,2,3

channel 5

Reserved Groups 0,1,2,3

channel 6

Reserved Groups 0,1,2,3

channel 7

Groups 1,2,3
channel 0

Groups 1,2,3
channel 1

Groups 1,2,3
channel 2

Groups 1,2,3
channel 3

Groups 1,2,3
channel 4

Groups 1,2,3
channel 5

Groups 1,2,3
channel 6

Groups 1,2,3
channel 7

SPECIAL FUNCTION MODE

If the mode bits are 00, then the special function mode is
selected, as shown in Table 14. Bits I21 to I16 of the serial data
word select the special function, while the remaining bits are
data required for execution of the special function, for example

The codes for the special functions are shown in Table 15. Table
16 shows the addresses for data readback.

the channel address for data readback.

Table 14. Special Function Mode

I23 I22 I21 I20 I19 I18 I17 I16 I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 I0
0 0 S5 S4 S3 S2 S1 S0 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0

Rev. PrF | Page 20 of 25

Preliminary Technical Data AD5372/AD5373

Table 15. Special Function Codes

SPECIAL FUNCTION CODE

S5 S4 S3 S2 S1 S0 F15-F0

0 0 0 0 0 0 0000 0000 0000 0000 NOP
0 0 0 0 0 1 XXXX XXXX XXXX X[F2:F0] Write control register

0 0 0 0 1 0 XX[F13:F0] Write data in F13:F0 to OFS0 register
0 0 0 0 1 1 XX[F13:F0] Write data in F13:F0 to OFS1 register
0 0 0 1 0 0 XX[F13:F0] Reserved
0 0 0 1 0 1

0 0 0 1 1 0 XXXX XXXX[F7:F0] Write data in F7:F0 to A/B Select Register 0
0 0 0 1 1 1 XXXX XXXX[F7:F0] Write data in F7:F0 to A/B Select Register 1
0 0 1 0 0 0 XXXX XXXX[F7:F0] Write data in F7:F0 to A/B Select Register 2
0 0 1 0 0 1 XXXX XXXX[F7:F0] Write data in F7:F0 to A/B Select Register 3
0 0 1 0 1 0 XXXX XXXX[F7:F0] Reserved
0 0 1 0 1 1 XXXX XXXX[F7:F0] Block write A/B Select Registers

DATA

See Table 14

Table 16. Address Codes for Data Readback

F15 F14 F13 F12 F11 F10 F9 F8 F7 REGISTER READ

0 0 0 X1A Register
0 0 1 X1B Register
0 1 0 C Register
0 1 1
1 0 0 0 0 0 0 0 1 Control Register
1 0 0 0 0 0 0 1 0 OFS0 Data Register
1 0 0 0 0 0 0 1 1 OFS1 Data Register
1 0 0 0 0 0 1 0 0 Reserved
1 0 0 0 0 0 1 1 0 A/B Select Register 0
1 0 0 0 0 0 1 1 1 A/B Select Register 1
1 0 0 0 0 1 0 0 0 A/B Select Register 2
1 0 0 0 0 1 0 0 1 A/B Select Register 3
1 0 0 0 0 1 0 1 0 Reserved

Note: F6 to F0 are don’t care for data readback function.

Bits F12 to F7 select channel to be read

back, from Channel 0 = 001000 to

Channel 31 = 100111

ACTION

F2 = 1 Æ Select B reg for input; F2 = 0 Æ Select A reg for input
F1 = 1 Æ En temp shutdown; F1 = 0 Æ Disable temp shutdown
F0 = 1 Æ Soft power down; F0 = 0 Æ soft power up

Select register for readback

F7:F0 = 0, write all 0’s (all channels use X2A register)
F7:F0 = 1, wrote all 1’s (all channels use X2B register)

M Register

Rev. PrF | Page 21 of 25

AD5372/AD5373 Preliminary Technical Data

Table 17. DACs Select by A/B Select Registers

Bits A/B Select

Register

0 VOUT7 VOUT6 VOUT5 VOUT4 VOUT3 VOUT2 VOUT1 VOUT0
1 VOUT15 VOUT14 VOUT13 VOUT12 VOUT11 VOUT10 VOUT9 VOUT8
2 VOU23 VOUT22 VOUT21 VOUT20 VOUT19 VOUT18 VOUT17 VOUT16
3 VOUT31 VOUT30 VOUT29 VOUT28 VOUT27 VOUT26 VOUT25 VOUT24

POWER SUPPLY DECOUPLING

In any circuit where accuracy is important, careful considera­tion of the power supply and ground return layout helps to
ensure the rated performance. The printed circuit board on
which the AD5372/AD5373 is mounted should be designed so
that the analog and digital sections are separated and confined
to certain areas of the board. If the AD5372/AD5373 is in a
system where multiple devices require an AGND-to-DGND
connection, the connection should be made at one point only.
The star ground point should be established as close as possible
to the device. For supplies with multiple pins (V
is recommended to tie these pins together and to decouple each
supply once.

The AD5372/AD5373 should have ample supply decoupling of
10 µF in parallel with 0.1 µF on each supply located as close to
the package as possible, ideally right up against the device. The
10 µF capacitors are the tantalum bead type. The 0.1 µF capaci­tor should have low effective series resistance (ESR) and
effective series inductance (ESI), such as the common ceramic
types that provide a low impedance path to ground at high
frequencies, to handle transient currents due to internal logic
switching.

F7 F6 F5 F4 F3 F2 F1 F0

this package during the assembly process.

POWER SUPPLY SEQUENCING

When the supplies are connected to the AD5372/AD5373 it is
important that the AGND and DGND pins are connected to the
relevant ground plane before the positive or negative supplies
are applied. In most applications this is not an issue as the
ground pins for the power supplies will be connected to the
ground pins of the AD5372/AD5373 via ground planes. Where
the AD5372/AD5373 is to be used in a hot-swap card care

, VDD, VCC), it

SS

should be taken to ensure that the ground pins are connected to
the supply grounds before the positive or negative supplies are
connected. This is required to prevent currents flowing in
directions other than towards an analog or digital ground.

Digital lines running under the device should be avoided,
because these couple noise onto the device. The analog ground
plane should be allowed to run under the AD5372/AD5373 to
avoid noise coupling. The power supply lines of the
AD5372/AD5373 should use as large a trace as possible to
provide low impedance paths and reduce the effects of glitches
on the power supply line. Fast switching digital signals should
be shielded with digital ground to avoid radiating noise to other
parts of the board, and should never be run near the reference
inputs. It is essential to mini mize noise on all V

REF

lines.

Avoid crossover of digital and analog signals. Traces on
opposite sides of the board should run at right angles to each
other. This reduces the effects of feedthrough through the
board. A microstrip technique is by far the best, but not always
possible with a double-sided board. In this technique, the
component side of the board is dedicated to ground plane,
while signal traces are placed on the solder side.

As is the case for all thin packages, care must be taken to avoid
flexing the package and to avoid a point load on the surface of

Rev. PrF | Page 22 of 25

Preliminary Technical Data AD5372/AD5373

INTERFACING EXAMPLES

The SPI interface of the AD5372/AD5373 is designed to allow
the parts to be easily connected to industry standard DSPs and
micro-controllers. Figure 11 shows how the AD5372/AD5373
could be connected to the Analog Devices Blackfin
Blackfin has an integrated SPI port which can be connected
directly to the SPI pins of the AD5372/AD5373 and
programmable I/O pins which can be used to set or read the
state of the digital input or output pins associated with the
interface.

SPISELx

SCK
MOSI
MISO

ADSP-BF531

Figure 11. Interfacing to a Blackfin DSP

PF10

PF9
PF8
PF7

®

DSP. The

AD537x

SYNC
SCLK
SDI
SDO

RESET
LDAC
CLR
BUSY

537x-0101

transmit and receive clocks (TCLK and RCLK) are also
connected together. The user can write to the AD5372/AD5373
by writing to the transmit register. A read operation can be
accomplished by first writing to the AD5372/AD5373 to tell the
part that a read operation is required. A second write operation
with a NOP instruction will cause the data to be read from the
AD5372/AD5373. The DSPs receive interrupt can be used to
indicate when the read operation is complete.

ADSP-21065L

Figure 12. Interfacing to an ADSP-21065L DSP

TFSx

RFSx

TCLKx

RCLKx

DTxA

DRxA

FLAG0
FLAG1
FLAG2
FLAG3

AD537x

SYNC

SCLK
SDI
SDO

RESET
LDAC
CLR
BUSY

537x-0101

The Analog Devices ADSP-21065L is a floating point DSP with
two serial ports (SPORTS). Figure 12 shows how one SPORT
can be used to control the AD5372/AD5373. In this example
the Transmit Frame Synchronization (TFS) pin is connected to
the Receive Frame Synchronization (RFS) pin. Similarly the

Rev. PrF | Page 23 of 25

AD5372/AD5373 Preliminary Technical Data

OUTLINE DIMENSIONS

0.75

0.60

0.45

SEATING

PLANE

1.60
MAX

1

PIN 1

12.00

BSC SQ

4964

48

10.00

BSC SQ

33

1.45

1.40

1.35

0.15

0.05

ROTATED 90° CCW

10°

SEATING
PLANE

VIEW A

6°
2°

0.08 MAX
COPLANARITY

0.20

0.09

7°

3.5°
0°

COMPLIANT TO JEDEC STANDARDS MS-026BCD

VIEW A

16

17

0.50

BSC

TOP VIEW

(PINS DOWN)

32

0.27

0.22

0.17

Figure 13. 64-Lead Low Profile Quad Flat Package [LQFP]

(ST-64-2)

Dimensions shown in millimeters

PAD

6.50
REF

0.30

0.23

0.18

PIN 1

56

15

INDICATOR

1

6.25

6.10 SQ

5.95

14

0.25 MIN

1.00

0.85

0.80

12° MAX

SEATING
PLANE

8.00

BSC SQ

PIN 1
INDICATOR

VIEW

0.60 MAX

TOP

0.80 MAX

0.65 TYP

0.50 BSC

COMPLIANT TO JEDEC STANDARDS MO-220-VLLD-2

7.75

BSC SQ

0.20 REF

0.50

0.40

0.30

0.05 MAX

0.02 NOM
COPLANARITY

0.08

43

42

29

28

0.60 MAX

EXPOSED

(BOTTOM VIEW)

Figure 14. 56-Lead Free Chip Scale Package [LFCSP]

(CP-56)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD5372BSTZ -40°C to +85°C 64-Lead LQFP ST-64
AD5372BCPZ -40°C to +85°C 56-Lead LFCSP CP-56
AD5373BSTZ -40°C to +85°C 64-Lead LQFP ST-64
AD5373BCPZ -40°C to +85°C 56-Lead LFCSP CP-56

Rev. PrF | Page 24 of 25

Preliminary Technical Data AD5372/AD5373

NOTES

©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.

PR05815-0-10/06(PrF)

Rev. PrF | Page 25 of 25