ANALOG DEVICES AD5371 Service Manual

40-Channel, 14-Bit,

www.BDTIC.com/ADI

FEATURES

40-channel DAC in 80-lead LQFP and 100-ball CSP_BGA
Guaranteed monotonic to 14 bits
Maximum output voltage span of 4 × V
Nominal output voltage span of −4 V to +8 V
Multiple, independent output voltage spans available
System calibration function allowing user-programmable

off

set and gain
Channel grouping and addressing features
Thermal shutdown function
DSP/microcontroller-compatible serial interface
SPI/LVDS serial interface

DV

CCVDDVSS AGND DGND

STATE

14

8 8

14

14

14

14

14

14

14

14

8 8

14

14

14

14

14

14

14

14

14

A/B SELECT

REGISTER

X1A

REGISTER

X1B

REGISTER

M REGISTER

C REGISTER

X1A

REGISTER

X1B

REGISTER

M REGISTER

C REGISTER

A/B SELECT

REGISTER

X1A

REGISTER

X1B

REGISTER

M REGISTER

C REGISTER

X1A

REGISTER

X1B

REGISTER

M REGISTER

C REGISTER

SPI/LVDS

SYNC

SDI

SCLK

SYNC

SDI

SCLK

SDO

BUSY

RESET

CLR

CONTROL
REGISTER

SERIAL

INTERFACE

MACHINE

AD5371

(20 V)

REF

FUNCTIONAL BLOCK DIAGRAM

TO

MUX2

14

14

TO

MUX2

14

14

14

14

14

14

14

MUX 1MUX 1MUX 1MUX 1

14

14

14

14

14

14

14

X2A

REGISTER

X2B

REGISTER

X2A

REGISTER

X2B

REGISTER

X2A

REGISTER

X2B

REGISTER

X2A

REGISTER

X2B

REGISTER

Serial Input, Voltage Output DAC

AD5371

2.5 V to 5.5 V digital interface
Digital reset (
Clear function to user-defined SIGGNDx
Simultaneous update of DAC outputs

APPLICATIONS

Level setting in automatic test equipment (ATE)
Variable optical attenuators (VOA)
Optical switches
Industrial control systems
Instrumentation

LDAC

OFS0

REGISTER

14

DAC 0

REGISTER

MUX 2

14

DAC 7

REGISTER

MUX 2

OFS1

REGISTER

14

DAC 0

REGISTER

MUX 2

14

DAC 7

REGISTER

MUX 2

GROUP 2 TO GROUP 4

ARE SAME AS GROUP 1

RESET

1414

14

14

1414

14

14

)

OFFSET

DAC 0

DAC 0

DAC 7

OFFSET

DAC 1

DAC 0

DAC 7

BUFFER

BUFFER

BUFFER

OUTPUT BUFF ER

POWER-DOW N

OUTPUT BUFF ER

POWER-DOW N

BUFFER

OUTPUT BUFF ER

POWER-DOW N

OUTPUT BUFF ER

POWER-DOW N

VREF2 SUPPLIES

GROUP 2 TO GROUP 4

GROUP 0

AND

CONTROL

AND

CONTROL

GROUP 1

AND

CONTROL

AND

CONTROL

VREF0

VOUT0

VOUT1

VOUT2

VOUT3

VOUT4

VOUT5

VOUT6

VOUT7

SIGGND0

VREF1

VOUT8

VOUT9

VOUT10

VOUT11

VOUT12

VOUT13

VOUT14

VOUT15

SIGGND1

VREF2

VOUT16
TO
VOUT39

Figure 1.

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2007–2008 Analog Devices, Inc. All rights reserved.

SIGGND4SIGGND3SIGGND2

05814-001

AD5371

www.BDTIC.com/ADI

TABLE OF CONTENTS

Features.............................................................................................. 1

Applications....................................................................................... 1

Functional Block Diagram ..............................................................1

Revision History ...............................................................................2

General Description......................................................................... 3

Specifications..................................................................................... 4

Performance Specifications......................................................... 4

AC Characteristics........................................................................ 5

Timing Characteristics ................................................................ 6

Absolute Maximum Ratings............................................................ 9

ESD Caution.................................................................................. 9

Pin Configurations and Function Descriptions......................... 10

Typical Performance Characteristics........................................... 13

Terminology.................................................................................... 15

Theory of Operation ......................................................................16

DAC Architecture....................................................................... 16

Channel Groups.......................................................................... 16

A/B Registers and Gain/Offset Adjustment............................ 17

Load DAC.................................................................................... 17

Offset DACs ................................................................................17

Output Amplifier........................................................................ 18

Transfer Function....................................................................... 18

Reference Selection .................................................................... 18

Calibration................................................................................... 19

Additional Calibration............................................................... 19

Reset Function............................................................................ 20

Clear Function............................................................................ 20

and

LDAC

Functions...................................................... 20

BUSY

Power-Down Mode.................................................................... 20

Thermal Shutdown Function ...................................................20

Toggle Mode................................................................................ 21

Serial Interface ................................................................................ 22

SPI Interface................................................................................ 22

LVDS Interface............................................................................ 22

SPI Write Mode .......................................................................... 22

SPI Readback Mode................................................................... 23

LVDS Operation......................................................................... 23

Register Update Rates................................................................ 23

Channel Addressing and Special Modes................................. 23

Special Function Mode.............................................................. 25

Applications Information.............................................................. 27

Power Supply Decoupling......................................................... 27

Power Supply Sequencing .........................................................27

Interfacing Examples ................................................................. 27

Outline Dimensions....................................................................... 28

Ordering Guide .......................................................................... 28

REVISION HISTORY

3/08—Rev. A to Rev. B

Added Table 1.................................................................................... 3

C

hanges to Timing Characteristics Section.................................. 6

Changes to Absolute Maximum Ratings Section......................... 9

Changes to Table 7.......................................................................... 11

Changes to Figure 16, Figure 18, and Figure 19......................... 14

Changes to A/B Registers and Gain/Offset Adjustment

Section and Load DAC Section .................................................... 17

Changes to Transfer Function Section......................................... 18

Changes to Calibration Section ....................................................19

Changes to Reset Function Section and Clear Function

Section.............................................................................................. 20

Changes to Table 9.......................................................................... 20

Changes to Register Update Rates Section.................................. 23

Rev. B | Page 2 of 28

11/07—Rev. 0 to Rev. A

Reformatted Specifications Table 1.................................................3

Reformatted Specifications Table 2.................................................6

Change to A/B Registers and Gain/Offset
A

djustment Section........................................................................ 19

Change to SPI Write Mode Section.............................................. 24

Changes to Ordering Guide.......................................................... 31

8/07—Revision 0: Initial Version

AD5371

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GENERAL DESCRIPTION

The AD53711 contains 40 14-bit DACs in a single 80-lead LQFP
or 100-ball CSP_BGA. The device provides buffered voltage
outputs with a span of 4× the reference voltage. The gain and
offset of each DAC can be independently trimmed to remove
errors. For even greater flexibility, the device is divided into five
groups of eight DACs. Three offset DACs allow the output range
of the groups to be adjusted. Group 0 can be adjusted by Offset
DAC 0, Group 1 can be adjusted by Offset DAC 1, and Group 2
to Group 4 can be adjusted by Offset DAC 2.

The AD5371 offers guaranteed operation over a wide supply

nge, with V

ra

from −16.5 V to −4.5 V and VDD from 9 V to

SS

16.5 V. The output amplifier headroom requirement is 1.4 V
operating with a load current of 1 mA.

1

Protected by U.S. Patent No. 5,969,657; other patents pending.

Table 1. High Channel Count Bipolar DACs

Model Resolution (Bits) Nominal Output Span Output Channels Linearity Error (LSB)

AD5360 16 4 × V
AD5361 14 4 × V
AD5362 16 4 × V
AD5363 14 4 × V
AD5370 16 4 × V

AD5371 14 4 × V

AD5372 16 4 × V
AD5373 14 4 × V
AD5378 14 ±8.75 V 32 ±3
AD5379 14 ±8.75 V 40 ±3

(20 V) 16 ±4

REF

(20 V) 16 ±1

REF

(20 V) 8 ±4

REF

(20 V) 8 ±1

REF

(12 V) 40 ±4

REF

(12 V) 40 ±1

REF

(12 V) 32 ±4

REF

(12 V) 32 ±1

REF

The AD5371 has a high speed serial interface that is compatible
with SPI, QSPI™, MICROWIRE™, and DSP interface standards
and can handle clock speeds of up to 50 MHz. It also has a
100 MHz low voltage differential signaling (LVDS) serial
interface.

The DAC registers are updated on reception of new data. All the
o

utputs can be updated simultaneously by taking the

LDAC
input low. Each channel has a programmable gain and an offset
adjust register to allow removal of gain and offset errors.

Each DAC output is gained and buffered on chip with respect
to

an external SIGGNDx input. The DAC outputs can also be

switched to SIGGNDx via the

CLR

pin.

Rev. B | Page 3 of 28

AD5371

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SPECIFICATIONS

PERFORMANCE SPECIFICATIONS

DVCC = 2.5 V to 5.5 V; VDD = 9 V to 16.5 V; VSS = −16.5 V to −8 V; VREF = 3 V; AGND = DGND = SIGGNDx = 0 V; CL = open circuit;

= open circuit; gain (M), offset (C), and DAC offset registers at default values; temperature range for the AD5371 is −40°C to +85°C; all

R

L

specifications T

Table 2.

Parameter Min Typ1 Max Unit Test Conditions/Comments1

ACCURACY

Resolution 14 Bits
Integral Nonlinearity (INL) −1 +1 LSB
Differential Nonlinearity (DNL) −1 +1 LSB Guaranteed monotonic by design
Zero-Scale Error −10 +10 mV Before calibration
Full-Scale Error −10 +10 mV Before calibration
Gain Error 0.1 % FSR
Zero-Scale Error2 1 LSB After calibration
Full-Scale Error2 1 LSB After calibration
Span Error of Offset DAC −35 +35 mV See the Offset DACs section for details
VOUTx Temperature Coefficient

(VOUT0 to VOUT39)

DC Crosstalk2 120 µV

REFERENCE INPUTS (VREF0, VREF1, VREF2)2

VREFx Input Current −10 +10 µA Per input; typically ±30 nA
VREFx Range 2 5 V ±2% for specified operation

SIGGND INPUTS (SIGGND0 TO SIGGND4)2

DC Input Impedance 50 kΩ Typically 55 kΩ
Input Range −0.5 +0.5 V
SIGGNDx Gain 0.995 1.005

OUTPUT CHARACTERISTICS2

Output Voltage Range VSS + 1.4 VDD − 1.4 V I
Nominal Output Voltage Range −4 +8 V
Short-Circuit Current 15 mA VOUTx to DVCC, VDD, or VSS
Load Current −1 +1 mA
Capacitive Load 2200 pF
DC Output Impedance 0.5 Ω

DIGITAL INPUTS

Input High Voltage 1.7 V DVCC = 2.5 V to 3.6 V

2.0 V DVCC = 3.6 V to 5.5 V
Input Low Voltage 0.8 V DVCC = 2.5 V to 5.5 V
Input Current −1 +1 µA

CLR High Impedance Leakage Current
Input Capacitance2 10 pF

DIGITAL OUTPUTS (SDO, BUSY)

Output Low Voltage 0.5 V Sinking 200 A
Output High Voltage (SDO) DVCC − 0.5 V Sourcing 200 A
SDO High Impedance Leakage Current −5 +5 µA
High Impedance Output Capacitance2 10 pF

MIN

to T

, unless otherwise noted.

MAX

5

−20 +20 µA

ppm
FSR/°C

Includes linearity, offset, and gain drift

Typically 20 µV; measured channel at midscale,
full-scale change on any other channel

= 1 mA

LOAD

Excluding CLR

pin

Rev. B | Page 4 of 28

AD5371

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Parameter Min Typ1Max Unit Test Conditions/Comments

1

LVDS INTERFACE (REDUCED RANGE LINK)

Digital Inputs

2

Input Voltage Range 875 1575 mV
Input Differential Threshold –0.1 +0.1 V
External Termination Resistance 80 100 132 Ω
Differential Input Voltage 100 mV

POWER REQUIREMENTS

DVCC 2.5 5.5 V
VDD 9 16.5 V
VSS −16.5 −4.5 V
Power Supply Sensitivity

2

∆Full Scale/∆VDD −75 dB
∆Full Scale/∆VSS −75 dB
∆Full Scale/∆DVCC −90 dB

DICC 2 mA

= 5.5 V, VIH = DVCC, VIL = GND; normal

DV

CC

operating conditions
IDD 18 mA Outputs unloaded, DAC outputs = 0 V
20 mA Outputs unloaded, DAC outputs = full scale
ISS −18 mA Outputs unloaded, DAC outputs = 0 V

−20 mA Outputs unloaded, DAC outputs = full scale
Power Dissipation Unloaded (P) 280 mW VSS = −8 V, VDD = 9.5 V, DVCC = 2.5 V
Power-Down Mode Control register power-down bit set

DICC 5 μA
IDD 35 μA
ISS −35 μA

Junction Temperature

1

Typical specifications are at 25°C.

2

Guaranteed by design and characterization; not production tested.

3

θJA represents the package thermal impedance.

3

130 °C TJ = TA + P

TOTAL

× θJA

AC CHARACTERISTICS

DVCC = 2.5 V; VDD = 15 V; VSS = −15 V; VREF = 3 V; AGND = DGND = SIGGNDx = 0 V; CL = 200 pF; RL = 10 kΩ; gain (M), offset (C),
and DAC offset registers at default values; all specifications T

Table 3. AC Characteristics

1

Parameter Min Typ Max Unit Test Conditions/Comments

DYNAMIC PERFORMANCE

Output Voltage Settling Time 20 μs Settling to 1 LSB from a full-scale change
30 μs DAC latch contents alternately loaded with all 0s and all 1s
Slew Rate 1 V/μs
Digital-to-Analog Glitch Energy 5 nV-s
Glitch Impulse Peak Amplitude 10 mV
Channel-to-Channel Isolation 100 dB VREF0, VREF1, VREF2 = 2 V p-p, 1 kHz
DAC-to-DAC Crosstalk 20 nV-s
Digital Crosstalk 0.2 nV-s
Digital Feedthrough 0.02 nV-s Effect of input bus activity on DAC output under test
Output Noise Spectral Density @ 10 kHz 250 nV/√Hz V

1

Guaranteed by design and characterization; not production tested.

MIN

to T

, unless otherwise noted.

MAX

= 0 V

REF

Rev. B | Page 5 of 28

AD5371

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TIMING CHARACTERISTICS

DVCC = 2.5 V to 5.5 V; VDD = 9 V to 16.5 V; VSS = −16.5 V to −8 V; VREFx = 3 V; AGND = DGND = SIGGNDx = 0 V; CL = 200 pF to GND;
R

= open circuit; gain (M), offset (C), and DAC offset registers at default values; all specifications T

L

MIN

to T

, unless otherwise noted.

MAX

Table 4. SPI Interface

Parameter

t1

1 , 2 , 3

Limit at T

MIN

, T

Unit Description

MAX

20 ns min SCLK cycle time
t2 8 ns min SCLK high time
t3 8 ns min SCLK low time
t4 11 ns min
t

5

20 ns min
t6 10 ns min
t

7

5 ns min Data setup time

falling edge to SCLK falling edge setup time

SYNC
Minimum SYNC

th

SCLK falling edge to SYNC rising edge

24

high time

t8 5 ns min Data hold time

4

t

9

t

1/1.5 μs typ/μs max

10

42 ns max

rising edge to BUSY falling edge

SYNC

pulse width low (single-channel update); see Table 9

BUSY
t11 600 ns max Single-channel update cycle time
t12 20 ns min
t13 10 ns min
t14 3 μs max
t15 0 ns min
t16 3 μs max

rising edge to LDAC falling edge

SYNC

pulse width low

LDAC

rising edge to DAC output response time

BUSY

rising edge to LDAC falling edge

BUSY

falling edge to DAC output response time

LDAC
t17 20/30 μs typ/μs max DAC output settling time
t18 140 ns max
t19 30 ns min
t20 400 μs max
t21 270 ns min

5

t

22

25 ns max SCLK rising edge to SDO valid

t23 80 ns max

1

Guaranteed by design and characterization; not production tested.

2

All input signals are specified with tR = tF = 2 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V.

3

See Figure 4 and Figure 5.

4

t9 is measured with the load circuit shown in Figure 2.

5

t22 is measured with the load circuit shown in Figure 3.

/RESET pulse activation time

CLR

pulse width low

RESET

time indicated by BUSY low

RESET

Minimum SYNC

rising edge to BUSY falling edge

RESET

high time in readback mode

Table 5. LVDS Interface

Parameter

1, 2, 3

Limit at T

MIN

, T

Unit Description

MAX

t1 12 ns min SCLK cycle time
t2 5 ns min SCLK pulse width high and low time
t3 5 ns min

to SCLK setup time

SYNC
t4 3 ns min Data setup time
t5 3 ns min Data hold time
t6 3 ns min
t7 10 ns min

1

Guaranteed by design and characterization; not production tested.

2

All input signals are specified with tR = tF = 2 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V.

3

See Figure 6.

SCLK to SYNC

high time

SYNC

Rev. B | Page 6 of 28

hold time

AD5371

T

V

V

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Circuit and Timing Diagrams

DV

TO

OUTPUT

PIN

Figure 2. Load Circuit for

CC

R

L

2.2k

Ω

C

L

50pF

BUSY

Timing Diagram

200µA I

O OUTPUT

PIN

C

L

V

OL

05814-002

50pF

200µA I

Figure 3. Load Circuit for SDO Timing Diagram

OL

OH

VOH (MIN) – VOL (MAX)

2

5814-003

t

1

SCLK

SYNC

BUSY

LDAC

OUTx

LDAC

OUTx

SDI

1

1

2

2

1

2

t

3

t

4

t

5

t

7

t

8

DB23

24

t

2

t

6

DB0

t

9

t

1

t

11

t

10

12

t

13

24

t

17

t

14

t

15

t

13

t

17

t

16

CLR

t

18

VOUTx

t

19

RESET

VOUTx

BUSY

1

LDAC ACTIVE DURING BUSY.

2

LDAC ACTIVE AFTER BUSY.

t

23

t

18

t

20

Figure 4. SPI Write Timing

Rev. B | Page 7 of 28

05814-004

AD5371

S

S

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SCLK

SYNC

SDI

INPUT WORD SPECIFIES

REGISTER T O BE READ

SDO

t

22

DB0 DB23DB23

LSB FROM PREVIOUS WRITE

t

21

NOP CONDITI ON

DB0

DB23 DB15

SELECTED REG ISTER DATA CLOCKED OUT

48

DB0

DB0

05814-005

Figure 5. SPI Read Timing

YNC

YNC

SCLK

t

3

t

1

t

6

SCLK

SDI

SDI

MSB

D23

t

2

t

4

t

5

LSB

D0

5814-006

Figure 6. LVDS Timing

Rev. B | Page 8 of 28

AD5371

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ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted. Transient currents of up to
60 mA do not cause SCR latch-up.

Table 6.

Parameter Rating

VDD to AGND −0.3 V to +17 V
VSS to AGND −17 V to +0.3 V
DVCC to DGND −0.3 V to +7 V
Digital Inputs to DGND −0.3 V to DVCC + 0.3 V
Digital Outputs to DGND −0.3 V to DVCC + 0.3 V
VREF0, VREF1, VREF2 to AGND −0.3 V to +5.5 V
VOUT0 through VOUT39 to AGND VSS − 0.3 V to VDD + 0.3 V
SIGGND0 through SIGGND4 to AGND −1 V to +1 V
AGND to DGND −0.3 V to +0.3 V
Operating Temperature Range (TA)

Industrial (B Version) −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Operating Junction Temperature

max)

(T

J

θJA Thermal Impedance

80-Lead LQFP 38.72°C/W

100-Ball CSP_BGA 40°C/W
Reflow Soldering

Peak Temperature 230°C

Time at Peak Temperature 10 sec to 40 sec

130°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

Rev. B | Page 9 of 28