ANALOG DEVICES AD5362, AD5363 Service Manual

8-Channel, 16-/14-Bit,

VDDV

FEATURES

8-channel DAC in 52-lead LQFP and 56-lead LFCSP packages Guaranteed monotonic to 16/14 bits Nominal output voltage range of −10 V to +10 V Multiple output voltage spans available Thermal shutdown function Channel monitoring multiplexer GPIO function System calibration function allowing user-programmable

offset and gain Channel grouping and addressing features Data error checking feature SPI-compatible serial interface

FUNCTIONAL BLOCK DIAGRAM

8

TO MUX 2s

n

X2A REGISTER

n

8

n

A/B MUX

X2B REGISTER

·

n

TO MUX 2s

n

·

n

·

A/B MUX

·

A/B MUX

X2A REG ISTER

X2B REG ISTER

X2A REGISTER

X2B REGISTER

X2A REGISTER

X2B REGISTER

·

TEMP_OUT

PEC

MON_IN0

MON_IN1

MON_OUT

GPIO

BIN/2S COMP

SYNC

SDI

SCLK

SDO

BUSY

RESET

CLR

DV

TEMP

SENSOR

CONTROL REGISTER

VOUT0 TO VOUT7

MUX

GPIO

REGISTER

SERIAL

INTERFACE

STATE

MACHINE

AD5362/

AD5363

CC

8

6

2

n

AGND DGND LDAC

SS

n = 16 FOR AD5362 n = 14 FOR AD5363

8

A/B SELECT

REGI STER

n

X1 REGI STER

n

M REGI STER

n

C REG ISTER

·

n

X1 REGI STER

n

M REGISTER

n

C REG ISTER

8

A/B SELECT

REGI STER

n

X1 REGI STER

n

M REGI STER

n

C REG ISTER

·

n

X1 REGI STER

n

M REGI STER

n

C REG ISTER

Serial Input, Voltage Output DAC

AD5362/AD5363

2.5 V to 5.5 V digital interface

·

Figure 1.

Digital reset ( Clear function to user-defined SIGGNDx Simultaneous update of DAC outputs

APPLICATIONS

Instrumentation Industrial control systems Level setting in automatic test equipment (ATE) Variable optical attenuators (VOA) Optical line cards

14

OFS0

REGI STER

nn

MUX

2

DAC 0

REGI STER

·

n

DAC 3

REGISTER

14

OFS1

REGISTER

nn

DAC 4

REGI STER

·

n

DAC 7

REGI STER

RESET

14

n

OFFSET

DAC 0

DAC 3

OFFSET

DAC 1

DAC 4

DAC 7

)

BUFFER

·

BUFFER

·

GROUP 0

OUTPUT B UFFER

AND POWER-

DOWN CONTROL

·

OUTPUT B UFFER

AND POWER-

DOWN CONTROL

GROUP 1

OUTPUT B UFFER

AND POWER-

DOWN CONTROL

·

OUTPUT B UFFER

AND POWER-

DOWN CONTROL

VREF0

VOUT0

VOUT1

VOUT2

VOUT3

SIGGND0

VREF1

VOUT4

VOUT5

VOUT6

VOUT7

SIGGND1

05762-001

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

AD5362/AD5363

REVISION HISTORY

3/08—Rev. 0 to Rev. A

Added 56-Lead LFCSP_VQ .............................................. Universal

Changes to Table 2 ............................................................................ 4

Added t

Changes to Figure 4 .......................................................................... 8

Changes to Table 6 .......................................................................... 11

Changes to A/B Registers and Gain/Offset Adjustment

Section .............................................................................................. 17

Parameter ......................................................................... 7

23

Rev. A | Page 2 of 28

Changes to Calibration Section .................................................... 19

Changes to Reset Function Section and

Functions Section ........................................................................... 20

Changes to Channel Addressing and Special Modes Section .. 23

Updated Outline Dimensions ....................................................... 27

Changes to Ordering Guide .......................................................... 28

1/08—Revision 0: Initial Version

BUSY

and

LDAC

AD5362/AD5363

GENERAL DESCRIPTION

The AD5362/AD5363 contain eight 16-/14-bit DACs in a single 52-lead LQFP package or 56-lead LFCSP package. The devices provide buffered voltage outputs with a span of 4× the reference voltage. The gain and offset of each DAC can be independently trimmed to remove errors. For even greater flexibility, the device is divided into two groups of four DACs, and the output range of each group can be independently adjusted by an offset DAC.

The AD5362/AD5363 offer guaranteed operation over a wide supply range with V

from −16.5 V to −4.5 V and VDD from 8 V

SS

to 16.5 V. The output amplifier headroom requirement is 1.4 V, operating with a load current of 1 mA.

Table 1. High Channel Count Bipolar DACs

Model Resolution (Bits) Nominal Output Span Output Channels Linearity Error (LSB)

AD5360 16 4 × V AD5361 14 4 × V

AD5362 16 4 × V AD5363 14 4 × V

AD5370 16 4 × V AD5371 14 4 × V AD5372 16 4 × V AD5373 14 4 × V

(20 V) 16 ±4

REF

(20 V) 16 ±1

REF

(20 V) 8 ±4

REF

(20 V) 8 ±1

REF

(12 V) 40 ±4

REF

(12 V) 40 ±1

REF

(12 V) 32 ±4

REF

(12 V) 32 ±1

REF

AD5378 14 ±8.75 V 32 ±3 AD5379 14 ±8.75 V 40 ±3

The AD5362/AD5363 have a high speed 4-wire serial interface that is compatible with SPI, QSPI™, MICROWIRE™, and DSP interface standards and can handle clock speeds of up to 50 MHz. All the outputs can be updated simultaneously by taking the

LDAC

input low. Each channel has a programmable

gain and an offset adjust register. Each DAC output is gained and buffered on chip with respect

to an external SIGGNDx input. The DAC outputs can also be switched to SIGGNDx via the

CLR

pin.

Rev. A | Page 3 of 28

AD5362/AD5363

SPECIFICATIONS

DVCC = 2.5 V to 5.5 V; VDD = 9 V to 16.5 V; VSS = −16.5 V to −4.5 V; V R

= open circuit; gain (M), offset (C), and DAC offset registers at default values; all specifications T

L

Table 2.

Parameter B Version1Unit Test Conditions/Comments

ACCURACY

Resolution 16 Bits AD5362

14 Bits AD5363

Integral Nonlinearity (INL) ±4 LSB max AD5362

±1 LSB max AD5363

Differential Nonlinearity (DNL) ±1 LSB max Guaranteed monotonic by design over temperature

Zero-Scale Error ±15 mV max Before calibration

Full-Scale Error ±20 mV max Before calibration

Gain Error 0.1 % FSR Before calibration

Zero-Scale Error

Full-Scale Error

2

1 LSB typ After calibration

Span Error of Offset DAC ±75 mV max See the Offset DACs section for details

VOUTx3 Temperature Coefficient 5 ppm FSR/°C typ Includes linearity, offset, and gain drift

DC Crosstalk

REFERENCE INPUTS (VREF0, VREF1)

2

180 μV max

2

VREFx Input Current ±10 μA max Per input; typically ±30 nA

VREFx Range SIGGND0 AND SIGGND1 INPUTS

2

2/5 V min/V max ±2% for specified operation

2

DC Input Impedance 50 kΩ min Typically 55 kΩ

Input Range ±0.5 V min/V max

SIGGNDx Gain 0.995/1.005 min/max OUTPUT CHARACTERISTICS

2

Output Voltage Range VSS + 1.4 V min I

V

− 1.4 V max I

DD

Nominal Output Voltage Range −10 to +10 V

Short-Circuit Current 15 mA max VOUTx3 to DVCC, VDD, or VSS

Load Current ±1 mA max

Capacitive Load 2200 pF max

DC Output Impedance 0.5 Ω max MONITOR PIN (MON_OUT)

2

Output Impedance

DAC Output at Positive Full Scale 1000 Ω typ

DAC Output at Negative Full Scale 500 Ω typ Three-State Leakage Current 100 nA typ Continuous Current Limit 2 mA max

DIGITAL INPUTS

Input High Voltage 1.7 V min DVCC = 2.5 V to 3.6 V

2.0 V min DV Input Low Voltage 0.8 V max DVCC = 2.5 V to 5.5 V Input Current ±1 μA max

±20 μA max Input Capacitance

2

10 pF max

= 5 V; AGND = DGND = SIGGND0 = SIGGND1 = 0 V;

REF

MIN

to T

, unless otherwise noted.

MAX

Typically 20 μV; measured channel at midscale, full-scale change on any other channel

= 1 mA

LOAD

= 1 mA

LOAD

= 3.6 V to 5.5 V

CC

, SYNC, SDI, and SCLK pins

RESET

, BIN/2SCOMP, and GPIO pins

CLR

Rev. A | Page 4 of 28

AD5362/AD5363

Parameter B Version1Unit Test Conditions/Comments

DIGITAL OUTPUTS (SDO, BUSY, GPIO, PEC)

Output Low Voltage 0.5 V max Sinking 200 μA Output High Voltage (SDO) DVCC − 0.5 V min Sourcing 200 μA High Impedance Leakage Current ±5 μA max SDO only High Impedance Output Capacitance

TEMPERATURE SENSOR (TEMP_OUT)

2

Accuracy ±1 °C typ @ 25°C ±5 °C typ −40°C < T < +85°C Output Voltage at 25°C 1.46 V typ Output Voltage Scale Factor 4.4 mV/°C typ Output Load Current 200 μA max Current source only Power-On Time 10 ms typ To within ±5°C

POWER REQUIREMENTS

DVCC 2.5/5.5 V min/V max VDD 8/16.5 V min/V max VSS −16.5/−4.5 V min/V max Power Supply Sensitivity

2

∆Full Scale/∆VDD −75 dB typ ∆Full Scale/∆VSS −75 dB typ

∆Full Scale/∆DVCC −90 dB typ DICC 2 mA max DVCC = 5.5 V, VIH = DVCC, VIL = GND IDD 8.5 mA max Outputs = 0 V and unloaded ISS 8.5 mA max Outputs = 0 V and unloaded Power-Down Mode Bit 0 in the control register is 1

DICC 5 μA typ

IDD 35 μA typ

ISS −35 μA typ Power Dissipation

Power Dissipation Unloaded (P) 209 mW max VSS = −12 V, VDD = 12 V, DVCC = 2.5 V

Junction Temperature

1

Temperature range for B version: −40°C to +85°C. Typical specifications are at 25°C.

2

Guaranteed by design and characterization; not production tested.

3

VOUTx refers to any of VOUT0 to VOUT7.

4

θJA represents the package thermal impedance.

4

2

10 pF typ

130 °C max TJ = TA + P

TOTAL

× θJA

Rev. A | Page 5 of 28

AD5362/AD5363

AC CHARACTERISTICS

DVCC = 2.5 V; VDD = 15 V; VSS = −15 V; V offset (C), and DAC offset registers at default values; all specifications T

Table 3.

Parameter B Version1Unit Test Conditions/Comments

DYNAMIC PERFORMANCE1

Output Voltage Settling Time 20 μs typ Full-scale change 30 μs max DAC latch contents alternately loaded with all 0s and all 1s Slew Rate 1 V/μs typ Digital-to-Analog Glitch Energy 5 nV-s typ Glitch Impulse Peak Amplitude 10 mV max Channel-to-Channel Isolation 100 dB typ VREF0, VREF1 = 2 V p-p, 1 kHz DAC-to-DAC Crosstalk 10 nV-s typ Digital Crosstalk 0.2 nV-s typ Digital Feedthrough 0.02 nV-s typ Effect of input bus activity on DAC output under test Output Noise Spectral Density @ 10 kHz 250 nV/√Hz typ VREF0 = VREF1 = 0 V

1

Guaranteed by design and characterization; not production tested.

= 5 V; AGND = DGND = SIGGND0 = SIGGND1 = 0 V; CL = 200 pF; RL = 10 kΩ; gain (M),

REF

MIN

to T

, unless otherwise noted.

MAX

Rev. A | Page 6 of 28

AD5362/AD5363

TIMING CHARACTERISTICS

DVCC = 2.5 V to 5.5 V; VDD = 9 V to 16.5 V; VSS = −16.5 V to −8 V; V R

= open circuit; gain (M), offset (C), and DAC offset registers at default values; all specifications T

L

= 5 V; AGND = DGND = SIGGND = 0 V; CL = 200 pF to GND;

REF

MIN

to T

, unless otherwise noted.

MAX

Table 4. SPI Interface

1, 2, 3

Parameter

t

1

Limit at T

MIN

, T

Unit Description

MAX

20 ns min SCLK cycle time t2 8 ns min SCLK high time t3 8 ns min SCLK low time t4 11 ns min t

5

20 ns min t6 10 ns min t

7

5 ns min Data setup time

falling edge to SCLK falling edge setup time

SYNC Minimum SYNC

th

SCLK falling edge to SYNC rising edge

24

high time

t8 5 ns min Data hold time

4

t

9

t

1/1.5 μs typ/μs max

10

42 ns max

rising edge to BUSY falling edge

SYNC

pulse width low (single-channel update); see Table 9

BUSY t11 600 ns max Single-channel update cycle time t12 20 ns min t13 10 ns min t14 3 μs max t15 0 ns min t16 3 μs max

rising edge to LDAC falling edge

SYNC

pulse width low

LDAC

rising edge to DAC output response time

BUSY

rising edge to LDAC falling edge

BUSY

falling edge to DAC output response time

LDAC t17 20/30 μs typ/μs max DAC output settling time t18 140 ns max t19 30 ns min t20 400 μs max t21 270 ns min

5

t

22

25 ns max SCLK rising edge to SDO valid

t23 80 ns max

1

Guaranteed by design and characterization; not production tested.

2

All input signals are specified with tR = tF = 2 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V.

3

See Figure 4 and Figure 5.

4

t9 is measured with the load circuit shown in Figure 2.

5

t22 is measured with the load circuit shown in Figure 3.

/RESET pulse activation time

CLR

pulse width low

RESET

time indicated by BUSY low

RESET

Minimum SYNC

rising edge to BUSY falling edge

RESET

high time in readback mode

TO

OUTPUT

Figure 2. Load Circuit for

DV

CC

R

2.2k

C

L

50pF

BUSY

L

Ω

V

OL

05762-002

Timing Diagram

Rev. A | Page 7 of 28

TO OUTPUT

50pF

C

200µA I

L

200µA I

OL

OH

Figure 3. Load Circuit for SDO Timing Diagram

VOH (MIN) – VOL (MAX)

2

05762-003

AD5362/AD5363

t

1

SCLK

SYNC

BUSY

LDAC

VOUTx

LDAC

VOUTx

SDI

1

2

1

2

t

3

t

4

t

5

t

7

t

8

DB23

24

t

2

t

6

DB0

t

9

t

1

t

11

t

10

12

t

13

24

t

17

t

14

t

15

t

13

t

17

t

16

CLR

VOUTx

RESET

VOUTx

BUSY

1

LDAC ACTIVE DURING BUSY.

2

LDAC ACTIVE AFTER BUSY.

t

18

t

19

t

18

t

20

t

23

05762-004

Figure 4. SPI Write Timing

Rev. A | Page 8 of 28

AD5362/AD5363

SCLK

SYNC

SDI

INPUT WORD SPECIFIES

REGISTER TO BE READ

SDO

t

22

DB0 DB23DB23

LSB FRO M PREVIOUS W RITE

t

21

NOP CONDITI ON

DB0

DB23 DB15

SELECTED REG ISTER DATA CLOCKED OUT

48

DB0

05762-005

Figure 5. SPI Read Timing

OUTPUT

VOLTAGE

V

MAX

ACTUAL TRANSFER FUNCTION

IDEAL TRANSFER FUNCTION

FULL-SCAL E ERROR + ZERO-SCALE ERROR

0

V

MIN

DAC CODE

ZERO-SCALE ERROR

N

2

– 1

n = 16 FOR AD5362 n = 14 FOR AD5363

05762-006

Figure 6. DAC Transfer Function

Rev. A | Page 9 of 28

ANALOG DEVICES AD5362, AD5363 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

FUNCTIONAL BLOCK DIAGRAM

APPLICATIONS

TABLE OF CONTENTS

REVISION HISTORY

GENERAL DESCRIPTION

SPECIFICATIONS

AC CHARACTERISTICS

TIMING CHARACTERISTICS