ANALOG DEVICES AD5346, AD5347, AD5348 Service Manual

查询AD5346BCP供应商

2.5 V to 5.5 V, Parallel Interface

Octal Voltage Output 8-/10-/12-Bit DACs

FEATURES

AD5346: octal 8-bit DAC
AD5347: octal 10-bit DAC
AD5348: octal 12-bit DAC
Low power operation: 1.4 mA (max) @ 3.6 V
Power-down to 120 nA @ 3 V, 400 nA @ 5 V
Guaranteed monotonic by design over all codes

BUF

GAIN
DB11

DB0

WR

CLR

LDAC

REF

.

.
.

CS
RD

A2

A1

A0

or 0 V to 2 × V

LDAC

pin

FUNCTIONAL BLOCK DIAGRAM

V

DD

INTER­FACE
LOGIC

REF

AGND

AD5348

INPUT

REGISTER

INPUT

REGISTER

INPUT

REGISTER

INPUT

REGISTER

INPUT

REGISTER

INPUT

REGISTER

INPUT

REGISTER

INPUT

REGISTER

DGND

REGISTER

REGISTER

REGISTER

REGISTER

REGISTER

REGISTER

REGISTER

REGISTER

Rail-to-rail output range: 0 V to V
Power-on reset to 0 V
Simultaneous update of DAC outputs via

CLR

Asynchronous

facility
Readback
Buffered/unbuffered reference inputs

WR

20 ns

time
38-lead TSSOP/6 mm × 6 mm 40-lead LFCSP packaging
Temperature range: –40°C to +105°C

APPLICATIONS

Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Optical networking
Automatic test equipment
Mobile communications
Programmable attenuators
Industrial process control

1

Protected by U.S. Patent No. 5,969,657; other patents pending.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

DAC

DAC

DAC

DAC

DAC

DAC

DAC

DAC

Figure 1.

AD5346/AD5347/AD5348

GENERAL DESCRIPTION

The AD5346/AD5347/AD53481 are octal 8-, 10-, and 12-bit
DACs, operating from a 2.5 V to 5.5 V supply. These devices
incorporate an on-chip output buffer that can drive the output
to both supply rails, and also allow a choice of buffered or
unbuffered reference input.

The AD5346/AD5347/AD5348 have a parallel interface.
selects the device and data is loaded into the input registers on
the rising edge of
DAC registers to be read back through the digital port.

The GAIN pin on these devices allows the output range to be
set at 0 V to V

Input data to the DACs is double-buffered, allowing simultane­ous update of multiple DACs in a system using the

An asynchronous
contents of the input register and the DAC register to all zeros.
These devices also incorporate a power-on reset circuit that
ensures that the DAC output powers on to 0 V and remains
there until valid data is written to the device.

All three parts are pin compatible, which allows users to select
the amount of resolution appropriate for their application
without redesigning their circuit board.

AB

V

REF

STRING

DAC A

STRING

DAC B

STRING

DAC C

STRING

DAC D

STRING

DAC E

STRING

DAC F

STRING
DAC G

STRING

DAC H

V

REF

V

CD

REF

GH

V

EF

REF

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]
Fax: [phone] © 2003 Analog Devices, Inc. All rights reserved.

WR

. A readback feature allows the internal

or 0 V to 2 × V

REF

POWER-ON

RESET

BUFFER

BUFFER

BUFFER

BUFFER

BUFFER

BUFFER

BUFFER

BUFFER

POWER-DOWN

CLR

input is also provided, which resets the

LOGIC

PD

.

REF

V

A

OUT

B

V

OUT

V

C

OUT

V

D

OUT

E

V

OUT

V

F

OUT

G

V

OUT

H

V

OUT

03331-0-001

www.analog.com

LDAC

CS

pin.

AD5346/AD5347/AD5348

TABLE OF CONTENTS

Specifications..................................................................................... 3

Power-On Reset .......................................................................... 17

AC Characteristics ............................................................................ 4

Timing Characteristics..................................................................... 5

Absolute Maximum Ratings............................................................ 6

ESD Caution.................................................................................. 6

AD5346 Pin Configurations and Function Descriptions ........... 7

AD5347 Pin Configurations and Function Descriptions ........... 8

AD5348 Pin Configurations and Function Descriptions ........... 9

Te r m in o l o g y .................................................................................... 10

Typical Performance Characteristics........................................... 12

Functional Description ..................................................................16

Digital-to-Analog Section......................................................... 16

Resistor String............................................................................. 16

DAC Reference Input .................................................................16

Output Amplifier........................................................................ 16

Parallel Interface ......................................................................... 17

Power-Down Mode .................................................................... 17

Suggested Data Bus Formats..................................................... 18

Applications Information.............................................................. 19

Typical Application Circuits ..................................................... 19

Driving V

from the Reference Voltage................................. 19

DD

Bipolar Operation Using the AD5346/AD5347/AD5348..... 19

Decoding Multiple AD5346/AD5347/AD5348s.................... 20

AD5346/AD5347/AD5348 as Digitally Programmable
Window Detectors

...................................................................... 20

Programmable Current Source ................................................ 20

Coarse and Fine Adjustment Using the
AD5346/AD5347/AD5348

....................................................... 21

Power Supply Bypassing and Grounding................................ 21

Outline Dimensions....................................................................... 23

Ordering Guides......................................................................... 24

REVISION HISTORY

Revision 0: Initial Version

Rev. 0 | Page 2 of 24

AD5346/AD5347/AD5348

SPECIFICATIONS

Table 1. VDD = 2.5 V to 5.5 V; V
unless otherwise noted

B Version
Parameter

DC PERFORMANCE

2

3,4

AD5346

Resolution 8 Bits
Relative Accuracy ±0.15 ±1 LSB
Differential Nonlinearity ±0.02 ±0.25 LSB Guaranteed monotonic by design over all codes

AD5347

Resolution 10 Bits
Relative Accuracy ±0.5 ±4 LSB
Differential Nonlinearity ±0.05 ±0.5 LSB Guaranteed monotonic by design over all codes

AD5348

Resolution 12 Bits
Relative Accuracy ±2 ±16 LSB

Differential Nonlinearity ±0.2 ±1 LSB Guaranteed monotonic by design over all codes
Offset Error ±0.4 ±3 % of FSR
Gain Error ±0.1 ±1 % of FSR
Lower Deadband5 10 60 mV Lower deadband exists only if offset error is negative
Upper Deadband
Offset Error Drift
Gain Error Drift
DC Power Supply Rejection

6

Ratio
DC Crosstalk

DAC REFERENCE INPUT

V

Input Range 1 VDD V Buffered reference mode

REF

V

Input Range 0.25 VDD V Unbuffered reference mode

REF

V

Input Impedance >10 MΩ Buffered reference mode and power-down mode

REF

5

6

6

6

6

90 kΩ Gain = +1; input impedance = R
45 kΩ Gain = +2; input impedance = R
Reference Feedthrough –90 dB Frequency = 10 kHz
Channel-to-Channel Isolation –75 dB Frequency = 10 kHz

OUTPUT CHARACTERISTICS

6

Minimum Output Voltage
Maximum Output Voltage

DC Output Impedance 0.5 Ω
Short Circuit Current 25 mA VDD = 5 V
16 mA VDD = 3 V
Power-Up Time 2.5 µs Coming out of power-down mode; VDD = 5 V

5 µs Coming out of power-down mode; VDD = 3 V
LOGIC INPUTS6

Input Current ±1 µA
VIL, Input Low Voltage 0.8 V VDD = 5 V ±10%

0.7 V VDD = 3 V ±10%

0.6 V VDD = 2.5 V
VIH, Input High Voltage 1.7 V VDD = 2.5 V to 5.5 V
Pin Capacitance 5 pF

= 2 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications T

REF

1

MIN

Min Typ Max Unit Conditions/Comments

10 60 mV VDD = 5 V; upper deadband exists only if V
–12 ppm of FSR/°C
–5 ppm of FSR/°C
–60 dB ∆VDD = ±10%

200 µV

= 2 kΩ to GND, 2 kΩ to VDD; CL = 200 pF to GND;

R

L

Gain = +1

4, 7

0.001 V min Rail-to-rail operation

4, 7

V

V max

–

DD

0.001

to T

DAC

DAC

MAX

,

= V

REF

DD

Rev. 0 | Page 3 of 24

AD5346/AD5347/AD5348

B Version
Parameter

LOGIC OUTPUTS

2

6

Min Typ Max Unit Conditions/Comments

1

VDD = 4.5 V to 5.5 V

Output Low Voltage, VOL 0.4 V I
Output High Voltage, VOH VDD – 1 V I

= 200 µA

SINK

SOURCE

= 200 µA

VDD = 2.5 V to 3.6 V

Output Low Voltage, VOL 0.4 V I
Output High Voltage, VOH VDD – 0.5 V I

= 200 µA

SINK

SOURCE

= 200 µA

POWER REQUIREMENTS

VDD 2.5 5.5 V
IDD (Normal Mode) VIH = VDD, VIL = GND

VDD = 4.5 V to 5.5 V 1 1.65 mA All DACs in unbuffered mode. In buffered mode,
VDD = 2.5 V to 3.6 V 0.8 1.4 mA

extra current is typically x µA per DAC, where x = 5 µA +
V

REF/RDAC

IDD (Power-Down Mode) VIH = VDD, VIL = GND

VDD = 4.5 V to 5.5 V 0.4 1 µA
VDD = 2.5 V to 3.6 V 0.12 1 µA

See footnotes after the AC Characteristics table.

AC CHARACTERISTICS

Table 2. VDD = 2.5 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications T

B Version

6

to T

1

MIN

, unless otherwise noted

MAX

Parameter2 Min Typ Max Unit Conditions/Comments

Output Voltage Settling Time V

REF

= 2 V
AD5346 6 8 µs 1/4 scale to 3/4 scale change (40 H to C0 H)
AD5347 7 9 µs 1/4 scale to 3/4 scale change (100 H to 300 H)
AD5348 8 10 µs 1/4 scale to 3/4 scale change (400 H to C00 H)

Slew Rate 0.7 V/µs
Major Code Transition Glitch

Energy

8 nV-s 1 LSB change around major carry

Digital Feedthrough 0.5 nV-s
Digital Crosstalk 1 nV-s
Analog Crosstalk 1 nV-s
DAC-to-DAC Crosstalk 3.5 nV-s
Multiplying Bandwidth 200 kHz V
Total Harmonic Distortion –70 dB V

= 2 V ±0.1 V p-p; unbuffered mode

REF

= 2. V ±0.1 V p-p; frequency = 10 kHz; unbuffered mode

REF

1

Temperature range: B Version: –40°C to +105°C; typical specifications are at 25°C.

2

See Terminology section.

3

Linearity is tested using a reduced code range: AD5346 (Code 8 to 255); AD5347 (Code 28 to 1023); AD5348 (Code 115 to 4095).

4

DC specifications tested with outputs unloaded.

5

This corresponds to x codes. x = deadband voltage/LSB size.

6

Guaranteed by design and characterization, not production tested.

7

For the amplifier output to reach its minimum voltage, offset error must be negative. For the amplifier output to reach its maximum voltage, V

the offset plus gain error must be positive.

200µA

I

OL

= VDD and

REF

TO OUTPUT

PIN

50pF

C

L

200µA

I

OH

VOH(min) + VOL(max)

Figure 2. Load Circuit for Digital Output Timing Specifications

Rev. 0 | Page 4 of 24

2

03331-0-002

AD5346/AD5347/AD5348

TIMING CHARACTERISTICS

Table 3. VDD = 2.5 V to 5.5 V; all specifications T

Parameter Limit at T

Data Write Mode (Figure 3)
t1 0 ns min
t2 0 ns min
t3 20 ns min
t4 5 ns min Data, GAIN, BUF setup time
t5 4.5 ns min Data, GAIN, BUF hold time
t6 5 ns min
t7 5 ns min

t8 4.5 ns min Synchronous mode. WR rising to LDAC rising.
t9 5 ns min
t10 4.5 ns min
t11 20 ns min
t12 10 ns min
t13 20 ns min
t14 20 ns min A0, A1, A2 setup time

t15 0 ns min A0, A1, A2 hold time
Data Readback Mode (Figure 4)
t16 0 ns min
t17 0 ns min

t18 0 ns min CS to falling edge of RD
t19 20 ns min
30 ns min
t20 0 ns min
t21 22 ns max
30 ns max
t22 4 ns min
30 ns max

t23 22 ns max
30 ns max
t

24

t

25

t

26

50 ns min

1

Guaranteed by design and characterization, not production tested.

2

All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.

3

See Figure 2.

CS

WR

DATA,

GAIN, BUF

1

LDAC

2

LDAC

CLR

A0–A2

Figure 3. Parallel Interface Write Timing Diagram Figure 4. Parallel Interface Read Timing Diagram

t

1

t

3

t

4

t

6

t

7

t

9

t

14

NOTES

1. SYNCHRONOUS LDAC UPDATE MODE

2. ASYNCHRONOUS LDAC UPDATE MODE

1, 2, 3

to T

MIN

, T

MIN

MAX

30 ns min
30 ns min
30 ns min

t

2

t

13

t

5

t

8

t

10

t

11

t

t

15

12

, unless otherwise noted

MAX

Unit Condition/Comments

CS to WR setup time
CS to WR hold time
WR pulse width

Synchronous mode.
Synchronous mode.

Asynchronous mode.
Asynchronous mode.
LDAC pulse width
CLR

pulse width

Time between

A0, A1, A2 to
A0, A1, A2 to

RD pulse width; VDD = 3.6 V to 5.5 V
RD pulse width; VDD = 2.5 V to 3.6 V
CS to RD hold time
Data access time after falling edge of
Data access time after falling edge of
Bus relinquish time after rising edge of

CS falling edge to data; VDD = 3.6 V to 5.5 V
CS falling edge to data; VDD = 2.5 V to 3.6 V

Time between
Time from

Time from
Time from

A0–A2

CS

RD

DATA

WR

03331-0-003

WR falling to LDAC falling.
LDAC falling to WR rising.

LDAC rising to WR rising.
WR rising to LDAC falling.

WR cycles

CS

setup time

CS

hold time

RD; VDD = 3.6 V to 5.5 V
RD VDD = 2.5 V to 3.6 V

RD

cycles

RD to WR
WR to RD, VDD = 3.6 V to 5.5 V
WR to RD, VDD = 2.5 V to 3.6 V

t

16

t

18

t

21

t

23

t

26

t

20

t

19

t

22

RD

t

17

t

24

t

25

03331-0-004

Rev. 0 | Page 5 of 24

AD5346/AD5347/AD5348

ABSOLUTE MAXIMUM RATINGS

Table 4. TA = 25°C, unless otherwise noted

Parameter Rating

VDD to GND –0.3 V to +7 V
Digital Input Voltage to GND –0.3 V to VDD + 0.3 V
Digital Output Voltage to GND –0.3 V to VDD + 0.3 V
Reference Input Voltage to GND –0.3 V to VDD + 0.3 V
V

to GND –0.3 V to VDD + 0.3 V

OUT

Operating Temperature Range

Industrial (B Version) –40°C to +105°C

Storage Temperature Range –65°C to +150°C
Junction Temperature 150°C
38-Lead TSSOP Package

Power Dissipation (TJ max − TA)/ θJA mW
θJA Thermal Impedance 98.3°C/W
θJC Thermal Impedance 8.9°C/W

40-Lead LFCSP Package

Power Dissipation (TJ max − TA)/ θJA mW
θJA Thermal Impedance (3-layer

board)

Lead Temperature, Soldering (10 sec) 300°C
IR Reflow, Peak Temperature 220°C

29.6°C/W

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. 0 | Page 6 of 24

AD5346/AD5347/AD5348

AD5346 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

CD

EF

V

REF

V

V

V

V

REF

REF

V

REF

V

OUT

V

OUT

V

OUT

V

OUT

AGND

V

OUT

V

OUT

OUT

V

OUT

DGND

BUF

LDAC

GH

EF

CD

DD

AB

A
B
C

D

E

F
G
H

A0
A1

1
2
3
4
5
6

8-BIT

AD5346

7

TOP VIEW

8

(Not to Scale)

9
10
11
12
13
14
15
16
17
18
19

38

PD

37

CLR

36

GAIN

35

WR

34

RD

33

CS

32

DB

7

31

DB

6

30

DB

5

29

DB

4

28

DB

3

DB

27

2

DB

26

1

DB

25

0

DGND

24
23

DGND
DGND

22

DGND

21
20

A2

03331-0-005

V

OUT

V

OUT

V

OUT

V

OUT

AGND
AGND

V

OUT

V

OUT

V

OUT

V

OUT

AB

REF

DD

DD

V

V

V

40 39 38 37 36 35 34 33 32 31

A

1
2

B
C

3

D

4
5
6

E

7

F

8
9

G
H

10

11 12 13 14 15 16 17 18 19 20

BUF

LDAC

DGND

Figure 6. AD5346 Pin Configuration—LFCSP

Figure 5. AD5346 Pin Configuration—TSSOP

Table 5. AD5346 Pin Function Descriptions

Pin Number

TSSOP LFCSP Mnemonic Function

1 35 V
2 36 V
3 37 V
4 38, 39 VDD

GH Reference Input for DACs G and H.

REF

EF Reference Input for DACs E and F.

REF

CD Reference Input for DACs C and D.

REF

Power Supply Pin(s). This part can operate from 2.5 V to 5.5 V, and the supply should be decoupled
with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND. Both V

package must be at the same potential.
5 40 V
6–9,

11–14

1–4,
7–10

AB Reference Input for DACs A and B.

REF

X Output of DAC X. Buffered output with rail-to-rail operation.

V

OUT

10 5, 6 AGND Analog Ground. Ground reference for analog circuitry.
15,

21–24

11,
17–20

DGND Digital Ground. Ground reference for digital circuitry.

16 12 BUF Buffer Control Pin. Controls whether the reference input to the DAC is buffered or unbuffered.
17 13

LDAC

Active Low Control Input. Updates the DAC registers with the contents of the input registers, which

allows all DAC outputs to be simultaneously updated.
18 14 A0 LSB Address Pin. Selects which DAC is to be written to.
19 15 A1 Address Pin. Selects which DAC is to be written to.
20 16 A2 MSB Address Pin. Selects which DAC is to be written to.
25–32 21–28 DB0–DB
33 29

34 30
35 31

CS

RD
WR

7

Eight Parallel Data Inputs. DB7 is the MSB of these eight bits.

Active Low Chip Select Input. Used in conjunction with

RD to read back data from a DAC.

with

Active Low Read Input. Used in conjunction with

Active Low Write Input. Used in conjunction with

WR to write data to the parallel interface, or

CS to read data back from the internal DACs.

CS to write data to the parallel interface.
36 32 GAIN Gain Control Pin. Controls whether the output range from the DAC is 0 V to V
37 33
38 34

CLR
PD

Asynchronous Active Low Control Input. Clears all input registers and DAC registers to zeros.
Power-Down Pin. This active low control pin puts all DACs into power-down mode.

GH

REF

REF

REF

V

V

V

8-BIT

AD5346

TOP VIEW

(Not to Scale)

A2

A1

A0

DD

PD

CLR

GAIN

WR

30

RD

29

CS

28

DB

7

27

DB

6

26

DB

5

25

DB

4

24

DB

3

23

DB

2

22

DB

1

21

DB

0

DGND

DGND

DGND

DGND

pins on the LFCSP

or 0 V to 2 × V

REF

03331-0-006

REF.

Rev. 0 | Page 7 of 24

AD5346/AD5347/AD5348

AD5347 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

CD

EF

V

V

V

V

REF

REF

REF

V

REF

V

OUT

V

OUT

V

OUT

V

OUT

AGND

V

OUT

V

OUT

V

OUT

V

OUT

DGND

BUF

LDAC

GH

EF

CD

DD

AB

A
B
C
D

E

F

G

H

A0
A1

1
2
3
4
5
6

10-BIT

AD5347

7

TOP VIEW

8

(Not to Scale)

9
10
11
12
13
14
15
16
17
18
19

38

PD

37

CLR

36

GAIN

35

WR

34

RD

33

CS

32

DB

9

31

DB

8

30

DB

7

29

DB

6

28

DB

5

DB

27

4

DB

26

3

DB

25

2

DB

24

1

23

DB

0

DGND

22

DGND

21
20

A2

03331-0-007

V

OUT

V

OUT

V

OUT

V

OUT

AGND
AGND

V

OUT

V

OUT

V

OUT

V

OUT

AB

REF

DD

DD

V

V

V

40 39 38 37 36 35 34 33 32 31

A

1
2

B
C

3

D

4
5
6

E

7

F

8
9

G

H

10

11 12 13 14 15 16 17 18 19 20

BUF

LDAC

DGND

Figure 8. AD5347 Pin Configuration—LFCSP

Figure 7. AD5347 Pin Configuration—TSSOP

Table 6. AD5347 Pin Function Descriptions

Pin Number

TSSOP LFCSP Mnemonic Function

1 35 V
2 36 V
3 37 V
4 38, 39 V

GH Reference Input for DACs G and H.

REF

EF Reference Input for DACs E and F.

REF

CD Reference Input for DACs C and D.

REF

DD

Power Supply Pin(s). This part can operate from 2.5 V to 5.5 V, and the supply should be decoupled
with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND. Both V

must be at the same potential.
5 40 V
6–9,

11–14

1–4,
7–10

AB Reference Input for DACs A and B.

REF

X Output of DAC X. Buffered output with rail-to-rail operation.

V

OUT

10 5, 6 AGND Analog Ground. Ground reference for analog circuitry.
15, 21–22

11,

DGND Digital Ground. Ground reference for digital circuitry.

17–18
16 12 BUF Buffer Control Pin. Controls whether the reference input to the DAC is buffered or unbuffered.
17 13

LDAC Active Low Control Input. Updates the DAC registers with the contents of the input registers, which

allows all DAC outputs to be simultaneously updated.

18 14 A0 LSB Address Pin. Selects which DAC is to be written to.
19 15 A1 Address Pin. Selects which DAC is to be written to.
20 16 A2 MSB Address Pin. Selects which DAC is to be written to.
23–32 19–28 DB0–DB
33 29

34 30
35 31

CS Active Low Chip Select Input. Used in conjunction with WR to write data to the parallel interface, or

RD Active Low Read Input. Used in conjunction with CS to read data back from the internal DACs.
WR Active Low Write Input. Used in conjunction with CS to write data to the parallel interface.

Ten Parallel Data Inputs. DB9 Is the MSB of these ten bits.

9

RD to read back data from a DAC.

with

36 32 GAIN Gain Control Pin. Controls whether the output range from the DAC is 0 V to V
37 33

38 34

CLR
PD

Asynchronous Active Low Control Input. Clears all input registers and DAC registers to zeros.
Power-Down Pin. This active low control pin puts all DACs into power-down mode.

GH

REF

REF

REF

V

V

V

10-BIT

PD

CLR

GAIN

AD5347

TOP VIEW

(Not to Scale)

A2

A1

A0

pins on the LFCSP package

DD

0

DGND

DGND

or 0 V to 2 × V

REF

WR

DB1DB

30

RD

29

CS

28

DB

9

27

DB

8

26

DB

7

25

DB

6

24

DB

5

23

DB

4

22

DB

3

21

DB

2

03331-0-008

.

REF

Rev. 0 | Page 8 of 24