Datasheet AD5346 Datasheet (Analog Devices)

2.5 V to 5.5 V, Parallel Interface

Octal Voltage Output 8-/10-/12-Bit DACs

FEATURES

AD5346: octal 8-bit DAC
AD5347: octal 10-bit DAC
AD5348: octal 12-bit DAC
Low power operation: 1.4 mA (max) @ 3.6 V
Power-down to 120 nA @ 3 V, 400 nA @ 5 V
Guaranteed monotonic by design over all codes

BUF

GAIN
DB11

DB0

WR

CLR

LDAC

REF

.

.
.

CS
RD

A2

A1

A0

or 0 V to 2 × V

LDAC

pin

FUNCTIONAL BLOCK DIAGRAM

V

DD

INTER­FACE
LOGIC

REF

AGND

AD5348

INPUT

REGISTER

INPUT

REGISTER

INPUT

REGISTER

INPUT

REGISTER

INPUT

REGISTER

INPUT

REGISTER

INPUT

REGISTER

INPUT

REGISTER

DGND

REGISTER

REGISTER

REGISTER

REGISTER

REGISTER

REGISTER

REGISTER

REGISTER

Rail-to-rail output range: 0 V to V
Power-on reset to 0 V
Simultaneous update of DAC outputs via

CLR

Asynchronous

facility
Readback
Buffered/unbuffered reference inputs

WR

20 ns

time
38-lead TSSOP/6 mm × 6 mm 40-lead LFCSP packaging
Temperature range: –40°C to +105°C

APPLICATIONS

Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Optical networking
Automatic test equipment
Mobile communications
Programmable attenuators
Industrial process control

1

Protected by U.S. Patent No. 5,969,657; other patents pending.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

DAC

DAC

DAC

DAC

DAC

DAC

DAC

DAC

Figure 1.

AD5346/AD5347/AD5348

GENERAL DESCRIPTION

The AD5346/AD5347/AD53481 are octal 8-, 10-, and 12-bit
DACs, operating from a 2.5 V to 5.5 V supply. These devices
incorporate an on-chip output buffer that can drive the output
to both supply rails, and also allow a choice of buffered or
unbuffered reference input.

The AD5346/AD5347/AD5348 have a parallel interface.
selects the device and data is loaded into the input registers on
the rising edge of
DAC registers to be read back through the digital port.

The GAIN pin on these devices allows the output range to be
set at 0 V to V

Input data to the DACs is double-buffered, allowing simultane­ous update of multiple DACs in a system using the

An asynchronous
contents of the input register and the DAC register to all zeros.
These devices also incorporate a power-on reset circuit that
ensures that the DAC output powers on to 0 V and remains
there until valid data is written to the device.

All three parts are pin compatible, which allows users to select
the amount of resolution appropriate for their application
without redesigning their circuit board.

AB

V

REF

STRING

DAC A

STRING

DAC B

STRING

DAC C

STRING

DAC D

STRING

DAC E

STRING

DAC F

STRING
DAC G

STRING

DAC H

V

REF

V

CD

REF

GH

V

EF

REF

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]
Fax: [phone] © 2003 Analog Devices, Inc. All rights reserved.

WR

. A readback feature allows the internal

or 0 V to 2 × V

REF

POWER-ON

RESET

BUFFER

BUFFER

BUFFER

BUFFER

BUFFER

BUFFER

BUFFER

BUFFER

POWER-DOWN

CLR

input is also provided, which resets the

LOGIC

PD

.

REF

V

A

OUT

B

V

OUT

V

C

OUT

V

D

OUT

E

V

OUT

V

F

OUT

G

V

OUT

H

V

OUT

03331-0-001

www.analog.com

LDAC

CS

pin.

AD5346/AD5347/AD5348

TABLE OF CONTENTS

Specifications..................................................................................... 3

Power-On Reset .......................................................................... 17

AC Characteristics ............................................................................ 4

Timing Characteristics..................................................................... 5

Absolute Maximum Ratings............................................................ 6

ESD Caution.................................................................................. 6

AD5346 Pin Configurations and Function Descriptions ........... 7

AD5347 Pin Configurations and Function Descriptions ........... 8

AD5348 Pin Configurations and Function Descriptions ........... 9

Te r m in o l o g y .................................................................................... 10

Typical Performance Characteristics........................................... 12

Functional Description ..................................................................16

Digital-to-Analog Section......................................................... 16

Resistor String............................................................................. 16

DAC Reference Input .................................................................16

Output Amplifier........................................................................ 16

Parallel Interface ......................................................................... 17

Power-Down Mode .................................................................... 17

Suggested Data Bus Formats..................................................... 18

Applications Information.............................................................. 19

Typical Application Circuits ..................................................... 19

Driving V

from the Reference Voltage................................. 19

DD

Bipolar Operation Using the AD5346/AD5347/AD5348..... 19

Decoding Multiple AD5346/AD5347/AD5348s.................... 20

AD5346/AD5347/AD5348 as Digitally Programmable
Window Detectors

...................................................................... 20

Programmable Current Source ................................................ 20

Coarse and Fine Adjustment Using the
AD5346/AD5347/AD5348

....................................................... 21

Power Supply Bypassing and Grounding................................ 21

Outline Dimensions....................................................................... 23

Ordering Guides......................................................................... 24

REVISION HISTORY

Revision 0: Initial Version

Rev. 0 | Page 2 of 24

AD5346/AD5347/AD5348

SPECIFICATIONS

Table 1. VDD = 2.5 V to 5.5 V; V
unless otherwise noted

B Version
Parameter

DC PERFORMANCE

2

3,4

AD5346

Resolution 8 Bits
Relative Accuracy ±0.15 ±1 LSB
Differential Nonlinearity ±0.02 ±0.25 LSB Guaranteed monotonic by design over all codes

AD5347

Resolution 10 Bits
Relative Accuracy ±0.5 ±4 LSB
Differential Nonlinearity ±0.05 ±0.5 LSB Guaranteed monotonic by design over all codes

AD5348

Resolution 12 Bits
Relative Accuracy ±2 ±16 LSB

Differential Nonlinearity ±0.2 ±1 LSB Guaranteed monotonic by design over all codes
Offset Error ±0.4 ±3 % of FSR
Gain Error ±0.1 ±1 % of FSR
Lower Deadband5 10 60 mV Lower deadband exists only if offset error is negative
Upper Deadband
Offset Error Drift
Gain Error Drift
DC Power Supply Rejection

6

Ratio
DC Crosstalk

DAC REFERENCE INPUT

V

Input Range 1 VDD V Buffered reference mode

REF

V

Input Range 0.25 VDD V Unbuffered reference mode

REF

V

Input Impedance >10 MΩ Buffered reference mode and power-down mode

REF

5

6

6

6

6

90 kΩ Gain = +1; input impedance = R
45 kΩ Gain = +2; input impedance = R
Reference Feedthrough –90 dB Frequency = 10 kHz
Channel-to-Channel Isolation –75 dB Frequency = 10 kHz

OUTPUT CHARACTERISTICS

6

Minimum Output Voltage
Maximum Output Voltage

DC Output Impedance 0.5 Ω
Short Circuit Current 25 mA VDD = 5 V
16 mA VDD = 3 V
Power-Up Time 2.5 µs Coming out of power-down mode; VDD = 5 V

5 µs Coming out of power-down mode; VDD = 3 V
LOGIC INPUTS6

Input Current ±1 µA
VIL, Input Low Voltage 0.8 V VDD = 5 V ±10%

0.7 V VDD = 3 V ±10%

0.6 V VDD = 2.5 V
VIH, Input High Voltage 1.7 V VDD = 2.5 V to 5.5 V
Pin Capacitance 5 pF

= 2 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications T

REF

1

MIN

Min Typ Max Unit Conditions/Comments

10 60 mV VDD = 5 V; upper deadband exists only if V
–12 ppm of FSR/°C
–5 ppm of FSR/°C
–60 dB ∆VDD = ±10%

200 µV

= 2 kΩ to GND, 2 kΩ to VDD; CL = 200 pF to GND;

R

L

Gain = +1

4, 7

0.001 V min Rail-to-rail operation

4, 7

V

V max

–

DD

0.001

to T

DAC

DAC

MAX

,

= V

REF

DD

Rev. 0 | Page 3 of 24

AD5346/AD5347/AD5348

B Version
Parameter

LOGIC OUTPUTS

2

6

Min Typ Max Unit Conditions/Comments

1

VDD = 4.5 V to 5.5 V

Output Low Voltage, VOL 0.4 V I
Output High Voltage, VOH VDD – 1 V I

= 200 µA

SINK

SOURCE

= 200 µA

VDD = 2.5 V to 3.6 V

Output Low Voltage, VOL 0.4 V I
Output High Voltage, VOH VDD – 0.5 V I

= 200 µA

SINK

SOURCE

= 200 µA

POWER REQUIREMENTS

VDD 2.5 5.5 V
IDD (Normal Mode) VIH = VDD, VIL = GND

VDD = 4.5 V to 5.5 V 1 1.65 mA All DACs in unbuffered mode. In buffered mode,
VDD = 2.5 V to 3.6 V 0.8 1.4 mA

extra current is typically x µA per DAC, where x = 5 µA +
V

REF/RDAC

IDD (Power-Down Mode) VIH = VDD, VIL = GND

VDD = 4.5 V to 5.5 V 0.4 1 µA
VDD = 2.5 V to 3.6 V 0.12 1 µA

See footnotes after the AC Characteristics table.

AC CHARACTERISTICS

Table 2. VDD = 2.5 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications T

B Version

6

to T

1

MIN

, unless otherwise noted

MAX

Parameter2 Min Typ Max Unit Conditions/Comments

Output Voltage Settling Time V

REF

= 2 V
AD5346 6 8 µs 1/4 scale to 3/4 scale change (40 H to C0 H)
AD5347 7 9 µs 1/4 scale to 3/4 scale change (100 H to 300 H)
AD5348 8 10 µs 1/4 scale to 3/4 scale change (400 H to C00 H)

Slew Rate 0.7 V/µs
Major Code Transition Glitch

Energy

8 nV-s 1 LSB change around major carry

Digital Feedthrough 0.5 nV-s
Digital Crosstalk 1 nV-s
Analog Crosstalk 1 nV-s
DAC-to-DAC Crosstalk 3.5 nV-s
Multiplying Bandwidth 200 kHz V
Total Harmonic Distortion –70 dB V

= 2 V ±0.1 V p-p; unbuffered mode

REF

= 2. V ±0.1 V p-p; frequency = 10 kHz; unbuffered mode

REF

1

Temperature range: B Version: –40°C to +105°C; typical specifications are at 25°C.

2

See Terminology section.

3

Linearity is tested using a reduced code range: AD5346 (Code 8 to 255); AD5347 (Code 28 to 1023); AD5348 (Code 115 to 4095).

4

DC specifications tested with outputs unloaded.

5

This corresponds to x codes. x = deadband voltage/LSB size.

6

Guaranteed by design and characterization, not production tested.

7

For the amplifier output to reach its minimum voltage, offset error must be negative. For the amplifier output to reach its maximum voltage, V

the offset plus gain error must be positive.

200µA

I

OL

= VDD and

REF

TO OUTPUT

PIN

50pF

C

L

200µA

I

OH

VOH(min) + VOL(max)

Figure 2. Load Circuit for Digital Output Timing Specifications

Rev. 0 | Page 4 of 24

2

03331-0-002

AD5346/AD5347/AD5348

TIMING CHARACTERISTICS

Table 3. VDD = 2.5 V to 5.5 V; all specifications T

Parameter Limit at T

Data Write Mode (Figure 3)
t1 0 ns min
t2 0 ns min
t3 20 ns min
t4 5 ns min Data, GAIN, BUF setup time
t5 4.5 ns min Data, GAIN, BUF hold time
t6 5 ns min
t7 5 ns min

t8 4.5 ns min Synchronous mode. WR rising to LDAC rising.
t9 5 ns min
t10 4.5 ns min
t11 20 ns min
t12 10 ns min
t13 20 ns min
t14 20 ns min A0, A1, A2 setup time

t15 0 ns min A0, A1, A2 hold time
Data Readback Mode (Figure 4)
t16 0 ns min
t17 0 ns min

t18 0 ns min CS to falling edge of RD
t19 20 ns min
30 ns min
t20 0 ns min
t21 22 ns max
30 ns max
t22 4 ns min
30 ns max

t23 22 ns max
30 ns max
t

24

t

25

t

26

50 ns min

1

Guaranteed by design and characterization, not production tested.

2

All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.

3

See Figure 2.

CS

WR

DATA,

GAIN, BUF

1

LDAC

2

LDAC

CLR

A0–A2

Figure 3. Parallel Interface Write Timing Diagram Figure 4. Parallel Interface Read Timing Diagram

t

1

t

3

t

4

t

6

t

7

t

9

t

14

NOTES

1. SYNCHRONOUS LDAC UPDATE MODE

2. ASYNCHRONOUS LDAC UPDATE MODE

1, 2, 3

to T

MIN

, T

MIN

MAX

30 ns min
30 ns min
30 ns min

t

2

t

13

t

5

t

8

t

10

t

11

t

t

15

12

, unless otherwise noted

MAX

Unit Condition/Comments

CS to WR setup time
CS to WR hold time
WR pulse width

Synchronous mode.
Synchronous mode.

Asynchronous mode.
Asynchronous mode.
LDAC pulse width
CLR

pulse width

Time between

A0, A1, A2 to
A0, A1, A2 to

RD pulse width; VDD = 3.6 V to 5.5 V
RD pulse width; VDD = 2.5 V to 3.6 V
CS to RD hold time
Data access time after falling edge of
Data access time after falling edge of
Bus relinquish time after rising edge of

CS falling edge to data; VDD = 3.6 V to 5.5 V
CS falling edge to data; VDD = 2.5 V to 3.6 V

Time between
Time from

Time from
Time from

A0–A2

CS

RD

DATA

WR

03331-0-003

WR falling to LDAC falling.
LDAC falling to WR rising.

LDAC rising to WR rising.
WR rising to LDAC falling.

WR cycles

CS

setup time

CS

hold time

RD; VDD = 3.6 V to 5.5 V
RD VDD = 2.5 V to 3.6 V

RD

cycles

RD to WR
WR to RD, VDD = 3.6 V to 5.5 V
WR to RD, VDD = 2.5 V to 3.6 V

t

16

t

18

t

21

t

23

t

26

t

20

t

19

t

22

RD

t

17

t

24

t

25

03331-0-004

Rev. 0 | Page 5 of 24

AD5346/AD5347/AD5348

ABSOLUTE MAXIMUM RATINGS

Table 4. TA = 25°C, unless otherwise noted

Parameter Rating

VDD to GND –0.3 V to +7 V
Digital Input Voltage to GND –0.3 V to VDD + 0.3 V
Digital Output Voltage to GND –0.3 V to VDD + 0.3 V
Reference Input Voltage to GND –0.3 V to VDD + 0.3 V
V

to GND –0.3 V to VDD + 0.3 V

OUT

Operating Temperature Range

Industrial (B Version) –40°C to +105°C

Storage Temperature Range –65°C to +150°C
Junction Temperature 150°C
38-Lead TSSOP Package

Power Dissipation (TJ max − TA)/ θJA mW
θJA Thermal Impedance 98.3°C/W
θJC Thermal Impedance 8.9°C/W

40-Lead LFCSP Package

Power Dissipation (TJ max − TA)/ θJA mW
θJA Thermal Impedance (3-layer

board)

Lead Temperature, Soldering (10 sec) 300°C
IR Reflow, Peak Temperature 220°C

29.6°C/W

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. 0 | Page 6 of 24

AD5346/AD5347/AD5348

AD5346 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

CD

EF

V

REF

V

V

V

V

REF

REF

V

REF

V

OUT

V

OUT

V

OUT

V

OUT

AGND

V

OUT

V

OUT

OUT

V

OUT

DGND

BUF

LDAC

GH

EF

CD

DD

AB

A
B
C

D

E

F
G
H

A0
A1

1
2
3
4
5
6

8-BIT

AD5346

7

TOP VIEW

8

(Not to Scale)

9
10
11
12
13
14
15
16
17
18
19

38

PD

37

CLR

36

GAIN

35

WR

34

RD

33

CS

32

DB

7

31

DB

6

30

DB

5

29

DB

4

28

DB

3

DB

27

2

DB

26

1

DB

25

0

DGND

24
23

DGND
DGND

22

DGND

21
20

A2

03331-0-005

V

OUT

V

OUT

V

OUT

V

OUT

AGND
AGND

V

OUT

V

OUT

V

OUT

V

OUT

AB

REF

DD

DD

V

V

V

40 39 38 37 36 35 34 33 32 31

A

1
2

B
C

3

D

4
5
6

E

7

F

8
9

G
H

10

11 12 13 14 15 16 17 18 19 20

BUF

LDAC

DGND

Figure 6. AD5346 Pin Configuration—LFCSP

Figure 5. AD5346 Pin Configuration—TSSOP

Table 5. AD5346 Pin Function Descriptions

Pin Number

TSSOP LFCSP Mnemonic Function

1 35 V
2 36 V
3 37 V
4 38, 39 VDD

GH Reference Input for DACs G and H.

REF

EF Reference Input for DACs E and F.

REF

CD Reference Input for DACs C and D.

REF

Power Supply Pin(s). This part can operate from 2.5 V to 5.5 V, and the supply should be decoupled
with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND. Both V

package must be at the same potential.
5 40 V
6–9,

11–14

1–4,
7–10

AB Reference Input for DACs A and B.

REF

X Output of DAC X. Buffered output with rail-to-rail operation.

V

OUT

10 5, 6 AGND Analog Ground. Ground reference for analog circuitry.
15,

21–24

11,
17–20

DGND Digital Ground. Ground reference for digital circuitry.

16 12 BUF Buffer Control Pin. Controls whether the reference input to the DAC is buffered or unbuffered.
17 13

LDAC

Active Low Control Input. Updates the DAC registers with the contents of the input registers, which

allows all DAC outputs to be simultaneously updated.
18 14 A0 LSB Address Pin. Selects which DAC is to be written to.
19 15 A1 Address Pin. Selects which DAC is to be written to.
20 16 A2 MSB Address Pin. Selects which DAC is to be written to.
25–32 21–28 DB0–DB
33 29

34 30
35 31

CS

RD
WR

7

Eight Parallel Data Inputs. DB7 is the MSB of these eight bits.

Active Low Chip Select Input. Used in conjunction with

RD to read back data from a DAC.

with

Active Low Read Input. Used in conjunction with

Active Low Write Input. Used in conjunction with

WR to write data to the parallel interface, or

CS to read data back from the internal DACs.

CS to write data to the parallel interface.
36 32 GAIN Gain Control Pin. Controls whether the output range from the DAC is 0 V to V
37 33
38 34

CLR
PD

Asynchronous Active Low Control Input. Clears all input registers and DAC registers to zeros.
Power-Down Pin. This active low control pin puts all DACs into power-down mode.

GH

REF

REF

REF

V

V

V

8-BIT

AD5346

TOP VIEW

(Not to Scale)

A2

A1

A0

DD

PD

CLR

GAIN

WR

30

RD

29

CS

28

DB

7

27

DB

6

26

DB

5

25

DB

4

24

DB

3

23

DB

2

22

DB

1

21

DB

0

DGND

DGND

DGND

DGND

pins on the LFCSP

or 0 V to 2 × V

REF

03331-0-006

REF.

Rev. 0 | Page 7 of 24

AD5346/AD5347/AD5348

AD5347 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

CD

EF

V

V

V

V

REF

REF

REF

V

REF

V

OUT

V

OUT

V

OUT

V

OUT

AGND

V

OUT

V

OUT

V

OUT

V

OUT

DGND

BUF

LDAC

GH

EF

CD

DD

AB

A
B
C
D

E

F

G

H

A0
A1

1
2
3
4
5
6

10-BIT

AD5347

7

TOP VIEW

8

(Not to Scale)

9
10
11
12
13
14
15
16
17
18
19

38

PD

37

CLR

36

GAIN

35

WR

34

RD

33

CS

32

DB

9

31

DB

8

30

DB

7

29

DB

6

28

DB

5

DB

27

4

DB

26

3

DB

25

2

DB

24

1

23

DB

0

DGND

22

DGND

21
20

A2

03331-0-007

V

OUT

V

OUT

V

OUT

V

OUT

AGND
AGND

V

OUT

V

OUT

V

OUT

V

OUT

AB

REF

DD

DD

V

V

V

40 39 38 37 36 35 34 33 32 31

A

1
2

B
C

3

D

4
5
6

E

7

F

8
9

G

H

10

11 12 13 14 15 16 17 18 19 20

BUF

LDAC

DGND

Figure 8. AD5347 Pin Configuration—LFCSP

Figure 7. AD5347 Pin Configuration—TSSOP

Table 6. AD5347 Pin Function Descriptions

Pin Number

TSSOP LFCSP Mnemonic Function

1 35 V
2 36 V
3 37 V
4 38, 39 V

GH Reference Input for DACs G and H.

REF

EF Reference Input for DACs E and F.

REF

CD Reference Input for DACs C and D.

REF

DD

Power Supply Pin(s). This part can operate from 2.5 V to 5.5 V, and the supply should be decoupled
with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND. Both V

must be at the same potential.
5 40 V
6–9,

11–14

1–4,
7–10

AB Reference Input for DACs A and B.

REF

X Output of DAC X. Buffered output with rail-to-rail operation.

V

OUT

10 5, 6 AGND Analog Ground. Ground reference for analog circuitry.
15, 21–22

11,

DGND Digital Ground. Ground reference for digital circuitry.

17–18
16 12 BUF Buffer Control Pin. Controls whether the reference input to the DAC is buffered or unbuffered.
17 13

LDAC Active Low Control Input. Updates the DAC registers with the contents of the input registers, which

allows all DAC outputs to be simultaneously updated.

18 14 A0 LSB Address Pin. Selects which DAC is to be written to.
19 15 A1 Address Pin. Selects which DAC is to be written to.
20 16 A2 MSB Address Pin. Selects which DAC is to be written to.
23–32 19–28 DB0–DB
33 29

34 30
35 31

CS Active Low Chip Select Input. Used in conjunction with WR to write data to the parallel interface, or

RD Active Low Read Input. Used in conjunction with CS to read data back from the internal DACs.
WR Active Low Write Input. Used in conjunction with CS to write data to the parallel interface.

Ten Parallel Data Inputs. DB9 Is the MSB of these ten bits.

9

RD to read back data from a DAC.

with

36 32 GAIN Gain Control Pin. Controls whether the output range from the DAC is 0 V to V
37 33

38 34

CLR
PD

Asynchronous Active Low Control Input. Clears all input registers and DAC registers to zeros.
Power-Down Pin. This active low control pin puts all DACs into power-down mode.

GH

REF

REF

REF

V

V

V

10-BIT

PD

CLR

GAIN

AD5347

TOP VIEW

(Not to Scale)

A2

A1

A0

pins on the LFCSP package

DD

0

DGND

DGND

or 0 V to 2 × V

REF

WR

DB1DB

30

RD

29

CS

28

DB

9

27

DB

8

26

DB

7

25

DB

6

24

DB

5

23

DB

4

22

DB

3

21

DB

2

03331-0-008

.

REF

Rev. 0 | Page 8 of 24

AD5346/AD5347/AD5348

V

AD5348 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

CD

EF

REF

V

V

V

V
V
V
V

V
V

GH

REF

CD

REF

V

AB

REF

OUT

OUT
OUT
OUT

AGND
V

OUT

V

OUT
OUT
OUT

DGND

BUF

LDAC

EF

DD

A
B
C
D

E

F
G
H

A0
A1

1
2
3
4
5
6

12-BIT

AD5348

7

TOP VIEW

8

(Not to Scale)

9
10
11
12
13
14
15
16
17
18
19

38

PD

37

CLR

36

GAIN

35

WR

34

RD

33

CS

32

DB

11

31

DB

10

30

DB

9

29

DB

8

28

DB

7

DB

27

6

DB

26

5

DB

25

4

DB

24

3

23

DB

2

DB

22

1

DB

21

0

20

A2

03331-0-009

V

OUT

V

OUT

V

OUT

V

OUT

AGND
AGND

V

OUT

V

OUT

V

OUT

V

OUT

AB

REF

DD

DD

V

V

V

40 39 38 37 36 35 34 33 32 31

A

1
2

B
C

3

D

4
5
6

E

7

F

8
9

G
H

10

11 12 13 14 15 16 17 18 19 20

BUF

LDAC

DGND

Figure 10. AD5348 Pin Configuration—LFCSP

Figure 9. AD5348 Pin Configuration—TSSOP

Table 7. AD5348 Pin Function Descriptions

Pin Number

TSSOP LFCSP Mnemonic Function

1 35 V
2 36 V
3 37 V
4 38, 39 VDD

GH Reference Input for DACs G and H.

REF

EF Reference Input for DACs E and F.

REF

CD Reference Input for DACs C and D.

REF

Power Supply Pin(s). This part can operate from 2.5 V to 5.5 V, and the supply should be decoupled with a
10 µF capacitor in parallel with a 0.1 µF capacitor to GND. Both V

pins on the LFCSP package must be at

DD

the same potential.
5 40 V
6–9,

11–14

1–4,
7–10

AB Reference Input for DACs A and B.

REF

X Output of DAC X. Buffered output with rail-to-rail operation.

V

OUT

10 5, 6 AGND Analog Ground. Ground reference for analog circuitry.
15 11 DGND Digital Ground. Ground reference for digital circuitry.
16 12 BUF Buffer Control Pin. Controls whether the reference input to the DAC is buffered or unbuffered.
17 13

LDAC

Active Low Control Input. Updates the DAC registers with the contents of the input registers, which allows

all DAC outputs to be simultaneously updated.
18 14 A0 LSB Address Pin. Selects which DAC is to be written to.
19 15 A1 Address Pin. Selects which DAC is to be written to.
20 16 A2 MSB Address Pin. Selects which DAC is to be written to.
21–32 17–28 DB0–DB11 Twelve Parallel Data Inputs. DB11 is the MSB of these 12 bits.
33 29

CS Active Low Chip Select Input. Used in conjunction with WR to write data to the parallel interface, or with

RD to read back data from a DAC.
34 30
35 31

RD
WR

Active Low Read Input. Used in conjunction with

Active Low Write Input. Used in conjunction with

CS to read data back from the internal DACs.

CS to write data to the parallel interface.
36 32 GAIN Gain Control Pin. Controls whether the output range from the DAC is 0 V to V
37 33
38 34

CLR
PD

Asynchronous Active Low Control Input. Clears all input registers and DAC registers to zeros.
Power-Down Pin. This active low control pin puts all DACs into power-down mode.

GH

REF

REF

REF

V

V

V

12-BIT

AD5348

TOP VIEW

(Not to Scale)

A2

A1

A0

REF

PD

CLR

GAIN

WR

30
29
28
27
26
25
24
23
22
21

0

DB3DB2DB1DB

or 0 V to 2 × V

RD
CS
DB
DB
DB
DB
DB
DB
DB
DB

REF

11
10
9
8
7
6
5
4

03331-0-010

.

Rev. 0 | Page 9 of 24

AD5346/AD5347/AD5348

V

TERMINOLOGY

Relative Accuracy

For the DAC, relative accuracy or integral nonlinearity (INL) is
a measure of the maximum deviation, in LSBs, from a straight
line passing through the actual endpoints of the DAC transfer
function. Typical INL versus code plots can be seen in Figure 14,
Figure 15, and Figure 16.

Differential Nonlinearity

Differential nonlinearity (DNL) is the difference between the
measured change and the ideal 1 LSB change between any two
adjacent codes. A specified differential nonlinearity of ± 1 LSB
maximum ensures monotonicity. This DAC is guaranteed
monotonic by design. Typical DNL versus code plots can be
seen in Figure 17, Figure 18, and Figure 19.

Gain Error

This is a measure of the span error of the DAC, including any
error in the gain of the buffer amplifier. It is the deviation in
slope of the actual DAC transfer characteristic from the ideal
and is expressed as a percentage of the full-scale range. This is
illustrated in Figure 11.

Offset Error

This is a measure of the offset error of the DAC and the output
amplifier. It is expressed as a percentage of the full-scale range.

OUTPUT

VOLTAGE

POSITIVE

OFFSET

VOLTAGE

ACTUAL

DAC CODE

Figure 12. Positive Offset Error and Gain Error

IDEAL

OUTPUT

IDEAL

GAIN ERROR
AND
OFFSET
ERROR

GAIN ERROR
AND
OFFSET
ERROR

03331-0-012

If the offset voltage is positive, the output voltage still positive at
zero input code. This is shown in Figure 12. Because the DACs
operate from a single supply, a negative offset cannot appear at
the output of the buffer amplifier. Instead, there is a code close
to zero at which the amplifier output saturates (amplifier
footroom). Below this code there is a dead band over which the
output voltage does not change. This is illustrated in Figure 13.

POSITIVE
GAIN ERROR

NEGATIVE
GAIN ERROR

03331-0-011

OUTPUT
OLTAGE

ACTUAL

IDEAL

DAC CODE

Figure 11. Gain Error

NEGATIVE

OFFSET

AMPLIFIER

FOOTROOM

(~1mV)

NEGATIVE

OFFSET

ACTUAL

DAC CODE

DEADBAND CODES

Figure 13. Negative Offset Error and Gain Error

03331-0-013

Rev. 0 | Page 10 of 24

AD5346/AD5347/AD5348

Offset Error Drift

This is a measure of the change in offset error with changes in
temperature. It is expressed in (ppm of full-scale range)/°C.

Gain Error Drift

This is a measure of the change in gain error with changes in
temperature. It is expressed in (ppm of full-scale range)/°C.

DC Power-Supply Rejection Ratio (PSRR)

This indicates how the output of the DAC is affected by changes
in the supply voltage. PSRR is the ratio of the change in V
a change in V
in dB. V

for full-scale output of the DAC. It is measured

DD

is held at 2 V and VDD is varied ±10%.

REF

OUT

to

DC Crosstalk

This is the dc change in the output level of one DAC at midscale
in response to a full-scale code change (all 0s to all 1s and vice
versa) and output change of another DAC. It is expressed in µV.

Reference Feedthrough

This is the ratio of the amplitude of the signal at the DAC
output to the reference input when the DAC output is not being

LDAC

updated, i.e.,

is high. It is expressed in dB.

Channel-to-Channel Isolation

This is a ratio of the amplitude of the signal at the output of one
DAC to a sine wave on the reference inputs of the other DACs.
It is measured by grounding one V
4 V p-p sine wave to the other V

pin and applying a 10 kHz,

REF

pins. It is expressed in dB.

REF

Major-Code Transition Glitch Energy

This is the energy of the impulse injected into the analog output
when the DAC changes state. It is normally specified as the area
of the glitch in nV-s and is measured when the digital code is
changed by 1 LSB at the major carry transition (011 . . . 11 to
100 . . . 00 or 100 . . . 00 to 011 . . . 11).

Digital Feedthrough

This is a measure of the impulse injected into the analog output
of the DAC from the digital input pins of the device, but it is

CS

measured when the DAC is not being written to,

held high.
It is specified in nV-s and is measured with a full-scale change
on the digital input pins, i.e., from all 0s to all 1s and vice versa.

Digital Crosstalk

This is the glitch impulse transferred to the output of one DAC
at midscale in response to a full-scale code change (all 0s to all
1s and vice versa) in the input register of another DAC. It is
expressed in nV-s.

Analog Crosstalk

This is the glitch impulse transferred to the output of one DAC
due to a change in the output of another DAC. It is measured by
loading one of the input registers with a full-scale code change

LDAC

(all 0s to all 1s and vice versa) while keeping

LDAC

pulse

low and monitor the output of the DAC whose

high. Then

digital code was not changed. The area of the glitch is expressed
in nV-s.

DAC-to-DAC Crosstalk

This is the glitch impulse transferred to the output of one DAC
due to a digital code change and subsequent output change of
another DAC. This includes both digital and analog crosstalk. It
is measured by loading one of the DACs with a full-scale code

LDAC

change (all 0s to all 1s and vice versa) with the

pin set
low and monitoring the output of another DAC. The energy of
the glitch is expressed in nV-s.

Multiplying Bandwidth

The amplifiers within the DAC have a finite bandwidth. The
multiplying bandwidth is a measure of this. A sine wave on the
reference (with full-scale code loaded to the DAC) appears on
the output. The multiplying bandwidth is the frequency at
which the output amplitude falls to 3 dB below the input.

Total Harmonic Distortion (THD)

This is the difference between an ideal sine wave and its
attenuated version using the DAC. The sine wave is used as the
reference for the DAC, and the THD is a measure of the
harmonics present on the DAC output. It is measured in dB.

Rev. 0 | Page 11 of 24

AD5346/AD5347/AD5348

TYPICAL PERFORMANCE CHARACTERISTICS

1.0
TA = 25°C

= 5V

V

DD

0.5

0.3

0.2

0.1

TA = 25°C
V

= 5V

DD

0

INL ERROR (LSB)

–0.5

–1.0

CODE

Figure 14. AD5346 Typical INL Plot

3

TA = 25°C

= 5V

V

DD

2

1

0

INL ERROR (LSB)

–1

–2

–3

0 200 1000

400 600 800

CODE

Figure 15. AD5347 Typical INL Plot

2501000 50 150 200

03331-0-014

03331-0-015

0

–0.1

DNL ERROR (LSB)

–0.2

–0.3

CODE

Figure 17. AD5346 Typical DNL Plot

0.6
= 25°C

T

A

= 5V

V

DD

0.4

0.2

0

–0.2

DNL ERROR (LSB)

–0.4

–0.6

2000

600400 800 1000

CODE

Figure 18. AD5347 Typical DNL Plot

250100 1500 50 200

03331-0-017

03331-0-018

12

TA = 25°C
V

= 5V

DD

8

4

0

–4

INL ERROR (LSB)

–8

–12

0 40001000 2000 3000

CODE

Figure 16. AD5348 Typical INL Plot

03331-0-016

Rev. 0 | Page 12 of 24

1.0

TA = 25°C

= 5V

V

DD

0.5

0

DNL ERROR (LSB)

–0.5

–1.0

10000

2000 3000 4000

CODE

Figure 19. AD5348 Typical DNL Plot

03331-0-019

AD5346/AD5347/AD5348

0.5
VDD = 5V

= 25°C

T

0.4

A

0.3

0.2

0.1

0

–0.1

ERROR (LSB)

–0.2

–0.3
–0.4
–0.5

012345

Figure 20. AD5346 INL and DNL Error vs. V

V

REF

MAX INL

MIN DNL

MIN INL

(V)

MAX DNL

REF

03331-0-031

0.2

TA = 25°C
V

= 2V

REF

0.1

0

–0.1

–0.2

–0.3

ERROR (% FSR)

–0.4

–0.5

–0.6

0 21 3

Figure 23. Offset Error and Gain Error vs. V

GAIN ERROR

OFFSET ERROR

VDD (V)

456

DD

03331-0-034

0.5

VDD = 5V
V

0.4

0.3

0.2

0.1

–0.1

ERROR (LSB)

–0.2

–0.3
–0.4
–0.5

= 2V

REF

0

–40 0–204020

TEMPERATURE (°C)

MAX INL

MAX DNL

MIN DNL

Figure 21. AD5346 INL and DNL Error vs. Temperature

MIN INL

60 80 100

03331-0-032

5

4

3

(V)

OUT

V

2

1

0

0 21 3

Figure 24. V

OUT

5V SOURCE

3V SOURCE

5V SINK

SINK/SOURCE CURRENT (mA)

3V SINK

456

Source and Sink Current Capability

03331-0-035

1.0

VDD = 5V

= 2V

V

REF

0.5

0

ERROR (% FSR)

–0.5

–1.0

–40 –20 0 4020

OFFSET ERROR

GAIN ERROR

8060 100

TEMPERATURE (°C)

Figure 22. AD5346 Offset Error and Gain Error vs. Temperature

03331-0-033

Rev. 0 | Page 13 of 24

1.0

0.9

0.8

0.7

0.6

0.5

(mA)

DD

I

0.4

0.3

0.2

0.1
0

ZERO SCALE HALF SCALE

Figure 25. Supply Current vs. DAC Code

DAC CODE

VDD = 5V
TA = 25°C

FULL SCALE

03331-0-036

AD5346/AD5347/AD5348

1.4

V

= 2V

REF

GAIN = 1 UNBUFFERED

1.2

1.0

0.8

(mA)

0.6

DD

I

0.4

0.2

0

2.5 3.53.0 4.0

TA = –40°C

SUPPLY VOLTAGE (V)

TA = +25°C

TA = +105°C

Figure 26. Supply Current vs. Supply Voltage

1.0

0.9

TA= 25°C

0.8

0.7

0.6

0.5

0.4

POWER-DOWN (µA)

0.3

DD

I

0.2

0.1

0

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
V

(V)

DD

Figure 27. Power-Down Current vs. Supply Voltage

4.5 5.0 5.5

03331-0-037

03331-0-038

TA= 25°C

= 5V

V

DD

= 5V

V

REF

V

A

OUT

CH1

LDAC

CH2

CH1 1V, CH2 5V, TIME BASE = 1µs/DIV

Figure 29. Half-Scale Settling (¼ to ¾ Scale Code)

TA= 25°C
VDD = 5V
V

= 2V

REF

CH1

V

DD

V

A

OUT

CH2

CH1 2V, CH2 200mV, TIME BASE = 200µs/DIV

Figure 30. Power-On Reset to 0 V

03331-0-040

03331-0-041

2.5

TA = 25°C

2.0

1.5

(mA)

DD

I

1.0

VDD = 3V

0.5

0

0 321 4

VDD = 5V

VLOGIC (V)

Figure 28. Supply Current vs. Logic Input Voltage

03331-0-039

5

Rev. 0 | Page 14 of 24

CH2

CH1

V

1

OUT

PD

CH1 2.00V, CH2 1.00V, TIME BASE = 20µs/DIV

Figure 31. Exiting Power-Down to Midscale

03331-0-042

AD5346/AD5347/AD5348

FREQUENCY

21

18

15

V

=

3V V

DD

12

9

6

3

=

5V

DD

FULL-SCALE ERROR (V)

0.02

0.01

–0.01

0

VDD = 5V
T

= 25°C

A

(V)

V

0

Figure 32. I

2.50

2.49

OUT

2.48

2.47

0.80.6 1.0 1.2 1.4
IDD (mA)

Histogram with VDD = 3 V and VDD = 5 V

DD

1µs/DIV

Figure 33. AD5348 Major Code Transition Glitch Energy

10

0

03331-0-043

03331-0-044

475

03331-0-046

03331-0-047

511

–0.02

0 21 3

Figure 35. Full-Scale Error vs. V

1.999

1.998

1.997

1.996

0

75

50

25

100

125

150

175

200

225

V

REF

250

456

(V)

REF

425

400

375

350

325

300

275

450

Figure 36. DAC-to-DAC Crosstalk

–10

–20

dB

–30

–40

–50

–60

10 1k100 10k

FREQUENCY (Hz)

100k 1M 10M

Figure 34. Multiplying Bandwidth (Small Signal Frequency Response)

03331-0-045

Rev. 0 | Page 15 of 24

AD5346/AD5347/AD5348

FUNCTIONAL DESCRIPTION

The AD5346/AD5347/AD5348 are octal resistor-string DACs
fabricated by a CMOS process with resolutions of 8, 10, and 12
bits, respectively. They are written to using a parallel interface.
They operate from single supplies of 2.5 V to 5.5 V, and the
output buffer amplifiers offer rail-to-rail output swing. The gain
of the buffer amplifiers can be set to 1 or 2 to give an output
voltage range of 0 V to V

or 0 V to 2 × V

REF

AD5347/AD5348 have reference inputs that may be buffered to
draw virtually no current from the reference source. The devices
have a power-down feature that reduces current consumption
to only 100 nA @ 3 V.

DIGITAL-TO-ANALOG SECTION

The architecture of one DAC channel consists of a reference
buffer and a resistor-string DAC followed by an output buffer
amplifier. The voltage at the V
voltage for the DAC. Figure 37 shows a block diagram of the
DAC architecture. Because the input coding to the DAC is
straight binary, the ideal output voltage is given by

D

VV

REFOUT ××=

Gain

N

2

where:

pin provides the reference

REF

The AD5346/

REF.

V

REF

R

R

TO OUTPUT
AMPLIFIER

03331-0-021

R

R

R

Figure 38. Resistor String

DAC REFERENCE INPUT

The DACs operate with an external reference. The AD5346/
AD5347/AD5348 have a reference input for each pair of DACs.
The reference inputs may be configured as buffered or
unbuffered. This option is controlled by the BUF pin.

In buffered mode (BUF = 1), the current drawn from an
external reference voltage is virtually zero because the imped­ance is at least 10 MΩ. The reference input range is 1 V to V

DD

.

D is the decimal equivalent of the binary code, which is loaded

to the DAC register:
0–255 for AD5346 (8 bits)
0–1023 for AD5347 (10 bits)
0–4095 for AD5348 (12 bits)

N is the DAC resolution.
Gain is the output amplifier gain (1 or 2).

V

AB

REF

INPUT

REGISTER

BUF

DAC

REGISTER

Figure 37. Single DAC Channel Architecture

RESISTOR

STRING

REFERENCE
BUFFER

(GAIN = +1 OR +2)

BUFFER AMPLIFIER

OUTPUT

V

OUT

RESISTOR STRING

The resistor string section is shown in Figure 38. It is simply a
string of resistors, each of value R. The digital code loaded to
the DAC register determines at what node on the string the
voltage is tapped off to be fed into the output amplifier. The
voltage is tapped off by closing one of the switches connecting
the string to the amplifier. Because it is a string of resistors, it is
guaranteed monotonic.

In unbuffered mode (BUF = 0), the user can have a reference
voltage as low as 0.25 V and as high as V

because there is no

DD

restriction due to headroom and footroom of the reference
amplifier. The impedance is still large at typically 90 kΩ for 0 V
to V

mode and 45 kΩ for 0 V to 2 × V

REF

mode.

REF

If using an external buffered reference (such as REF192), there
is no need to use the on-chip buffer.

OUTPUT AMPLIFIER

The output buffer amplifier is capable of generating output
voltages to within 1 mV of either rail. Its actual range depends

, GAIN, the load on V

on V

REF

A

03331-0-020

If a gain of +1 is selected (GAIN = 0), the output range is

0.001 V to V

REF

.

If a gain of +2 is selected (GAIN = +1), the output range is

0.001 V to 2 × V

. However, because of clamping, the

REF

maximum output is limited to V

The output amplifier is capable of driving a load of 2 kΩ to
GND or V

, in parallel with 500 pF to GND or VDD. The source

DD

and sink capabilities of the output amplifier can be seen in
Figure 24.

The slew rate is 0.7 V/µs with a half-scale settling time to ±0.5 LSB
(at 8 bits) of 6 s with the output unloaded. See Figure 29.

, and offset error.

OUT

– 0.001 V.

DD

Rev. 0 | Page 16 of 24

AD5346/AD5347/AD5348

T

PARALLEL INTERFACE

The AD5346/AD5347/AD5348 load their data as a single 8-,
10-, or 12-bit word.

Double-Buffered Interface

The AD5346/AD5347/AD5348 DACs all have double-buffered
interfaces consisting of an input register and a DAC register.
DAC data, BUF, and GAIN inputs are written to the input regis­ter under control of the Chip Select (CS) and Write (WR) pins.

Access to the DAC register is controlled by the

LDAC

When

is high, the DAC register is latched and the input

register may change state without affecting the contents of the

LDAC

DAC register. However, when

is brought low, the DAC
register becomes transparent and the contents of the input
register are transferred to it. The gain and buffer control signals
are also double-buffered and are updated only when
taken low.

This is useful if the user requires simultaneous updating of all
DACs and peripherals. The user can write to all input registers
individually and then, by pulsing the

LDAC

outputs update simultaneously.

These parts contain an extra feature whereby the DAC register
is not updated unless its input register has been updated since
the last time that
LDAC

is brought low, the DAC registers are filled with the

LDAC

was brought low. Normally, when

contents of the input registers. In the case of the AD5346/
AD5347/AD5348, the part updates the DAC register only if the
input register has been changed since the last time the DAC
register was updated. This removes unnecessary crosstalk.

Clear Input (

CLR

is an active low, asynchronous clear that resets the input

CLR

)

and DAC registers.

Chip Select Input (CS)

CS

is an active low input that selects the device.

Write Input (WR)

WR

is an active low input that controls writing of data to the

device. Data is latched into the input register on the rising edge

WR

.

of

Read Input (RD)

RD

is an active low input that controls when data is read back
from the internal DAC registers. On the falling edge of
is shifted onto the data bus. Under the conditions of a high
capacitive load and high supplies, the user must ensure that the
dynamic current remains at an acceptable level, therefore
ensuring that the die temperature is within specification. The

die temperature can be calculated as

T

DIE

= T

AMBIENT

+ V

DD (IDD

+ I

LDAC

input low, all

DYNA MIC)θJA

function.

LDAC

is

RD

, data

where I
c = capacitance or the data bus
v = V

Load DAC Input (

LDAC

and therefore updates the outputs. The
double-buffering of the DAC data, GAIN data, and BUF. There
are two

• Synchronous Mode. In this mode, the DAC register is

updated after new data is read in on the rising edge of the
WR
shown in Figure 3.

• Asynchronous Mode. In this mode, the outputs are not

updated at the same time that the input register is written
to. When
the contents of the input register.

POWER-ON RESET

The AD5346/AD5347/AD5348 have a power-on reset function,
so that they power up in a defined state. The power-on state is

• Normal operation

• Reference input buffered

• 0 V to V

• Output voltage set to 0 V

Both input and DAC registers are filled with zeros and remain
so until a valid write sequence is made to the device. This is
particularly useful in applications where it is important to know
the state of the DAC outputs while the device is powering up.

POWER-DOWN MODE

The AD5346/AD5347/AD5348 have low power consumption,
dissipating typically 2.4 mW with a 3 V supply and 5 mW with
a 5 V supply. Power consumption can be further reduced when
the DACs are not in use by putting them into power-down
mode, which is selected by taking the PD pin low.

When the
cal power consumption of 1 mA at 5 V (0.8 mA at 3 V). In
power-down mode, however, the supply current falls to 400 nA
at 5 V (120 nA at 3 V) when the DACs are powered down. Not
only does the supply current drop, but the output stage is also
internally switched from the output of the amplifier, making it
open-circuit. This has the advantage that the outputs are three­state while the part is in power-down mode, and provides a
defined input condition for whatever is connected to the outputs
of the DAC amplifiers. The output stage is illustrated in Figure 39.

= cvf and

DYNA MIC

DD

f = readback frequency

LDAC

)

transfers data from the input register to the DAC register,

LDAC

function enables

LDAC

modes:

LDAC

input.

LDAC

REF

PD

pin is high, the DACs work normally with a typi-

Figure 39. Output Stage During Power-Down

can be tied permanently low or pulsed as

goes low, the DAC register is updated with

output range

RESISTOR

STRING DAC

AMPLIFIER

POWER-DOWN

CIRCUITRY

V

OU

03331-0-022

Rev. 0 | Page 17 of 24

AD5346/AD5347/AD5348

The bias generator, the output amplifier, the resistor string, and
all other associated linear circuitry are all shut down when the
power-down mode is activated. However, the contents of the
registers are unaffected when in power-down. The time to exit
power-down is typically 2.5 s for V
3 V. This is the time from a rising edge on the
the output voltage deviates from its power-down voltage. See
Figure 31.

SUGGESTED DATA BUS FORMATS

In many applications, the GAIN and BUF pins are hardwired.
However, if more flexibility is required, they can be included in
a data bus. This enables the user to software program GAIN,
giving the option of doubling the resolution in the lower half of
the DAC range. In a bused system, GAIN and BUF may be
treated as data inputs because they are written to the device
during a write operation and take effect when
low. This means that the reference buffers and the output
amplifier gain of multiple DAC devices can be controlled using
common GAIN and BUF lines. Note that GAIN and BUF are

RD

not read back during an

operation.

= 5 V and 5 µs when VDD =

DD

PD

pin to when

LDAC

is taken

The AD5347 and AD5348 data bus must be at least 10 and 12
bits wide, respectively, and are best suited to a 16-bit data bus
system.

Examples of data formats for putting GAIN and BUF on a
16-bit data bus are shown in Figure 40. Note that any unused
bits above the actual DAC data may be used for GAIN and BUF.

AD5347

X

AD5348

X = UNUSED BIT

Figure 40. AD5347/AD5348 Data Format for Word Load with

GAIN and BUF Data on 16-Bit Bus

DB0DB1DB2DB3DB4DB5DB6DB7DB8DB9GAINXX BUFX

DB0DB1DB2DB3DB4DB5DB6DB7DB8DB9GAINXX BUF DB11 DB10

03331-0-048

Table 8. AD5346/AD5347/AD5348 Truth Table

CLR

LDAC CS

WR

RD

A2 A1 A0 Function

1 1 1 X X X X X No Data Transfer
1 1 X 1 1 X X X No Data Transfer
0 X X X X X X X Clear All Registers
1 1 0
1 1 0
1 1 0
1 1 0
1 1 0
1 1 0
1 1 0
1 1 0

0→1
0→1
0→1
0→1
0→1
0→1
0→1

0→1
1 X 0 1
1 X 0 1
1 X 0 1
1 X 0 1
1 X 0 1
1 X 0 1
1 X 0 1
1 X 0 1

1 0 0 0 Load DAC A Input Register
1 0 0 1 Load DAC B Input Register
1 0 1 0 Load DAC C Input Register
1 0 1 1 Load DAC D Input Register
1 1 0 0 Load DAC E Input Register
1 1 0 1 Load DAC F Input Register
1 1 1 0 Load DAC G Input Register
1 1 1 1 Load DAC H Input Register
1→0
1→0
1→0
1→0
1→0
1→0

1→0

1→0

0 0 0 Read Back DAC Register A
0 0 1 Read Back DAC Register B
0 1 0 Read Back DAC Register C
0 1 1 Read Back DAC Register D
1 0 0 Read Back DAC Register E
1 0 1 Read Back DAC Register F
1 1 0 Read Back DAC Register G

1 1 1 Read Back DAC Register H
1 0 X X 1 X X X Update DAC Registers
X X 0 0 0 X X X Invalid Operation
X = Don’t Care

Rev. 0 | Page 18 of 24

AD5346/AD5347/AD5348

APPLICATIONS INFORMATION

TYPICAL APPLICATION CIRCUITS

The AD5346/AD5347/AD5348 can be used with a wide range
of reference voltages, especially if the reference inputs are
configured as unbuffered, in which case the devices offer full,
one-quadrant multiplying capability over a reference range of

0.25 V to V

. More typically, these devices may be used with a

DD

fixed, precision reference voltage. Figure 41 shows a typical
setup for the devices when using an external reference
connected to the reference inputs. Suitable references for 5 V
operation are the AD780, ADR381, and REF192 (2.5 V refer­ences). For 2.5 V operation, suitable external references are the
AD589 and the AD1580 (1.2 V band gap references).

V

= 2.5V to 5.5V

DD

0.1µF

V

IN

EXT

V

V

DD

GND

DD

= 2.5V

OUT

= 5V

REF

AND V

REF

AD780/ADR381/REF192

WITH V

OR AD589/AD1580 WITH

*ONLY ONE CHANNEL OF V

Figure 41. AD5346/AD5347/AD5348 Using an External Reference

10µF

*

V

REF

AD5346/AD5347/

AD5348

SHOWN

OUT

V

DD

GND

V

*

OUT

03331-0-024

DRIVING VDD FROM THE REFERENCE VOLTAGE

If an output range of 0 V to VDD is required, the simplest
solution is to connect the reference inputs to V
supply may not be very accurate and may be noisy, the devices
can be powered from the reference voltage, for example, by
using a 5 V reference such as the ADM663 or ADM666, as
shown in Figure 42.

6V TO 16V

. Be cause this

DD

BIPOLAR OPERATION USING THE AD5346/AD5347/AD5348

The AD5346/AD5347/AD5348 have been designed for single­supply operation, but a bipolar output range is also possible by
using the circuit shown in Figure 43. This circuit has an output
voltage range of ±5 V. Rail-to-rail operation at the amplifier
output is achievable using an AD820, an AD8519, or an OP196
as the output amplifier.

5V

0.1µF 10µF

V

IN

EXT

V

GND

OUT

0.1µF

REF

*ONLY ONE CHANNEL OF V

V

*

REF

AD5346/AD5347/

AD5348

AND V

REF

V

DD

GND

OUT

R3

10kΩ

V

*

OUT

SHOWN

Figure 43. Bipolar Operation with the AD5346/ AD5347/AD5348

The output voltage for any input code can be calculated as
follows:

V

= [(1 + R4/R3) × (R2/(R1 + R2) × (2 × V

OUT

R4 × V

REF

/R3

where:

D is the decimal equivalent of the code loaded to the DAC.
N is the DAC resolution.
V

is the reference voltage input.

REF

with:

R1

10kΩ

R4

20kΩ

R2
20kΩ

+5V

–5V

REF

±5V

AD820/AD8519/

OP196

03331-0-026

× D/2N)] –

0.1µF

V

IN

ADM663/ADM666

SENSE

EXT
REF

V

OUT(2)

GND

GND

SHDNVSET

*ONLY ONE CHANNEL OF V

Figure 42. Using an ADM663/ADM666 as Power and

Reference to the AD5346/AD5347/AD5348

REF

10µF

0.1µF

AND V

V

DD

*

V

REF

V

AD5346/AD5347/

AD5348

GND

SHOWN

OUT

OUT

*

03331-0-025

V

REF

R1 = R3 = 10 kΩ
R2 = R4 = 20 kΩ
V

DD

GAIN = 2

Rev. 0 | Page 19 of 24

= 5 V

= 5 V

V

= (10 × D/2N) – 5

OUT

AD5346/AD5347/AD5348

A

V

DECODING MULTIPLE AD5346/AD5347/AD5348s

The CS pin on these devices can be used in applications to
decode a number of DACs. In this application, all DACs in the

WR

system receive the same data and

pulses, but only the CS to

one of the DACs will be active at any one time, so data will only

CS

be written to the DAC whose

is low.

The 74HC139 is used as a 2-line to 4-line decoder to address
any of the DACs in the system. To prevent timing errors from
occurring, the enable input should be brought to its inactive
state while the coded address inputs are changing state.
Figure 44 shows a diagram of a typical setup for decoding
multiple devices in a system. Once data has been written
sequentially to all DACs in a system, all the DACs can be
updated simultaneously using a common

CLR

mon

line can also be used to reset all DAC outputs to 0 V.

A0
A1
A2

WR

LDAC

CLR

V

DD

V

CC

ENABLE

CODED

DDRESS

1G

1A

1B

Figure 44. Decoding Multiple DAC Devices

74HC139

DGND

1Y0

1Y1

1Y2

1Y3

LDAC

line. A com-

AD5346/AD5347

A0

/AD5348

A1
A2
WR

DATA
INPUTS

LDAC
CLR
CS

AD5346/AD5347

/AD5348

A0
A1
A2
WR

DATA

LDAC

INPUTS
CLR
CS

AD5346/AD5347

/AD5348

A0
A1
A2
WR

DATA
INPUTS

LDAC
CLR
CS

AD5346/AD5347

/AD5348

A0
A1
A2
WR

DATA
INPUTS

LDAC
CLR
CS

DATA BUS

03331-0-027

AD5346/AD5347/AD5348 AS DIGITALLY
PROGRAMMABLE WINDOW DETECTORS

A digitally programmable upper/lower limit detector using two
of the DACs in the AD5346/AD5347/AD5348 is shown in
Figure 45. Any pair of DACs in the device may be used, but for
simplicity the description refers to DACs A and B.

The upper and lower limits for the test are loaded to DACs A
and B which, in turn, set the limits on the CMP04. If a signal at
the V

input is not within the programmed window, an LED

IN

indicates the fail condition.

5V

REF

10µF

0.1µF

AB

V

REF

AD5346/AD5347/

AD5348

GND

V

IN

V

DD

A

V

OUT

CMP04

V

B

OUT

1kΩ 1kΩ
FAIL PASS

1/2

1/6 74HC05

Figure 45. Programmable Window Detector

PASS/
FAIL

03331-0-028

PROGRAMMABLE CURRENT SOURCE

Figure 46 shows the AD5346/AD5347/AD5348 used as the
control element of a programmable current source. In this
example, the full-scale current is set to 1 mA. The output
voltage from the DAC is applied across the current setting
resistor of 4.7 kΩ in series with the 470 Ω adjustment
potentiometer, which gives an adjustment of about ±5%.
Suitable transistors to place in the feedback loop of the ampli­fier include the BC107 and the 2N3904, which enable the
current source to operate from a minimum V
operating range is determined by the operating characteristics
of the transistor. Suitable amplifiers include the AD820 and the
OP295, both having rail-to-rail operation on their outputs. The
current for any digital input code and resistor value can be
calculated as follows:

REF

D

mA

N

R

)2( ×

VGI

×=

where:

G is the gain of the buffer amplifier (1 or 2).
D is the digital input code.
N is the DAC resolution (8, 10, or 12 bits).
R is the sum of the resistor plus adjustment potentiometer in kΩ.

VDD = 5V

0.1µF

V

IN

EXT

V

GND

OUT

0.1µF

REF

*ONLY ONE CHANNEL OF V

Figure 46. Programmable Current Source

10µF

V

V

*V

REF

AD5346/AD5347/

AD5348

GND

AND V

REF

OUT

DD

SHOWN

OUT

*

SOURCE

5V

of 6 V. The

V

SOURCE

LOAD

4.7kΩ

470Ω

03331-0-029

Rev. 0 | Page 20 of 24

AD5346/AD5347/AD5348

COARSE AND FINE ADJUSTMENT USING THE AD5346/AD5347/AD5348

Two of the DACs in the AD5346/AD5347/AD5348 can be
paired together to form a coarse and fine adjustment function,
as shown in Figure 47. As with the window comparator
previously described, the description refers to DACs A and B.

DAC A provides the coarse adjustment, while DAC B provides
the fine adjustment. Varying the ratio of R1 and R2 changes the
relative effect of the coarse and fine adjustments. With the
resistor values shown, the output amplifier has unity gain for
the DAC A output, so the output range is 0 V to (V
For DAC B, the amplifier has a gain of 7.6 × 10
a range equal to 2 LSBs of DAC A.

The circuit is shown with a 2.5 V reference, but reference
voltages up to V

may be used. The op amps indicated allow a

DD

rail-to-rail output swing.

V

= 5V

V

IN

EXT

V

OUT

REF

GND

AD780/ADR381/REF192

WITH V

= 5V

DD

DD

0.1µF

0.1µF

Figure 47. Coarse and Fine Adjus tment

10µF

V

V

AB

REF

AD5346/AD5347/

AD5348

GND

R4

390Ω

DD

A

V

OUT

R1

390Ω

R2

51.2kΩ

V

B

OUT

– 1 LSB).

REF

–3

, giving DAC B

R3

51.2kΩ

5V

03331-0-030

V

OUT

POWER SUPPLY BYPASSING AND GROUNDING

In any circuit where accuracy is important, careful consideration
of the power supply and ground return layout helps to ensure
the rated performance.

The printed circuit board on which the AD5346/AD5347/
AD5348 is mounted should be designed so that the analog and
digital sections are separated and are confined to certain areas
of the board. This facilitates the use of ground planes that can
be separated easily. A minimum etch technique is generally best
for ground planes because it gives the best shielding. Digital and
analog ground planes should be joined in one place only. If the
AD5346/AD5347/AD5348 is the only device requiring an
AGND-to-DGND connection, then the ground planes should
be connected at the AGND and DGND pins of the AD5346/
AD5347/AD5348. If the AD5346/AD5347/AD5348 is in a
system where multiple devices require AGND-to-DGND
connections, the connection should be made at one point only, a
star ground point that should be established as close as possible
to the AD5346/AD5347/AD5348.

The AD5346/AD5347/AD5348 should have ample supply
bypassing of 10 µF in parallel with 0.1 µF on the supply located
as close to the package as possible, ideally right up against the
device. The 10 µF capacitors are the tantalum bead type. The

0.1 µF capacitor should have low effective series resistance
(ESR) and effective series inductance (ESI), such as the
common ceramic types that provide a low impedance path to
ground at high frequencies to handle transient currents due to
internal logic switching.

The power supply lines of the device should use the largest trace
possible to provide low impedance paths and to reduce the
effects of glitches on the power supply line. Fast switching
signals such as clocks should be shielded with digital ground to
avoid radiating noise to other parts of the board, and should
never be run near the reference inputs. Avoid crossover of
digital and analog signals. Traces on opposite sides of the board
should run at right angles to each other to reduce the effects of
feedthrough through the board. A microstrip technique is by far
the best, but not always possible with a double-sided board. In
this technique, the component side of the board is dedicated to
ground plane, while signal traces are placed on the solder side.

Rev. 0 | Page 21 of 24

AD5346/AD5347/AD5348

Table 9. Overview of AD53xx Parallel Devices

Additional Pin Functions
Part No. Resolution DNL V

SINGLES

AD5330 8 ±0.25 1 6 µs
AD5331 10 ±0.5 1 7 µs
AD5340 12 ±1.0 1 8 µs
AD5341 12 ±1.0 1 8 µs

DUALS

AD5332 8 ±0.25 2 6 µs
AD5333 10 ±0.5 2 7 µs
AD5342 12 ±1.0 2 8 µs
AD5343 12 ±1.0 1 8 µs

QUADS

AD5334 8 ±0.25 2 6 µs
AD5335 10 ±0.5 2 7 µs
AD5336 10 ±0.5 4 7 µs

Pins Settling Time BUF GAIN HBEN CLR Package Pins

REF

9 9

9

9 9

9
9
9

9 9 9 9

9
9 9
9 9

9

9

9 9

9

9

9 9

9

9

TSSOP 20
TSSOP 20
TSSOP 24
TSSOP 20

TSSOP 20
TSSOP 24
TSSOP 28
TSSOP 20

TSSOP 24
TSSOP 24
TSSOP 28

AD5344 12 ±1.0 4 8 µs TSSOP 28

OCTALS

AD5346 8 ±0.25 4 6 µs
AD5347 10 ±0.5 4 7 µs
AD4348 12 ±1.0 4 8 µs

9 9
9 9
9 9

9

9

9

TSSOP, LFCSP 38, 40
TSSOP, LFCSP 38, 40
TSSOP, LFCSP 38, 40

Table 10. Overview of AD53xx Serial Devices

Part No. Resolution DNL V
SINGLES

AD5300 8 ±0.25 0 (V
AD5310 10 ±0.5 0 (V
AD5320 12 ±1.0 0 (V
AD5301 8 ±0.25 0 (V
AD5311 10 ±0.5 0 (V
AD5321 12 ±1.0 0 (V

DUALS

Pins Settling Time Interface Package Pins

REF

= VDD) 4 µs SPI® SOT-23, MSOP 6, 8

REF

= VDD) 6 µs SPI SOT-23, MSOP 6, 8

REF

= VDD) 8 µs SPI SOT-23, MSOP 6, 8

REF

= VDD) 6 µs 2-Wire SOT-23, MSOP 6, 8

REF

= VDD) 7 µs 2-Wire SOT-23, MSOP 6, 8

REF

= VDD) 8 µs 2-Wire SOT-23, MSOP 6, 8

REF

AD5302 8 ±0.25 2 6 µs SPI MSOP 8
AD5312 10 ±0.5 2 7 µs SPI MSOP 8
AD5322 12 ±1.0 2 8 µs SPI MSOP 8
AD5303 8 ±0.25 2 6 µs SPI TSSOP 16
AD5313 10 ±0.5 2 7 µs SPI TSSOP 16
AD5323 12 ±1.0 2 8 µs SPI TSSOP 16

QUADS

AD5304 8 ±0.25 1 6 µs SPI MSOP 10
AD5314 10 ±0.5 1 7 µs SPI MSOP 10
AD5324 12 ±1.0 1 8 µs SPI MSOP 10
AD5305 8 ±0.25 1 6 µs 2-Wire MSOP 10
AD5315 10 ±0.5 1 7 µs 2-Wire MSOP 10
AD5325 12 ±1.0 1 8 µs 2-Wire MSOP 10
AD5306 8 ±0.25 4 6 µs 2-Wire TSSOP 16
AD5316 10 ±0.5 4 7 µs 2-Wire TSSOP 16
AD5326 12 ±1.0 4 8 µs 2-Wire TSSOP 16
AD5307 8 ±0.25 2 6 µs SPI TSSOP 16
AD5317 10 ±0.5 2 7 µs SPI TSSOP 16
AD5327 12 ±1.0 2 8 µs SPI TSSOP 16

OCTALS

AD5308 8 ±0.25 2 6 µs SPI TSSOP 16
AD5318 10 ±0.5 2 7 µs SPI TSSOP 16
AD5328 12 ±1.0 2 8 µs SPI TSSOP 16

Rev. 0 | Page 22 of 24

AD5346/AD5347/AD5348

R

OUTLINE DIMENSIONS

9.80

9.70

9.60

PIN 1

INDICATO

1.00

0.85

0.80

PIN 1

0.15

0.05

COPLANARITY

12° MAX

SEATING
PLANE

38

0.50

0.10

BSC

COMPLIANT TO JEDEC STANDARDS MO-153BD-1

0.27

0.17

20

191

SEATING
PLANE

1.20

MAX

4.50

4.40

4.30

0.20

0.09

6.40 BSC

8°
0°

Figure 48. 38-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-38)

Dimensions shown in millimeters

6.00

BSC SQ

TOP

VIEW

0.80 MAX

0.65 TYP

0.30

0.23

0.18

COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-2

5.75

BSC SQ

0.20 REF

0.05 MAX

0.02 NOM

0.60 MAX

0.50

BSC

0.50

0.40

0.30

COPLANARITY

0.08

0.60 MAX

31

30

21

20

BOTTOM

VIEW

4.50
REF

Figure 49. 40-Lead Lead Frame Chip Scale Package [LFCSP]

(CP-40)

Dimensions shown in millimeters

0.70

0.60

0.45

PIN 1

40

11

INDICATOR

1

4.25

4.10 SQ

3.95

10

0.25MIN

Rev. 0 | Page 23 of 24

AD5346/AD5347/AD5348

ORDERING GUIDES

Table 11. AD5346 Ordering Guide

Model Temperature Range Package Description Package Option

AD5346BRU –40°C to +105°C TSSOP (Thin Shrink Small Outline Package) RU-38
AD5346BRU-REEL –40°C to +105°C TSSOP (Thin Shrink Small Outline Package) RU-38
AD5346BRU-REEL7 –40°C to +105°C TSSOP (Thin Shrink Small Outline Package) RU-38
AD5346BCP –40°C to +105°C LFCSP (Lead Frame Chip Scale Package) CP-40
AD5346BCP-REEL –40°C to +105°C LFCSP (Lead Frame Chip Scale Package) CP-40
AD5346BCP-REEL7 –40°C to +105°C LFCSP (Lead Frame Chip Scale Package) CP-40

Table 12. AD5347 Ordering Guide

Model Temperature Range Package Description Package Option

AD5347BRU –40°C to +105°C TSSOP (Thin Shrink Small Outline Package) RU-38
AD5347BRU-REEL –40°C to +105°C TSSOP (Thin Shrink Small Outline Package) RU-38
AD5347BRU-REEL7 –40°C to +105°C TSSOP (Thin Shrink Small Outline Package) RU-38
AD5347BCP –40°C to +105°C LFCSP (Lead Frame Chip Scale Package) CP-40
AD5347BCP-REEL –40°C to +105°C LFCSP (Lead Frame Chip Scale Package) CP-40
AD5347BCP-REEL7 –40°C to +105°C LFCSP (Lead Frame Chip Scale Package) CP-40

Table 13. AD5348 Ordering Guide

Model Temperature Range Package Description Package Option

AD5348BRU –40°C to +105°C TSSOP (Thin Shrink Small Outline Package) RU-38
AD5348BRU-REEL –40°C to +105°C TSSOP (Thin Shrink Small Outline Package) RU-38
AD5348BRU-REEL7 –40°C to +105°C TSSOP (Thin Shrink Small Outline Package) RU-38
AD5348BCP –40°C to +105°C LFCSP (Lead Frame Chip Scale Package) CP-40
AD5348BCP-REEL –40°C to +105°C LFCSP (Lead Frame Chip Scale Package) CP-40
AD5348BCP-REEL7 –40°C to +105°C LFCSP (Lead Frame Chip Scale Package) CP-40

© 2003 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.

C03331–0–11/03(0)

Rev. 0 | Page 24 of 24