Datasheet AD5330, AD5331, AD5340, AD5341 Datasheet (ANALOG DEVICES)

2.5 V to 5.5 V, 115 μA, Parallel Interface

V

Single Voltage-Output 8-/10-/12-Bit DACs

FEATURES

AD5330: single 8-bit DAC in 20-lead TSSOP AD5331: single 10-bit DAC in 20-lead TSSOP AD5340: single 12-bit DAC in 24-lead TSSOP AD5341: single 12-bit DAC in 20-lead TSSOP Low power operation: 115 μA @ 3 V, 140 μA @ 5 V

REF

PD

LDAC

FUNCTIONAL BLOCK DIAGRAM

POWER-ON

RESET

Power-down to 80 nA @ 3 V, 200 nA @ 5 V via

2.5 V to 5.5 V power supply Double-buffered input logic Guaranteed monotonic by design over all codes Buffered/unbuffered reference input options Output range: 0 V to V

or 0 V to 2 × V

REF

Power-on reset to 0 V Simultaneous update of DAC outputs via Asynchronous

CLR

facility Low power parallel data interface On-chip rail-to-rail output buffer amplifiers Temperature range: −40°C to +105°C

APPLICATIONS

Portable battery-powered instruments Digital gain and offset adjustment Programmable voltage and current sources Programmable attenuators Industrial process control

AD5330/AD5331/AD5340/AD5341

GENERAL DESCRIPTION

The AD5330/AD5331/AD5340/AD53411 are single 8-/10-/12bit DACs. They operate from a 2.5 V to 5.5 V supply consuming just 115 μA at 3 V and feature a power-down mode that further reduces the current to 80 nA. The devices incorporate an on-chip output buffer that can drive the output to both supply rails, but the AD5330, AD5340, and AD5341 allow a choice of buffered or unbuffered reference input.

The AD5330/AD5331/AD5340/AD5341 have a parallel interface. input registers on the rising edge of

The GAIN pin allows the output range to be set at 0 V to V 0 V to 2 × V

Input data to the DACs is double-buffered, allowing simultaneous update of multiple DACs in a system using the

An asynchronous contents of the input register and the DAC register to all zeros. These devices also incorporate a power-on reset circuit that ensures that the DAC output powers on to 0 V and remains there until valid data is written to the device.

The AD5330/AD5331/AD5340/AD5341 are available in thin shrink small outline packages (TSSOP).

1

Protected by U.S. Patent Number 5,969,657.

REF

3 12

CS

selects the device and data is loaded into the

WR

.

REF

CLR

input is also provided, which resets the

DD

AD5330

LDAC

REF

pin.

or

1

BUF

GAIN

8

DB

20

7

.

13

DB

0

6

CS

7

WR

9

CLR

10

LDAC

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

INPUT

REGISTER

RESET

INTERFACE LOGIC

DAC

REGISTER

Figure 1. AD5330

8-BIT

DAC

BUFFER

POWER-DOWN

LOGIC

11 5

PD GND

4

V

OUT

6852-001

AD5330/AD5331/AD5340/AD5341

REVISION HISTORY

2/08—Rev. 0 to Rev. A

Updated Format .................................................................. Universal

Changes to Table 4 .......................................................................... 16

Replaced Driving V

Updated Outline Dimensions ....................................................... 24

Changes to Ordering Guide .......................................................... 25

4/00—Revision 0: Initial Version

from the Reference Voltage Section ..... 21

DD

Rev. A | Page 2 of 28

AD5330/AD5331/AD5340/AD5341

SPECIFICATIONS

VDD = 2.5 V to 5.5 V, V

Table 1.

Parameter

1

DC PERFORMANCE

AD5330

Resolution 8 Bits Relative Accuracy ±0.15 ±1 LSB Differential Nonlinearity ±0.02 ±0.25 LSB Guaranteed monotonic by design over all codes

AD5331

Resolution 10 Bits Relative Accuracy ±0.5 ±4 LSB Differential Nonlinearity ±0.05 ±0.5 LSB Guaranteed monotonic by design over all codes

AD5340/AD5341

Resolution 12 Bits Relative Accuracy ±2 ±16 LSBs

Differential Nonlinearity ±0.2 ±1 LSB Guaranteed monotonic by design over all codes Offset Error ±0.4 ±3 % of FSR Gain Error ±0.15 ±1 % of FSR Lower Deadband Upper Deadband 10 60 mV VDD = 5 V; upper deadband exists only if V Offset Error Drift Gain Error Drift

6

DC Power Supply Rejection Ratio6 −60 dB ΔVDD = ±10%

DAC REFERENCE INPUT

V

Input Range 1 VDD V Buffered reference (AD5330, AD5340, and AD5341)

REF

0.25 VDD V Unbuffered reference V

Input Impedance >10 MΩ Buffered reference (AD5330, AD5340, and AD5341)

REF

180 kΩ Unbuffered reference; gain = 1, input impedance = R 90 kΩ Unbuffered reference; gain = 2, input impedance = R Reference Feedthrough −90 dB Frequency = 10 kHz

OUTPUT CHARACTERISTICS

Minimum Output Voltage Maximum Output Voltage DC Output Impedance 0.5 Ω Short-Circuit Current 25 mA VDD = 5 V 15 mA VDD = 3 V Power-Up Time 2.5 μs Coming out of power-down mode; VDD = 5 V 5 μs Coming out of power-down mode; VDD = 3 V

LOGIC INPUTS

6

Input Current ±1 μA Input Low Voltage, VIL 0.8 V VDD = 5 V ± 10%

0.6 V VDD = 3 V ± 10%

0.5 V VDD = 2.5 V Input High Voltage, VIH 2.4 V VDD = 5 V ± 10%

2.1 V VDD = 3 V ± 10%

2.0 V VDD = 2.5 V Pin Capacitance 3 pF

= 2 V, RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications T

REF

B Version

2

Unit Conditions/Comments Min Typ Max

3, 4

5

6

−5 ppm of FSR/°C

6

4, 7

10 60 mV Lower deadband exists only if offset error is negative

−12 ppm of FSR/°C

0.001 V min Rail-to-rail operation V

− 0.001 V max

DD

MIN

to T

, unless otherwise noted.

MAX

REF

= VDD

DAC

Rev. A | Page 3 of 28

AD5330/AD5331/AD5340/AD5341

2

Unit Conditions/Comments Min Typ Max

Parameter

1

B Version

POWER REQUIREMENTS

VDD 2.5 5.5 V IDD (Normal Mode) DACs active and excluding load currents. Unbuffered

VDD = 4.5 V to 5.5 V 140 250 μA Reference, VIH = VDD, VIL = GND VDD = 2.5 V to 3.6 V 115 200 μA IDD increases by 50 μA at V

In buffered mode, extra current is (5 + V where R

is the resistance of the resistor string.

DAC

> VDD − 100 mV.

REF

REF/RDAC

) μA,

IDD (Power-Down Mode)

VDD = 4.5 V to 5.5 V 0.2 1 μA VDD = 2.5 V to 3.6 V 0.08 1 μA

1

See the Terminology section.

2

Temperature range: B Version: −40°C to +105°C; typical specifications are at 25°C.

3

Linearity is tested using a reduced code range: AD5330 (Code 8 to Code 255); AD5331 (Code 28 to Code 1023); AD5340/AD5341 (Code 115 to Code 4095).

4

DC specifications tested with output unloaded.

5

This corresponds to x codes. x = deadband voltage/LSB size.

6

Guaranteed by design and characterization, not production tested.

7

For the amplifier output to reach its minimum voltage, offset error must be negative. For the amplifier output to reach its maximum voltage, V

gain error must be positive.

= VDD and offset plus

REF

AC CHARACTERISTICS1

VDD = 2.5 V to 5.5 V. RL = 2 kΩ to GND, CL = 200 pF to GND; all specifications T

Table 2.

Parameter

2

Output Voltage Settling Time V

B Version

3

Unit Conditions/Comments Min Typ Max

REF

AD5330 6 8 μs ¼ scale to ¾ scale change (0x40 to 0xC0) AD5331 7 9 μs ¼ scale to ¾ scale change (0x100 to 0x300) AD5340 8 10 μs ¼ scale to ¾ scale change (0x400 to 0xC00)

AD5341 8 10 μs ¼ scale to ¾ scale change (0x400 to 0xC00) Slew Rate 0.7 V/μs Major Code Transition Glitch Energy 6 nV/s 1 LSB change around major carry Digital Feedthrough 0.5 nV/s Multiplying Bandwidth 200 kHz V Total Harmonic Distortion −70 dB V

1

Guaranteed by design and characterization, not production tested.

2

See the Terminology section.

3

Temperature range: B Version: −40°C to +105°C; typical specifications are at 25°C.

REF

MIN

to T

, unless otherwise noted.

MAX

= 2 V; see Figure 29

= 2 V ± 0.1 V p-p; unbuffered mode = 2.5 V ± 0.1 V p-p; frequency = 10 kHz

Rev. A | Page 4 of 28

AD5330/AD5331/AD5340/AD5341

TIMING CHARACTERISTICS

VDD = 2.5 V to 5.5 V, all specifications T

1, 2, 3

MIN

to T

, unless otherwise noted.

MAX

Table 3.

Parameter Limit at T

t1 0 ns min

t2 0 ns min t3 20 ns min

MIN

, T

Unit Condition/Comments

MAX

to WR setup time.

CS

to WR hold time.

CS

pulse width.

WR t4 5 ns min Data, GAIN, BUF, HBEN setup time. t5 4.5 ns min Data, GAIN, BUF, HBEN hold time. t6 5 ns min t7 5 ns min t8 4.5 ns min t9 5 ns min t10 4.5 ns min t11 20 ns min t12 20 ns min t13 50 ns min

1

Guaranteed by design and characterization, not production tested.

2

All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.

3

See Figure 2.

Synchronous mode; WR

Synchronous mode; LDAC

Synchronous mode; WR

Asynchronous mode; LDAC

Asynchronous mode; WR

pulse width.

LDAC

pulse width.

CLR

Time between WR

t

CS

WR

DATA,

GAIN,

BUF,

HBEN

1

LDAC

2

LDAC

CLR

NOTES:

1

SYNCHRONOUS LDAC UPDAT E MODE

2

ASYNCHRONOUS LDAC UPDAT E MODE

1

t

6

t

3

t

2

t

13

t

5

t

4

t

8

t

7

t

9

10

t

11

Figure 2. Parallel Interface Timing Diagram

falling to LDAC falling.

falling to WR rising.

rising to LDAC rising.

rising to WR rising.

rising to LDAC falling.

cycles.

t

12

06852-002

Rev. A | Page 5 of 28

AD5330/AD5331/AD5340/AD5341

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 4.

Parameter Rating

VDD to GND −0.3 V to +7 V Digital Input Voltage to GND −0.3 V to VDD + 0.3 V Digital Output Voltage to GND −0.3 V to VDD + 0.3 V Reference Input Voltage to GND −0.3 V to VDD + 0.3 V V

to GND −0.3 V to VDD + 0.3 V

OUT

Operating Temperature Range

Industrial (B Version) −40°C to +105°C Storage Temperature Range −65°C to +150°C Junction Temperature 150°C TSSOP Package

Power Dissipation (TJ max – TA)/θJA mW

θJA Thermal Impedance (20-Lead TSSOP)1 85°C/W

θJA Thermal Impedance (24-Lead TSSOP)1 80°C/W Reflow Soldering

Peak Temperature 260°C

Time at Peak Temperature 20 sec to 40 sec

1

Thermal resistance (JEDEC 4-layer (2S2P) board).

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

Rev. A | Page 6 of 28

AD5330/AD5331/AD5340/AD5341

V

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

REF

3 12

POWER-ON

RESET

1

BUF

GAIN

DB

CS

WR

CLR

LDAC

INTERFACE LO GIC

REGISTER

RESET

INPUT

8

20

7

. .

13

0

6

7

9

10

DAC

REGISTER

8-BIT

DAC

Figure 3. AD5330 Functional Block Diagram Figure 4. AD5330 Pin Configuration

Table 5. AD5330 Pin Function Descriptions

Pin No. Mnemonic Description

1 BUF Buffer Control Pin. This pin controls whether the reference input to the DAC is buffered or unbuffered. 2 NC No Connect. 3 V 4 V

Reference Input.

REF

Output of DAC. Buffered output with rail-to-rail operation.

OUT

5 GND Ground reference point for all circuitry on the part. 6 7

Active Low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface.

CS

Active Low Write Input. This is used in conjunction with CS to write data to the parallel interface.

WR 8 GAIN Gain Control Pin. This controls whether the output range from the DAC is 0 V to V 9 10 11

CLR

LDAC

PD 12 VDD

Asynchronous active low control input that clears all input registers and DAC registers to zero. Active low control input that updates the DAC registers with the contents of the input registers. Power-Down Pin. This active low control pin puts the DAC into power-down mode. Power Supply Input. These parts can operate from 2.5 V to 5.5 V and the supply should be decoupled with a

10 μF capacitor in parallel with a 0.1 μF capacitor to GND.

13 to 20 DB0 to DB7 Eight Parallel Data Inputs. DB7 is the MSB of these eight bits.

AD5330

BUFFER

DD

POWER-DOW N

LOGIC

11 5

PD GND

REF

20

DB

7

19

DB

6

18

DB

5

17

DB

4

16

DB

3

15

DB

2

14

DB

1

13

DB

0

12

V

DD

11

PD

06852-004

.

1

BUF

2

4

V

OUT

06852-003

NC

V

3

REF

V

4

OUT

5

GND

6

CS

7

WR

8

GAIN

9

CLR

10

LDAC

NC = NO CONNECT

or 0 V to 2 × V

REF

8-BIT

AD5330

TOP VIEW

(Not to Scale)

Rev. A | Page 7 of 28

AD5330/AD5331/AD5340/AD5341

V

DB

GAIN

DB

CS

WR

CLR

LDAC

REF

3 12

POWER-ON

RESET

1

8

2

9

8

20

7

. .

13

0

6

7

9

10

INTERFACE LOGIC

REGISTER

RESET

INPUT

DAC

REGISTER

10-BIT

DAC

BUFFER

DD

AD5331

POWER-DOW N

LOGIC

11 5

PD GND

4

V

OUT

06852-005

Figure 5. AD5331 Functional Block Diagram Figure 6. AD5331 Pin Configuration

Table 6. AD5331 Pin Function Descriptions

Pin No. Mnemonic Description

1 DB8 Parallel Data Input. 2 DB9 Most Significant Bit of Parallel Data Input. 3 V

4 V

Unbuffered Reference Input.

REF

Output of DAC. Buffered output with rail-to-rail operation.

OUT

5 GND Ground reference point for all circuitry on the part. 6 7

Active Low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface.

CS

Active Low Write Input. This is used in conjunction with CS to write data to the parallel interface.

WR 8 GAIN Gain Control Pin. This controls whether the output range from the DAC is 0 V to V 9 10 11

CLR

LDAC

PD 12 VDD

Active low control input that clears all input registers and DAC registers to zero. Active low control input that updates the DAC registers with the contents of the input registers. Power-Down Pin. This active low control pin puts the DAC into power-down mode. Power Supply Input. These parts can operate from 2.5 V to 5.5 V and the supply should be decoupled with a

10 μF capacitor in parallel with a 0.1 μF capacitor to GND.

13 to 20 DB0 to DB7 Eight Parallel Data Inputs.

1

DB

8

2

DB

9

V

3

REF

V

4

OUT

5

GND

6

CS

7

WR

8

GAIN

9

CLR

10

LDAC

or 0 V to 2 × V

REF

10-BIT

AD5331

TOP VIEW

(Not to Scale)

REF

20

DB

7

19

DB

6

18

DB

5

17

DB

4

16

DB

3

15

DB

2

14

DB

1

13

DB

0

12

V

DD

11

PD

06852-006

.

Rev. A | Page 8 of 28

AD5330/AD5331/AD5340/AD5341

V

REF

4 14

POWER-ON

INTERFACE LOGIC

REGISTER

RESET

INPUT

DAC

REGISTER

12-BIT

DAC

DB

BUF

GAIN

DB

CS

WR

CLR

LDAC

1

10

2

11

3

10

24

9

. .

15

0

8

9

11

12

Figure 7. AD5340 Functional Block Diagram Figure 8. AD5340 Pin Configuration

Table 7. AD5340 Pin Function Descriptions

Pin No. Mnemonic Description

1 DB10 Parallel Data Input. 2 DB11 Most Significant Bit of Parallel Data Input. 3 BUF Buffer Control Pin. This pin controls whether the reference input to the DAC is buffered or unbuffered. 4 V 5 V

Reference Input.

REF

Output of DAC. Buffered output with rail-to-rail operation.

OUT

6 NC No Connect. 7 GND Ground reference point for all circuitry on the part.

8 9

Active Low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface.

CS

Active Low Write Input. This is used in conjunction with CS to write data to the parallel interface.

WR 10 GAIN Gain Control Pin. This controls whether the output range from the DAC is 0 V to V 11 12 13

CLR

LDAC

PD 14 VDD

Asynchronous active low control input that clears all input registers and DAC registers to zero. Active low control input that updates the DAC registers with the contents of the input registers. Power-Down Pin. This active low control pin puts the DAC into power-down mode. Power Supply Input. These parts can operate from 2.5 V to 5.5 V and the supply should be decoupled with a

10 μF capacitor in parallel with a 0.1 μF capacitor to GND.

15 to 24 DB0 to DB9 Ten Parallel Data Inputs.

AD5340

BUFFER

DD

POWER-DOW N

LOGIC

13 7

PD GND

REF

24

DB

9

23

DB

8

22

DB

7

21

DB

6

20

DB

5

19

DB

4

18

DB

3

17

DB

2

16

DB

1

15

DB

0

14

V

DD

13

PD

06852-008

.

1

DB

10

2

DB

5

V

OUT

06852-007

11

3

BUF

4

V

REF

V

5

OUT

NC

6

7

GND

8

CS

9

WR

10

GAIN

11

CLR

12

LDAC

or 0 V to 2 × V

REF

12-BIT

AD5340

TOP VIEW

(Not to Scale)

Rev. A | Page 9 of 28

AD5330/AD5331/AD5340/AD5341

V

REF

3 12

POWER-ON

RESET

HIGH BYTE

INTERFACE LOGIC

RESET

REGISTER

LOW BYTE REGISTER

DAC

REGISTER

12-BIT

DAC

BUF

GAIN

DB

HBEN

CS

WR

CLR

LDAC

2

8

20

7

. .

13

0

1

6

7

9

10

Figure 9. AD5341 Functional Block Diagram Figure 10. AD5341 Pin Configuration

Table 8. AD5341 Pin Function Descriptions

Pin No. Mnemonic Description

1 HBEN

High Byte Enable Pin. This pin is used when writing to the device to determine if data is written to the high byte register or the low byte register.

2 BUF Buffer Control Pin. This pin controls whether the reference input to the DAC is buffered or unbuffered. 3 V 4 V

Reference Input.

REF

Output of DAC. Buffered output with rail-to-rail operation.

OUT

5 GND Ground reference point for all circuitry on the part. 6

7

Active low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface.

CS

Active Low Write Input. This is used in conjunction with CS to write data to the parallel interface.

WR 8 GAIN Gain Control Pin. This controls whether the output range from the DAC is 0 V to V 9 10 11

CLR

LDAC

PD 12 VDD

Asynchronous active low control input that clears all input registers and DAC registers to zero. Active low control input that updates the DAC registers with the contents of the input registers. Power-Down Pin. This active low control pin puts the DAC into power-down mode. Power Supply Input. These parts can operate from 2.5 V to 5.5 V and the supply should be decoupled with a

10 μF capacitor in parallel with a 0.1 μF capacitor to GND.

13 to 20 DB0 to DB7 Eight Parallel Data Inputs. DB7 is the MSB of these eight bits.

AD5341

BUFFER

DD

POWER-DOW N

LOGIC

11 5

PD GND

1

HBEN

2

4

V

OUT

06852-009

BUF

3

V

REF

V

4

OUT

5

GND

GAIN

CLR

LDAC

REF

(Not to Scale)

6

CS

7

WR

8

9

10

or 0 V to 2 × V

10-BIT

AD5341

TOP VIEW

REF

20

DB

7

19

DB

6

18

DB

5

17

DB

4

16

DB

3

15

DB

2

14

DB

1

13

DB

0

12

V

DD

11

PD

06852-010

.

Rev. A | Page 10 of 28

AD5330/AD5331/AD5340/AD5341

V

TERMINOLOGY

Relative Accuracy or Integral Nonlinearity (INL)

For the DAC, relative accuracy or INL is a measure of the maximum deviation, in LSBs, from a straight line passing through the actual endpoints of the DAC transfer function. Typical INL vs. code plots can be seen in Figure 14, Figure 15, and Figure 16.

Differential Nonlinearity (DNL)

DNL is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ±1 LSB maximum ensures monotonicity. This DAC is guaranteed monotonic by design. Typical DNL vs. code plots can be seen in Figure 17, Figure 18, and Figure 19.

Gain Error

This is a measure of the span error of the DAC (including any error in the gain of the buffer amplifier). It is the deviation in slope of the actual DAC transfer characteristic from the ideal, expressed as a percentage of the full-scale range. This is illustrated in Figure 11.

Offset Error

This is a measure of the offset error of the DAC and the output amplifier. It is expressed as a percentage of the full-scale range. If the offset voltage is positive, the output voltage is still positive at zero input code. This is shown in Figure 12. Because the DACs operate from a single supply, a negative offset cannot appear at the output of the buffer amplifier. Instead, there is a code close to zero at which the amplifier output saturates (amplifier footroom). Below this code, there is a deadband over which the output voltage does not change. This is illustrated in Figure 13.

VOLTAGE

POSITIVE

OFFSET

NEGATIVE

OFFSET

OUTPUT

VOLTAGE

DAC CODE

Figure 12. Positive Offset Error and Gain Error

DAC CODE

GAIN ERRO R AND OFFSET ERROR

ACTUAL

IDEAL

GAIN ERROR AND OFFSET ERROR

ACTUAL

IDEAL

06852-012

OUTPUT OLTAGE

DAC CODE

Figure 11. Gain Error

POSITIVE GAIN ERROR

NEGATIVE GAIN ERROR

ACTUAL

IDEAL

AMPLI FIER

FOOTROOM

NEGATIVE

06852-011

Rev. A | Page 11 of 28

(~1mV)

OFFSET

DEADBAND CODES

Figure 13. Negative Offset Error and Gain Error

6852-013

AD5330/AD5331/AD5340/AD5341

Offset Error Drift

This is a measure of the change in offset error with changes in temperature. It is expressed in (ppm of full-scale range)/°C.

Gain Error Drift

This is a measure of the change in gain error with changes in temperature. It is expressed in (ppm of full-scale range)/°C.

Power-Supply Rejection Ratio (PSRR)

This indicates how the output of the DAC is affected by changes in the supply voltage. PSRR is the ratio of the change in V a change in V in decibels. V

for full-scale output of the DAC. It is measured

DD

is held at 2 V and VDD is varied ±10%.

REF

OUT

to

Reference Feedthrough

This is the ratio of the amplitude of the signal at the DAC output to the reference input when the DAC output is not being updated (that is,

LDAC

is high). It is expressed in decibels.

Major-Code Transition Glitch Energy

Major-code transition glitch energy is the energy of the impulse injected into the analog output when the DAC changes state. It is normally specified as the area of the glitch in nV/s and is measured when the digital code is changed by 1 LSB at the major carry transition (011 … 11 to 100 … 00 or 100 … 00 to 011 … 11).

Digital Feedthrough

Digital Feedthrough is a measure of the impulse injected into the analog output of the DAC from the digital input pins of the device; it is measured when the DAC is not being written to (

CS

held high). It is specified in nV/s and is measured with a fullscale change on the digital input pins, that is, from all 0s to all 1s and vice versa.

Multiplying Bandwidth

The amplifiers within the DAC have a finite bandwidth. The multiplying bandwidth is a measure of this. A sine wave on the reference (with a full-scale code loaded to the DAC) appears on the output. The multiplying bandwidth is the frequency at which the output amplitude falls to 3 dB below the input.

Total Harmonic Distortion (THD)

This is the difference between an ideal sine wave and its attenuated version using the DAC. The sine wave is used as the reference for the DAC and THD is a measure of the harmonics present on the DAC output. It is measured in decibels.

Rev. A | Page 12 of 28

AD5330/AD5331/AD5340/AD5341

TYPICAL PERFORMANCE CHARACTERISTICS

1.0

= 25°C

T

A

= 5V

V

DD

0.5

0

INL ERROR (L SBs)

–0.5

–1.0

0 50 100 150 200 250

CODE

Figure 14. AD5330 Typical INL Plot

3

= 25°C

T

A

V

= 5V

DD

2

1

0

–1

INL ERROR (L SBs)

0.3 T

= 25°C

A

V

= 5V

DD

0.2

0.1

0

–0.1

DNL ERROR (LSBs)

–0.2

–0.3

0 50 100 150 200 250

06852-015

CODE

06852-018

Figure 17. AD5330 Typical DNL Plot

0.6

= 25°C

T

A

V

= 5V

DD

0.4

0.2

0

–0.2

DNL ERROR (LSBs)

–2

–3

0 200 400 500 800 1000

CODE

Figure 15. AD5331 Typical INL Plot

12

TA = 25°C

= 5V

V

DD

8

4

0

–4

INL ERROR (L SBs)

–8

–12

0 1000 2000 3000 4000

CODE

Figure 16. AD5340/AD5341 Typical INL Plot

–0.4

–0.6

0 200 400 600 800 1000

06852-016

CODE

6852-019

Figure 18. AD5331 Typical DNL Plot

1.0

TA = 25°C

= 5V

V

DD

0.5

0

DNL ERROR (LSBs)

–0.5

–1.0

06852-017

0 1000 2000 3000 4000

CODE

06852-020

Figure 19. AD5340/AD5341 Typical DNL Plot

Rev. A | Page 13 of 28

AD5330/AD5331/AD5340/AD5341

1.00

0.75

0.50

TA = 25°C

= 5V

V

DD

0.2

0.1

TA = 25°C

= 2V

V

REF

0

GAIN ERROR

0.25

0

–0.25

ERROR (L SBs)

–0.50

–0.75

–1.00

2345

Figure 20. AD5330 INL and DNL Error vs. V

1.00 VDD = 5V

= 3V

V

REF

0.75

0.50

0.25

0

–0.25

ERROR (LSBs)

–0.50

–0.75

–1.00

–40 0 40 80 120

MAX INL

MAX DNL

MIN DNL

MIN INL

V

(V)

REF

MAX INLMAX DNL

MIN INL

TEMPERATURE (° C)

REF

MIN DNL

Figure 21. AD5330 INL Error and DNL Error vs. Temperature

1.0 VDD = 5V

= 2V

V

REF

0.5

GAIN ERROR

–0.1

–0.2

ERROR (%)

–0.3

–0.4

–0.5

–0.6

0123456

06852-021

VDD (V)

OFFSET ERROR

06852-024

Figure 23. Offset Error and Gain Error vs. VDD

5

4

3

(V)

OUT

V

2

1

0

0123456

06852-022

Figure 24. V

300

TA = 25°C

= 2V

V

REF

250

200

5V SOURCE

3V SOURCE

5V SINK

SINK/SOURCE CURRENT (mA)

Source and Sink Current Capability

OUT

VDD = 5.5V

3V SINK

06852-025

0

ERROR (%)

–0.5

–1.0

–40 0 40 80 120

OFFSET ERROR

TEMPERATURE ( °C)

Figure 22. AD5330 Offset Error and Gain Error vs. Temperature

6852-023

Rev. A | Page 14 of 28

150

(µA)

DD

I

100

50

0

ZERO-SCALE FULL-SCAL E

V

DD

= 3.6V

DAC CODE

Figure 25. Supply Current vs. DAC Code

06852-026

AD5330/AD5331/AD5340/AD5341

2

V

300

= 25°C

T

A

200

(µA)

DD

I

100

0

2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V)

Figure 26. Supply Current vs. Supply Voltage

0.5

= 25°C

T

A

0.4

0.3

(µA)

DD

I

0.2

0.1

CH2

CLK

5V

V

OUT

CH1

1V

06852-027

TIME BASE = 5µs/DIV

Figure 29. Half-Scale Settling (¼ to ¾ Scale Code Change)

TA = 25°C V

= 5V

DD

V

= 2V

REF

CH1

00m

2V

CH2

V

DD

V

A

OUT

TA = 25°C V

= 5V

DD

06852-030

0

2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V)

Figure 27. Power-Down Current vs. Supply Voltage

1800

T

= 25°C

A

1600

1400

1200

1000

(µA)

DD

800

I

600

400

200

0

012345

V

= 5V

DD

VDD = 3V

V

LOGIC

(V)

Figure 28. Supply Current vs. Logic Input Voltage

06852-028

TIME BASE = 200µs/DIV

06852-031

Figure 30. Power-On Reset to 0 V

TA = 25°C

= 5V

V

DD

= 2V

V

REF

CH1

500mV

V

A

OUT

CH2

5V

06852-029

PD

TIME BASE = 1µs/DIV

06852-032

Figure 31. Exiting Power-Down to Midscale

Rev. A | Page 15 of 28

AD5330/AD5331/AD5340/AD5341

10

0

VDD = 3V

FREQUENCY

80 90 100 110 120 130 140 150 160 170 190180 200

Histogram with VDD = 3 V and VDD = 5 V Figure 34. Multiplying Bandwidth (Small-Signal Frequency Response)

DD

VOLTS

Figure 32. I

0.917

0.916

0.915

0.914

0.913

0.912

0.911

0.910

0.909

0.908

0.907

0.906

0.905

0.904

0.903

IDD (µA)

250ns/DIV

VDD = 5V

06852-033

6852-034

–10

–20

(dB)

–30

–40

–50

–60

0.01 0.1 1 10010 10k1k

0.4 TA = 25°C

V

= 5V

DD

0.2

0

FULL-SCAL E ERROR (%FSR)

–0.2

012 435

FREQUENCY (kHz)

V

REF

Figure 33. AD5340 Major-Code Transition Glitch Energy Figure 35. Full-Scale Error vs. V

(V)

06852-035

06852-036

REF

Rev. A | Page 16 of 28

AD5330/AD5331/AD5340/AD5341

V

THEORY OF OPERATION

The AD5330/AD5331/AD5340/AD5341 are single resistorstring DACs fabricated on a CMOS process with resolutions of 8, 10, and 12 bits, respectively. They are written to using a parallel interface. They operate from single supplies of 2.5 V to

5.5 V and the output buffer amplifiers offer rail-to-rail output swing. The AD5330, AD5340, and AD5341 have a reference input that can be buffered to draw virtually no current from the reference source. The reference input of the AD5331 is unbuffered. The devices have a power-down feature that reduces current consumption to only 80 nA @ 3 V.

DIGITAL-TO-ANALOG SECTION

The architecture of one DAC channel consists of a reference buffer and a resistor-string DAC followed by an output buffer amplifier. The voltage at the V

pin provides the reference

REF

voltage for the DAC. Figure 36 shows a block diagram of the DAC architecture. Because the input coding to the DAC is straight binary, the ideal output voltage is given by

OUT

REF

D

N

2

VV

××=

Gain

where:

D is the decimal equivalent of the binary code, which is loaded

to the DAC register:

0 to 255 for AD5330 (8 Bits) 0 to 1023 for AD5331 (10 Bits) 0 to 4095 for AD5340/AD5341 (12 Bits)

N is the DAC resolution. Gain is the output amplifier gain (1 or 2).

REF

GAIN

BUF

V

OUT

06852-037

INPUT

REGISTER

REFERENCE

BUFFER

DAC

REGISTER

Figure 36. Single DAC Channel Architecture

RESISTOR

STRING

OUTPUT

BUFFER AMPL IFIER

RESISTOR STRING

The resistor-string section is shown in Figure 37. It is simply a string of resistors, each of value R. The digital code loaded to the DAC register determines at what node on the string the voltage is tapped off to be fed into the output amplifier. The voltage is tapped off by closing one of the switches connecting the string to the amplifier. Because it is a string of resistors, it is guaranteed monotonic.

DAC REFERENCE INPUT

There is a reference input pin for the DAC. The reference input is buffered on the AD5330, AD5340, and AD5341 but can be configured as unbuffered also. The reference input of the AD5331 is unbuffered. The buffered/unbuffered option is controlled by the BUF pin.

In buffered mode (BUF = 1), the current drawn from an external reference voltage is virtually zero because the impedance is at least 10 MΩ. The reference input range is 1 V to 5 V with a 5 V supply.

In unbuffered mode (BUF = 0), the user can have a reference voltage as low as 0.25 V and as high as V restriction due to headroom and footroom of the reference amplifier. The impedance is still large at typically 180 kΩ for 0 V to V

mode and 90 kΩ for 0 V to 2 × V

REF

an external buffered reference (for example, REF192), there is no need to use the on-chip buffer.

OUTPUT AMPLIFIER

The output buffer amplifier is capable of generating output voltages to within 1 mV of either rail. Its actual range depends

, GAIN, the load on V

on V

REF

If a gain of 1 is selected (GAIN = 0), the output range is 0.001 V

.

to V

REF

If a gain of 2 is selected (GAIN = 1), the output range is 0.001 V to 2 × V output is limited to V

The output amplifier is capable of driving a load of 2 kΩ to GND or 2 kΩ to V to V can be seen in Figure 24.

The slew rate is 0.7 V/μs with a half-scale settling time to ±0.5 LSB (at eight bits) of 6 μs with the output unloaded (see Figure 29).

. However, because of clamping, the maximum

REF

. The source and sink capabilities of the output amplifier

DD

REF

R

Figure 37. Resistor String

– 0.001 V.

DD

in parallel with 500 pF to GND or 500 pF

DD

TO OUTPUT AMPLIFIER

DD

, and offset error.

OUT

06852-038

because there is no

mode. If there is

REF

Rev. A | Page 17 of 28

AD5330/AD5331/AD5340/AD5341

X

PARALLEL INTERFACE

The AD5330, AD5331, and AD5340 load their data as a single 8-, 10-, or 12-bit word, while the AD5341 loads data as a low byte of eight bits and a high byte containing four bits.

DOUBLE-BUFFERED INTERFACE

The AD5330/AD5331/AD5340/AD5341 DACs all have doublebuffered interfaces consisting of an input register and a DAC register. DAC data, BUF, and GAIN inputs are written to the

CS

input register under the control of chip select (

Access to the DAC register is controlled by the

LDAC

When

is high, the DAC register is latched and the input

) and write (WR).

LDAC

function.

register may change state without affecting the contents of the DAC register. However, when

LDAC

is brought low, the DAC register becomes transparent and the contents of the input register are transferred to it. The gain and buffer control signals are also double-buffered and are only updated when

LDAC

is

taken low.

Double-buffering is also useful where the DAC data is loaded in two bytes, as in the AD5341, because it allows the whole data word to be assembled in parallel before updating the DAC register. This prevents spurious outputs that can occur if the DAC register is updated with only the high byte or the low byte.

These parts contain an extra feature whereby the DAC register is not updated unless its input register has been updated since

LDAC

the last time that LDAC

is brought low, the DAC register is filled with the

was brought low. Normally, when

contents of the input register. In the case of the AD5330/ AD5331/AD5340/AD5341, the parts only update the DAC register if the input register has been changed since the last time the DAC register was updated. This removes unnecessary crosstalk.

CLEAR INPUT (CLR)

CLR

is an active low, asynchronous clear that resets the input

and DAC registers.

CHIP SELECT INPUT (CS)

CS

is an active low input that selects the device.

WRITE INPUT (WR)

WR

is an active low input that controls writing of data to the

device. Data is latched into the input register on the rising

WR

edge of

.

LOAD DAC INPUT (LDAC)

LDAC

transfers data from the input register to the DAC register

(and therefore updates the outputs). Use of the

LDAC

function enables double-buffering of the DAC data, GAIN, and BUF. There are two

LDAC

modes: synchronous mode and

asynchronous mode.

In synchronous mode, the DAC register is updated after new data is read in on the rising edge of the

WR

input.

LDAC

can

be tied permanently low or pulsed, as shown in . Figure 2

In asynchronous mode, the outputs are not updated at the same

LDAC

time that the input register is written to. When

goes low, the DAC register is updated with the contents of the input register.

HIGH BYTE ENABLE INPUT (HBEN)

High byte enable is a control input on the AD5341 only. It determines if data is written to the high byte input register or the low byte input register.

The low data byte of the AD5341 consists of Data Bits [0:7] at the data inputs DB of Data Bits [8:11] at the data inputs DB Figure 38. DB

to DB7, whereas the high byte consists

0

to DB3, as shown in

0

to DB7 are ignored during a high byte write, but

4

they can be used for data to set up the reference input as buffered/ unbuffered, and buffer amplifier gain (see Figure 42).

HIGH BYTE

XX

DB

7

= UNUSED BIT

XX

LOW BYTE

DB

6

Figure 38. Data Format for AD5341

4

5

DB

10

11

DB

2

3

DB

8

9

DB

0

1

06852-039

POWER-ON RESET

The AD5330/AD5331/AD5340/AD5341 are provided with a power-on reset function, so that they power up in a defined state. The power-on state is

• Normal operation

• Reference input unbuffered

• 0 V to V

• Output voltage set to 0 V

Both input and DAC registers are filled with zeros and remain as such until a valid write sequence is made to the device. This is particularly useful in applications where it is important to know the state of the DAC outputs while the device is powering up.

output range

REF

Rev. A | Page 18 of 28

AD5330/AD5331/AD5340/AD5341

POWER-DOWN MODE

The AD5330/AD5331/AD5340/AD5341 have low power consumption, dissipating only 0.35 mW with a 3 V supply and

0.7 mW with a 5 V supply. Power consumption can be further reduced when the DAC is not in use by putting it into power-

PD

down mode, which is selected by taking Pin

When the

PD

pin is high, the DAC works normally with a typical power consumption of 140 μA at 5 V (115 μA at 3 V). In power-down mode, however, the supply current falls to 200 nA at 5 V (80 nA at 3 V) when the DAC is powered down. Not only does the supply current drop, but the output stage is also internally switched from the output of the amplifier, making it open-circuit. This has the advantage that the output is three-state while the part is in power-down mode and provides a defined input condition for whatever is connected to the output of the DAC amplifier. The output stage is illustrated in

. Figure 39

low.

The bias generator, the output amplifier, the resistor string, and all other associated linear circuitry are shut down when the power-down mode is activated. However, the contents of the registers are unaffected when in power-down. The time to exit power-down is typically 2.5 μs for V V

DD

when the output voltage deviates from its power-down voltage (see ). Figure 31

WR

1

Function

Table 9. AD5330/AD5331/AD5340 Truth Table

CLR LDAC CS

1 1 1 X No data transfer

1 1 X 1 No data transfer 0 X X X 1 1 0 1 0 0 1 0 X X Update DAC register

1

X = don’t care.

0→1 0→1

Clear all registers Load input register Load input register and DAC register

RESISTOR

STRING DAC

Figure 39. Output Stage During Power-Down

AMPLIFIER

V

OUT

POWER-DOWN

CIRCUITRY

= 5 V and 5 μs when

DD

06852-040

= 3 V. This is the time from a rising edge on the PD pin to

Table 10. AD5341 Truth Table1

CLR

LDAC

CS WR

HBEN Function

1 1 1 X X No data transfer

1 1 X 1 X No data transfer 0 X X X X 1 1 0 1 1 0 1 0 0 1 0 0 1 0 X X X Update DAC register

1

X = don’t care.

0→1 0→1 0→1 0→1

0 1 0 1

Clear all registers Load low byte input register Load high byte input register Load low byte input register and DAC register Load high byte input register and DAC register

Rev. A | Page 19 of 28

AD5330/AD5331/AD5340/AD5341

SUGGESTED DATABUS FORMATS

In most applications, GAIN and BUF are hard-wired. However, if more flexibility is required, they can be included in a databus. This enables the user to software program GAIN, giving the option of doubling the resolution in the lower half of the DAC range. In a bused system, GAIN and BUF can be treated as data inputs because they are written to the device during a write

LDAC

operation and take effect when

is taken low. This means that the reference buffers and the output amplifier gain of multiple DAC devices can be controlled using common GAIN and BUF lines.

In the case of the AD5330, this means that the databus must be wider than eight bits. The AD5331 and AD5340 databuses must be at least 10 bits and 12 bits wide, respectively, and are best suited to a 16-bit databus system.

Examples of data formats for putting GAIN and BUF on a 16-bit databus are shown in Figure 40. Note that any unused bits above the actual DAC data can be used for BUF and GAIN. DAC devices can be controlled using common GAIN and BUF lines.

AD5330

GAIN XXXX

X

DB

XBUF

DB

6

7

5

DB

0DB1DB2DB3DB4

AD5331

GAIN XXXXBUF DB9DB

8

DB

0DB1DB2DB3DB4DB5DB6DB7

AD5340

GAINBUF DB9 DB

X = UNUSED BIT

XX DB

DB

10

11

8

0DB1DB2DB3DB4DB5DB6DB7

Figure 40. GAIN and BUF Data on a 16-Bit Bus

06852-041

The AD5341 is a 12-bit device that uses byte load, so only four bits of the high byte are actually used as data. Two of the unused bits can be used for GAIN and BUF data by connecting them to the GAIN and BUF inputs; for example, Bit 6 and Bit 7, as shown in Figure 41 and Figure 42.

8-BIT

DATA BUS

DB

Figure 41. AD5341 Data Format for Byte Load with GAIN and BUF Data

DATA INPUTS

7DB6

BUF

GAIN

LDAC

CLR

CS

WR

HBEN

on 8-Bit Bus

AD5341

6852-042

In this case, the low byte is written to first in a write operation with HBEN = 0. Bit 6 and Bit 7 of DAC data are written into GAIN and BUF registers but have no effect. The high byte is then written to. Only the lower four bits of data are written into the DAC high byte register, so Bit 6 and Bit 7 can be GAIN and BUF data.

LDAC

is used to update the DAC, GAIN, and BUF values.

BUF GAIN

DB

7

X = UNUSED BIT

XX DB

DB

5

6

LOW BYTE

DB

4

DB

11

3

HIGH BYTE

Figure 42. AD5341 with GAIN and BUF Data on 8-Bit Bus

DB

10

2

DB

8

9

DB

0

1

06852-043

Rev. A | Page 20 of 28

AD5330/AD5331/AD5340/AD5341

V

A

V

APPLICATIONS INFORMATION

TYPICAL APPLICATION CIRCUITS

The AD5330/AD5331/AD5340/AD5341 can be used with a wide range of reference voltages, especially if the reference inputs are configured to be unbuffered, in which case the devices offer full, one-quadrant multiplying capability over a reference range of 0.25 V to V

. More typically, these devices

DD

can be used with a fixed, precision reference voltage. Figure 43 shows a typical setup for the devices when using an external reference connected to the unbuffered reference inputs. If the reference inputs are unbuffered, the reference input range is from 0.25 V to V

, but if the on-chip reference buffers are

DD

used, the reference range is reduced. Suitable references for 5 V operation are the AD780 and REF192. For 2.5 V operation, a suitable external reference is the AD589, a 1.23 V band gap reference.

= 2.5V TO 5.5

DD

0.1µF 10µF

V

IN

EXT

V

GND

OR

OUT

= 5V

DD

REF

AD780/REF192 WITH V

D589 WITH VDD = 2.5V

Figure 43. AD5330/AD5331/AD5340/AD5341 Using External Reference

+

V

REF

DD

AD5330/AD5331/

AD5340/AD5341

GND

V

OUT

06852-044

DRIVING VDD FROM THE REFERENCE VOLTAGE

If an output range of 0 V to VDD is required, the simplest solution is to connect the reference inputs to V supply may not be very accurate and may be noisy, the devices can be powered from the reference voltage, for example using a 5 V reference such as the ADP667, as shown in Figure 44.

6V TO 16

0.1µF

V

IN

ADP667

V

VSET

OUT

GND SHDN

Figure 44. Using an ADP667 as Power and Reference to

+

10µF

V

DD

V

REF

0.1µF

AD5330/AD5331/ AD5340/AD5341

GND

AD5330/AD5331/AD5340/AD5341

. Because this

DD

V

OUT

06852-045

BIPOLAR OPERATION USING THE AD5330/AD5331/ AD5340/AD5341

The AD5330/AD5331/AD5340/AD5341 are designed for single-supply operation, but bipolar operation is achievable using the circuit shown in Figure 45. The circuit shown has been configured to achieve an output voltage range of –5 V < V

< +5 V. Rail-to-rail operation at the amplifier output is

O

achievable using an AD820 or OP295 as the output amplifier.

The output voltage for any input code can be calculated as follows:

V

= [(1 + R4/R3) × (R2/(R1 + R2) × (2 × V

O

R4 × V

REF

/R3

× D/2N)] –

REF

where:

D is the decimal equivalent of the code loaded to the DAC. N is the DAC resolution. V

is the reference voltage input.

REF

with:

= 2.5 V.

V

REF

R1 = R3 = 10 kΩ. R2 = R4 = 20 kΩ and V

= (10 × D/2N) − 5.

V

O

0.1µF 10µF

V

IN

EXT

V

REF

AD589 WITH V

Figure 45. Bipolar Operation using the AD5330/AD5331/AD5340/AD5341

OUT

GND

AD780/REF192 WITH V

= 5V

DD

OR

DD

0.1µF

= 2.5V

= 5 V.

DD

= 5

DD

+

R3

10kΩ

V

DD

V

REF

AD5330/AD5331/

AD5340/AD5341

GND

V

OUT

R1

10kΩ

20kΩ

R2 20kΩ

R4

+5V

= ±5V

V

O

–5V

DECODING MULTIPLE AD5330/AD5331/ AD5340/AD5341

The CS pin on these devices can be used in applications to decode a number of DACs. In this application, all DACs in the system receive the same data and of the DACs is active at any one time, so data is only written to the DAC whose

CS

is low. If multiple AD5341s are being used, a common HBEN line is also required to determine if the data is written to the high byte or low byte register of the selected DAC.

The 74HC139 is used as a 2-line to 4-line decoder to address any of the DACs in the system. To prevent timing errors, the enable input should be brought to its inactive state while the coded address inputs are changing state. Figure 46 shows a diagram of a typical setup for decoding multiple devices in a system. Once data has been written sequentially to all DACs in

WR

pulses, but only CS to one

06852-046

Rev. A | Page 21 of 28

AD5330/AD5331/AD5340/AD5341

A

V

a system, all the DACs can be updated simultaneously using a common

LDAC

line. A common

CLR

line can also be used to

reset all DAC outputs to zero.

AD5330/AD5331/

AD5340/AD5341

HBEN*

WR

LDAC

CLR

ENABLE

CODED

DDRESS

G1

A1

B1

V

DD

V

CC

74HC139

DGND

1Y0

1Y1

1Y2

1Y3

*AD5341 ONLY

HBEN*

WR LDAC CLR CS

AD5330/AD5331/

AD5340/AD5341

HBEN*

WR LDAC CLR CS

AD5330/AD5331/

AD5340/AD5341

HBEN*

WR LDAC CLR CS

AD5330/AD5331/

AD5340/AD5341

HBEN*

WR LDAC CLR CS

DATA

INPUTS

DATA

INPUTS

DATA

INPUTS

DATA

INPUTS

DATA BUS

Figure 46. Decoding Multiple DAC Devices

PROGRAMMABLE CURRENT SOURCE

Figure 47 shows the AD5330/AD5331/AD5340/AD5341 used as the control element of a programmable current source. In this example, the full-scale current is set to 1 mA. The output voltage from the DAC is applied across the current setting resistor of 4.7 kΩ in series with the 470 Ω adjustment potentiometer, which gives an adjustment of about ±5%. Suitable transistors to place in the feedback loop of the amplifier include the BC107 and the 2N3904, which enable the current source to operate from a minimum V determined by the operating characteristics of the transistor. Suitable amplifiers include the AD820 and the OP295, both having rail-to-rail operation on their outputs. The current for any digital input code and resistor value can be calculated as follows:

VGI

REF

D

××=

N

×

where:

G is the gain of the buffer amplifier (1 or 2). D is the digital equivalent of the digital input code. N is the DAC resolution (8, 10, or 12 bits). R is the sum of the resistor plus adjustment potentiometer

in kilo ohms.

of 6 V. The operating range is

SOURCE

mA

)2( R

= 5

DD

+

V

REF

0.1µF

AD5330/AD5331/

AD5340/AD5341

V

DD

GND

V

SOURCE

LOAD

4.7kΩ

470Ω

06852-048

AD820/ OP295

5V

V

OUT

V

IN

EXT

V

GND

OUT

= 5V

DD

REF

AD780/REF192 WITH V

0.1µF 10µF

Figure 47. Programmable Current Source

POWER SUPPLY BYPASSING AND GROUNDING

In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. The printed circuit board on which the AD5330/AD5331/AD5340/AD5341 are mounted should be designed so that the analog and digital sections are separated and confined to certain areas of the board. If the device is in a system where multiple devices require an AGNDto-DGND connection, the connection should be made at one point only. The star ground point should be established as

06852-047

closely as possible to the device. The AD5330/AD5331/ AD5340/AD5341 should have ample supply bypassing of 10 μF in parallel with 0.1 μF on the supply located as close to the package as possible, ideally right up against the device. The 10 μF capacitors are the tantalum bead type. The 0.1 μF capacitor should have low effective series resistance (ESR) and effective series inductance (ESI), like the common ceramic types that provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching.

The power supply lines of the device should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals such as clocks should be shielded with digital ground to avoid radiating noise to other parts of the board, and should never be run near the reference inputs. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This reduces the effects of feedthrough through the board. A microstrip technique is by far the best, but not always possible with a double-sided board. In this technique, the component side of the board is dedicated to the ground plane while signal traces are placed on the solder side.

Rev. A | Page 22 of 28

AD5330/AD5331/AD5340/AD5341

Table 11. Overview of AD53xx Parallel Devices

Additional Pin Functions

Part No. Resolution Bits DNL No. of V Singles

Pins Settling Time

REF

AD5330 8 ±0.25 1 6 μs BUF GAIN AD5331 10 ±0.5 1 7 μs GAIN AD5340 12 ±1.0 1 8 μs BUF GAIN AD5341 12 ±1.0 1 8 μs BUF GAIN HBEN

Duals

AD5332 8 ±0.25 2 6 μs AD5333 10 ±0.5 2 7 μs BUF GAIN AD5342 12 ±1.0 2 8 μs BUF GAIN AD5343 12 ±1.0 1 8 μs HBEN

Quads

AD5334 8 ±0.25 2 6 μs GAIN AD5335 10 ±0.5 2 7 μs HBEN AD5336 10 ±0.5 4 7 μs GAIN AD5344 12 ±1.0 4 8 μs TSSOP 28

CLR

CLR CLR CLR CLR

CLR CLR CLR

Package No. of Pins BUF GAIN HBEN

TSSOP 20 TSSOP 20 TSSOP 24 TSSOP 20

TSSOP 20 TSSOP 24 TSSOP 28 TSSOP 20

TSSOP 24 TSSOP 24 TSSOP 28

Table 12. Overview of AD53xx Serial Devices

Part No. Resolution Bits No. of DACs DNL Interface Settling Time Package No of Pins Singles

AD5300 8 1 ±0.25 SPI 4 μs SOT-23, MSOP 6, 8 AD5310 10 1 ±0.5 SPI 6 μs SOT-23, MSOP 6, 8 AD5320 12 1 ±1.0 SPI 8 μs SOT-23, MSOP 6, 8 AD5301 8 1 ±0.25 2-Wire 6 μs SOT-23, MSOP 6, 8 AD5311 10 1 ±0.5 2-Wire 7 μs SOT-23, MSOP 6, 8 AD5321 12 1 ±1.0 2-Wire 8 μs SOT-23, MSOP 6, 8

Duals

AD5302 8 2 ±0.25 SPI 6 μs MSOP 10 AD5312 10 2 ±0.5 SPI 7 μs MSOP 10 AD5322 12 2 ±1.0 SPI 8 μs MSOP 10 AD5303 8 2 ±0.25 SPI 6 μs TSSOP 16 AD5313 10 2 ±0.5 SPI 7 μs TSSOP 16 AD5323 12 2 ±1.0 SPI 8 μs TSSOP 16

Quads

AD5304 8 4 ±0.25 SPI 6 μs MSOP, LFCSP 10 AD5314 10 4 ±0.5 SPI 7 μs MSOP, LFCSP 10 AD5324 12 4 ±1.0 SPI 8 μs MSOP, LFCSP 10 AD5305 8 4 ±0.25 2-Wire 6 μs MSOP 10 AD5315 10 4 ±0.5 2-Wire 7 μs MSOP 10 AD5325 12 4 ±1.0 2-Wire 8 μs MSOP 10 AD5306 8 4 ±0.25 2-Wire 6 μs TSSOP 16 AD5316 10 4 ±0.5 2-Wire 7 μs TSSOP 16 AD5326 12 4 ±1.0 2-Wire 8 μs TSSOP 16 AD5307 8 4 ±0.25 SPI 6 μs TSSOP 16 AD5317 10 4 ±0.5 SPI 7 μs TSSOP 16 AD5327 12 4 ±1.0 SPI 8 μs TSSOP 16

Rev. A | Page 23 of 28

AD5330/AD5331/AD5340/AD5341

Y

OUTLINE DIMENSIONS

6.60

6.50

6.40

PIN 1

0.15

0.05

COPLANARIT

20

1

0.65

BSC

0.30

0.19

0.10

COMPLIANT TO JEDEC STANDARDS MO-153-AC

1.20 MAX

11

10

SEATING PLANE

4.50

4.40

4.30

6.40 BSC

0.20

0.09 8°

0°

0.75

0.60

0.45

Figure 48. 20-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-20)

Dimensions shown in millimeters

7.90

7.80

7.70

24

PIN 1

0.65

0.15

0.05

0.10 COPLANARITY

BSC

0.30

0.19

COMPLIANT TO JEDEC STANDARDS MO-153-AD

Figure 49. 24-Lead Thin Shrink Small Outline Package [TSSOP]

Dimensions shown in millimeters

13

121

1.20

MAX

SEATING PLANE

(RU-24)

4.50

4.40

4.30

6.40 BSC

0.20

0.09

8° 0°

0.75

0.60

0.45

Rev. A | Page 24 of 28

AD5330/AD5331/AD5340/AD5341

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD5330BRU –40°C to +105°C 20-Lead Thin Shrink Small Outline Package [TSSOP] RU-20 AD5330BRU-REEL –40°C to +105°C 20-Lead Thin Shrink Small Outline Package [TSSOP] RU-20 AD5330BRU-REEL7 –40°C to +105°C 20-Lead Thin Shrink Small Outline Package [TSSOP] RU-20 AD5330BRUZ AD5330BRUZ-REEL AD5330BRUZ-REEL7 AD5331BRU –40°C to +105°C 20-Lead Thin Shrink Small Outline Package [TSSOP] RU-20 AD5331BRU-REEL –40°C to +105°C 20-Lead Thin Shrink Small Outline Package [TSSOP] RU-20 AD5331BRU-REEL7 –40°C to +105°C 20-Lead Thin Shrink Small Outline Package [TSSOP] RU-20 AD5331BRUZ AD5331BRUZ-REEL AD5331BRUZ-REEL7 AD5340BRU –40°C to +105°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24 AD5340BRU-REEL –40°C to +105°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24 AD5340BRU-REEL7 –40°C to +105°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24 AD5340BRUZ AD5340BRUZ-REEL AD5340BRUZ-REEL7 AD5341BRU –40°C to +105°C 20-Lead Thin Shrink Small Outline Package [TSSOP] RU-20 AD5341BRU-REEL –40°C to +105°C 20-Lead Thin Shrink Small Outline Package [TSSOP] RU-20 AD5341BRU-REEL7 –40°C to +105°C 20-Lead Thin Shrink Small Outline Package [TSSOP] RU-20 AD5341BRUZ AD5341BRUZ-REEL AD5341BRUZ-REEL7

1

Z = RoHS Compliant Part.

1