ANALOG DEVICES AD5330, AD5331, AD5340, AD5341 Service Manual

2.5 V to 5.5 V, 115 μA, Parallel Interface

V

Single Voltage-Output 8-/10-/12-Bit DACs

FEATURES

AD5330: single 8-bit DAC in 20-lead TSSOP AD5331: single 10-bit DAC in 20-lead TSSOP AD5340: single 12-bit DAC in 24-lead TSSOP AD5341: single 12-bit DAC in 20-lead TSSOP Low power operation: 115 μA @ 3 V, 140 μA @ 5 V

REF

PD

LDAC

FUNCTIONAL BLOCK DIAGRAM

POWER-ON

RESET

Power-down to 80 nA @ 3 V, 200 nA @ 5 V via

2.5 V to 5.5 V power supply Double-buffered input logic Guaranteed monotonic by design over all codes Buffered/unbuffered reference input options Output range: 0 V to V

or 0 V to 2 × V

REF

Power-on reset to 0 V Simultaneous update of DAC outputs via Asynchronous

CLR

facility Low power parallel data interface On-chip rail-to-rail output buffer amplifiers Temperature range: −40°C to +105°C

APPLICATIONS

Portable battery-powered instruments Digital gain and offset adjustment Programmable voltage and current sources Programmable attenuators Industrial process control

AD5330/AD5331/AD5340/AD5341

GENERAL DESCRIPTION

The AD5330/AD5331/AD5340/AD53411 are single 8-/10-/12bit DACs. They operate from a 2.5 V to 5.5 V supply consuming just 115 μA at 3 V and feature a power-down mode that further reduces the current to 80 nA. The devices incorporate an on-chip output buffer that can drive the output to both supply rails, but the AD5330, AD5340, and AD5341 allow a choice of buffered or unbuffered reference input.

The AD5330/AD5331/AD5340/AD5341 have a parallel interface. input registers on the rising edge of

The GAIN pin allows the output range to be set at 0 V to V 0 V to 2 × V

Input data to the DACs is double-buffered, allowing simultaneous update of multiple DACs in a system using the

An asynchronous contents of the input register and the DAC register to all zeros. These devices also incorporate a power-on reset circuit that ensures that the DAC output powers on to 0 V and remains there until valid data is written to the device.

The AD5330/AD5331/AD5340/AD5341 are available in thin shrink small outline packages (TSSOP).

1

Protected by U.S. Patent Number 5,969,657.

REF

3 12

CS

selects the device and data is loaded into the

WR

.

REF

CLR

input is also provided, which resets the

DD

AD5330

LDAC

REF

pin.

or

1

BUF

GAIN

8

DB

20

7

.

13

DB

0

6

CS

7

WR

9

CLR

10

LDAC

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

INPUT

REGISTER

RESET

INTERFACE LOGIC

DAC

REGISTER

Figure 1. AD5330

8-BIT

DAC

BUFFER

POWER-DOWN

LOGIC

11 5

PD GND

4

V

OUT

6852-001

AD5330/AD5331/AD5340/AD5341

REVISION HISTORY

2/08—Rev. 0 to Rev. A

Updated Format .................................................................. Universal

Changes to Table 4 .......................................................................... 16

Replaced Driving V

Updated Outline Dimensions ....................................................... 24

Changes to Ordering Guide .......................................................... 25

4/00—Revision 0: Initial Version

from the Reference Voltage Section ..... 21

DD

Rev. A | Page 2 of 28

AD5330/AD5331/AD5340/AD5341

SPECIFICATIONS

VDD = 2.5 V to 5.5 V, V

Table 1.

Parameter

1

DC PERFORMANCE

AD5330

Resolution 8 Bits Relative Accuracy ±0.15 ±1 LSB Differential Nonlinearity ±0.02 ±0.25 LSB Guaranteed monotonic by design over all codes

AD5331

Resolution 10 Bits Relative Accuracy ±0.5 ±4 LSB Differential Nonlinearity ±0.05 ±0.5 LSB Guaranteed monotonic by design over all codes

AD5340/AD5341

Resolution 12 Bits Relative Accuracy ±2 ±16 LSBs

Differential Nonlinearity ±0.2 ±1 LSB Guaranteed monotonic by design over all codes Offset Error ±0.4 ±3 % of FSR Gain Error ±0.15 ±1 % of FSR Lower Deadband Upper Deadband 10 60 mV VDD = 5 V; upper deadband exists only if V Offset Error Drift Gain Error Drift

6

DC Power Supply Rejection Ratio6 −60 dB ΔVDD = ±10%

DAC REFERENCE INPUT

V

Input Range 1 VDD V Buffered reference (AD5330, AD5340, and AD5341)

REF

0.25 VDD V Unbuffered reference V

Input Impedance >10 MΩ Buffered reference (AD5330, AD5340, and AD5341)

REF

180 kΩ Unbuffered reference; gain = 1, input impedance = R 90 kΩ Unbuffered reference; gain = 2, input impedance = R Reference Feedthrough −90 dB Frequency = 10 kHz

OUTPUT CHARACTERISTICS

Minimum Output Voltage Maximum Output Voltage DC Output Impedance 0.5 Ω Short-Circuit Current 25 mA VDD = 5 V 15 mA VDD = 3 V Power-Up Time 2.5 μs Coming out of power-down mode; VDD = 5 V 5 μs Coming out of power-down mode; VDD = 3 V

LOGIC INPUTS

6

Input Current ±1 μA Input Low Voltage, VIL 0.8 V VDD = 5 V ± 10%

0.6 V VDD = 3 V ± 10%

0.5 V VDD = 2.5 V Input High Voltage, VIH 2.4 V VDD = 5 V ± 10%

2.1 V VDD = 3 V ± 10%

2.0 V VDD = 2.5 V Pin Capacitance 3 pF

= 2 V, RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications T

REF

B Version

2

Unit Conditions/Comments Min Typ Max

3, 4

5

6

−5 ppm of FSR/°C

6

4, 7

10 60 mV Lower deadband exists only if offset error is negative

−12 ppm of FSR/°C

0.001 V min Rail-to-rail operation V

− 0.001 V max

DD

MIN

to T

, unless otherwise noted.

MAX

REF

= VDD

DAC

Rev. A | Page 3 of 28

AD5330/AD5331/AD5340/AD5341

2

Unit Conditions/Comments Min Typ Max

Parameter

1

B Version

POWER REQUIREMENTS

VDD 2.5 5.5 V IDD (Normal Mode) DACs active and excluding load currents. Unbuffered

VDD = 4.5 V to 5.5 V 140 250 μA Reference, VIH = VDD, VIL = GND VDD = 2.5 V to 3.6 V 115 200 μA IDD increases by 50 μA at V

In buffered mode, extra current is (5 + V where R

is the resistance of the resistor string.

DAC

> VDD − 100 mV.

REF

REF/RDAC

) μA,

IDD (Power-Down Mode)

VDD = 4.5 V to 5.5 V 0.2 1 μA VDD = 2.5 V to 3.6 V 0.08 1 μA

1

See the Terminology section.

2

Temperature range: B Version: −40°C to +105°C; typical specifications are at 25°C.

3

Linearity is tested using a reduced code range: AD5330 (Code 8 to Code 255); AD5331 (Code 28 to Code 1023); AD5340/AD5341 (Code 115 to Code 4095).

4

DC specifications tested with output unloaded.

5

This corresponds to x codes. x = deadband voltage/LSB size.

6

Guaranteed by design and characterization, not production tested.

7

For the amplifier output to reach its minimum voltage, offset error must be negative. For the amplifier output to reach its maximum voltage, V

gain error must be positive.

= VDD and offset plus

REF

AC CHARACTERISTICS1

VDD = 2.5 V to 5.5 V. RL = 2 kΩ to GND, CL = 200 pF to GND; all specifications T

Table 2.

Parameter

2

Output Voltage Settling Time V

B Version

3

Unit Conditions/Comments Min Typ Max

REF

AD5330 6 8 μs ¼ scale to ¾ scale change (0x40 to 0xC0) AD5331 7 9 μs ¼ scale to ¾ scale change (0x100 to 0x300) AD5340 8 10 μs ¼ scale to ¾ scale change (0x400 to 0xC00)

AD5341 8 10 μs ¼ scale to ¾ scale change (0x400 to 0xC00) Slew Rate 0.7 V/μs Major Code Transition Glitch Energy 6 nV/s 1 LSB change around major carry Digital Feedthrough 0.5 nV/s Multiplying Bandwidth 200 kHz V Total Harmonic Distortion −70 dB V

1

Guaranteed by design and characterization, not production tested.

2

See the Terminology section.

3

Temperature range: B Version: −40°C to +105°C; typical specifications are at 25°C.

REF

MIN

to T

, unless otherwise noted.

MAX

= 2 V; see Figure 29

= 2 V ± 0.1 V p-p; unbuffered mode = 2.5 V ± 0.1 V p-p; frequency = 10 kHz

Rev. A | Page 4 of 28

AD5330/AD5331/AD5340/AD5341

TIMING CHARACTERISTICS

VDD = 2.5 V to 5.5 V, all specifications T

1, 2, 3

MIN

to T

, unless otherwise noted.

MAX

Table 3.

Parameter Limit at T

t1 0 ns min

t2 0 ns min t3 20 ns min

MIN

, T

Unit Condition/Comments

MAX

to WR setup time.

CS

to WR hold time.

CS

pulse width.

WR t4 5 ns min Data, GAIN, BUF, HBEN setup time. t5 4.5 ns min Data, GAIN, BUF, HBEN hold time. t6 5 ns min t7 5 ns min t8 4.5 ns min t9 5 ns min t10 4.5 ns min t11 20 ns min t12 20 ns min t13 50 ns min

1

Guaranteed by design and characterization, not production tested.

2

All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.

3

See Figure 2.

Synchronous mode; WR

Synchronous mode; LDAC

Synchronous mode; WR

Asynchronous mode; LDAC

Asynchronous mode; WR

pulse width.

LDAC

pulse width.

CLR

Time between WR

t

CS

WR

DATA,

GAIN,

BUF,

HBEN

1

LDAC

2

LDAC

CLR

NOTES:

1

SYNCHRONOUS LDAC UPDAT E MODE

2

ASYNCHRONOUS LDAC UPDAT E MODE

1

t

6

t

3

t

2

t

13

t

5

t

4

t

8

t

7

t

9

10

t

11

Figure 2. Parallel Interface Timing Diagram

falling to LDAC falling.

falling to WR rising.

rising to LDAC rising.

rising to WR rising.

rising to LDAC falling.

cycles.

t

12

06852-002

Rev. A | Page 5 of 28

AD5330/AD5331/AD5340/AD5341

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 4.

Parameter Rating

VDD to GND −0.3 V to +7 V Digital Input Voltage to GND −0.3 V to VDD + 0.3 V Digital Output Voltage to GND −0.3 V to VDD + 0.3 V Reference Input Voltage to GND −0.3 V to VDD + 0.3 V V

to GND −0.3 V to VDD + 0.3 V

OUT

Operating Temperature Range

Industrial (B Version) −40°C to +105°C Storage Temperature Range −65°C to +150°C Junction Temperature 150°C TSSOP Package

Power Dissipation (TJ max – TA)/θJA mW

θJA Thermal Impedance (20-Lead TSSOP)1 85°C/W

θJA Thermal Impedance (24-Lead TSSOP)1 80°C/W Reflow Soldering

Peak Temperature 260°C

Time at Peak Temperature 20 sec to 40 sec

1

Thermal resistance (JEDEC 4-layer (2S2P) board).

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

Rev. A | Page 6 of 28

AD5330/AD5331/AD5340/AD5341

V

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

REF

3 12

POWER-ON

RESET

1

BUF

GAIN

DB

CS

WR

CLR

LDAC

INTERFACE LO GIC

REGISTER

RESET

INPUT

8

20

7

. .

13

0

6

7

9

10

DAC

REGISTER

8-BIT

DAC

Figure 3. AD5330 Functional Block Diagram Figure 4. AD5330 Pin Configuration

Table 5. AD5330 Pin Function Descriptions

Pin No. Mnemonic Description

1 BUF Buffer Control Pin. This pin controls whether the reference input to the DAC is buffered or unbuffered. 2 NC No Connect. 3 V 4 V

Reference Input.

REF

Output of DAC. Buffered output with rail-to-rail operation.

OUT

5 GND Ground reference point for all circuitry on the part. 6 7

Active Low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface.

CS

Active Low Write Input. This is used in conjunction with CS to write data to the parallel interface.

WR 8 GAIN Gain Control Pin. This controls whether the output range from the DAC is 0 V to V 9 10 11

CLR

LDAC

PD 12 VDD

Asynchronous active low control input that clears all input registers and DAC registers to zero. Active low control input that updates the DAC registers with the contents of the input registers. Power-Down Pin. This active low control pin puts the DAC into power-down mode. Power Supply Input. These parts can operate from 2.5 V to 5.5 V and the supply should be decoupled with a

10 μF capacitor in parallel with a 0.1 μF capacitor to GND.

13 to 20 DB0 to DB7 Eight Parallel Data Inputs. DB7 is the MSB of these eight bits.

AD5330

BUFFER

DD

POWER-DOW N

LOGIC

11 5

PD GND

REF

20

DB

7

19

DB

6

18

DB

5

17

DB

4

16

DB

3

15

DB

2

14

DB

1

13

DB

0

12

V

DD

11

PD

06852-004

.

1

BUF

2

4

V

OUT

06852-003

NC

V

3

REF

V

4

OUT

5

GND

6

CS

7

WR

8

GAIN

9

CLR

10

LDAC

NC = NO CONNECT

or 0 V to 2 × V

REF

8-BIT

AD5330

TOP VIEW

(Not to Scale)

Rev. A | Page 7 of 28

AD5330/AD5331/AD5340/AD5341

V

DB

GAIN

DB

CS

WR

CLR

LDAC

REF

3 12

POWER-ON

RESET

1

8

2

9

8

20

7

. .

13

0

6

7

9

10

INTERFACE LOGIC

REGISTER

RESET

INPUT

DAC

REGISTER

10-BIT

DAC

BUFFER

DD

AD5331

POWER-DOW N

LOGIC

11 5

PD GND

4

V

OUT

06852-005

Figure 5. AD5331 Functional Block Diagram Figure 6. AD5331 Pin Configuration

Table 6. AD5331 Pin Function Descriptions

Pin No. Mnemonic Description

1 DB8 Parallel Data Input. 2 DB9 Most Significant Bit of Parallel Data Input. 3 V

4 V

Unbuffered Reference Input.

REF

Output of DAC. Buffered output with rail-to-rail operation.

OUT

5 GND Ground reference point for all circuitry on the part. 6 7

Active Low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface.

CS

Active Low Write Input. This is used in conjunction with CS to write data to the parallel interface.

WR 8 GAIN Gain Control Pin. This controls whether the output range from the DAC is 0 V to V 9 10 11

CLR

LDAC

PD 12 VDD

Active low control input that clears all input registers and DAC registers to zero. Active low control input that updates the DAC registers with the contents of the input registers. Power-Down Pin. This active low control pin puts the DAC into power-down mode. Power Supply Input. These parts can operate from 2.5 V to 5.5 V and the supply should be decoupled with a

10 μF capacitor in parallel with a 0.1 μF capacitor to GND.

13 to 20 DB0 to DB7 Eight Parallel Data Inputs.

1

DB

8

2

DB

9

V

3

REF

V

4

OUT

5

GND

6

CS

7

WR

8

GAIN

9

CLR

10

LDAC

or 0 V to 2 × V

REF

10-BIT

AD5331

TOP VIEW

(Not to Scale)

REF

20

DB

7

19

DB

6

18

DB

5

17

DB

4

16

DB

3

15

DB

2

14

DB

1

13

DB

0

12

V

DD

11

PD

06852-006

.

Rev. A | Page 8 of 28

AD5330/AD5331/AD5340/AD5341

V

REF

4 14

POWER-ON

INTERFACE LOGIC

REGISTER

RESET

INPUT

DAC

REGISTER

12-BIT

DAC

DB

BUF

GAIN

DB

CS

WR

CLR

LDAC

1

10

2

11

3

10

24

9

. .

15

0

8

9

11

12

Figure 7. AD5340 Functional Block Diagram Figure 8. AD5340 Pin Configuration

Table 7. AD5340 Pin Function Descriptions

Pin No. Mnemonic Description

1 DB10 Parallel Data Input. 2 DB11 Most Significant Bit of Parallel Data Input. 3 BUF Buffer Control Pin. This pin controls whether the reference input to the DAC is buffered or unbuffered. 4 V 5 V

Reference Input.

REF

Output of DAC. Buffered output with rail-to-rail operation.

OUT

6 NC No Connect. 7 GND Ground reference point for all circuitry on the part.

8 9

Active Low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface.

CS

Active Low Write Input. This is used in conjunction with CS to write data to the parallel interface.

WR 10 GAIN Gain Control Pin. This controls whether the output range from the DAC is 0 V to V 11 12 13

CLR

LDAC

PD 14 VDD

Asynchronous active low control input that clears all input registers and DAC registers to zero. Active low control input that updates the DAC registers with the contents of the input registers. Power-Down Pin. This active low control pin puts the DAC into power-down mode. Power Supply Input. These parts can operate from 2.5 V to 5.5 V and the supply should be decoupled with a

10 μF capacitor in parallel with a 0.1 μF capacitor to GND.

15 to 24 DB0 to DB9 Ten Parallel Data Inputs.

AD5340

BUFFER

DD

POWER-DOW N

LOGIC

13 7

PD GND

REF

24

DB

9

23

DB

8

22

DB

7

21

DB

6

20

DB

5

19

DB

4

18

DB

3

17

DB

2

16

DB

1

15

DB

0

14

V

DD

13

PD

06852-008

.

1

DB

10

2

DB

5

V

OUT

06852-007

11

3

BUF

4

V

REF

V

5

OUT

NC

6

7

GND

8

CS

9

WR

10

GAIN

11

CLR

12

LDAC

or 0 V to 2 × V

REF

12-BIT

AD5340

TOP VIEW

(Not to Scale)

Rev. A | Page 9 of 28

ANALOG DEVICES AD5330, AD5331, AD5340, AD5341 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

FUNCTIONAL BLOCK DIAGRAM

APPLICATIONS

GENERAL DESCRIPTION

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS