Datasheet AD5316R Datasheet (ANALOG DEVICES)

Quad, 10-Bit nanoDAC with 2 ppm/°C

Data Sheet

FEATURES

Low drift 2.5 V on-chip reference: 2 ppm/°C typical Tiny package: 3 mm × 3 mm, 16-lead LFCSP

Total unadjusted error (TUE): ±0.1% of FSR maximum Offset error: ±1.5 mV maximum Gain error: ±0.1% of FSR maximum High drive capability: 20 mA, 0.5 V from supply rails User-selectable gain of 1 or 2 (GAIN pin) Reset to zero scale or midscale (RSTSEL pin)

1.8 V logic compatibility 400 kHz I 4 I Low glitch: 0.5 nV-sec Robust 3.5 kV HBM and 1.5 kV FICDM ESD rating Low power: 3.3 mW at 3 V

2.7 V to 5.5 V power supply

−40°C to +105°C temperature range

APPLICATIONS

Digital gain and offset adjustment Programmable attenuators Industrial automation Data acquisition systems

GENERAL DESCRIPTION

The AD5316R, a member of the nanoDAC® family, is a low power, quad, 10-bit buffered voltage output DAC. The device includes a 2.5 V, 2 ppm/°C internal reference (enabled by default) and a gain select pin giving a full-scale output of 2.5 V (gain = 1) or 5 V (gain = 2). The device operates from a single 2.7 V to 5.5 V supply, is guaranteed monotonic by design, and exhibits less than 0.1% FSR gain error and 1.5 mV offset error performance. The device is available in a 3 mm × 3 mm LFCSP package and in a TSSOP package.

The AD5316R also incorporates a power-on reset circuit and a RSTSEL pin; the RSTSEL pin ensures that the DAC outputs power up to zero scale or midscale and remain at that level until a valid write takes place. The part contains a per-channel power-down feature that reduces the current consumption of the device in power-down mode to 4 μA at 3 V.

The AD5316R uses a versatile 2-wire serial interface that operates at clock rates up to 400 kHz and includes a V for 1.8 V/3 V/5 V logic.

C-compatible serial interface

C addresses available

pin intended

LOGIC

Reference, I

C Interface

AD5316R

FUNCTIONAL BLOCK DIAGRAM

LOGIC

SCL

SDA

AD5316R

INTERFACE LOGIC

INPUT

GND

DAC

POWER-ON

RESET

RSTSEL GAINLDAC RESET

Figure 1.

Table 1. Related Devices

Interface Reference 12-Bit 10-Bit

SPI Internal AD5684R AD5317R External AD5684 AD5317 I2C Internal AD5694R External AD5694 AD53161

The AD5316R and the AD5316 are not pin-to-pin or software compatible.

PRODUCT HIGHLIGHTS

1. Precision DC Performance.

Total unadjusted error: ±0.1% of FSR maximum Offset error: ±1.5 mV maximum Gain error: ±0.1% of FSR maximum

2. Low Drift 2.5 V On-Chip Reference.

2 ppm/°C typical temperature coefficient 5 ppm/°C maximum temperature coefficient

3. Two Pa ckage Opti ons .

3 mm × 3 mm, 16-lead LFCSP 16-lead TSSOP

REF

STRING

DAC A

STRING

DAC B

STRING

DAC C

STRING

DAC D

GAIN =

×1/×2

2.5V

REFERENCE

BUFFER

POWER-

DOWN LOGIC

OUT

10819-001

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

AD5316R Data Sheet

Features .............................................................................................. 1

Applications ....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

AC Characteristics ........................................................................ 4

Timing Characteristics ................................................................ 5

Absolute Maximum Ratings ............................................................ 6

Thermal Resistance ...................................................................... 6

ESD Caution .................................................................................. 6

Pin Configurations and Function Descriptions ........................... 7

Typical Performance Characteristics ............................................. 8

Term ino log y .................................................................................... 14

Theory of Operation ...................................................................... 16

Digital-to-Analog Converter .................................................... 16

Transfer Function ....................................................................... 16

DAC Architecture ....................................................................... 16

Serial Interface ............................................................................ 17

Write and Update Commands .................................................. 17

I2C Slave Address ........................................................................ 18

Serial Operation ......................................................................... 18

Write Operation.......................................................................... 18

Read Operation........................................................................... 19

Multiple DAC Readback Sequence .......................................... 19

Power-Down Operation ............................................................ 20

Load DAC (Hardware LDAC

Mask Register ................................................................. 21

Hardware Reset Pin (

Reset Select Pin (RSTSEL) ........................................................ 21

Internal Reference Setup ........................................................... 22

Solder Heat Reflow ..................................................................... 22

Long-Term Temperature Drift ................................................. 22

Thermal Hysteresis .................................................................... 22

Applications Information .............................................................. 23

Microprocessor Interfacing ....................................................... 23

AD5316R to ADSP-BF531 Interface ....................................... 23

Layout Guidelines....................................................................... 23

Galvanically Isolated Interface ................................................. 23

Outline Dimensions ....................................................................... 24

Ordering Guide .......................................................................... 24

LDAC

Pin) ........................................... 20

) ................................................... 21

RESET

REVISION HISTORY

7/12—Rev. 0 to R e v. A

Change to Features Section ............................................................. 1

Change to Relative Accuracy Parameter in Tabl e 2 ..................... 3

Change to Differential Nonlinearity Parameter in Table 2 ......... 3

Changes to Ordering Guide .......................................................... 24

7/12—Revision 0: Initial Version

Rev. A | Page 2 of 24

Data Sheet AD5316R

Resolution

Bits

Full-Scale Error

+0.01

±0.1

% of FSR

All 1s loaded to DAC register

DC Power Supply Rejection Ratio4

0.15 mV/V

DAC code = midscale; VDD = 5 V ± 10%

Capacitive Load Stability

RL = ∞

Short-Circuit Current6

40 mA

Output Voltage Noise Density4

240 nV/√Hz

At TA, f = 10 kHz, CL = 10 nF

Thermal Hysteresis4

125 ppm

First cycle

SPECIFICATIONS

VDD = 2.7 V to 5.5 V; V

Table 2.

Parameter Min Typ Max Unit Test Conditions/Comments

STATIC PERFORMANCE3

Relative Accuracy ±0.12 ±0.5 LSB Differential Nonlinearity ±0.5 LSB Guaranteed monotonic by design Zero-Code Error 0.4 1.5 mV All 0s loaded to DAC register Offset Error +0.1 ±1.5 mV

Gain Error ±0.02 ±0.1 % of FSR Total Unadjusted Error ±0.01 ±0.1 % of FSR External reference, gain = 2, TSSOP ±0.2 % of FSR Internal reference, gain = 1, TSSOP Offset Error Drift4 ±1 µV/°C Gain Temperature Coefficient4 ±1 ppm Of FSR/°C

= 2.5 V; 1.8 V ≤ V

REF

≤ 5.5 V; RL = 2 kΩ; CL = 200 pF; all specifications T

LOGIC

MIN

to T

, unless otherwise noted.

MAX

1, 2

DC Crosstalk4 ±2 µV

Due to single channel, full-scale output

change ±3 µV/mA Due to load current change ±2 µV Due to power-down (per channel) OUTPUT CHARACTERISTICS4

Output Voltage Range 0 V 0 2 × V

V Gain = 1

REF

V Gain = 2 (see Figure 26)

REF

10 nF RL = 1 kΩ Resistive Load5 1 kΩ Load Regulation DAC code = midscale 80 µV/mA 5 V ± 10%; −30 mA ≤ I 80 µV/mA 3 V ± 10%; −20 mA ≤ I

≤ +30 mA

OUT

≤ +20 mA

OUT

Load Impedance at Rails7 25 Ω See Figure 26 Power-Up Time 2.5 µs Coming out of power-down mode; VDD = 5 V

REFERENCE OUTPUT

Output Voltage8 2.4975 2.5025 V At TA Reference TC9 2 5 ppm/°C See the Terminology section Output Impedance4 0.04 Ω Output Voltage Noise4 12 µV p-p 0.1 Hz to 10 Hz

Load Regulation, Sourcing4 20 µV/mA At TA Load Regulation, Sinking4 40 µV/mA At TA Output Current Load Capability4 ±5 mA VDD ≥ 3 V Line Regulation4 100 µV/V At TA Long-Term Stability/Drift4 12 ppm After 1000 hours at 125°C

25 ppm Additional cycles LOGIC INPUTS4

Input Current ±2 µA Per pin Input Low Voltage, V Input High Voltage, V Pin Capacitance 2 pF

0.3 × V

INL

0.7 × V

INH

LOGI C

Rev. A | Page 3 of 24

LOGI C

AD5316R Data Sheet

+ 1.5

5.5 V Gain = 2

Total Harmonic Distortion4

−80 dB

At TA, BW = 20 kHz, VDD = 5 V, f

= 1 kHz

Parameter Min Typ Max Unit Test Conditions/Comments

1, 2

LOGIC OUTPUTS (SDA)4

Output Low Voltage, VOL 0.4 V I

= 3 mA

SINK

Floating State Output Capacitance 4 pF

POWER REQUIREMENTS

1.8 5.5 V

LOGI C

3 µA

LOGI C

VDD 2.7 5.5 V Gain = 1

REF

IDD VIH = VDD, VIL = GND, VDD = 2.7 V to 5.5 V

Normal Mode10 0.59 0.7 mA Internal reference off

1.1 1.3 mA Internal reference on, at full scale All Power-Down Modes11 1 4 µA −40°C to +85°C

6 µA −40°C to +105°C

Temperature range is −40°C to +105°C.

The AD5316R and the AD5316 are not pin-to-pin or software compatible.

DC specifications are tested with the outputs unloaded, unless otherwise noted. Upper dead band (10 mV) exists only when V

with gain = 2. Linearity calculated using a reduced code range of 4 to 1020.

Guaranteed by design and characterization; not production tested.

Channel A and Channel B can have a combined output current of up to 30 mA. Similarly, Channel C and Channel D can have a combined output current of up to

30 mA up to a junction temperature of 110°C.

VDD = 5 V. The device includes current limiting that is intended to protect the device during temporary overload conditions. Junction temperature can be exceeded

during current limit. Operation above the specified maximum junction temperature may impair device reliability.

When drawing a load current at either rail, the output voltage headroom with respect to that rail is limited by the 25 Ω typical channel resistance of the output

devices. For example, when sinking 1 mA, the minimum output voltage = 25 Ω × 1 mA = 25 mV (see Figure 26).

Initial accuracy presolder reflow is ±750 µV; output voltage includes the effects of preconditioning drift. See the Solder Heat Reflow section.

Reference is trimmed and tested at two temperatures and is characterized from −40°C to +105°C. Reference temperature coefficient is calculated as per the box method.

See the Terminology section for more information.

Interface inactive. All DACs active. DAC outputs unloaded.

All DACs powered down.

= VDD with gain = 1 or when V

REF

/2 = VDD

REF

AC CHARACTERISTICS

VDD = 2.7 V to 5.5 V; V

Table 3.

Parameter

1, 2

Min Typ Max Unit Test Conditions/Comments3

Output Voltage Settling Time 5 7 µs ¼ to ¾ scale settling to ±1 LSB Slew Rate 0.8 V/µs Digital-to-Analog Glitch Impulse 0.5 nV-sec 1 LSB change around major carry transition Digital Feedthrough 0.13 nV-sec Digital Crosstalk 0.1 nV-sec Analog Crosstalk 0.2 nV-sec DAC-to-DAC Crosstalk 0.3 nV-sec

Output Noise Spectral Density 300 nV/√Hz DAC code = midscale, 10 kHz, gain = 2 Output Noise 6 µV p-p 0.1 Hz to 10 Hz

Guaranteed by design and characterization; not production tested.

See the Terminology section.

Temperature range is −40°C to +105°C; typical at 25°C.

Digitally generated sine wave at 1 kHz.

= 2.5 V; 1.8 V ≤ V

REF

≤ 5.5 V; RL = 2 kΩ; CL = 200 pF; all specifications T

LOGIC

MIN

to T

, unless otherwise noted.

MAX

OUT

Rev. A | Page 4 of 24

Data Sheet AD5316R

0 0.9

µs

, data hold time

t12

20 ns

SCL

SDA

LDAC

START CONDITION

REPEATED START CONDITION

STOP CONDITION

NOTES

ASYNCHRONOUS LDAC UPDATE MO DE .

SYNCHRONOUS LDAC UPDATE MO DE .

10819-002

TIMING CHARACTERISTICS

VDD = 2.7 V to 5.5 V; 1.8 V ≤ V

≤ 5.5 V; all specifications T

LOGIC

MIN

to T

, unless otherwise noted.

MAX

Table 4.

Parameter

1, 2

Min Max Unit Description

t1 2.5 µs SCL cycle time t2 0.6 µs t t3 1.3 µs t t4 0.6 µs t t5 100 ns t

t7 0.6 µs t t8 0.6 µs t t9 1.3 µs t

0 300 ns tR, rise time of SCL and SDA when receiving

4, 5

20 + 0.1CB 300 ns tF, fall time of SCL and SDA when transmitting/receiving

, SCL high time

HIGH

, SCL low time

LOW

, start/repeated start hold time

HD,STA

, data setup time

SU ,DAT

HD,DAT

, repeated start setup time

SU,STA

, stop condition setup time

SU,STO

, bus free time between a stop condition and a start condition

BUF

LDAC pulse width

t13 400 ns

0 50 ns Pulse width of suppressed spike

400 pF Capacitive load for each bus line

See Figure 2.

Guaranteed by design and characterization; not production tested.

A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH min of the SCL signal) to bridge the undefined region of the SCL

falling edge.

tR and tF are measured from 0.3 × VDD to 0.7 × VDD.

CB is the total capacitance of one bus line in pF.

Input filtering on the SCL and SDA inputs suppresses noise spikes that are less than 50 ns.

SCL rising edge to

LDAC rising edge

Timing Diagram

Figure 2. 2-Wire Serial Interface Timing Diagram

Rev. A | Page 5 of 24

AD5316R Data Sheet

Human Body Model (HBM)

3.5 kV

16-Lead LFCSP

°C/W

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 5.

Parameter Rating

VDD to GND −0.3 V to +7 V V

to GND −0.3 V to +7 V

LOGI C

to GND −0.3 V to VDD + 0.3 V

OUT

to GND −0.3 V to VDD + 0.3 V

REF

Digital Input Voltage to GND1 −0.3 V to V SDA and SCL to GND −0.3 V to +7 V Operating Temperature Range −40°C to +105°C Storage Temperature Range −65°C to +150°C Junction Temperature 125°C Reflow Soldering Peak Temperature,

Pb Free (J-STD-020)

ESD

260°C

LOGI C

+ 0.3 V

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. This value was measured using a JEDEC standard 4-layer board with zero airflow. For the LFCSP package, the exposed pad must be tied to GND.

Table 6. Thermal Resistance

Package Type θJA Unit

16-Lead TSSOP 112.6 °C/W

ESD CAUTION

Field-Induced Charged Device

Model (FICDM)

Excluding SDA and SCL.

1.5 kV

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Rev. A | Page 6 of 24

Data Sheet AD5316R

5 7 V

Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.

RSTSEL

12 11 10

3 4

A1 SCL A0

LOGIC

OUT

GND

OUT

SDA

OUT

LDAC

GAIN

OUT

REF

RSTSEL

RESET

AD5316R

NOTES

1. THE EXPOSED PAD MUST BE TIED TO GND.

TOP VIEW

(Not to S cale)

10819-006

OUT

GND

OUT

REF

SDA

RESET A1 SCL

GAIN LDAC

LOGIC

RSTSEL

TOP VIEW

(Not to S cale)

AD5316R

10819-007

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

Figure 3. 16-Lead LFCSP Pin Configuration

Table 7. Pin Function Descriptions

Pin No.

Mnemonic Description LFCSP TSSOP

1 3 V

A Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.

OUT

2 4 GND Ground Reference Point for All Circuitry on the Part. 3 5 VDD

Power Supply Input. The part can be operated from 2.7 V to 5.5 V. The supply should be decoupled with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND.

4 6 V

6 8 SDA

C Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.

OUT

Serial Data Input. This pin is used in conjunction with the SCL line to clock data into or out of the 24-bit input shift register. SDA is a bidirectional, open-drain data line that should be pulled to the supply with an external pull-up resistor.

7 9

LDAC LDAC can be operated in two modes, asynchronous update mode and synchronous update mode.

Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data; all DAC outputs are simultaneously updated. This pin can also be tied permanently low.

8 10 GAIN

Gain Select Pin. When this pin is tied to GND, all four DAC outputs have a span of 0 V to V When this pin is tied to V

9 11 V

Digital Power Supply. Voltage ranges from 1.8 V to 5.5 V.

LOGI C

10 12 A0 Address Input. Sets the first LSB of the 7-bit slave address. 11 13 SCL

Serial Clock Line. This pin is used in conjunction with the SDA line to clock data into or out of the

24-bit input shift register. 12 14 A1 Address Input. Sets the second LSB of the 7-bit slave address. 13 15

RESET Asynchronous Reset Input. The RESET input is falling edge sensitive. When RESET is activated

(low), the input register and the DAC register are updated with zero scale or midscale, depending

on the state of the RSTSEL pin. When

15 1 V

16 2 V 17 N/A EPAD Exposed Pad. The exposed pad must be tied to GND.

REF

B Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.

OUT

Power-On Reset Pin. When this pin is tied to GND, all four DACs are powered up to zero scale.

When this pin is tied to V

Reference Voltage. The AD5316R has an internal reference. When the internal reference is used,

is the reference output pin. When an external reference is used, V

REF

pin. By default, the internal reference is used, and this pin is a reference output.

Rev. A | Page 7 of 24

Figure 4. 16-Lead TSSOP Pin Configuration

, all four DAC outputs have a span of 0 V to 2 × V

RESET is low, all LDAC pulses are ignored.

, all four DACs are powered up to midscale.

REF

is the reference input

REF

AD5316R Data Sheet

–40 –20 0 20 40 60 80 100 120

REF

(V)

TEMPERATURE (°C)

DEVICE 1 DEVICE 2 DEVICE 3 DEVICE 4 DEVICE 5

2.4980

2.4985

2.4990

2.4995

2.5000

2.5005

2.5010

2.5015

2.5020 V

= 5V

10819-212

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

NUMBER OF UNI TS

TEMPERAT URE DRIFT (ppm/°C)

VDD = 5V

10819-250

2.498 2.499 2.500 2.501 2.502

HITS

REF

(V)

0 HOUR 168 HOURS 500 HOURS 1000 HOURS

VDD = 5.5V

10819-251

1600

200

400

600

800

1000

1200

1400

10 100 1k 10k 100k 1M

NSD (nV/ Hz)

FREQUENCY ( Hz )

= 5V

= 25°C

10819-111

CH1 2µV M1.0s

= 5V

= 25°C

10819-112

2.5000

2.4999

2.4998

2.4997

2.4996

2.4995

2.4994

2.4993 –0.005 –0.003 –0.001 0.001 0.003 0.005

REF

(V)

LOAD

(A)

VDD = 5V T

= 25°C

10819-113

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 5. Internal Reference Voltage vs. Temperature

Figure 6. Reference Output Temperature Drift Histogram

Figure 8. Internal Reference Noise Spectral Density vs. Frequency

Figure 9. Internal Reference Noise, 0.1 Hz to 10 Hz

Figure 7. Reference Long-Term Stability (Drift)

Figure 10. Internal Reference Voltage vs. Load Current

Rev. A | Page 8 of 24

Data Sheet AD5316R

2.5002

2.5000

2.4998

2.4996

2.4994

2.4992

2.4990

2.5 3.0 3.5 4.0 4.5 5.0 5.5

REF

(V)

SUPPLY VOLTAGE (V)

TA = 25°C

10819-117

DEVICE 1

DEVICE 3

DEVICE 2

10819-118

0.5

–0.5

–0.3

–0.1

0.1

0.3

0 156 312 468 624 780 936

INL (LSB)

CODE

VDD = 5V T

= 25°C

INTERNAL RE FERENCE = 2.5V

DNL (LSB)

CODE

10819-119

0.5

–0.5

–0.3

–0.1

0.1

0.3

CODE

0 156 312 468 624 780 936

VDD = 5V T

= 25°C

INTERNAL RE FERENCE = 2.5V

–10

–8

–6

–4

–2

–40 1106010

ERROR (LSB)

TEMPERATURE (°C)

INL

DNL

= 5V

= 25°C

INTERNAL RE FERENCE = 2.5V

10819-124

–10

–8

–6

–4

–2

0 5.04.54.03.53.02.52.01.51.00.5

ERROR (LSB)

REF

(V)

INL

DNL

VDD = 5V T

= 25°C

10819-125

–10

–8

–6

–4

–2

2.7 5.24.74.23.73.2

ERROR (LSB)

SUPPLY VOLTAGE (V)

INL

DNL

VDD = 5V T

= 25°C

INTERNAL RE FERENCE = 2.5V

10819-126

Figure 11. Internal Reference Voltage vs. Supply Voltage

Figure 12. INL

Figure 14. INL Error and DNL Error vs. Temperature

Figure 15. INL Error and DNL Error vs. V

REF

Figure 13. DNL

Figure 16. INL Error and DNL Error vs. Supply Voltage

Rev. A | Page 9 of 24

AD5316R Data Sheet

0.10

–0.10

–0.08

–0.06

–0.04

–0.02

0.02

0.04

0.06

0.08

–40 –20 0 20 40 60 80 100 120

ERROR (% of FSR)

TEMPERATURE (°C)

GAIN ERROR

FULL-S CALE ERROR

= 5V

= 25°C

INTERNAL RE FERENCE = 2.5V

10819-127

1.4

1.2

1.0

0.8

0.6

0.4

0.2

–40 –20 0 20 40 60 80 100 120

ERROR (mV)

TEMPERATURE (°C)

OFFSET ERROR

ZERO-CO DE E RROR

= 5V

= 25°C

INTERNAL RE FERENCE = 2.5V

10819-128

0.10

–0.10

–0.08

–0.06

–0.04

–0.02

0.02

0.04

0.06

0.08

2.7 5.24.74.23.73.2

ERROR (% of FSR)

SUPPLY VOLTAGE (V)

GAIN ERROR

FULL-S CALE ERROR

VDD = 5V T

= 25°C

INTERNAL RE FERENCE = 2.5V

10819-129

1.5

–1.5

–1.0

–0.5

0.5

1.0

2.7 5.24.74.23.73.2

ERROR (mV)

SUPPLY VOLTAGE (V)

ZERO-CO DE E RROR

OFFSET ERROR

= 5V

= 25°C

INTERNAL RE FERENCE = 2.5V

10819-130

0.10

0.09

0.08

0.07

0.06

0.05

0.04

0.03

0.02

0.01

–40 –20 0

20 40 60 80 100 120

TOTAL UNADJUS TED ERROR (% of FSR)

TEMPERATURE (°C)

VDD = 5V T

= 25°C

INTERNAL RE FERENCE = 2.5V

10819-131

0.10

0.08

0.06

0.04

0.02

–0.02

–0.04

–0.06

–0.08

–0.10

2.7 5.24.74.23.73.2

TOTAL UNADJUS TED ERROR (% of FSR)

SUPPLY VOLTAGE (V)

VDD = 5V T

= 25°C

INTERNAL RE FERENCE = 2.5V

10819-132

Figure 17. Gain Error and Full-Scale Error vs. Temperature

Figure 18. Zero-Code Error and Offset Error vs. Temperature

Figure 20. Zero-Code Error and Offset Error vs. Supply Voltage

Figure 21. TUE vs. Temperature

Figure 19. Gain Error and Full-Scale Error vs. Supply Voltage

Figure 22. TUE vs. Supply Voltage, Gain = 1

Rev. A | Page 10 of 24

Data Sheet AD5316R

10819-133

–0.01

–0.02

–0.03

–0.04

–0.05

–0.06

–0.07

–0.08

–0.09

–0.10

0 156 312 468 624 780 936 1023

TOTAL UNADJUS TED ERROR (% of FSR)

CODE

VDD = 5V T

= 25°C

INTERNAL RE FERENCE = 2.5V

540 560 580 600 620 640

HITS

(mA)

= 5V

= 25°C EXTERNAL REFERENCE = 2. 5V

10819-135

1000 1020 1040 1060 1080 1100 1120 1140

HITS

IDD FULL SCALE (mA)

= 5V

= 25°C INTERNAL REFERENCE = 2. 5V

10819-136

1.0

–1.0

–0.8

–0.6

–0.4

–0.2

0.2

0.4

0.6

0.8

0 5 10 15 20 25 30

ΔV

OUT

(V)

LOAD CURRENT ( mA)

SOURCING, 2.7V

SOURCING, 5V

SINKING, 2.7V

SINKING, 5V

10819-200

–2

–1

–0.06 –0.04 –0.02 0 0.02 0.04 0.06

OUT

(V)

LOAD CURRENT ( A)

0xFFFF

0x4000

0x8000

0xC000

0x0000

VDD = 5V T

= 25°C INTERNAL REFERENCE = 2. 5V GAIN = 2

10819-138

–2

–1

–0.06 –0.04 –0.02 0 0.02 0.04 0.06

OUT

(V)

LOAD CURRENT ( A)

0xFFFF

0x4000

0x8000

0xC000

0x0000

= 3V

= 25°C EXTERNAL RE FERENCE = 2.5V GAIN = 1

10819-139

Figure 23. TUE vs. Code

Figure 24. IDD Histogram with External Reference, 5 V

Figure 26. Headroom/Footroom vs. Load Current

Figure 27. Source and Sink Capability at 5 V

Figure 25. I

Histogram with Internal Reference, V

= 2.5 V, Gain = 2

REF

Figure 28. Source and Sink Capability at 3 V

Rev. A | Page 11 of 24

AD5316R Data Sheet

0.2

0.4

0.6

0.8

1.0

1.2

1.4

–40 1106010

CURRENT (mA)

TEMPERATURE (°C)

FULL-SCALE

ZERO CODE

EXTERNAL RE FERENCE, FULL-SCALE

10819-140

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

10 32016040 8020

OUT

(V)

TIME (µs)

OUT

= 5V

= 25°C INTERNAL RE FERENCE = 2.5V ¼ TO ¾ SCALE

10819-141

–0.01

0.06

0.01

0.02

0.03

0.04

0.05

–1

–10 15100 5–5

OUT

(V)

TIME (µs)

OUT

= 25°C INTERNAL RE FERENCE = 2.5V

10819-142

–5 100 5

OUT

(V)

TIME (µs)

OUT

= 5V

= 25°C

INTERNAL RE FERENCE = 2.5V

GAIN = 1

GAIN = 2

10819-143

2.4988

2.5008

2.5003

2.4998

2.4993

0 128 104 62

OUT

(V)

TIME (µs)

CHANNEL B T

= 25°C

= 5.25V INTERNAL RE FERENCE = 2.5V CODE = 0x7FF F TO 0x8000 ENERGY = 0. 227206nV-sec

10819-144

–0.002

–0.001

0.001

0.002

0.003

0 252010 155

OUT

AC-COUPLED ( V )

TIME (µs)

10819-145

OUT

Figure 29. Supply Current vs. Temperature

Figure 32. Exiting Power-Down to Midscale

Figure 30. Settling Time

Figure 31. Power-On Reset to 0 V

Figure 33. Digital-to-Analog Glitch Impulse

Figure 34. Analog Crosstalk, V

Rev. A | Page 12 of 24

OUT

Data Sheet AD5316R

CH1 10µV M1.0s A CH1 802mV

= 5V

= 25°C

EXTERNAL RE FERENCE = 2.5V

10819-146

CH1 10µV M1.0s A CH1 802mV

= 5V

= 25°C

INTERNAL RE FERENCE = 2.5V

10819-147

200

400

600

800

1000

1200

1400

1600

10 1M100k1k 10k100

NSD (nV/ Hz)

FREQUENCY ( Hz )

FULL-SCALE MIDSCALE ZERO-SCALE

= 5V

= 25°C

INTERNAL RE FERENCE = 2.5V

10819-148

–180

–160

–140

–120

–100

–80

–60

–40

–20

0 20000160008000 1200040002000 1800010000 140006000

THD (dBV)

FREQUENCY ( Hz )

VDD = 5V T

= 25°C

INTERNAL RE FERENCE = 2.5V

10819-149

3.0

3.1

3.2

3.3

3.4

3.5

3.6

3.7

3.8

3.9

4.0

1.590 1.6301.6201.600 1.610 1.6251.605 1.6151.595

OUT

(V)

TIME (ms)

0nF

0.1nF

0.22nF

4.7nF 10nF

VDD = 5V T

= 25°C

INTERNAL RE FERENCE = 2.5V

10819-150

Figure 35. 0.1 Hz to 10 Hz Output Noise Plot, 2.5 V External Reference

Figure 36. 0.1 Hz to 10 Hz Output Noise Plot, 2.5 V Internal Reference

Figure 38. Total Harmonic Distortion at 1 kHz

Figure 39. Settling Time vs. Capacitive Load

Figure 37. Noise Spectral Density

Rev. A | Page 13 of 24

AD5316R Data Sheet

TERMINOLOGY

Relative Accuracy or Integral Nonlinearity (INL)

Relative accuracy or integral nonlinearity is a measurement of the maximum deviation, in LSBs, from a straight line passing through the endpoints of the DAC transfer function. Figure 12 shows a typical INL vs. code plot.

Differential Nonlinearity (DNL)

Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ±1 LSB maximum ensures monotonicity. The AD5316R is guaranteed monotonic by design. Figure 13 shows a typical DNL vs. code plot.

Zero-Code Error

Zero-code error is a measurement of the output error when zero code (0x0000) is loaded to the DAC register. Ideally, the output should be 0 V. The zero-code error is always positive in the AD5316R because the output of the DAC cannot go below 0 V due to a combination of the offset errors in the DAC and the output amplifier. Zero-code error is expressed in mV. Figure 18 shows a plot of zero-code error vs. temperature.

Full-Scale Error

Full-scale error is a measurement of the output error when fullscale code (0xFFFF) is loaded to the DAC register. Ideally, the output should be V

− 1 LSB. Full-scale error is expressed as a

percentage of the full-scale range (% of FSR). Figure 17 shows a plot of full-scale error vs. temperature.

Gain Error

Gain error is a measurement of the span error of the DAC. It is the deviation in slope of the DAC transfer characteristic from the ideal expressed in % of FSR.

Gain Temperature Coefficient

Gain temperature coefficient is a measurement of the change in gain error with changes in temperature. It is expressed in ppm of FSR/°C.

Offset Error

Offset error is a measurement of the difference between V (actual) and V

(ideal) expressed in mV in the linear region

OUT

of the transfer function. It can be negative or positive.

Offset Error Drift

Offset error drift is a measurement of the change in offset error with changes in temperature. It is expressed in µV/°C.

DC Power Supply Rejection Ratio (PSRR)

DC PSRR indicates how the output of the DAC is affected by changes in the supply voltage. PSRR is the ratio of the change in V

to a change in VDD for midscale output of the DAC. It

OUT

is measured in mV/V. V

is held at 2.5 V, a nd VDD is varied

REF

by ±10%.

Rev. A | Page 14 of 24

Output Voltage Settling Time

The output voltage settling time is the amount of time it takes for the output of a DAC to settle to a specified level for a ¼ to ¾ full-scale input change.

Digital-to-Analog Glitch Impulse

Digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the DAC register changes state. It is normally specified as the area of the glitch in nV-sec, and is measured when the digital input code is changed by 1 LSB at the major carry transition (0x7FFF to 0x8000) (see Figure 33).

Digital Feedthrough

Digital feedthrough is a measurement of the impulse injected into the analog output of the DAC from the digital inputs of the DAC, but is measured when the DAC output is not updated. It is specified in nV-sec and measured with a full-scale code change on the data bus, that is, from all 0s to all 1s and vice versa.

Noise Spectral Density (NSD)

Noise spectral density is a measurement of the internally generated random noise. Random noise is characterized as a spectral density (nV/√Hz) and is measured by loading the DAC to midscale and measuring noise at the output. It is measured in nV/√Hz. Figure 37 shows a plot of noise spectral density.

DC Crosstalk

DC crosstalk is the dc change in the output level of one DAC in response to a change in the output of another DAC. It is measured with a full-scale output change on one DAC (or soft power-down and power-up) while monitoring another DAC kept at midscale. It is expressed in μV.

DC crosstalk due to load current change is a measurement of the impact that a change in load current on one DAC has on another DAC kept at midscale. It is expressed in μV/mA.

Digital Crosstalk

Digital crosstalk is the glitch impulse transferred to the output of one DAC at midscale in response to a full-scale code change (all 0s to all 1s and vice versa) in the input register of another DAC. It is expressed in nV-sec.

Analog Crosstalk

Analog crosstalk is the glitch impulse transferred to the output of one DAC in response to a change in the output of another DAC. To measure analog crosstalk, load one of the input registers with a full-scale code change (all 0s to all 1s and vice versa), and then execute a software LDAC and monitor the output of the DAC whose digital code was not changed. The area of the glitch is expressed in nV-sec.

Data Sheet AD5316R

DAC-to-DAC Crosstalk

DAC-to-DAC crosstalk is the glitch impulse transferred to the output of one DAC in response to a digital code change and subsequent analog output change of another DAC. It is measured by loading one channel with a full-scale code change (all 0s to all 1s and vice versa) using the write to and update commands while monitoring the output of another channel that is at midscale. The energy of the glitch is expressed in nV-sec.

Total Harmonic Distortion (THD)

THD is the difference between an ideal sine wave and its attenuated version using the DAC. The sine wave is used as the reference for the DAC; THD is a measurement of the harmonics present on the DAC output. It is measured in dB.

Voltage Reference Temperature Coefficient (TC)

Voltage reference TC is a measurement of the change in the reference output voltage with a change in temperature. The reference TC is calculated using the box method, which defines the TC as the maximum change in the reference output over a given temperature range expressed in ppm/°C, as follows:



 

REFnom



−

REFminREFmax

TempRangeV



10×

 



where:

is the maximum reference output measured over the

REFmax

total temperature range.

is the minimum reference output measured over the total

REFmin

temperature range.

is the nominal reference output voltage, 2.5 V.

REFnom

TempRange is the specified temperature range of −40°C to

+105°C.

Rev. A | Page 15 of 24

AD5316R Data Sheet













×=

REF

OUT

GainVV

INPUT

2.5V REF

DAC

RESISTOR

STRING

REF (+)

REF

GND

REF (–)

OUT

GAIN

(GAIN = 1 OR 2)

10819-052

TO OUTPUT AMPLIFIER

REF

10819-053

THEORY OF OPERATION

DIGITAL-TO-ANALOG CONVERTER

The AD5316R is a quad, 10-bit, serial input, voltage output DAC with an internal reference. The part operates from supply voltages of 2.7 V to 5.5 V. Data is written to the AD5316R in a 24-bit word format via a 2-wire serial interface. The AD5316R incorporates a power-on reset circuit to ensure that the DAC output powers up to a known output state. The device also has a software power-down mode that reduces the typical current consumption to 1 µA.

TRANSFER FUNCTION

The internal reference is on by default. Because the input coding to the DAC is straight binary, the ideal output voltage when using an external reference is given by

where:

is the value of the external reference.

REF

Gain is the gain of the output amplifier and is set to 1 by default.

The gain can be set to 1 or 2 using the gain select pin. When the GAIN pin is tied to GND, all four DAC outputs have a span of 0 V to V have a span of 0 V to 2 × V

. When this pin is tied to VDD, all four DAC outputs

REF

D is the decimal equivalent of the binary code that is loaded to the DAC register (0 to 1023). N is the DAC resolution (10 bits).

DAC ARCHITECTURE

The DAC architecture consists of a string DAC followed by an output amplifier. Figure 40 shows a block diagram of the DAC architecture.

Figure 40. Single DAC Channel Architecture Block Diagram

The resistor string structure is shown in Figure 41. Each resistor in the string has a value R. The code loaded to the DAC register determines the node on the string from which the voltage is tapped off and fed into the output amplifier. The voltage is tapped off by closing one of the switches that connect the string to the amplifier. Because the AD5316R is a string of resistors, it is guaranteed monotonic.

Figure 41. Resistor String Structure

Internal Reference

The AD5316R on-chip reference is on at power-up but can be disabled via a write to a control register. For more information, see the Internal Reference Setup section.

The 2.5 V, 2 ppm/°C internal reference provides a full-scale output of 2.5 V or 5 V, depending on the state of the GAIN pin. The internal reference is available at the V

pin. This buffered

REF

reference is capable of driving external loads of up to 10 mA.

Output Amplifiers

The output buffer amplifier can generate rail-to-rail voltages on its output for an output range of 0 V to V depends on the value of V

, the GAIN pin, the offset error,

REF

. The actual range

and the gain error. The GAIN pin selects the gain of the output.

• When this pin is tied to GND, all four outputs have a gain

of 1, and the output range is from 0 V to V

• When this pin is tied to V

, all four outputs have a gain

of 2, and the output range is from 0 V to 2 × V

REF

The output amplifiers are capable of driving a load of 1 kΩ in parallel with 2 nF to GND. The slew rate is 0.8 V/µs with a ¼ to ¾ scale settling time of 5 µs.

Rev. A | Page 16 of 24

Data Sheet AD5316R

0 1 1 1 Internal reference setup register

1 1 1 1 All DACs

DB23 DB22 DB21

DB20

DB19 DB18 DB17

DB16

DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4

DB3

DB2 DB1 DB0

C3 C2 C1 C0 DAC D DAC C DAC B DAC A D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X

COMMAND DAC ADDRESS DAC DATA DAC DATA

COMMAND BYTE DATA HIGH BYTE DATA LOW BYTE

10819-300

SERIAL INTERFACE

The AD5316R has a 2-wire, I2C-compatible serial interface (see

C-Bus Specification, Version 2.1, January 2000, available

the I from Philips Semiconductor). See Figure 2 for a timing diagram of a typical write sequence. The AD5316R can be connected to

an I

C bus as a slave device, under the control of a master device. The AD5316R supports standard (100 kHz) and fast (400 kHz) data transfer modes. Support is not provided for 10-bit addressing or general call addressing.

Input Shift Register

The input shift register of the AD5316R is 24 bits wide. Data is loaded into the device, MSB first, as a 24-bit word under the control of the serial clock input, SCL. The input shift register consists of an 8-bit command byte and a 16-bit data-word (see Figure 42). The first eight MSBs make up the command byte.

• The first four bits of the command byte are the command

bits (C3, C2, C1, and C0), which control the mode of operation of the device (see Tab le 8).

• The last four bits of the command byte are the address bits

(DAC D, DAC C, DAC B, and DAC A), which select the DAC that is operated on by the command (see Tabl e 9).

Table 8. Command Definitions

Command Bits

C3 C2 C1 C0 Command

0 0 0 0 No operation 0 0 0 1

0 0 1 0

0 0 1 1 Write to and update DAC Channel n 0 1 0 0 Power down/power up DAC 0 1 0 1 0 1 1 0 Software reset (power-on reset)

1 X1 X1 X1 Reserved

X = don’t care.

Write to Input Register n (dependent

LDAC)

on Update DAC Register n with contents

of Input Register n

Hardware

LDAC mask register

Table 9. Address Bits and Selected DACs

Address Bits

Selected DAC Channels

0 0 0 1 DAC A 0 0 1 0 DAC B 0 0 1 1 DAC A and DAC B 0 1 0 0 DAC C 0 1 0 1 DAC A and DAC C 0 1 1 0 DAC B and DAC C 0 1 1 1 DAC A, DAC B, and DAC C 1 0 0 0 DAC D 1 0 0 1 DAC A and DAC D … … … … …

Any combination of DAC channels can be selected using the address bits.

The 8-bit command byte is followed by two data bytes, which contain the data-word. The data-word comprises the 10-bit input code, followed by six don’t care bits (see Figure 42). The data bits are transferred to the input register on the 24 falling edges of SCL.

Commands can be executed on one DAC channel, any two or three DAC channels, or on all four DAC channels, depending on the address bits selected (see Table 9).

WRITE AND UPDATE COMMANDS

For more information about the

LDAC

DAC (Hardware

Pin) section.

Write to Input Register n (Dependent on

Command 0001 allows the user to write to each DAC’s dedicated input register individually. When input register is transparent (if not controlled by the mask register).

Update DAC Register n with Contents of Input Register n

Command 0010 loads the DAC registers/outputs with the contents of the input registers selected by the address bits (see Tabl e 9) and updates the DAC outputs directly.

Write to and Update DAC Channel n (Independent of

Command 0011 allows the user to write to the DAC registers and update the DAC outputs directly, independent of the state

LDAC

of the

pin.

LDAC

function, see the Load

LDAC

)

is low, the

LDAC

)

DAC D DAC C DAC B DAC A

Figure 42. Input Shift Register Contents

Rev. A | Page 17 of 24

AD5316R Data Sheet

GND 1 0

FRAME 2

COMMAND BYTE

FRAME 1

SLAVE ADDRESS

1 9 91

SCL

START BY

MASTER

ACK BY

AD5316R

ACK BY

AD5316R

SDA

R/W

DB23A0A11000 1 DB22 DB21 DB20 DB19 DB18 DB17 DB16

1 9 91

ACK BY

AD5316R

ACK BY

AD5316R

FRAME 4

LEAST SIGNIFICANT

DATA BYTE

FRAME 3

MOST SIGNIFICANT

DATA BYTE

STOP BY MASTER

SCL

(CONTINUED)

SDA

(CONTINUED)

DB15 DB14 DB13 DB12 DB11 DB10 DB9

DB8

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

10819-303

I2C SLAVE ADDRESS

The AD5316R has a 7-bit I2C slave address. The five MSBs are 00011 and the two LSBs (A1 and A0) are set by the state of the A1 and A0 address pins. The ability to make hardwired changes to A1 and A0 allows the user to incorporate up to four AD5316R devices on one bus (see Table 10).

Table 10. Device Address Selection

A1 Pin Connection A0 Pin Connection A1 Bit A0 Bit

GND GND 0 0 GND V

LOGI C

0 1

LOGI C

1 1

LOGI C

SERIAL OPERATION

The 2-wire I2C serial bus protocol operates as follows:

1. The master initiates a data transfer by establishing a start

condition when a high-to-low transition on the SDA line occurs while SCL is high. The following byte is the address byte, which consists of the 7-bit slave address.

2. The slave device with the transmitted address responds by

pulling SDA low during the 9 the acknowledge bit). At this stage, all other devices on the bus remain idle while the selected device waits for data to be written to, or read from, its input shift register.

clock pulse (this is called

3. Data is transmitted over the serial bus in sequences of nine

clock pulses (eight data bits followed by an acknowledge bit). Transitions on the SDA line must occur during the low period of SCL; SDA must remain stable during the high period of SCL.

4. After all data bits are read or written, a stop condition is

established. In write mode, the master pulls the SDA line high during the 10 read mode, the master issues a no acknowledge for the 9

clock pulse to establish a stop condition. In

clock pulse (that is, the SDA line remains high). The master then brings the SDA line low before the 10 then high again during the 10

clock pulse to establish a

clock pulse and

stop condition.

WRITE OPERATION

When writing to the AD5316R, the user must begin with a start

command followed by an address byte (R/ DAC acknowledges that it is prepared to receive data by pulling SDA low. The AD5316R requires two bytes of data for the DAC and a command byte that controls various DAC functions. Three bytes of data must, therefore, be written to the DAC with the command byte followed by the most significant data byte and the least significant data byte, as shown in Figure 43. All these data bytes are acknowledged by the AD5316R. A stop condition follows.

= 0), after which the

Figure 43. I

C Write Operation

Rev. A | Page 18 of 24

Data Sheet AD5316R

FRAME 2

COMMAND BYTE

FRAME 1

SLAVE ADDRESS

1000 1 A1 A0 R/W DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16

9 91

START BY

MASTER

ACK BY

AD5316R

ACK BY

AD5316R

SCL

SDA

1 9 91

ACK BY

AD5316R

REPEATED START BY MASTER

ACK BY

MASTER

FRAME 4

MOST SIGNIFICANT

DATA BYTE n

FRAME 3

SLAVE ADDRESS

ACK BY

MASTER

NACK BY

MASTER

STOP BY MASTER

FRAME 6

MOST SIGNIFICANT

DATA BYTE n + 1

FRAME 5

LEAST SIGNIFICANT

DATA BYTE n

1000 1 A1 A0 R/W DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8

SDA

SCL

(CONTINUED)

SDA

(CONTINUED)

DB7 DB6 DB5 DB4 DB3 DB2 DB1

DB0

DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8

10819-304

READ OPERATION

When reading data back from the AD5316R, the user must begin

with a start command followed by an address byte (R/ which the DAC acknowledges that it is prepared to receive data by pulling SDA low. The address byte must be followed by the command byte, which determines both the read command that is to follow and the pointer address to read from; the command byte is also acknowledged by the DAC. The user configures the channel to read back the contents of one or more DAC registers and sets the readback command to active using the command byte.

Following this, the master establishes a repeated start condition, and the address is resent with R/

= 1. This byte is acknowledged by the DAC, indicating that it is prepared to transmit data. Two bytes of data are then read from the DAC, as shown in Figure 44. A NACK condition from the master, followed by a stop condition, completes the read sequence. If more than one DAC is selected, Channel A is read back by default.

= 0), after

MULTIPLE DAC READBACK SEQUENCE

When reading data back from multiple AD5316R DACs, the

user begins with an address byte (R/ DAC acknowledges that it is prepared to receive data by pulling SDA low. The address byte must be followed by the command byte, which is also acknowledged by the DAC. The user selects the first channel to read back using the command byte.

Following this, the master establishes a repeated start condition, and the address is resent with R/ by the DAC, indicating that it is prepared to transmit data. The first two bytes of data are then read from DAC Input Register n (selected using the command byte), most significant byte first, as shown in Figure 44. The next two bytes read back are the contents of DAC Input Register n + 1, and the next bytes read back are the contents of DAC Input Register n + 2. Data is read from the DAC input registers in this auto-incremented fashion until a NACK followed by a stop condition follows. If the contents of DAC Input Register D are read out, the next two bytes of data that are read are the contents of DAC Input Register A.

= 0), after which the

= 1. This byte is acknowledged

Figure 44. I

C Read Operation

Rev. A | Page 19 of 24

AD5316R Data Sheet

RESISTOR NETWORK

OUT

DAC

POWER-DOWN

CIRCUITRY

AMPLIFIER

10819-058

SDA

SCL

OUT

DAC

INPUT SHIFT

OUTPUT

AMPLIFIER

LDAC

REF

INPUT

10-BIT

DAC

10819-059

POWER-DOWN OPERATION

Command 0100 is designated for the power-down function. The AD5316R provides three separate power-down modes (see Table 11). These power-down modes are software programmable by setting Bit DB7 to Bit DB0 in the input shift register (see Tabl e 12). Two bits are associated with each DAC channel. Table 11 shows how the state of these two bits corresponds to

= 5 V.

pin.

the mode of operation of the device.

Table 11. Modes of Operation

Operating Mode PDx1 PDx0

Normal Operation 0 0 Power-Down Modes

1 kΩ to GND 0 1 100 kΩ to GND 1 0 Three-State 1 1

Any or all DACs (DAC A to DAC D) can be powered down to the selected mode by setting the corresponding bits in the input shift register. See Table 12 for the contents of the input shift register during the power-down/power-up operation.

When both Bit PDx1 and Bit PDx0 (where x is the DAC selected) in the input shift register are set to 0, the part works normally with its normal power consumption of 1.1 mA at 5 V. When Bit PDx1, Bit PDx0, or both Bit PDx1 and Bit PDx0 are set to 1, the part is in power-down mode. In power-down mode, the supply current falls to 4 μA at 5 V.

In power-down mode, the output stage is internally switched from the output of the amplifier to a resistor network of known values. In this way, the output impedance of the part is known when the part is in power-down mode.

Table 11 lists the three power-down options. The output is connected internally to GND through either a 1 kΩ or a 100 kΩ resistor, or it is left open-circuited (three-state). The output stage is illustrated in Figure 45.

Figure 45. Output Stage During Power-Down

The bias generator, output amplifier, resistor string, and other associated linear circuitry are shut down when power-down mode is activated. However, the contents of the DAC registers are unaffected in power-down mode, and the DAC registers can be updated while the device is in power-down mode. The time required to exit power-down is typically 2.5 µs for V

To reduce the current consumption further, the on-chip reference can be powered off (see the Internal Reference Setup section).

LOAD DAC (HARDWARE LDAC PIN)

The AD5316R DAC has double buffered interfaces consisting of two banks of registers: input registers and DAC registers. The user can write to any combination of the input registers (see Tab le 9). Updates to the DAC registers are controlled by the

Figure 46. Simplified Diagram of Input Loading Circuitry for a Single DAC

LDAC

Table 12. 24-Bit Input Shift Register Contents for Power-Down/Power-Up Operation1

DB23 (MSB) DB22 DB21 DB20 DB19 to DB16

DB15 to DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1

0 1 0 0 X X PDD1 PDD0 PDC1 PDC0 PDB1 PDB0 PDA1 PDA0

X = don’t care.

Command bits (C3 to C0)

Address bits (don’t care)

Don’t care

Power-down select, DAC D

Power-down select, DAC C

Power-down select, DAC B

Power-down select, DAC A

Rev. A | Page 20 of 24

DB0 (LSB)

Data Sheet AD5316R

Instantaneous DAC Updating (

For instantaneous updating of the DACs,

LDAC

Held Low)

LDAC

is held low while data is clocked into the input register using Command 0001. Both the addressed input register and the DAC register are updated on

the 24

clock, and the output begins to change (see Table 14).

Deferred DAC Updating (

For deferred updating of the DACs,

LDAC

Pulsed Low)

LDAC

is held high while data is clocked into the input register using Command 0001. All DAC outputs are asynchronously updated by pulling

clock. The update occurs on the falling edge of

LDAC

low after the LDAC

LDAC MASK REGISTER

Command 0101 is reserved for the software When this command is executed, the address bits are ignored. When writing to the DAC using Command 0101, the 4-bit mask register (DB3 to DB0) is loaded. Bit DB3 of the register corresponds to DAC D; Bit DB2 corresponds to DAC C; Bit DB1 corresponds to DAC B; and Bit DB0 corresponds to DAC A.

The default value of these bits is 0; that is, the normally. Setting any of these bits to 1 forces the selected DAC channel to ignore transitions on the state of the hardware

LDAC

pin. This flexibility is useful in appli-

LDAC

cations where the user wishes to select which channels respond

LDAC

to the

LDAC

The control over the hardware LDAC

ware

pin.

mask register allows the user extra flexibility and

LDAC

pin (see Table 13). Setting the

bit (DB3 to DB0) to 0 for a DAC channel allows the hard-

LDAC

pin to control the updating of that channel.

LDAC

function.

LDAC

mask

LDAC

pin works

pin, regardless of the

Table 13.

LDAC (DB3 to DB0)

0 1 or 0 1 X1

X = don’t care.

HARDWARE RESET PIN (

RESET to either zero scale or midscale. The clear code value is user selectable via the reset select pin (RSTSEL). It is necessary to keep RESET

When the the cleared value until a new value is programmed. The outputs cannot be updated with a new value while the

There is also a software executable reset function that resets the DAC to the power-on reset code. Command 0110 is designated for this software reset function (see Table 8). Any events on LDAC

RESET SELECT PIN (RSTSEL)

The AD5316R contains a power-on reset circuit that controls the output voltage during power-up. When the RSTSEL pin is tied to GND, the outputs power up to zero scale (note that this is outside the linear region of the DAC). When the RSTSEL pin is tied to V remain powered up at the level set by the RSTSEL pin until a valid write sequence is made to the DAC.

LDAC

Overwrite Definition

Load

Bit

LDAC

Operation

LDAC

Determined by the LDAC DAC channels are updated. (DAC

channels see LDAC

RESET

)

pin as 1.)

is an active low reset that allows the outputs to be cleared

low for a minimum of 30 ns to complete the operation.

RESET

signal is returned high, the output remains at

RESET

pin is low.

RESET

during power-on reset are ignored.

, the outputs power up to midscale. The outputs

pin.

Table 14. Write Commands and

Command Description

0001

0010

0011 Write to and update DAC Channel n V

A high to low transition on the hardware

masked (blocked) by the

When the

Write to Input Register n (dependent on LDAC

Update DAC Register n with contents of Input Register n

LDAC

pin is permanently tied low, the

LDAC

mask register.

Pin Truth Table1

)

pin always updates the contents of the DAC register with the contents of the input register on channels that are not

mask bits are ignored.

LDAC

Rev. A | Page 21 of 24

Hardware Pin State

Data update No change (no update)

LOGI C

GND2 Data update Data update

No change

LOGI C

GND No change

Data update Data update

LOGI C

GND Data update Data update

LDAC

Input Register Contents DAC Register Contents

Updated with input register contents

AD5316R Data Sheet

2.498 2.499 2.500 2.501 2.502

HITS

REF

(V)

POSTSOLDER HEAT REFLOW

PRESOLDER HEAT REFLOW

10819-060

2.498 2.499 2.500 2.501 2.502

HITS

REF

(V)

0 HOUR 168 HOURS 500 HOURS 1000 HOURS

10819-061

500–50–100–150–200

HITS

DISTORTION (ppm)

FIRST TEMPERATURE SWEEP SUBSEQUENT TEMPERATURE SWEEPS

10819-062

INTERNAL REFERENCE SETUP

By default, the internal reference is on at power-up. To re duc e the supply current, the on-chip reference can be turned off. Command 0111 is reserved for setting up the internal reference. To turn off the internal reference, set the software programmable bit, DB0, in the input shift register using Command 0111, as shown in Table 16. Tab le 15 shows how the state of the DB0 bit corresponds to the mode of operation.

Table 15. Internal Reference Setup Register

Internal Reference Setup Register (Bit DB0) Action

0 Reference on (default) 1 Reference off

SOLDER HEAT REFLOW

As with all IC reference voltage circuits, the reference value experiences a shift induced by the soldering process. Analog Devices, Inc., performs a reliability test called precondition to mimic the effect of soldering a device to a board. The output voltage specification in Table 2 includes the effect of this reliability test.

Figure 47 shows the effect of solder heat reflow (SHR) as measured through the reliability test (precondition).

LONG-TERM TEMPERATURE DRIFT

Figure 48 shows the change in the V in life test at 150°C.

Figure 48. Reference Drift to 1000 Hours

value after 1000 hours

REF

THERMAL HYSTERESIS

Thermal hysteresis is the voltage difference induced on the reference voltage by sweeping the temperature from ambient to cold, then to hot, and then back to ambient.

Thermal hysteresis data is shown in Figure 49. It is measured by sweeping the temperature from ambient to −40°C, then to +105°C, and then back to ambient. The V the two ambient measurements (shown in blue in Figure 49). The same temperature sweep and measurements were immediately repeated, and the results are shown in red in Figure 49.

delta is then measured between

REF

Figure 47. SHR Reference Voltage Shift

Table 16. 24-Bit Input Shift Register Contents for Internal Reference Setup Command1

DB23 (MSB) DB22 DB21 DB20 DB19 to DB16 DB15 to DB1 DB0 (LSB)

0 1 1 1 X X 1 or 0

X = don’t care.

Command bits (C3 to C0) Address bits (don’t care) Don’t care Reference setup register

Rev. A | Page 22 of 24

Figure 49. Thermal Hysteresis

ADSP-BF531

SCL

GPIO1

SDAGPIO2

LDACPF9 RESETPF8

AD5316R

10819-164

AD5316R

GND

PLANE

BOARD

10819-166

ENCODE

SERIAL

CLOCK IN

CONTROLLER

ADuM1400

SERIAL

DATA OUT

RESET OUT

LOAD DAC

OUT

DECODE

TO SCL

TO SDA

TO RESET

TO LDAC

ENCODE DECODE

ENCODE

DECODE

10819-167

Data Sheet AD5316R

APPLICATIONS INFORMATION

MICROPROCESSOR INTERFACING

Microprocessor interfacing to the AD5316R is via a serial bus that uses a standard protocol that is compatible with DSP processors and microcontrollers. The communications channel requires a 2-wire interface consisting of a clock signal and a data signal.

AD5316R TO ADSP-BF531 INTERFACE

The I2C interface of the AD5316R is designed for easy connection to industry-standard DSPs and microcontrollers. Figure 50 shows the AD5316R connected to the Analog Devices Blackfin® processor. The Blackfin processor has an integrated I that can be connected directly to the I

Figure 50. AD5316R to ADSP-BF531 Interface

C pins of the AD5316R.

LAYOUT GUIDELINES

In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. The PCB on which the AD5316R is mounted should be designed so that the AD5316R lies on the analog plane.

The AD5316R should have ample supply bypassing of 10 µF in parallel with 0.1 µF on each supply, located as close to the package as possible, ideally right up against the device. The 10 µF capacitor is the tantalum bead type. The 0.1 µF capacitor should have low effective series resistance (ESR) and low effective series inductance (ESI), such as the common ceramic types; these capacitors provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching.

In systems where many devices are on one board, it is often useful to provide some heat sinking capability to allow the power to dissipate easily.

The AD5316R LFCSP models have an exposed pad beneath the device. Connect this pad to the GND supply for the part. For optimum performance, use special considerations to design the motherboard and to mount the package.

C port

Rev. A | Page 23 of 24

For enhanced thermal, electrical, and board level performance, solder the exposed pad on the bottom of the LFCSP package to the corresponding thermal land paddle on the PCB. Design thermal vias into the PCB land paddle area to further improve heat dissipation.

The GND plane on the device can be increased (as shown in Figure 51) to provide a natural heat sinking effect.

Figure 51. Paddle Connection to Board

GALVANICALLY ISOLATED INTERFACE

In many process control applications, it is necessary to provide an isolation barrier between the controller and the unit being controlled to protect and isolate the controlling circuitry from any hazardous common-mode voltages that may occur.

The Analog Devices iCoupler® products provide voltage isolation in excess of 2.5 kV. The serial loading structure of the AD5316R makes the part ideal for isolated interfaces because the number of interface lines is kept to a minimum. Figure 52 shows a 4-channel isolated interface to the AD5316R using the ADuM1400. For more information, visit http://www.analog.com/icouplers.

Figure 52. Isolated Interface

AD5316R Data Sheet

3.10

3.00 SQ

2.90

0.30

0.23

0.18

1.75

1.60 SQ

1.45

08-16-2010-E

0.50

BSC

BOTTOM VIEWTOP VIEW

EXPOSED

PAD

PIN 1 INDICATOR

0.50

0.40

0.30

SEATING

PLANE

0.05 MAX

0.02 NOM

0.20 REF

0.25 MIN

COPLANARITY

0.08

PIN 1

INDICATOR

FOR PROP E R CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CO NFIGURATI ON AND FUNCTIO N DE S CRIPTIONS SECTION OF THIS DATA SHEET.

0.80

0.75

0.70

COMPLIANT

JEDEC STANDARDS MO-220-WEED-6.

PIN 1

SEATING PLANE

8° 0°

4.50

4.40

4.30

6.40

BSC

5.10

5.00

4.90

0.65

BSC

0.15

0.05

1.20 MAX

0.20

0.09

0.75

0.60

0.45

0.30

0.19

COPLANARITY

0.10

COMPLI ANT TO JEDEC STANDARDS MO-153-AB

OUTLINE DIMENSIONS

Figure 53. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]

3 mm × 3 mm Body, Very Very Thin Quad

(CP-16-22)

Dimensions shown in millimeters

ORDERING GUIDE

Temperature

Model1 Resolution

AD5316RBCPZ-RL7 10 Bits −40°C to +105°C ±0.5 LSB ±5 (max) 16-Lead LFCSP_WQ CP-16-22 DJT AD5316RBRUZ 10 Bits −40°C to +105°C ±0.5 LSB ±5 (max) 16-Lead TSSOP RU-16 AD5316RBRUZ-RL7 10 Bits −40°C to +105°C ±0.5 LSB ±5 (max) 16-Lead TSSOP RU-16

Z = RoHS Compliant Part.

I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).

registered trademarks are the property of their respective owners. D10819-0-7/12(A)

Range

Figure 54. 16-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-16)

Dimensions shown in millimeters

Reference Accuracy (INL)

Rev. A | Page 24 of 24

Tempco

(ppm/°C)

Package Description

Package Option

Branding

Datasheet AD5316R Datasheet (ANALOG DEVICES)

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

PRODUCT HIGHLIGHTS

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

AC CHARACTERISTICS

TIMING CHARACTERISTICS

Timing Diagram

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

ESD CAUTION

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

TERMINOLOGY

THEORY OF OPERATION

DIGITAL-TO-ANALOG CONVERTER

TRANSFER FUNCTION

DAC ARCHITECTURE

Internal Reference

Output Amplifiers

SERIAL INTERFACE

Input Shift Register

WRITE AND UPDATE COMMANDS

Update DAC Register n with Contents of Input Register n

I2C SLAVE ADDRESS

SERIAL OPERATION

WRITE OPERATION

READ OPERATION

MULTIPLE DAC READBACK SEQUENCE

POWER-DOWN OPERATION

RESET SELECT PIN (RSTSEL)

INTERNAL REFERENCE SETUP

SOLDER HEAT REFLOW

LONG-TERM TEMPERATURE DRIFT

THERMAL HYSTERESIS

APPLICATIONS INFORMATION

MICROPROCESSOR INTERFACING

AD5316R TO ADSP-BF531 INTERFACE

LAYOUT GUIDELINES

GALVANICALLY ISOLATED INTERFACE

OUTLINE DIMENSIONS

ORDERING GUIDE