ANALOG DEVICES AD5316R Service Manual

Quad, 10-Bit nanoDAC with 2 ppm/°C

V

Data Sheet

FEATURES

Low drift 2.5 V on-chip reference: 2 ppm/°C typical Tiny package: 3 mm × 3 mm, 16-lead LFCSP

Total unadjusted error (TUE): ±0.1% of FSR maximum Offset error: ±1.5 mV maximum Gain error: ±0.1% of FSR maximum High drive capability: 20 mA, 0.5 V from supply rails User-selectable gain of 1 or 2 (GAIN pin) Reset to zero scale or midscale (RSTSEL pin)

1.8 V logic compatibility 400 kHz I 4 I Low glitch: 0.5 nV-sec Robust 3.5 kV HBM and 1.5 kV FICDM ESD rating Low power: 3.3 mW at 3 V

2.7 V to 5.5 V power supply

−40°C to +105°C temperature range

APPLICATIONS

Digital gain and offset adjustment Programmable attenuators Industrial automation Data acquisition systems

GENERAL DESCRIPTION

The AD5316R, a member of the nanoDAC® family, is a low power, quad, 10-bit buffered voltage output DAC. The device includes a 2.5 V, 2 ppm/°C internal reference (enabled by default) and a gain select pin giving a full-scale output of 2.5 V (gain = 1) or 5 V (gain = 2). The device operates from a single 2.7 V to 5.5 V supply, is guaranteed monotonic by design, and exhibits less than 0.1% FSR gain error and 1.5 mV offset error performance. The device is available in a 3 mm × 3 mm LFCSP package and in a TSSOP package.

The AD5316R also incorporates a power-on reset circuit and a RSTSEL pin; the RSTSEL pin ensures that the DAC outputs power up to zero scale or midscale and remain at that level until a valid write takes place. The part contains a per-channel power-down feature that reduces the current consumption of the device in power-down mode to 4 μA at 3 V.

The AD5316R uses a versatile 2-wire serial interface that operates at clock rates up to 400 kHz and includes a V for 1.8 V/3 V/5 V logic.

2

C-compatible serial interface

C addresses available

pin intended

LOGIC

2

Reference, I

C Interface

AD5316R

FUNCTIONAL BLOCK DIAGRAM

LOGIC

SCL

SDA

DD

AD5316R

REGISTER

A1

A0

REGISTER

INTERFACE LOGIC

REGISTER

INPUT

GND

DAC

REGISTER

DAC

REGISTER

DAC

REGISTER

DAC

REGISTER

POWER-ON

RESET

RSTSEL GAINLDAC RESET

Figure 1.

Table 1. Related Devices

Interface Reference 12-Bit 10-Bit

SPI Internal AD5684R AD5317R External AD5684 AD5317 I2C Internal AD5694R External AD5694 AD53161

1

The AD5316R and the AD5316 are not pin-to-pin or software compatible.

PRODUCT HIGHLIGHTS

1. Precision DC Performance.

Total unadjusted error: ±0.1% of FSR maximum Offset error: ±1.5 mV maximum Gain error: ±0.1% of FSR maximum

2. Low Drift 2.5 V On-Chip Reference.

2 ppm/°C typical temperature coefficient 5 ppm/°C maximum temperature coefficient

3. Two Pa ckage Opti ons .

3 mm × 3 mm, 16-lead LFCSP 16-lead TSSOP

REF

STRING

DAC A

STRING

DAC B

STRING

DAC C

STRING

DAC D

GAIN =

×1/×2

2.5V

REFERENCE

BUFFER

POWER-

DOWN LOGIC

V

A

OUT

V

B

OUT

V

C

OUT

V

D

OUT

10819-001

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

AD5316R Data Sheet

REVISION HISTORY

7/12—Rev. 0 to R e v. A

Change to Features Section ............................................................. 1

Change to Relative Accuracy Parameter in Tabl e 2 ..................... 3

Change to Differential Nonlinearity Parameter in Table 2 ......... 3

Changes to Ordering Guide .......................................................... 24

7/12—Revision 0: Initial Version

Rev. A | Page 2 of 24

Data Sheet AD5316R

Resolution

10

Bits

Full-Scale Error

+0.01

±0.1

% of FSR

All 1s loaded to DAC register

DC Power Supply Rejection Ratio4

0.15 mV/V

DAC code = midscale; VDD = 5 V ± 10%

Capacitive Load Stability

2

nF

RL = ∞

Short-Circuit Current6

40 mA

Output Voltage Noise Density4

240 nV/√Hz

At TA, f = 10 kHz, CL = 10 nF

Thermal Hysteresis4

125 ppm

First cycle

SPECIFICATIONS

VDD = 2.7 V to 5.5 V; V

Table 2.

Parameter Min Typ Max Unit Test Conditions/Comments

STATIC PERFORMANCE3

Relative Accuracy ±0.12 ±0.5 LSB Differential Nonlinearity ±0.5 LSB Guaranteed monotonic by design Zero-Code Error 0.4 1.5 mV All 0s loaded to DAC register Offset Error +0.1 ±1.5 mV

Gain Error ±0.02 ±0.1 % of FSR Total Unadjusted Error ±0.01 ±0.1 % of FSR External reference, gain = 2, TSSOP ±0.2 % of FSR Internal reference, gain = 1, TSSOP Offset Error Drift4 ±1 µV/°C Gain Temperature Coefficient4 ±1 ppm Of FSR/°C

= 2.5 V; 1.8 V ≤ V

REF

≤ 5.5 V; RL = 2 kΩ; CL = 200 pF; all specifications T

LOGIC

MIN

to T

, unless otherwise noted.

MAX

1, 2

DC Crosstalk4 ±2 µV

Due to single channel, full-scale output

change ±3 µV/mA Due to load current change ±2 µV Due to power-down (per channel) OUTPUT CHARACTERISTICS4

Output Voltage Range 0 V 0 2 × V

V Gain = 1

REF

V Gain = 2 (see Figure 26)

REF

10 nF RL = 1 kΩ Resistive Load5 1 kΩ Load Regulation DAC code = midscale 80 µV/mA 5 V ± 10%; −30 mA ≤ I 80 µV/mA 3 V ± 10%; −20 mA ≤ I

≤ +30 mA

OUT

≤ +20 mA

OUT

Load Impedance at Rails7 25 Ω See Figure 26 Power-Up Time 2.5 µs Coming out of power-down mode; VDD = 5 V

REFERENCE OUTPUT

Output Voltage8 2.4975 2.5025 V At TA Reference TC9 2 5 ppm/°C See the Terminology section Output Impedance4 0.04 Ω Output Voltage Noise4 12 µV p-p 0.1 Hz to 10 Hz

Load Regulation, Sourcing4 20 µV/mA At TA Load Regulation, Sinking4 40 µV/mA At TA Output Current Load Capability4 ±5 mA VDD ≥ 3 V Line Regulation4 100 µV/V At TA Long-Term Stability/Drift4 12 ppm After 1000 hours at 125°C

25 ppm Additional cycles LOGIC INPUTS4

Input Current ±2 µA Per pin Input Low Voltage, V Input High Voltage, V Pin Capacitance 2 pF

0.3 × V

INL

0.7 × V

INH

V

LOGI C

Rev. A | Page 3 of 24

V

LOGI C

AD5316R Data Sheet

V

+ 1.5

5.5 V Gain = 2

Total Harmonic Distortion4

−80 dB

At TA, BW = 20 kHz, VDD = 5 V, f

= 1 kHz

Parameter Min Typ Max Unit Test Conditions/Comments

1, 2

LOGIC OUTPUTS (SDA)4

Output Low Voltage, VOL 0.4 V I

= 3 mA

SINK

Floating State Output Capacitance 4 pF

POWER REQUIREMENTS

V

1.8 5.5 V

LOGI C

I

3 µA

LOGI C

VDD 2.7 5.5 V Gain = 1

REF

IDD VIH = VDD, VIL = GND, VDD = 2.7 V to 5.5 V

Normal Mode10 0.59 0.7 mA Internal reference off

1.1 1.3 mA Internal reference on, at full scale All Power-Down Modes11 1 4 µA −40°C to +85°C

6 µA −40°C to +105°C

1

Temperature range is −40°C to +105°C.

2

The AD5316R and the AD5316 are not pin-to-pin or software compatible.

3

DC specifications are tested with the outputs unloaded, unless otherwise noted. Upper dead band (10 mV) exists only when V

with gain = 2. Linearity calculated using a reduced code range of 4 to 1020.

4

Guaranteed by design and characterization; not production tested.

5

Channel A and Channel B can have a combined output current of up to 30 mA. Similarly, Channel C and Channel D can have a combined output current of up to

30 mA up to a junction temperature of 110°C.

6

VDD = 5 V. The device includes current limiting that is intended to protect the device during temporary overload conditions. Junction temperature can be exceeded

during current limit. Operation above the specified maximum junction temperature may impair device reliability.

7

When drawing a load current at either rail, the output voltage headroom with respect to that rail is limited by the 25 Ω typical channel resistance of the output

devices. For example, when sinking 1 mA, the minimum output voltage = 25 Ω × 1 mA = 25 mV (see Figure 26).

8

Initial accuracy presolder reflow is ±750 µV; output voltage includes the effects of preconditioning drift. See the Solder Heat Reflow section.

9

Reference is trimmed and tested at two temperatures and is characterized from −40°C to +105°C. Reference temperature coefficient is calculated as per the box method.

See the Terminology section for more information.

10

Interface inactive. All DACs active. DAC outputs unloaded.

11

All DACs powered down.

= VDD with gain = 1 or when V

REF

/2 = VDD

REF

AC CHARACTERISTICS

VDD = 2.7 V to 5.5 V; V

Table 3.

Parameter

1, 2

Min Typ Max Unit Test Conditions/Comments3

Output Voltage Settling Time 5 7 µs ¼ to ¾ scale settling to ±1 LSB Slew Rate 0.8 V/µs Digital-to-Analog Glitch Impulse 0.5 nV-sec 1 LSB change around major carry transition Digital Feedthrough 0.13 nV-sec Digital Crosstalk 0.1 nV-sec Analog Crosstalk 0.2 nV-sec DAC-to-DAC Crosstalk 0.3 nV-sec

Output Noise Spectral Density 300 nV/√Hz DAC code = midscale, 10 kHz, gain = 2 Output Noise 6 µV p-p 0.1 Hz to 10 Hz

1

Guaranteed by design and characterization; not production tested.

2

See the Terminology section.

3

Temperature range is −40°C to +105°C; typical at 25°C.

4

Digitally generated sine wave at 1 kHz.

= 2.5 V; 1.8 V ≤ V

REF

≤ 5.5 V; RL = 2 kΩ; CL = 200 pF; all specifications T

LOGIC

MIN

to T

, unless otherwise noted.

MAX

OUT

Rev. A | Page 4 of 24

Data Sheet AD5316R

t

3

0 0.9

µs

t

, data hold time

t12

20 ns

SCL

SDA

t

1

t

3

LDAC

1

LDAC

2

START CONDITION

REPEATED START CONDITION

STOP CONDITION

NOTES

1

ASYNCHRONOUS LDAC UPDATE MO DE .

2

SYNCHRONOUS LDAC UPDATE MO DE .

t

4

t

6

t

5

t

7

t

8

t

2

t

13

t

4

t

11

t

10

t

12

t

12

t

9

10819-002

TIMING CHARACTERISTICS

VDD = 2.7 V to 5.5 V; 1.8 V ≤ V

≤ 5.5 V; all specifications T

LOGIC

MIN

to T

, unless otherwise noted.

MAX

Table 4.

Parameter

1, 2

Min Max Unit Description

t1 2.5 µs SCL cycle time t2 0.6 µs t t3 1.3 µs t t4 0.6 µs t t5 100 ns t

6

t7 0.6 µs t t8 0.6 µs t t9 1.3 µs t

4

t

0 300 ns tR, rise time of SCL and SDA when receiving

10

4, 5

t

20 + 0.1CB 300 ns tF, fall time of SCL and SDA when transmitting/receiving

11

, SCL high time

HIGH

, SCL low time

LOW

, start/repeated start hold time

HD,STA

, data setup time

SU ,DAT

HD,DAT

, repeated start setup time

SU,STA

, stop condition setup time

SU,STO

, bus free time between a stop condition and a start condition

BUF

LDAC pulse width

t13 400 ns

6

t

0 50 ns Pulse width of suppressed spike

SP

5

C

400 pF Capacitive load for each bus line

B

1

See Figure 2.

2

Guaranteed by design and characterization; not production tested.

3

A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH min of the SCL signal) to bridge the undefined region of the SCL

falling edge.

4

tR and tF are measured from 0.3 × VDD to 0.7 × VDD.

5

CB is the total capacitance of one bus line in pF.

6

Input filtering on the SCL and SDA inputs suppresses noise spikes that are less than 50 ns.

SCL rising edge to

LDAC rising edge

Timing Diagram

Figure 2. 2-Wire Serial Interface Timing Diagram

Rev. A | Page 5 of 24

AD5316R Data Sheet

Human Body Model (HBM)

3.5 kV

16-Lead LFCSP

70

°C/W

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 5.

Parameter Rating

VDD to GND −0.3 V to +7 V V

to GND −0.3 V to +7 V

LOGI C

V

to GND −0.3 V to VDD + 0.3 V

OUT

V

to GND −0.3 V to VDD + 0.3 V

REF

Digital Input Voltage to GND1 −0.3 V to V SDA and SCL to GND −0.3 V to +7 V Operating Temperature Range −40°C to +105°C Storage Temperature Range −65°C to +150°C Junction Temperature 125°C Reflow Soldering Peak Temperature,

Pb Free (J-STD-020)

ESD

260°C

LOGI C

+ 0.3 V

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. This value was measured using a JEDEC standard 4-layer board with zero airflow. For the LFCSP package, the exposed pad must be tied to GND.

Table 6. Thermal Resistance

Package Type θJA Unit

16-Lead TSSOP 112.6 °C/W

ESD CAUTION

Field-Induced Charged Device

Model (FICDM)

1

Excluding SDA and SCL.

1.5 kV

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Rev. A | Page 6 of 24

Data Sheet AD5316R

5 7 V

D

Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.

14

16

RSTSEL

12 11 10

1

3 4

A1 SCL A0

9

V

LOGIC

V

OUT

A

V

DD

2

GND

V

OUT

C

6

SDA

5

V

OUT

D

7

LDAC

8

GAIN

16

V

OUT

B

15

V

REF

14

RSTSEL

13

RESET

AD5316R

NOTES

1. THE EXPOSED PAD MUST BE TIED TO GND.

TOP VIEW

(Not to S cale)

10819-006

1

2

3

4

5

6

7

8

V

OUT

B

V

OUT

A

GND

V

OUT

D

V

OUT

C

V

DD

V

REF

SDA

16

15

14

13

12

11

10

9

RESET A1 SCL

GAIN LDAC

V

LOGIC

A0

RSTSEL

TOP VIEW

(Not to S cale)

AD5316R

10819-007

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

Figure 3. 16-Lead LFCSP Pin Configuration

Table 7. Pin Function Descriptions

Pin No.

Mnemonic Description LFCSP TSSOP

1 3 V

A Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.

OUT

2 4 GND Ground Reference Point for All Circuitry on the Part. 3 5 VDD

Power Supply Input. The part can be operated from 2.7 V to 5.5 V. The supply should be decoupled with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND.

4 6 V

6 8 SDA

C Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.

OUT

Serial Data Input. This pin is used in conjunction with the SCL line to clock data into or out of the 24-bit input shift register. SDA is a bidirectional, open-drain data line that should be pulled to the supply with an external pull-up resistor.

7 9

LDAC LDAC can be operated in two modes, asynchronous update mode and synchronous update mode.

Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data; all DAC outputs are simultaneously updated. This pin can also be tied permanently low.

8 10 GAIN

Gain Select Pin. When this pin is tied to GND, all four DAC outputs have a span of 0 V to V When this pin is tied to V

9 11 V

Digital Power Supply. Voltage ranges from 1.8 V to 5.5 V.

LOGI C

10 12 A0 Address Input. Sets the first LSB of the 7-bit slave address. 11 13 SCL

Serial Clock Line. This pin is used in conjunction with the SDA line to clock data into or out of the

24-bit input shift register. 12 14 A1 Address Input. Sets the second LSB of the 7-bit slave address. 13 15

RESET Asynchronous Reset Input. The RESET input is falling edge sensitive. When RESET is activated

(low), the input register and the DAC register are updated with zero scale or midscale, depending

on the state of the RSTSEL pin. When

15 1 V

16 2 V 17 N/A EPAD Exposed Pad. The exposed pad must be tied to GND.

REF

B Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.

OUT

Power-On Reset Pin. When this pin is tied to GND, all four DACs are powered up to zero scale.

When this pin is tied to V

Reference Voltage. The AD5316R has an internal reference. When the internal reference is used,

V

is the reference output pin. When an external reference is used, V

REF

pin. By default, the internal reference is used, and this pin is a reference output.

Rev. A | Page 7 of 24

Figure 4. 16-Lead TSSOP Pin Configuration

, all four DAC outputs have a span of 0 V to 2 × V

DD

RESET is low, all LDAC pulses are ignored.

, all four DACs are powered up to midscale.

DD

.

REF

is the reference input

REF

.

AD5316R Data Sheet

–40 –20 0 20 40 60 80 100 120

V

REF

(V)

TEMPERATURE (°C)

DEVICE 1 DEVICE 2 DEVICE 3 DEVICE 4 DEVICE 5

2.4980

2.4985

2.4990

2.4995

2.5000

2.5005

2.5010

2.5015

2.5020 V

DD

= 5V

10819-212

90

0

10

20

30

40

50

60

70

80

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

NUMBER OF UNI TS

TEMPERAT URE DRIFT (ppm/°C)

VDD = 5V

10819-250

60

0

10

20

30

40

50

2.498 2.499 2.500 2.501 2.502

HITS

V

REF

(V)

0 HOUR 168 HOURS 500 HOURS 1000 HOURS

VDD = 5.5V

10819-251

1600

0

200

400

600

800

1000

1200

1400

10 100 1k 10k 100k 1M

NSD (nV/ Hz)

FREQUENCY ( Hz )

V

DD

= 5V

T

A

= 25°C

10819-111

CH1 2µV M1.0s

1

V

DD

= 5V

T

A

= 25°C

10819-112

2.5000

2.4999

2.4998

2.4997

2.4996

2.4995

2.4994

2.4993 –0.005 –0.003 –0.001 0.001 0.003 0.005

V

REF

(V)

I

LOAD

(A)

VDD = 5V T

A

= 25°C

10819-113

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 5. Internal Reference Voltage vs. Temperature

Figure 6. Reference Output Temperature Drift Histogram

Figure 8. Internal Reference Noise Spectral Density vs. Frequency

Figure 9. Internal Reference Noise, 0.1 Hz to 10 Hz

Figure 7. Reference Long-Term Stability (Drift)

Figure 10. Internal Reference Voltage vs. Load Current

Rev. A | Page 8 of 24

ANALOG DEVICES AD5316R Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

PRODUCT HIGHLIGHTS

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

AC CHARACTERISTICS

TIMING CHARACTERISTICS

Timing Diagram

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

ESD CAUTION

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS