Datasheet AD5304, AD5324, AD5314 Datasheet (Analog Devices)

2.5 V to 5.5 V, 500 ␮A, Quad Voltage Output

a

8-/10-/12-Bit DACs in 10-Lead microSOIC

FEATURES
AD5304

Four Buffered 8-Bit DACs in 10-Lead microSOIC

AD5314

Four Buffered 10-Bit DACs in 10-Lead microSOIC

AD5324

Four Buffered 12-Bit DACs in 10-Lead microSOIC

Low Power Operation: 500 ␮A @ 3 V, 600 ␮A @ 5 V

2.5 V to 5.5 V Power Supply
Guaranteed Monotonic By Design Over All Codes
Power-Down to 80 nA @ 3 V, 200 nA @ 5 V
Double-Buffered Input Logic
Output Range: 0–V

REF

Power-On-Reset to Zero Volts
Simultaneous Update of Outputs (LDAC Function)
Low Power, SPI™, QSPI™, MICROWIRE™, and

DSP-Compatible 3-Wire Serial Interface
On-Chip Rail-to-Rail Output Buffer Amplifiers
Temperature Range –40ⴗC to +105ⴗC

APPLICATIONS
Portable Battery-Powered Instruments
Digital Gain and Offset Adjustment
Programmable Voltage and Current Sources
Programmable Attenuators
Industrial Process Control

FUNCTIONAL BLOCK DIAGRAM

AD5304/AD5314/AD5324*

GENERAL DESCRIPTION

The AD5304/AD5314/AD5324 are quad 8-, 10- and 12-bit
buffered voltage output DACs in a 10-lead microSOIC package
that operate from a single 2.5 V to 5.5 V supply consuming
500 µA at 3 V. Their on-chip output amplifiers allow rail-to­rail output swing to be achieved with a slew rate of 0.7 V/µs.
A 3-wire serial interface is used which operates at clock rates
up to 30 MHz and is compatible with standard SPI, QSPI,
MICROWIRE and DSP interface standards.

The references for the four DACs are derived from one reference
pin. The outputs of all DACs may be updated simultaneously
using the software LDAC function. The parts incorporate a
power-on-reset circuit that ensures that the DAC outputs power
up to zero volts and remain there until a valid write takes place
to the device. The parts contain a power-down feature that
reduces the current consumption of the device to 200 nA @ 5 V
(80 nA @ 3 V).

The low power consumption of these parts in normal operation
makes them ideally suited to portable battery-operated equipment.
The power consumption is 3 mW at 5 V, 1.5 mW at 3 V, reducing
to 1 µW in power-down mode.

V

DD

LDAC

INPUT

REGISTER

SCLK

SYNC

DIN

*Protected by U.S. Patent No. 5,969,657; other patents pending.

SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corporation.

INTERFACE

LOGIC

POWER-ON

RESET

INPUT

REGISTER

INPUT

REGISTER

INPUT

REGISTER

AD5304/AD5314/AD5324

GND

REV. B

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

REFIN

DAC

REGISTER

DAC

REGISTER

DAC

REGISTER

DAC

REGISTER

STRING

DAC A

STRING

DAC B

STRING

DAC C

STRING

DAC D

POWER-DOWN

LOGIC

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 2000

BUFFER

V

A

OUT

BBUFFER

V

OUT

V

CBUFFER

OUT

V

DBUFFER

OUT

AD5304/AD5314/AD5324–SPECIFICATIONS

GND; CL = 200 pF to GND; All specifications T

Parameter

1

DC PERFORMANCE

3, 4

B Version
Min Typ Max Unit Conditions/Comments

MIN

to T

unless otherwise noted.)

MAX

2

(VDD = 2.5 V to 5.5 V; V

= 2 V; RL = 2 k⍀ to

REF

AD5304

Resolution 8 Bits
Relative Accuracy ± 0.15 ± 1 LSB
Differential Nonlinearity ± 0.02 ± 0.25 LSB Guaranteed Monotonic by Design Over All Codes

AD5314

Resolution 10 Bits
Relative Accuracy ± 0.5 ± 4 LSB
Differential Nonlinearity ± 0.05 ± 0.5 LSB Guaranteed Monotonic by Design Over All Codes

AD5324

Resolution 12 Bits
Relative Accuracy ± 2 ± 16 LSB

Differential Nonlinearity ± 0.2 ± 1 LSB Guaranteed Monotonic by Design Over All Codes
Offset Error ± 0.4 ± 3 % of FSR See Figures 2 and 3
Gain Error ± 0.15 ± 1 % of FSR See Figures 2 and 3
Lower Deadband 20 60 mV Lower Deadband Exists Only If Offset Error Is Negative
Offset Error Drift
Gain Error Drift
DC Power Supply Rejection Ratio
DC Crosstalk

DAC REFERENCE INPUTS

V

Input Range 0.25 V

REF

V

Input Impedance 37 45 kΩ Normal Operation

REF

5

5

5

5

5

–12 ppm of FSR/°C
–5 ppm of FSR/°C
–60 dB ∆VDD = ±10%
200 µVR

DD

V

= 2 kΩ to GND or V

L

DD

>10 MΩ Power-Down Mode

Reference Feedthrough –90 dB Frequency = 10 kHz

OUTPUT CHARACTERISTICS

Minimum Output Voltage
Maximum Output Voltage

5

6

6

0.001 V This is a measure of the minimum and maximum drive

VDD – 0.001 V capability of the output amplifier.
DC Output Impedance 0.5 Ω
Short Circuit Current 25 mA VDD = 5 V

16 mA VDD = 3 V
Power-Up Time 2.5 µs Coming Out of Power-Down Mode. VDD = 5 V

5 µs Coming Out of Power-Down Mode. VDD = 3 V

LOGIC INPUTS

5

Input Current ± 1 µA
VIL, Input Low Voltage 0.8 V VDD = 5 V ± 10%

0.6 V VDD = 3 V ± 10%

0.5 V VDD = 2.5 V

VIH, Input High Voltage 2.4 V VDD = 5 V ± 10%

2.1 V VDD = 3 V ± 10%

2.0 V VDD = 2.5 V

Pin Capacitance 3 pF

POWER REQUIREMENTS

V

DD

IDD (Normal Mode)

7

VDD = 4.5 V to 5.5 V 600 900 µAV
VDD = 2.5 V to 3.6 V 500 700 µAV

2.5 5.5 V

= VDD and VIL = GND

IH

= VDD and VIL = GND

IH

IDD (Power-Down Mode)

VDD = 4.5 V to 5.5 V 0.2 1 µAV
VDD = 2.5 V to 3.6 V 0.08 1 µAV

NOTES

1

See Terminology.

2

Temperature range: B Version: –40°C to +105°C; typical at 25°C.

3

DC specifications tested with the outputs unloaded.

4

Linearity is tested using a reduced code range: AD5304 (Code 8 to 248); AD5314 (Code 28 to 995); AD5324 (Code 115 to 3981).

5

Guaranteed by design and characterization, not production tested.

6

In order for the amplifier output to reach its minimum voltage, Offset Error must be negative. In order for the amplifier output to reach its maximum voltage,

= VDD and “Offset plus Gain” Error must be positive.

V

REF

7

IDD specification is valid for all DAC codes. Interface inactive. All DACs active. Load currents excluded.

Specifications subject to change without notice.

= VDD and VIL = GND

IH

= VDD and VIL = GND

IH

–2–

REV. B

AD5304/AD5314/AD5324

(VDD = 2.5 V to 5.5 V; RL = 2 k⍀ to GND; CL = 200 pF to GND; all specifications T

AC CHARACTERISTICS

Parameter

Output Voltage Settling Time V

2

1

otherwise noted.)

B Version
Min Typ Max Unit Conditions/Comments

3

= VDD = 5 V

REF

AD5304 6 8 µs 1/4 Scale to 3/4 Scale
AD5314 7 9 µs 1/4 Scale to 3/4 Scale
AD5324 8 10 µs 1/4 Scale to 3/4 Scale

Change
Change
Change

to T

MIN

(40 Hex to C0 Hex)
(100 Hex to 300 Hex)

(400 Hex to C00 Hex)
Slew Rate 0.7 V/µs
Major-Code Transition Glitch Energy 12 nV-s 1 LSB Change Around Major Carry
Digital Feedthrough 1 nV-s
Digital Crosstalk 1 nV-s
DAC-to-DAC Crosstalk 3 nV-s
Multiplying Bandwidth 200 kHz V
Total Harmonic Distortion –70 dB V

NOTES

1

Guaranteed by design and characterization, not production tested.

2

See Terminology.

3

Temperature range: B Version: –40°C to +105°C

Specifications subject to change without notice.

TIMING CHARACTERISTICS

Limit at T

; typical at 25°C.

1, 2, 3

(VDD = 2.5 V to 5.5 V. All specifications T

, T

MIN

MAX

= 2 V ± 0.1 V p-p

REF

= 2.5 V ± 0.1 V p-p. Frequency = 10 kHz

REF

to T

MIN

unless otherwise noted)

MAX

Parameter VDD = 2.5 V to 3.6 V VDD = 3.6 V to 5.5 V Unit Conditions/Comments

t

1

t

2

t

3

t

4

t

5

t

6

t

7

t

8

NOTES

1

Guaranteed by design and characterization, not production tested.

2

All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.

3

See Figure 1.

Specifications subject to change without notice.

40 33 ns min SCLK Cycle Time
16 13 ns min SCLK High Time
16 13 ns min SCLK Low Time
0 0 ns min SYNC to SCLK Rising Edge Setup Time
5 5 ns min Data Setup Time

4.5 4.5 ns min Data Hold Time
0 0 ns min SCLK Falling Edge to SYNC Rising Edge
80 33 ns min Minimum SYNC High Time

MAX

unless

REV. B

SCLK

SYNC

DIN

t

1

t

t

t

8

DB15

t

4

t

6

t

5

3

2

DB0

t

7

Figure 1. Serial Interface Timing Diagram

–3–

AD5304/AD5314/AD5324

TOP VIEW

(Not to Scale)

10

9

8

7

6

1

2

3

4

5

V

DD

V

OUT

A

GND

DIN

SCLK

SYNC

V

OUT

D

AD5304/
AD5314/

AD5324

V

OUT

B

V

OUT

C

REFIN

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS

(TA = 25°C unless otherwise noted)

1, 2

PIN CONFIGURATION

VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

Digital Input Voltage to GND . . . . . . . –0.3 V to V

Reference Input Voltage to GND . . . . –0.3 V to V

V

A–D to GND . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V

OUT

+ 0.3 V

DD

+ 0.3 V

DD

Operating Temperature Range

Industrial (B Version) . . . . . . . . . . . . . . . –40°C to +105°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Junction Temperature (T

max) . . . . . . . . . . . . . . . . . . 150°C

J

10-Lead microSOIC Package

Power Dissipation . . . . . . . . . . . . . . . . . . (T

max – TA)/θ

J

JA

θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . 206°C/W

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 44°C/W

θ

JC

Reflow Soldering

Peak Temperature . . . . . . . . . . . . . . . . . . . . . 220 +5/–0°C

Time at Peak Temperature . . . . . . . . . . . . 10 sec to 40 sec

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; and functional operation of
the device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

2

Transient currents of up to 100 mA will not cause SCR latch-up.

PIN FUNCTION DESCRIPTIONS

Pin
No. Mnemonic Function

1V
2V
3V
4V

DD

A Buffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.

OUT

B Buffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.

OUT

C Buffered Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.

OUT

5 REFIN Reference Input Pin for All Four DACs. It has an input range from 0.25 V to V
6V

D Buffered Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.

OUT

Power Supply Input. These parts can be operated from 2.5 V to 5.5 V and the supply should be decoupled to GND.

.

DD

7 GND Ground Reference Point for All Circuitry on the Part.
8 DIN Serial Data Input. This device has a 16-bit shift register. Data is clocked into the register on the falling edge of

the serial clock input. The DIN input buffer is powered down after each write cycle.

9 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data

can be transferred at clock speeds up to 30 MHz. The SCLK input buffer is powered down after each write cycle.

10 SYNC Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it

enables the input shift register and data is transferred in on the falling edges of the following 16 clocks. If SYNC is
taken high before the sixteenth falling edge of SCLK, the rising edge of SYNC acts as an interrupt and the
write sequence is ignored by the device.

ORDERING GUIDE

Temperature Package Package Branding

Model Range Description Option Information

AD5304BRM –40°C to +105°C 10-Lead microSOIC RM-10 DBB
AD5314BRM –40°C to +105°C 10-Lead microSOIC RM-10 DCB
AD5324BRM –40°C to +105°C 10-Lead microSOIC RM-10 DDB

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD5304/AD5314/AD5324 features proprietary ESD protection circuitry, permanent damage
may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

–4–

REV. B

AD5304/AD5314/AD5324

TERMINOLOGY
RELATIVE ACCURACY

For the DAC, relative accuracy or integral nonlinearity (INL) is
a measure of the maximum deviation, in LSBs, from a straight
line passing through the endpoints of the DAC transfer function.
Typical INL versus Code plots can be seen in Figures 4, 5, and 6.

DIFFERENTIAL NONLINEARITY

Differential Nonlinearity (DNL) is the difference between the
measured change and the ideal 1 LSB change between any two
adjacent codes. A specified differential nonlinearity of ±1 LSB
maximum ensures monotonicity. This DAC is guaranteed mono­tonic by design. Typical DNL versus Code plots can be seen in
Figures 7, 8, and 9.

OFFSET ERROR

This is a measure of the offset error of the DAC and the output
amplifier. It is expressed as a percentage of the full-scale range.

GAIN ERROR

This is a measure of the span error of the DAC. It is the devia­tion in slope of the actual DAC transfer characteristic from the
ideal expressed as a percentage of the full-scale range.

OFFSET ERROR DRIFT

This is a measure of the change in offset error with changes in
temperature. It is expressed in (ppm of full-scale range)/°C.

GAIN ERROR DRIFT

This is a measure of the change in gain error with changes in
temperature. It is expressed in (ppm of full-scale range)/°C.

POWER-SUPPLY REJECTION RATIO (PSRR)

This indicates how the output of the DAC is affected by changes
in the supply voltage. PSRR is the ratio of the change in V
a change in V
in dBs. V

for full-scale output of the DAC. It is measured

DD

is held at 2 V and VDD is varied ±10%.

REF

OUT

to

DC CROSSTALK

This is the dc change in the output level of one DAC at midscale
in response to a full-scale code change (all 0s to all 1s and vice
versa) and output change of another DAC. It is expressed in µV.

REFERENCE FEEDTHROUGH

This is the ratio of the amplitude of the signal at the DAC
output to the reference input when the DAC output is not being
updated. It is expressed in dBs.

DIGITAL CROSSTALK

This is the glitch impulse transferred to the output of one DAC
at midscale in response to a full-scale code change (all 0s to all
1s and vice versa) in the input register of another DAC. It is
expressed in nV-secs.

DAC-TO-DAC CROSSTALK

This is the glitch impulse transferred to the output of one DAC
due to a digital code change and subsequent output change of
another DAC. This includes both digital and analog crosstalk. It
is measured by loading one of the DACs with a full-scale code
change (all 0s to all 1s and vice versa) with the LDAC bit set low
and monitoring the output of another DAC. The energy of the
glitch is expressed in nV-secs.

MULTIPLYING BANDWIDTH

The amplifiers within the DAC have a finite bandwidth. The
multiplying bandwidth is a measure of this. A sine wave on the
reference (with full-scale code loaded to the DAC) appears on
the output. The multiplying bandwidth is the frequency at which
the output amplitude falls to 3 dB below the input.

TOTAL HARMONIC DISTORTION

This is the difference between an ideal sine wave and its attenuated
version using the DAC. The sine wave is used as the reference
for the DAC and the THD is a measure of the harmonics present
on the DAC output. It is measured in dBs.

GAIN ERROR

OUTPUT

VOLTAGE

NEGATIVE

OFFSET

ERROR

AMPLIFIER

FOOTROOM

(1mV)

NEGATIVE

OFFSET

ERROR

IDEAL

DAC CODE

DEADBAND CODES

OFFSET ERROR

ACTUAL

PLUS

Figure 2. Transfer Function with Negative Offset

MAJOR-CODE TRANSITION GLITCH ENERGY

Major-code transition glitch energy is the energy of the impulse
injected into the analog output when the code in the DAC
register changes state. It is normally specified as the area of the
glitch in nV-secs and is measured when the digital code is changed
by 1 LSB at the major carry transition (011 . . . 11 to 100 . . . 00
or 100 . . . 00 to 011 . . . 11).

DIGITAL FEEDTHROUGH

Digital feedthrough is a measure of the impulse injected into the
analog output of the DAC from the digital input pins of the device
when the DAC output is not being written to (SYNC held high). It
is specified in nV-secs and is measured with a worst-case change on
the digital input pins, e.g., from all 0s to all 1s or vice versa.

REV. B

–5–

GAIN ERROR

PLUS

OFFSET ERROR

OUTPUT

VOLTAGE

POSITIVE

OFFSET

ACTUAL

IDEAL

DAC CODE

Figure 3. Transfer Function with Positive Offset

AD5304/AD5314/AD5324

1.0

TA = 25ⴗC
V

= 5V

DD

0.5

0

INL ERROR – LSBs

–0.5

–1.0

50 250100 150 200

0

CODE

Figure 4. AD5304 Typical INL Plot

0.3
TA = 25ⴗC

= 5V

V

DD

0.2

0.1

0

–0.1

DNL ERROR – LSBs

–0.2

3

TA = 25ⴗC

= 5V

V

DD

2

1

0

–1

INL ERROR – LSBs

–2

–3

0

200 1000

400 600 800

CODE

Figure 5. AD5314 Typical INL Plot

0.6
TA = 25ⴗC

= 5V

V

DD

0.4

0.2

0

–0.2

DNL ERROR – LSBs

–0.4

12

TA = 25ⴗC

= 5V

V

8

DD

4

0

–4

INL ERROR – LSBs

–8

–12

0 4000

1000 2000 3000

CODE

Figure 6. AD5324 Typical INL Plot

1

TA = 25ⴗC
V

= 5V

DD

0.5

0

DNL ERROR – LSBs

–0.5

–0.3

0 50 250100 150 200

CODE

Figure 7. AD5304 Typical DNL Plot

0.5

VDD = 5V

= 25ⴗC

T

A

0.25

0

ERROR – LSBs

–0.25

–0.5

01 5234

MAX INL

MIN DNL

MIN INL

V

REF

MAX DNL

– V

Figure 10. AD5304 INL and DNL
Error vs. V

REF

–0.6

2000

CODE

600400

800 1000

Figure 8. AD5314 Typical DNL Plot

0.5

VDD = 5V

0.4

0.3

0.2

0.1

–0.1

ERROR – LSBs

–0.2

–0.3

–0.4

–0.5

= 3V

V

REF

0

ⴚ40 0 40

MAX INL

MAX DNL

TEMPERATURE – ⴰC

MIN DNL

MIN INL

80 120

Figure 11. AD5304 INL Error and
DNL Error vs. Temperature

–1

10000

2000

CODE

3000 4000

Figure 9. AD5324 Typical DNL Plot

1

VDD = 5V

= 2V

V

REF

0.5

GAIN ERROR

0

ERROR – %

–0.5

–1

ⴚ40 0 40

OFFSET ERROR

80 120

TEMPERATURE – ⴰC

Figure 12. AD5304 Offset Error and
Gain Error vs. Temperature

–6–

REV. B

AD5304/AD5314/AD5324

V

LOGIC

– Volts

1000

400

0 0.5 4.5

1.5 2.5 3.5

700

600

900

800

I

DD

– ␮A

1.0 2.0 3.0 4.0 5.0

500

TA = 25ⴗC

VDD = 5V

VDD = 3V

0.2

TA = 25ⴰC

ERROR – %

0.1

–0.1

–0.2

–0.3

–0.4

–0.5

–0.6

= 2V

V

REF

0

OFFSET ERROR

01 3

25

VDD – Volts

GAIN ERROR

46

Figure 13. Offset Error and Gain
Error vs. V

600

500

400

300

– ␮A

DD

I

200

DD

ⴚ40ⴰC

+25ⴰC

+105ⴰC

5

5V SOURCE

3

– Volts

OUT

2

V

1

0

01 3446

Figure 14. V

3V SOURCE

5V SINK

25

SINK/SOURCE CURRENT – mA

Source and Sink

OUT

3V SINK

Current Capability

0.5

0.4

0.3

– ␮A

DD

I

0.2

ⴚ40ⴰC

ⴙ25ⴰC

600

TA = 25ⴰC

= 5V

V

DD

500

400

A

␮

300

–

DD

I

200

100

= 2V

V

REF

0

ZERO – SCALE

FULL – SCALE

CODE

Figure 15. Supply Current vs. DAC
Code

100

0

2.5

3.0

3.5
VDD – Volts

4.5 5.5

4.0

Figure 16. Supply Current vs. Supply
Voltage

= 25ⴰC

T

A

5µs

= 5V

V

DD

= 5V

V

REF

CH1

V

A

OUT

SCLK

CH2

CH1 1V, CH2 5V, TIME BASE= 1␮s/DIV

Figure 19. Half-Scale Settling (1/4 to
3/4 Scale Code Change)

5.0

0.1

ⴙ105ⴰC

0

2.5

3.0 4.0
VDD – Volts

4.5

5.0

5.53.5

Figure 17. Power-Down Current vs.
Supply Voltage

TA = 25ⴰC

= 5V

V

DD

= 2V

V

REF

CH1

V

DD

V

A

CH2

CH1 2V, CH2 200mV, TIME BASE = 200␮s/DIV

OUT

Figure 20. Power-On Reset to 0 V

Figure 18. Supply Current vs. Logic
Input Voltage

TA = 25ⴰC

= 5V

V

DD

= 2V

V

REF

CH1

V

A

OUT

SCLK

CH2

CH1 500mV, CH2 5V, TIME BASE= 1␮s/DIV

Figure 21. Exiting Power-Down to
Midscale

REV. B

–7–

AD5304/AD5314/AD5324

VDD = 5VVDD = 3V

FREQUENCY

300 350 600400 450 500 550

IDD – ␮A

Figure 22. IDD Histogram with
V

= 3 V and VDD = 5 V

DD

0.02

VDD = 5V

= 25ⴗC

T

A

0.01

0

2.50

2.49

– Volts

OUT

V

2.48

2.47
1␮s/DIV

Figure 23. AD5324 Major-Code
Transition Glitch Energy

1mV/DIV

10

0

–10

–20

dB

–30

–40

–50

–60

0.01

0.1 1 10 100 1k 10k
FREQUENCY – kHz

Figure 24. Multiplying Bandwidth
(Small-Signal Frequency Response)

–0.01

FULL-SCALE ERROR – Volts

–0.02

01 3

25

V

REF

46

– Volts

Figure 25. Full-Scale Error vs. V

REF

150ns/DIV

Figure 26. DAC-to-DAC Crosstalk

–8–

REV. B

AD5304/AD5314/AD5324

FUNCTIONAL DESCRIPTION

The AD5304/AD5314/AD5324 are quad resistor-string DACs
fabricated on a CMOS process with resolutions of 8, 10, and 12
bits respectively. Each contains four output buffer amplifiers and
is written to via a 3-wire serial interface. They operate from
single supplies of 2.5 V to 5.5 V and the output buffer amplifiers
provide rail-to-rail output swing with a slew rate of 0.7 V/µs. The
four DACs share a single reference input pin. The devices have
programmable power-down modes, in which all DACs may be
turned off completely with a high-impedance output.

Digital-to-Analog Section

The architecture of one DAC channel consists of a resistor-string
DAC followed by an output buffer amplifier. The voltage at the
REFIN pin provides the reference voltage for the DAC. Figure
27 shows a block diagram of the DAC architecture. Since the
input coding to the DAC is straight binary, the ideal output
voltage is given by:

VD

×

V

OUT

REF

=

N

2

where

D = decimal equivalent of the binary code, which is loaded to the
DAC register;

0–255 for AD5304 (8 Bits)
0–1023 for AD5314 (10 Bits)
0–4095 for AD5324 (12 Bits)

N = DAC resolution

REFIN

DAC Reference Inputs

There is a single reference input pin for the four DACs. The
reference input is unbuffered. The user can have a reference
voltage as low as 0.25 V and as high as V

since there is no

DD

restriction due to headroom and footroom of any reference
amplifier.

It is recommended to use a buffered reference in the external
circuit (e.g., REF192). The input impedance is typically 45 kΩ.

Output Amplifier

The output buffer amplifier is capable of generating rail-to-rail
voltages on its output, which gives an output range of 0 V to V

DD

when the reference is VDD. It is capable of driving a load of
2 kΩ to GND or V

in parallel with 500 pF to GND or VDD.

DD,

The source and sink capabilities of the output amplifier can be
seen in the plot in Figure 14.

The slew rate is 0.7 V/µs with a half-scale settling time to
± 0.5 LSB (at 8 bits) of 6 µs.

POWER-ON RESET

The AD5304/AD5314/AD5324 are provided with a power-on
reset function, so that they power up in a defined state. The
power-on state is:

– Normal operation.
– Output voltage set to 0 V.

Both input and DAC registers are filled with zeros and remain
so until a valid write sequence is made to the device. This is
particularly useful in applications where it is important to know
the state of the DAC outputs while the device is powering up.

INPUT

REGISTER

DAC

REGISTER

RESISTOR

STRING

OUTPUT BUFFER

AMPLIFIER

V

A

OUT

Figure 27. DAC Channel Architecture

Resistor String

The resistor string section is shown in Figure 28. It is simply a
string of resistors, each of value R. The digital code loaded to the
DAC register determines at which node on the string the voltage
is tapped off to be fed into the output amplifier. The voltage is
tapped off by closing one of the switches connecting the string to
the amplifier. Because it is a string of resistors, it is guaranteed
monotonic.

R

R

R

R

R

TO OUTPUT
AMPLIFIER

SERIAL INTERFACE

The AD5304/AD5314/AD5324 are controlled over a versatile,
3-wire serial interface, which operates at clock rates up to 30 MHz
and is compatible with SPI, QSPI, MICROWIRE, and DSP
interface standards.

Input Shift Register

The input shift register is 16 bits wide. Data is loaded into the
device as a 16-bit word under the control of a serial clock input,
SCLK. The timing diagram for this operation is shown in Figure 1.
The 16-bit word consists of four control bits followed by 8, 10,
or 12 bits of DAC data, depending on the device type. Data
is loaded MSB first (Bit 15) and the first two bits determine
whether the data is for DAC A, DAC B, DAC C, or DAC D.
Bits 13 and 12 control the operating mode of the DAC. Bit 13 is
PD, which determines whether the part is in normal or power­down mode. Bit 12 is LDAC, which controls when DAC registers
and outputs are updated.

Table I. Address Bits for the AD53x4

A1 A0 DAC Addressed

0 0 DAC A
0 1 DAC B
1 0 DAC C
1 1 DAC D

REV. B

Figure 28. Resistor String

–9–

AD5304/AD5314/AD5324

BIT15
(MSB)

A1

A0

LDACPD

D7 D6 D5

D4

DATA BITS

Figure 29. AD5304 Input Shift Register Contents

BIT15
(MSB)

A1

A0

PD

LDAC

D9 D8 D7

D6

DATA BITS

Figure 30. AD5314 Input Shift Register Contents

BIT15
(MSB)

A1

A0

PD

LDAC

D11 D10 D9

D8

Figure 31. AD5324 Input Shift Register Contents

Address and Control Bits

PD: 0: All four DACs go into power-down mode consuming

only 200 nA @ 5 V. The DAC outputs enter a high­impedance state.
1: Normal operation.

LDAC: 0: All four DAC registers and hence all DAC outputs

updated simultaneously on completion of the write
sequence.
1: Addressed input register only is updated. There is
no change in the content of the DAC registers.

The AD5324 uses all 12 bits of DAC data, the AD5314 uses
10 bits and ignores the two LSBs. The AD5304 uses eight bits
and ignores the last four bits. The data format is straight binary,
with all zeros corresponding to 0 V output and all ones corre­sponding to full-scale output (V

–1 LSB).

REF

The SYNC input is a level-triggered input that acts as a frame
synchronization signal and chip enable. Data can only be trans­ferred into the device while SYNC is low. To start the serial data
transfer, SYNC should be taken low, observing the minimum
SYNC to SCLK active edge setup time, t

. After SYNC goes low,

4

serial data will be shifted into the device's input shift register on
the falling edges of SCLK for sixteen clock pulses. Any data and
clock pulses after the sixteenth falling edge of SCLK will be
ignored because the SCLK and DIN input buffers are powered
down. No further serial data transfer will occur until SYNC is
taken high and low again.

SYNC may be taken high after the falling edge of the sixteenth
SCLK pulse, observing the minimum SCLK falling edge to
SYNC rising edge time, t

.

7

After the end of serial data transfer, data will automatically be
transferred from the input shift register to the input register of
the selected DAC. If SYNC is taken high before the sixteenth
falling edge of SCLK, the data transfer will be aborted and the
DAC input registers will not be updated.

When data has been transferred into three of the DAC input
registers, all DAC registers and all DAC outputs may simulta­neously be updated by setting LDAC low when writing to the
remaining DAC input register.

BIT0
(LSB)

D3 D2 D1

D5 D4 D3

D7 D6 D5

DATA BITS

D0

X

D2

D1 D0

D4

D3 D2 D1 D0

XXX

BIT0
(LSB)

XX

BIT0
(LSB)

Low-Power Serial Interface

To reduce the power consumption of the device even further, the
interface only powers up fully when the device is being written
to, i.e., on the falling edge of SYNC. As soon as the 16-bit control
word has been written to the part, the SCLK and DIN input
buffers are powered down. They only power up again following
a falling edge of SYNC.

Double-Buffered Interface

The AD5304/AD5314/AD5324 DACs all have double-buffered
interfaces consisting of two banks of registers—input registers
and DAC registers. The input register is directly connected to
the input shift register and the digital code is transferred to the
relevant input register on completion of a valid write sequence.
The DAC register contains the digital code used by the resis­tor string.

Access to the DAC register is controlled by the LDAC bit. When
the LDAC bit is set high, the DAC register is latched and hence
the input register may change state without affecting the contents
of the DAC register. However, when the LDAC bit is set low,
all DAC registers are updated after a complete write sequence.

This is useful if the user requires simultaneous updating of all DAC
outputs. The user may write to three of the input registers indi­vidually and then, by setting the LDAC bit low when writing
to the remaining DAC input register, all outputs will update
simultaneously.

These parts contain an extra feature whereby the DAC register
is not updated unless its input register has been updated since
the last time that LDAC was brought low. Normally, when LDAC
is brought low, the DAC registers are filled with the contents of
the input registers. In the case of the AD5304/AD5314/AD5324,
the part will only update the DAC register if the input register
has been changed since the last time the DAC register was
updated, thereby removing unnecessary digital crosstalk.

POWER-DOWN MODE

The AD5304/AD5314/AD5324 have low power consumption,
dissipating only 1.5 mW with a 3 V supply and 3 mW with a 5 V
supply. Power consumption can be further reduced when the
DACs are not in use by putting them into power-down mode,
which is selected by a zero on Bit 13 (PD) of the control word.

–10–

REV. B

AD5304/AD5314/AD5324

When the PD bit is set to 1, all DACs work normally with a
typical power consumption of 600 µA at 5 V (500 µA at 3 V).
However, in power-down mode, the supply current falls to 200 nA
at 5 V (80 nA at 3 V) when all DACs are powered down. Not
only does the supply current drop, but the output stage is also
internally switched from the output of the amplifier making it
open-circuit. This has the advantage that the output is three­stated while the part is in power-down mode, and provides a
defined input condition for whatever is connected to the output
of the DAC amplifier. The output stage is illustrated in Figure 32.

The bias generator, the output amplifier, the resistor string, and
all other associated linear circuitry are all shut down when the
power-down mode is activated. However, the contents of the
registers are unaffected when in power-down. The time to exit
power-down is typically 2.5 µs for VDD = 5 V and 5 µs when
V

= 3 V. This is the time from the falling edge of the sixteenth

DD

SCLK pulse to when the output voltage deviates from its power­down voltage. See Figure 21 for a plot.

RESISTOR

STRING DAC

AMPLIFIER

POWER-DOWN

CIRCUITRY

V

OUT

Figure 32. Output Stage During Power-Down

MICROPROCESSOR INTERFACING
AD5304/AD5314/AD5324 to ADSP-2101/ADSP-2103 Interface

Figure 33 shows a serial interface between the AD5304/AD5314/
AD5324 and the ADSP-2101/ADSP-2103. The ADSP-2101/
ADSP-2103 should be set up to operate in the SPORT Transmit
Alternate Framing Mode. The ADSP-2101/ADSP-2103 SPORT
is programmed through the SPORT control register and should
be configured as follows: Internal Clock Operation, Active-Low
Framing, 16-Bit Word Length. Transmission is initiated by writing
a word to the Tx register after the SPORT has been enabled.
The data is clocked out on each rising edge of the DSP’s serial
clock and clocked into the AD5304/AD5314/AD5324 on the
falling edge of the DAC’s SCLK.

ADSP-2101/

ADSP-2103*

TFS

DT

SCLK

*ADDITIONAL PINS OMITTED FOR CLARITY.

AD5304/
AD5314/

AD5324*

SYNC

DIN

SCLK

Figure 33. AD5304/AD5314/AD5324 to ADSP-2101/
ADSP-2103 Interface

AD5304/AD5314/AD5324 to 68HC11/68L11 Interface

Figure 34 shows a serial interface between the AD5304/AD5314/
AD5324 and the 68HC11/68L11 microcontroller. SCK of the
68HC11/68L11 drives the SCLK of the AD5304/AD5314/
AD5324, while the MOSI output drives the serial data line (DIN)
of the DAC. The SYNC signal is derived from a port line (PC7).
The setup conditions for correct operation of this interface are
as follows: the 68HC11/68L11 should be configured so that its
CPOL bit is a 0 and its CPHA bit is a 1. When data is being
transmitted to the DAC, the SYNC line is taken low (PC7).
When the 68HC11/68L11 is configured as above, data appearing
on the MOSI output is valid on the falling edge of SCK. Serial
data from the 68HC11/68L11 is transmitted in 8-bit bytes with
only eight falling clock edges occurring in the transmit cycle. Data
is transmitted MSB first. In order to load data to the AD5304/
AD5314/AD5324, PC7 is left low after the first eight bits are
transferred, a second serial write operation is performed to the
DAC, and PC7 is taken high at the end of this procedure.

68HC11/68L11*

PC7

SCK

MOSI

*ADDITIONAL PINS OMITTED FOR CLARITY.

AD5304/
AD5314/
AD5324*

SYNC

SCLK

DIN

Figure 34. AD5304/AD5314/AD5324 to 68HC11/68L11
Interface

AD5304/AD5314/AD5324 to 80C51/80L51 Interface

Figure 35 shows a serial interface between the AD5304/AD5314/
AD5324 and the 80C51/80L51 microcontroller. The setup for
the interface is as follows: TxD of the 80C51/80L51 drives SCLK
of the AD5304/AD5314/AD5324, while RxD drives the serial
data line of the part. The SYNC signal is again derived from a
bit-programmable pin on the port. In this case port line P3.3 is
used. When data is to be transmitted to the AD5304/AD5314/
AD5324, P3.3 is taken low. The 80C51/80L51 transmits data
only in 8-bit bytes; thus only eight falling clock edges occur in
the transmit cycle. To load data to the DAC, P3.3 is left low
after the first eight bits are transmitted, and a second write cycle
is initiated to transmit the second byte of data. P3.3 is taken high
following the completion of this cycle. The 80C51/80L51 outputs
the serial data in a format which has the LSB first. The AD5304/
AD5314/AD5324 requires its data with the MSB as the first bit
received. The 80C51/80L51 transmit routine should take this
into account.

80C51/80L51*

P3.3

TxD

RxD

AD5304/
AD5314/
AD5324*

SYNC

SCLK

DIN

REV. B

*ADDITIONAL PINS OMITTED FOR CLARITY.

Figure 35. AD5304/AD5314/AD5324 to 80C51/80L51
Interface

–11–

AD5304/AD5314/AD5324

AD5304/AD5314/AD5324 to MICROWIRE Interface

Figure 36 shows an interface between the AD5304/AD5314/
AD5324 and any MICROWIRE-compatible device. Serial data is
shifted out on the falling edge of the serial clock, SK and is
clocked into the AD5304/AD5314/AD5324 on the rising edge
of SK, which corresponds to the falling edge of the DAC’s SCLK.

MICROWIRE*

CS

SK

SO

*ADDITIONAL PINS OMITTED FOR CLARITY.

AD5304/
AD5314/
AD5324*

SYNC

SCLK

DIN

Figure 36. AD5304/AD5314/AD5324 to MICROWIRE
Interface

APPLICATIONS
Typical Application Circuit

The AD5304/AD5314/AD5324 can be used with a wide range
of reference voltages where the devices offer full, one-quadrant
multiplying capability over a reference range of 0 V to V

DD

.
More typically, these devices are used with a fixed, precision
reference voltage. Suitable references for 5 V operation are the
AD780 and REF192 (2.5 V references). For 2.5 V operation, a
suitable external reference would be the AD589, a 1.23 V band­gap reference. Figure 37 shows a typical setup for the AD5304/
AD5314/AD5324 when using an external reference.

VDD = 2.5V TO 5.5V

0.1␮F

10␮F

AD5304/
AD5314/

AD5324

V

IN

V

OUT

EXT
REF

AD780/REF192

= 5V

WITH V

DD

OR AD589 WITH

= 2.5V

V

DD

1␮F

SERIAL

INTERFACE

REFIN

SCLK

DIN

SYNC

A0

GND

V

A

OUT

V

B

OUT

V

C

OUT

D

V

OUT

Figure 37. AD5304/AD5314/AD5324 Using External
Reference

If an output range of 0 V to VDD is required, the simplest solu­tion is to connect the reference input to V

. As this supply may

DD

not be very accurate and may be noisy, the AD5304/AD5314/
AD5324 may be powered from the reference voltage; for example,
using a 5 V reference such as the REF195. The REF195 will
output a steady supply voltage for the AD5304/AD5314/AD5324.
The current required from the REF195 is 600 µA supply current
and approximately 112 µA into the reference input. This is with no
load on the DAC outputs. When the DAC outputs are loaded, the
REF195 also needs to supply the current to the loads. The total
current required (with a 10 kΩ load on each output) is:

712 µA + 4(5 V/10 kΩ) = 2.70 mA

The load regulation of the REF195 is typically 2 ppm/mA, which
results in an error of 5.4 ppm (27 µV) for the 2.7 mA current
drawn from it. This corresponds to a 0.0014 LSB error at 8 bits
and 0.022 LSB error at 12 bits.

Bipolar Operation Using the AD5304/AD5314/AD5324

The AD5304/AD5314/AD5324 have been designed for single­supply operation, but a bipolar output range is also possible
using the circuit in Figure 38. This circuit will give an output
voltage range of ±5 V. Rail-to-rail operation at the amplifier output
is achievable using an AD820 or an OP295 as the output amplifier.

R2 = 10k⍀

6V TO 16V

10␮F

REF195

V

IN

GND

R1 = 10k⍀

0.1␮F
5V

V

DD

V

OUT

1␮F

REFIN

GND

D

AD5304

IN

SCLK

SERIAL

INTERFACE

V

OUT

V

OUT

V

OUT

V

OUT

S

Y

N

+5V

AD820/
OP295

A

–5V

B

C

D

C

ⴞ5V

Figure 38. Bipolar Operation with the AD5304

The output voltage for any input code can be calculated as
follows:

V

= [(REFIN × D/2N) × (R1+R2)/R1 – REFIN × (R2/R1)]

OUT

where:

D is the decimal equivalent of the code loaded to the DAC.

N is the DAC resolution.

REFIN is the reference voltage input.

with:

REFIN = 5 V, R1 = R2 = 10 kΩ:

V

= (10 × D/2N) – 5 V

OUT

Opto-Isolated Interface for Process Control Applications

The AD5304/AD5314/AD5324 have a versatile 3-wire serial
interface making them ideal for generating accurate voltages
in process control and industrial applications. Due to noise,
safety requirements or distance, it may be necessary to isolate
the AD5304/AD5314/AD5324 from the controller. This can easily
be achieved by using opto-isolators, which will provide isolation in
excess of 3 kV. The actual data rate achieved may be limited by
the type of optocouplers chosen. The serial loading structure
of the AD5304/AD5314/ AD5324 makes them ideally suited for
use in opto-isolated applications. Figure 39 shows an opto-iso­lated interface to the AD5304 where DIN, SCLK, and SYNC
are driven from optocouplers. The power supply to the part
also needs to be isolated. This is done by using a transformer. On
the DAC side of the transformer, a 5 V regulator provides the 5 V
supply required for the AD5304.

–12–

REV. B

AD5304/AD5314/AD5324

5V

POWER

SCLK

SYNC

DIN

REGULATOR

V

10k⍀

V

10k⍀

V

10k⍀

DD

SCLK

DD

DD

AD5304

SYNC

DIN

V

DD

GND

10␮F

REFIN

V

OUT

V

OUT

V

OUT

V

OUT

0.1␮F

A

B

C

D

Figure 39. AD5304 in an Opto-Isolated Interface

Decoding Multiple AD5304/AD5314/AD5324s

The SYNC pin on the AD5304/AD5314/AD5324 can be used
in applications to decode a number of DACs. In this application,
all the DACs in the system receive the same serial clock and
serial data, but the SYNC to only one of the devices will be active
at any one time, allowing access to four channels in this 16­channel system. The 74HC139 is used as a 2-to-4-line decoder
to address any of the DACs in the system. To prevent timing
errors, the enable input should be brought to its inactive state
while the coded address inputs are changing state. Figure 40
shows a diagram of a typical setup for decoding multiple
AD5304 devices in a system.

SCLK

DIN

ENABLE

CODED

ADDRESS

1G

1A

1B

V

DD

V

CC

74HC139

DGND

1Y0

1Y1

1Y2

1Y3

SYNC

DIN

SCLK

SYNC

DIN

SCLK

SYNC

DIN

SCLK

SYNC

DIN

SCLK

AD5304

AD5304

AD5304

AD5304

V

A

OUT

B

V

OUT

C

V

OUT

D

V

OUT

V

A

OUT

V

B

OUT

C

V

OUT

D

V

OUT

V

A

OUT

V

B

OUT

C

V

OUT

D

V

OUT

V

A

OUT

V

B

OUT

C

V

OUT

D

V

OUT

Figure 40. Decoding Multiple AD5304 Devices in a System

AD5304/AD5314/AD5324 as a Digitally Programmable
Window Detector

A digitally programmable upper/lower limit detector using two
of the DACs in the AD5304/AD5314/AD5324 is shown in
Figure 41. The upper and lower limits for the test are loaded to
DACs A and B which, in turn, set the limits on the CMP04. If
the signal at the V

input is not within the programmed window,

IN

an LED will indicate the fail condition. Similarly, DACs C and
D can be used for window detection on a second V

5V

V

REF

SYNC

DIN

SCLK

0.1␮F

*ADDITIONAL PINS OMITTED FOR CLARITY

REFIN

SYNC

DIN

SCLK

10␮F

V

1/2
AD5304/
AD5314/
AD5324*

GND

V

IN

DD

V

A

OUT

V

B

OUT

1/2

CMP04

signal.

IN

1k⍀

FAIL PASS

PASS/FAIL

1/6 74HC05

1k⍀

Figure 41. Window Detection

POWER SUPPLY BYPASSING AND GROUNDING

In any circuit where accuracy is important, careful consideration
of the power supply and ground return layout helps to ensure the
rated performance. The printed circuit board on which the
AD5304/AD5314/AD5324 is mounted should be designed so
that the analog and digital sections are separated, and confined
to certain areas of the board. If the AD5304/AD5314/AD5324
is in a system where multiple devices require an AGND-to-DGND
connection, the connection should be made at one point only.
The star ground point should be established as close as possible
to the device. The AD5304/AD5314/AD5324 should have ample
supply bypassing of 10 µF in parallel with 0.1 µF on the supply
located as close to the package as possible, ideally right up against
the device. The 10 µF capacitors are the tantalum bead type. The

0.1 µF capacitor should have low Effective Series Resistance
(ESR) and Effective Series Inductance (ESI), like the common
ceramic types that provide a low impedance path to ground at
high frequencies, to handle transient currents due to internal logic
switching.

The power supply lines of the AD5304/AD5314/AD5324 should
use as large a trace as possible to provide low impedance paths
and reduce the effects of glitches on the power supply line. Fast
switching signals such as clocks should be shielded with digital
ground to avoid radiating noise to other parts of the board, and
should never be run near the reference inputs. Avoid crossover
of digital and analog signals. Traces on opposite sides of the
board should run at right angles to each other. This reduces the
effects of feedthrough through the board. A microstrip technique is
by far the best, but not always possible with a double-sided
board. In this technique, the component side of the board is
dedicated to ground plane while signal traces are placed on the
solder side.

REV. B

–13–

AD5304/AD5314/AD5324

Table II. Overview of All AD53xx Serial Devices

No. of Settling

Part No. Resolution DACs DNL Interface Time Package Pins

SINGLES

AD5300 8 1 ± 0.25 SPI 4 µs SOT-23, microSOIC 6, 8
AD5310 10 1 ± 0.5 SPI 6 µs SOT-23, microSOIC 6, 8
AD5320 12 1 ± 1.0 SPI 8 µs SOT-23, microSOIC 6, 8

AD5301 8 1 ± 0.25 2-Wire 6 µs SOT-23, microSOIC 6, 8
AD5311 10 1 ± 0.5 2-Wire 7 µs SOT-23, microSOIC 6, 8
AD5321 12 1 ± 1.0 2-Wire 8 µs SOT-23, microSOIC 6, 8

DUALS

AD5302 8 2 ± 0.25 SPI 6 µs microSOIC 8
AD5312 10 2 ± 0.5 SPI 7 µs microSOIC 8
AD5322 12 2 ± 1.0 SPI 8 µs microSOIC 8

AD5303 8 2 ± 0.25 SPI 6 µs TSSOP 16
AD5313 10 2 ± 0.5 SPI 7 µs TSSOP 16
AD5323 12 2 ± 1.0 SPI 8 µs TSSOP 16

QUADS

AD5304 8 4 ± 0.25 SPI 6 µs microSOIC 10
AD5314 10 4 ± 0.5 SPI 7 µs microSOIC 10
AD5324 12 4 ± 1.0 SPI 8 µs microSOIC 10

AD5305 8 4 ± 0.25 2-Wire 6 µs microSOIC 10
AD5315 10 4 ± 0.5 2-Wire 7 µs microSOIC 10
AD5325 12 4 ± 1.0 2-Wire 8 µs microSOIC 10

AD5306 8 4 ± 0.25 2-Wire 6 µs TSSOP 16
AD5316 10 4 ± 0.5 2-Wire 7 µs TSSOP 16
AD5326 12 4 ± 1.0 2-Wire 8 µs TSSOP 16

AD5307 8 4 ± 0.25 SPI 6 µs TSSOP 16
AD5317 10 4 ± 0.5 SPI 7 µs TSSOP 16
AD5327 12 4 ± 1.0 SPI 8 µs TSSOP 16

Visit our web-page at http://www.analog.com/support/standard_linear/selection_guides/AD53xx.html

–14–

REV. B

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

10-Lead microSOIC

(RM-10)

0.122 (3.10)

0.114 (2.90)

AD5304/AD5314/AD5324

0.122 (3.10)

0.114 (2.90)

0.037 (0.94)

0.031 (0.78)

0.006 (0.15)

0.002 (0.05)

10 6

PIN 1

0.0197 (0.50) BSC

0.120 (3.05)

0.112 (2.85)

51

0.012 (0.30)

0.006 (0.15)

0.199 (5.05)

0.187 (4.75)

0.043 (1.10)
MAX

SEATING
PLANE

0.009 (0.23)

0.005 (0.13)

0.120 (3.05)

0.112 (2.85)

6ⴗ
0ⴗ

C3721a–2.5–6/00 (rev. B) 00929

0.028 (0.70)

0.016 (0.40)

REV. B

PRINTED IN U.S.A.

–15–