Analog Devices AD5304 14 24 d Datasheet

2.5 V to 5.5 V, 500 ␮A, Quad Voltage Output
8-/10-/12-Bit DACs in 10-Lead MSOP

FEATURES
AD5304: 4 Buffered 8-Bit DACs in 10-Lead MSOP

A Version: ⴞ1 LSB INL, B Version: ⴞ0.625 LSB INL

AD5314: 4 Buffered 10-Bit DACs in 10-Lead MSOP

A Version: ⴞ4 LSB INL, B Version: ⴞ2.5 LSB INL

AD5324: 4 Buffered 12-Bit DACs in 10-Lead MSOP

A Version: ⴞ16 LSB INL, B Version: ⴞ10 LSB INL

Low Power Operation: 500 ␮A @ 3 V, 600 ␮A @ 5 V

2.5 V to 5.5 V Power Supply
Guaranteed Monotonic by Design over All Codes
Power-Down to 80 nA @ 3 V, 200 nA @ 5 V
Double-Buffered Input Logic
Output Range: 0 V to V

REF

Power-On Reset to 0 V
Simultaneous Update of Outputs (LDAC Function)
Low Power, SPI

®

, QSPI™, MICROWIRE™, and

DSP Compatible 3-Wire Serial Interface
On-Chip Rail-to-Rail Output Buffer Amplifiers
Temperature Range –40ⴗC to +105ⴗC

APPLICATIONS
Portable Battery-Powered Instruments
Digital Gain and Offset Adjustment
Programmable Voltage and Current Sources
Programmable Attenuators
Industrial Process Control

AD5304/AD5314/AD5324

*

GENERAL DESCRIPTION

The AD5304/AD5314/AD5324 are quad 8-, 10-, and 12-bit
buffered voltage output DACs in a 10-lead MSOP that operate
from a single 2.5 V to 5.5 V supply, consuming 500 mA at 3 V.
Their on-chip output amplifiers allow rail-to-rail output swing
to be achieved with a slew rate of 0.7 V/ms. A 3-wire serial
interface is used, which operates at clock rates up to 30 MHz
and is compatible with standard SPI, QSPI, MICROWIRE,
and DSP interface standards.

The references for the four DACs are derived from one reference
pin. The outputs of all DACs may be updated simultaneously
using the software LDAC function. The parts incorporate a
power-on reset circuit, which ensures that the DAC outputs
power up to 0 V and remain there until a valid write takes place
to the device. The parts contain a power-down feature that
reduces the current consumption of the device to 200 nA @
5 V (80 nA @ 3 V).

The low power consumption of these parts in normal operation
makes them ideally suited to portable battery-operated equip­ment. The power consumption is 3 mW at 5 V, 1.5 mW at 3 V,
reducing to 1 mW in power-down mode.

FUNCTIONAL BLOCK DIAGRAM

V

DD

LDAC

INPUT

REGISTER

SCLK

SYNC

DIN

*Protected by U.S. Patent No. 5,969,657; other patents pending.

INTERFACE

LOGIC

POWER-ON

RESET

INPUT

REGISTER

INPUT

REGISTER

INPUT

REGISTER

AD5304/AD5314/AD5324

GND

REV. D

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.

REFIN

DAC

REGISTER

DAC

REGISTER

DAC

REGISTER

DAC

REGISTER

STRING

DAC A

STRING

DAC B

STRING

DAC C

STRING

DAC D

POWER-DOWN

LOGIC

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2003 Analog Devices, Inc. All rights reserved.

BUFFER

A

V

OUT

BBUFFER

V

OUT

V

CBUFFER

OUT

V

DBUFFER

OUT

AD5304/AD5314/AD5324–SPECIFICATIONS

GND; CL = 200 pF to GND; all specifications T

Parameter

1

DC PERFORMANCE

3, 4

A Version
Min Typ Max Min Typ Max Unit Conditions/Comments

MIN

to T

, unless otherwise noted.)

MAX

2

B Version

2

(VDD = 2.5 V to 5.5 V; V

= 2 V; RL = 2 k⍀ to

REF

AD5304

Resolution 8 8 Bits
Relative Accuracy ± 0.15 ± 1 ± 0.15 ± 0.625 LSB
Differential Nonlinearity ± 0.02 ± 0.25 ± 0.02 ± 0.25 LSB Guaranteed Monotonic by Design over All Codes

AD5314

Resolution 10 10 Bits
Relative Accuracy ± 0.5 ± 4 ± 0.5 ± 2.5 LSB
Differential Nonlinearity ± 0.05 ± 0.5 ± 0.05 ± 0.5 LSB Guaranteed Monotonic by Design over All Codes

AD5324

Resolution 12 12 Bits
Relative Accuracy ± 2 ± 16 ± 2 ± 10 LSB

Differential Nonlinearity ± 0.2 ± 1 ± 0.2 ± 1 LSB Guaranteed Monotonic by Design over All Codes
Offset Error ± 0.4 ± 3 ± 0.4 ± 3% of FSR See Figures 2 and 3
Gain Error ± 0.15 ± 1 ± 0.15 ± 1% of FSR See Figures 2 and 3
Lower Deadband 20 60 20 60 mV Lower deadband exists only if offset error is

Offset Error Drift
Gain Error Drift
DC Power Supply Rejection Ratio
DC Crosstalk

DAC REFERENCE INPUTS

V

Input Range 0.25 VDD0.25 V

REF

V

Input Impedance 37 45 37 45 kW Normal Operation

REF

5

5

5

5

5

–12 –12 ppm of FSR/∞C
–5 –5 ppm of FSR/∞C
–60 –60 dB ⌬VDD = ± 10%
200 200 mVR

V

DD

>10 >10 MW Power-Down Mode

negative.

= 2 kW to GND or V

L

DD

Reference Feedthrough –90 –90 dB Frequency = 10 kHz

OUTPUT CHARACTERISTICS

Minimum Output Voltage
Maximum Output Voltage

5

6

6

0.001 0.001 V This is a measure of the minimum and maximum
VDD – 0.001 VDD – 0.001 V drive capability of the output amplifier.

DC Output Impedance 0.5 0.5 W
Short Circuit Current 25 25 mA VDD = 5 V

16 16 mA VDD = 3 V

Power-Up Time 2.5 2.5 ms Coming out of Power-Down Mode. VDD = 5 V

55ms Coming out of Power-Down Mode. VDD = 3 V

LOGIC INPUTS

5

Input Current ± 1 ± 1 mA
VIL, Input Low Voltage 0.8 0.8 V VDD = 5 V ± 10%

0.6 0.6 V VDD = 3 V ± 10%

0.5 0.5 V VDD = 2.5 V

VIH, Input High Voltage 2.4 2.4 V VDD = 5 V ± 10%

2.1 2.1 V VDD = 3 V ± 10%

2.0 2.0 V VDD = 2.5 V

Pin Capacitance 3 3 pF

POWER REQUIREMENTS

V

DD

IDD (Normal Mode)

7

VDD = 4.5 V to 5.5 V 600 900 600 900 mAV

VDD = 2.5 V to 3.6 V 500 700 500 700 mAV
IDD (Power-Down Mode)

VDD = 4.5 V to 5.5 V 0.2 1 .02 1 mAV

VDD = 2.5 V to 3.6 V 0.08 1 0.08 1 mAV

NOTES

1

See the Terminology section.

2

Temperature range (A, B Version): –40∞C to +105∞C; typical at +25∞C.

3

DC specifications tested with the outputs unloaded.

4

Linearity is tested using a reduced code range: AD5304 (Code 8 to 248); AD5314 (Code 28 to 995); AD5324 (Code 115 to 3981).

5

Guaranteed by design and characterization, not production tested.

6

For the amplifier output to reach its minimum voltage, offset error must be negative. For the amplifier output to reach its maximum voltage, V
error must be positive.

7

IDD specification is valid for all DAC codes. Interface inactive. All DACs active. Load currents excluded.

Specifications subject to change without notice.

2.5 5.5 2.5 5.5 V

= VDD and VIL = GND

IH

= VDD and VIL = GND

IH

= VDD and VIL = GND

IH

= VDD and VIL = GND

IH

= VDD and offset plus gain

REF

REV. D–2–

AD5304/AD5314/AD5324

(VDD = 2.5 V to 5.5 V; RL = 2 k⍀ to GND; CL = 200 pF to GND; all specifications T

AC CHARACTERISTICS

Parameter

2

1

otherwise noted.)

A, B Version
Min Typ Max Unit Conditions/Comments

3

Output Voltage Settling Time V

= VDD = 5 V

REF

MIN

to T

MAX

, unless

AD5304 6 8 ms 1/4 Scale to 3/4 Scale Change (0x40 to 0xC0)
AD5314 7 9 ms 1/4 Scale to 3/4 Scale Change (0x100 to 0x300)
AD5324 8 10 ms 1/4 Scale to 3/4 Scale Change (0x400 to 0xC00)

Slew Rate 0.7 V/ms

Major-Code Transition Glitch Energy 12 nV-s 1 LSB Change around Major Carry

Digital Feedthrough 1 nV-s

Digital Crosstalk 1 nV-s

DAC-to-DAC Crosstalk 3 nV-s

Multiplying Bandwidth 200 kHz V

Total Harmonic Distortion –70 dB V

NOTES

1

Guaranteed by design and characterization, not production tested.

2

See the Terminology section.

3

Temperature range (A, B Version): –40∞C to +105∞ C; typical at +25∞C.

Specifications subject to change without notice.

TIMING CHARACTERISTICS

Limit at T

1, 2, 3

MIN

(VDD = 2.5 V to 5.5 V. All specifications T

, T

MAX

= 2 V ± 0.1 V p-p

REF

= 2.5 V ± 0.1 V p-p. Frequency = 10 kHz

REF

to T

MIN

, unless otherwise noted.)

MAX

Parameter VDD = 2.5 V to 3.6 V VDD = 3.6 V to 5.5 V Unit Conditions/Comments

t

1

t

2

t

3

t

4

t

5

t

6

t

7

t

8

NOTES

1

Guaranteed by design and characterization, not production tested.

2

All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.

3

See Figure 1.

Specifications subject to change without notice.

40 33 ns min SCLK Cycle Time
16 13 ns min SCLK High Time
16 13 ns min SCLK Low Time
16 13 ns min SYNC to SCLK Falling Edge Setup Time
55ns min Data Setup Time

4.5 4.5 ns min Data Hold Time
00ns min SCLK Falling Edge to SYNC Rising Edge
80 33 ns min Minimum SYNC High Time

REV. D

SCLK

SYNC

DIN

t

1

t

t

t

8

DB15

t

4

t

6

t

5

3

2

DB0

t

7

Figure 1. Serial Interface Timing Diagram

–3–

AD5304/AD5314/AD5324

ABSOLUTE MAXIMUM RATINGS

(TA = 25∞C, unless otherwise noted.)

VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

Digital Input Voltage to GND . . . . . . . –0.3 V to V

Reference Input Voltage to GND . . . . –0.3 V to V

A–D to GND . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V

V

OUT

Operating Temperature Range

Industrial (A, B Version) . . . . . . . . . . . . . –40∞C to +105∞C

Storage Temperature Range . . . . . . . . . . . –65∞C to +150∞C

Junction Temperature (T

max) . . . . . . . . . . . . . . . . . 150∞C

J

1, 2

+ 0.3 V

DD

+ 0.3 V

DD

10-Lead MSOP

Power Dissipation . . . . . . . . . . . . . . . . . . (T

max – TA)/␪

J

␪JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 206∞C/W

␪

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 44∞C/W

JC

Reflow Soldering

Peak Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . 220∞C

Time at Peak Temperature . . . . . . . . . . . . . 10 sec to 40 sec

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause perma­nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating condi­tions for extended periods may affect device reliability.

2

Transient currents of up to 100 mA will not cause SCR latch-up.

ORDERING GUIDE

Model Temperature Range Package Description Package Option Branding

AD5304ARM –40∞C to +105∞C 10-Lead MSOP RM-10 DBA
AD5304ARM-REEL7 –40∞C to +105∞C 10-Lead MSOP RM-10 DBA
AD5314ARM –40∞C to +105∞C 10-Lead MSOP RM-10 DCA
AD5314ARM-REEL7 –40∞C to +105∞C 10-Lead MSOP RM-10 DCA
AD5324ARM –40∞C to +105∞C 10-Lead MSOP RM-10 DDA
AD5324ARM-REEL7 –40∞C to +105∞C 10-Lead MSOP RM-10 DDA
AD5304BRM –40∞C to +105∞C 10-Lead MSOP RM-10 DBB
AD5304BRM-REEL –40∞C to +105∞C 10-Lead MSOP RM-10 DBB
AD5304BRM-REEL7 –40∞C to +105∞C 10-Lead MSOP RM-10 DBB
AD5304BRMZ-REEL* –40∞C to +105∞C 10-Lead MSOP RM-10 DBB
AD5314BRM –40∞C to +105∞C 10-Lead MSOP RM-10 DCB
AD5314BRM-REEL –40∞C to +105∞C 10-Lead MSOP RM-10 DCB
AD5314BRM-REEL7 –40∞C to +105∞C 10-Lead MSOP RM-10 DCB
AD5324BRM –40∞C to +105∞C 10-Lead MSOP RM-10 DDB
AD5324BRM-REEL –40∞C to +105∞C 10-Lead MSOP RM-10 DDB
AD5324BRM-REEL7 –40∞C to +105∞C 10-Lead MSOP RM-10 DDB

*A pb (lead) free product

JA

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD5304/AD5314/AD5324 feature proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions
are recommended to avoid performance degradation or loss of functionality.

REV. D–4–

PIN CONFIGURATION

AD5304/AD5314/AD5324

V

V

OUT

V

OUT

V

OUT

REFIN

DD

A

B

C

1

AD5304/

2

AD5314/

3

AD5324

4

TOP VIEW

(Not to Scale)

5

SYNC

10

SCLK

9

DIN

8

GND

7

6

V

D

OUT

PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic Function

1V

DD

Power Supply Input. These parts can be operated from 2.5 V to 5.5 V and the supply should be decoupled

to GND.
2V
3V
4V
5 REFIN Reference Input Pin for All Four DACs. It has an input range from 0.25 V to V
6V

ABuffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.

OUT

BBuffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.

OUT

CBuffered Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.

OUT

DBuffered Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.

OUT

DD

.

7GND Ground Reference Point for All Circuitry on the Part.
8DIN Serial Data Input. This device has a 16-bit shift register. Data is clocked into the register on the falling

edge of the serial clock input. The DIN input buffer is powered down after each write cycle.
9 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input.

Data can be transferred at clock speeds up to 30 MHz. The SCLK input buffer is powered down after each

write cycle.
10 SYNC Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes

low, it enables the input shift register and data is transferred in on the falling edges of the following 16

clocks. If SYNC is taken high before the 16th falling edge of SCLK, the rising edge of SYNC acts as an

interrupt and the write sequence is ignored by the device.

REV. D

–5–