ANALOG DEVICES AD5304, AD5314, AD5324 Service Manual

2.5 V to 5.5 V, 500 μA, Quad Voltage Output

V

8-/10-/12-Bit DACs in 10-Lead Packages

Data Sheet

FEATURES

AD5304: 4 buffered 8-Bit DACs in 10-lead MSOP and

10-lead LFCSP A, W Version: ±1 LSB INL, B Version: ±0.625 LSB INL

AD5314: 4 buffered 10-Bit DACs in 10-lead MSOP and

10-lead LFCSP A, W Version: ±4 LSB INL, B Version: ±2.5 LSB INL

AD5324: 4 buffered 12-Bit DACs in 10-lead MSOP and

10-lead LFCSP A, W Version: ±16 LSB INL, B Version: ±10 LSB INL

Low power operation: 500 µA @ 3 V, 600 µA @ 5 V

2.5 V to 5.5 V power supply Guaranteed monotonic by design over all codes Power-down to 80 nA @ 3 V, 200 nA @ 5 V Double-buffered input logic Output range: 0 V to V Power-on reset to 0 V Simultaneous update of outputs ( Low power-, SPI®-, QSPI™-, MICROWIRE™-, and DSP-

compatible 3-wire serial interface On-chip, rail-to-rail output buffer amplifiers Temperature range −40°C to +105°C Qualified for automotive applications

APPLICATIONS

Portable battery-powered instruments Digital gain and offset adjustment Programmable voltage and current sources Programmable attenuators Industrial process controls

REF

LDAC

function)

FUNCTIONAL BLOCK DIAGRAM

AD5304/AD5314/AD5324

GENERAL DESCRIPTION

The AD5304/AD5314/AD53241 are quad 8-, 10-, and 12-bit buffered voltage output DACs in 10-lead MSOP and 10-lead LFCSP packages that operate from a single 2.5 V to 5.5 V supply, consuming 500 µA at 3 V. Their on-chip output amplifiers allow rail-to-rail output swing to be achieved with a slew rate of 0.7 V/µs. A 3-wire serial interface is used; it operates at clock rates up to 30 MHz and is compatible with standard SPI, QSPI, MICROWIRE, and DSP interface standards.

The references for the four DACs are derived from one reference pin. The outputs of all DACs can be updated simultaneously using

REFIN

LDAC

function. The parts incorporate a power-on

the software reset circuit, and ensure that the DAC outputs power up to 0 V and remains there until a valid write takes place to the device. The parts contain a power-down feature that reduces the current consumption of the device to 200 nA @ 5 V (80 nA @ 3 V).

The low power consumption of these parts in normal operation makes them ideally suited to portable battery-operated equipment. The power consumption is 3 mW at 5 V, 1.5 mW at 3 V, reducing to 1 µW in power-down mode.

1

Protected by U.S. Patent No. 5,969,657.

DD

AD5304/AD5314/AD5324

SCLK

SYNC

DIN

Rev. H

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

LOGIC

INTERFACE

INPUT

REGISTER

INPUT

REGISTER

INPUT

REGISTER

INPUT

REGISTER

LDAC

REGISTER

GND

Figure 1.

BUFFER

DAC

STRING

DAC A

BUFFER

STRING

DAC B

BUFFER

STRING

DAC C

BUFFER

STRING

DAC D

POWER-DOWN LOGICPOWER-ON RESET

V

A

OUT

V

B

OUT

V

C

OUT

V

D

OUT

00929-001

AD5304/AD5314/AD5324 Data Sheet

REVISION HISTORY

9/11—Rev. G to Rev. H

Changes to Table 4 ............................................................................ 6

5/11—Rev. F to Rev. G

Added W Version ............................................................... Universal

Added EPAD Notation to Figure 4 ................................................. 7

Updated Outline Dimensions ....................................................... 22

Changes to Ordering Guide .......................................................... 23

Added Automotive Products Section .......................................... 23

9/06—Rev. E to Rev. F

Updated Format .................................................................. Universal

Changes to Specifications Section .................................................. 3

Changes to Table 5 ............................................................................ 7

Updated Outline Dimensions ...................................................... 22

Changes to Ordering Guide .......................................................... 23

5/05—Rev. D to Rev. E

Added 10-lead LFCSP package ......................................... Universal

Changes to Title ................................................................................ 1

Changes to Ordering Guide ............................................................ 4

Theory of Operation ...................................................................... 14

Functional Description .............................................................. 14

Power-On Reset .......................................................................... 14

Serial Interface ............................................................................ 14

Power-Down Mode .................................................................... 16

Microprocessor Interfacing ....................................................... 16

Applications Information .............................................................. 18

Typical Application Circuit ....................................................... 18

Decoding Multiple AD5304/AD5314/AD5324s .................... 19

Power Supply Bypassing and Grounding ................................ 20

Outline Dimensions ....................................................................... 22

Ordering Guide .......................................................................... 23

Automotive Products ................................................................. 23

8/03—Rev. C to Rev. D

Added A Version ................................................................ Universal

Changes to Features .......................................................................... 1

Changes to Specifications ................................................................. 2

Changes to Absolute Maximum Ratings ........................................ 4

Changes to Ordering Guide ............................................................. 4

Changes to Figure 6 ........................................................................ 11

Added OCTALS Section to Table 2 .............................................. 15

Updated Outline Dimensions ....................................................... 16

Rev. H | Page 2 of 24

Data Sheet AD5304/AD5314/AD5324

SPECIFICATIONS

VDD = 2.5 V to 5.5 V; V

Table 1.

Parameter1

DC PERFORMANCE

AD5304

Resolution 8 8 Bits Relative Accuracy ±0.15 ±1 ±0.15 ±0.625 LSB Differential Nonlinearity ±0.02 ±0.25 ±0.02 ±0.25 LSB

AD5314

Resolution 10 10 Bits Relative Accuracy ±0.5 ±4 ±0.5 ±2.5 LSB Differential Nonlinearity ±0.05 ±0.5 ±0.05 ±0.5 LSB

AD5324

Resolution 12 12 Bits Relative Accuracy ±2 ±16 ±2 ±10 LSB Differential Nonlinearity ±0.2 ±1 ±0.2 ±1 LSB

Offset Error ±0.4 ±3 ±0.4 ±3 % of FSR See Figure 2 and Figure 3

Gain Error ±0.15 ±1 ±0.15 ±1 % of FSR See Figure 2 and Figure 3

Lower Dead Band 20 60 20 60 mV

Offset Error Drift5 –12 –12

Gain Error Drift5 –5 –5

DC Power Supply Rejection

5

Ratio

DC Crosstalk5 200 200 μV RL = 2 kΩ to GND or VDD

DAC REFERENCE INPUTS5

V

Input Range 0.25 V

REF

V

Input Impedance 37 45 37 45 kΩ Normal operation

REF

Reference Feedthrough

OUTPUT CHARACTERISTICS5

Minimum Output Voltage6 0.001

Maximum Output Voltage6 V

DC Output Impedance

Short Circuit Current

Power-Up Time

= 2 V; RL = 2 k to GND; CL = 200 pF to GND; all specifications T

REF

A, W Version

2

B Version2

MIN

to T

, unless otherwise noted.

MAX

Min Typ Max Min Typ Max Unit Test Conditions/Comments

3, 4

Guaranteed monotonic by design over all codes

Lower dead band exists only if offset error is negative

ppm of FSR/°C

–60 –60 dB ΔVDD = ±10%

>10 –90

0.25 V

DD

>10 –90

V

DD

MΩ Power-down mode dB Frequency = 10 kHz

0.001

V

Measurement of the minimum and maximum

– 0.001

DD

V

– 0.001

DD

V drive capability of the output amplifier

0.5 25 16 16 mA V

2.5

0.5 Ω 25 mA VDD = 5 V

2.5 μs

= 3 V

DD

Coming out of powerdown mode VDD = 5 V

5 5 μs

Coming out of powerdown mode V

DD

= 3 V

Rev. H | Page 3 of 24

AD5304/AD5314/AD5324 Data Sheet

A, W Version

Parameter1

LOGIC INPUTS5

Input Current VIL, Input Low Voltage

Min Typ Max Min Typ Max Unit Test Conditions/Comments

VIH, Input High Voltage 2.4

Pin Capacitance

POWER REQUIREMENTS

2.1

2.0 3 3

VDD 2.5 5.5 2.5 5.5 V IDD (Normal Mode)7

VDD = 4.5 V to 5.5 V VDD = 2.5 V to 3.6 V

IDD (Power-Down Mode)

VDD = 4.5 V to 5.5 V VDD = 2.5 V to 3.6 V

1

See the Terminology section.

2

Temperature range (A, B, W Version): −40°C to +105°C; typical at +25°C.

3

DC specifications tested with the outputs unloaded.

4

Linearity is tested using a reduced code range: AD5304 (Code 8 to Code 248); AD5314 (Code 28 to Code 995); AD5324 (Code 115 to Code 3981).

5

Guaranteed by design and characterization, not production tested.

6

For the amplifier output to reach its minimum voltage, offset error must be negative. For the amplifier output to reach its maximum voltage, V

gain error must be positive.

7

IDD specification is valid for all DAC codes; interface inactive; all DACs active; load currents excluded.

600 900 600 900 μA VIH = VDD and VIL = GND 500 700 500 700 μA VIH = VDD and VIL = GND

0.2 1 0.2 1 μA VIH = VDD and VIL = GND

0.08 1 0.08 1 μA VIH = VDD and VIL = GND

2

B Version2

±1 ±1 μA

0.8 0.8 V VDD = 5 V ± 10%

0.6 0.6 V V

0.5 0.5 V V

2.4

2.1

2.0

V VDD = 5 V ± 10% V V V V

pF

= 3 V ± 10%

DD

= 2.5 V

DD

= 3 V ± 10%

DD

= 2.5 V

DD

= VDD and offset plus

REF

AC CHARACTERISTICS

VDD = 2.5 V to 5.5 V; RL = 2 k to GND; CL = 200 pF to GND; all specifications T

Table 2.

A, B, W Version3

Parameter1, 2

Min Typ Max Unit Test Conditions/Comments

Output Voltage Settling Time V

AD5304 6 8 μs ¼ scale to ¾ scale change (0x40 to 0xC0) AD5314 7 9 μs ¼ scale to ¾ scale change (0x100 to 0x300)

AD5324 8 10 μs ¼ scale to ¾ scale change (0x400 to 0xC00) Slew Rate 0.7 V/μs Major-Code Transition Glitch Energy 12 nV-sec 1 LSB change around major carry Digital Feedthrough 1 nV-sec Digital Crosstalk 1 nV-sec DAC-to-DAC Crosstalk 3 nV-sec Multiplying Bandwidth 200 kHz V Total Harmonic Distortion –70 dB V

1

See the Terminology section.

2

Guaranteed by design and characterization, not production tested.

3

Temperature range (A, B, W Version): −40°C to +105°C; typical at +25°C.

MIN

to T

, unless otherwise noted.

MAX

= VDD = 5 V

REF

= 2 V ± 0.1 V p-p

REF

= 2.5 V ± 0.1 V p-p; frequency = 10 kHz

REF

Rev. H | Page 4 of 24

Data Sheet AD5304/AD5314/AD5324

TIMING CHARACTERISTICS

VDD = 2.5 V to 5.5 V; all specifications T

Table 3.

Parameter

1, 2, 3

VDD = 2.5 V to 3.6 V VDD = 3.6 V to 5.5 V Unit Test Conditions/Comments

t1 40 33 ns min SCLK cycle time t2 16 13 ns min SCLK high time t3 16 13 ns min SCLK low time t4 16 13 ns min

t5 5 5 ns min Data setup time t6 4.5 4.5 ns min Data hold time t7 0 0 ns min t8 80 33 ns min

1

Guaranteed by design and characterization, not production tested.

2

All input signals are specified with tr = tf = 5 ns (10% to 90 % of VDD) and timed from a voltage level of (VIL + VIH)/2.

3

See Figure 2.

SCLK

t

8

SYNC

DIN DB15

to T

MIN

Limit at T

t

4

t

6

t

5

, unless otherwise noted.

MAX

, T

MIN

MAX

t

1

t

3

2

DB0

t

7

Figure 2. Serial Interface Timing Diagram

to SCLK falling edge setup time

SYNC

SCLK falling edge to SYNC Minimum SYNC

high time

rising edge

00929-002

Rev. H | Page 5 of 24

AD5304/AD5314/AD5324 Data Sheet

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 4.

Parameter1 Rating

V

to GND –0.3 V to +7 V

DD

Digital Input Voltage to GND –0.3 V to V Reference Input Voltage to GND –0.3 V to V V

A through V

OUT

Operating Temperature Range

D to GND –0.3 V to VDD + 0.3 V

OUT

+ 0.3 V

DD

+ 0.3 V

DD

Industrial (A, B, W Version) –40°C to +105°C

Storage Temperature Range –65°C to +150°C

Junction Temperature (T 10-Lead MSOP

Power Dissipation (TJ max – TA)/ θ

θ

Thermal Impedance 206°C/W

JA

θ

Thermal Impedance 44°C/W

JC

10-Lead LFCSP

Power Dissipation (TJ max – TA)/ θ

θ

Thermal Impedance 84°C/W

JA

Reflow Soldering

max) 150°C

J

JA

Peak Temperature (Pb-free) 260°C

Peak Temperature (non Pb-free) 220°C

Time at Peak Temperature 10 sec to 40 sec

1

Transient currents of up to 100 mA do not cause SCR latch-up.

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

Rev. H | Page 6 of 24

Data Sheet AD5304/AD5314/AD5324

V

T

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

1

V

DD

2

V

A

OUT

V

B

3

OUT

C

V

4

OUT

(Not to S cale)

5

V

OUT

REFIN

DD

A

B

C

1

AD5304/

2

AD5314/

3

AD5324

4

TOP VIEW

(Not to Scale)

5

SYNC

10

9

SCLK

DIN

8

GND

7

V

D

6

OUT

0929-003

Figure 3. 10-Lead MSOP Pin Configuration

REFIN

NOTES

1. THE EXPOSED PAD IS THE GROUND REFERENCE POIN FOR ALL CIRCUITRY ON THE PART. IT CAN BE CONNECTED TO 0 V OR LEFT UNCONNECTED PROVIDED THERE IS A CONNECTION TO 0 V VIA THE GND PIN.

Figure 4. 10-Lead LFCSP Pin Configuration

Table 5. Pin Function Descriptions

Pin No. Mnemonic Description

1 V 2 V 3 V 4 V

Power Supply Input. These parts can be operated from 2.5 V to 5.5 V and the supply can be decoupled to GND.

DD

A Buffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.

OUT

B Buffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.

OUT

C Buffered Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.

OUT

5 REFIN Reference Input Pin for All Four DACs. It has an input range from 0.25 V to VDD. 6 V

D Buffered Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.

OUT

7 GND Ground Reference Point for All Circuitry on the Part. 8 DIN

Serial Data Input. This device has a 16-bit shift register. Data is clocked into the register on the falling edge of the serial clock input. The DIN input buffer is powered down after each write cycle.

9 SCLK

Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at clock speeds up to 30 MHz. The SCLK input buffer is powered down after each write cycle.

10

Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it

SYNC

enables the input shift register and data is transferred in on the falling edges of the following 16 clocks. If SYNC taken high before the 16th falling edge of SCLK, the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the device.

Exposed Paddle

1

For the 10-Lead LFCSP only.

Ground Reference Point for All Circuitry on the Part. Can be connected to 0 V or left unconnected provided there is

1

a connection to 0 V via the GND pin.

AD5304/ AD5314/

AD5324

TOP VIEW

10

SYNC

SCLK

9

8

DIN

7

GND

V

D

6

OUT

00929-004

is

Rev. H | Page 7 of 24

AD5304/AD5314/AD5324 Data Sheet

TYPICAL PERFORMANCE CHARACTERISTICS

1.0

0.5

TA = 25°C V

= 5V

DD

0.3

0.2

0.1

T

A

V

DD

= 25°C

= 5V

0

INL ERROR (LS B)

–0.5

–1.0

0 50 100 150 200 250

CODE

Figure 5. AD5304 Typical INL Plot

3

= 25°C

T

A

V

= 5V

DD

2

1

0

INL ERROR (LS B)

–1

–2

–3

0 200 400 600 800 1000

CODE

Figure 6. AD5314 Typical INL Plot

12

TA = 25°C V

= 5V

DD

8

4

0

–0.1

DNL ERRO R (LSB)

–0.2

–0.3

0 50 100 150 200 250

00929-005

CODE

00929-008

Figure 8. AD5304 Typical DNL Plot

0.6

= 25°C

T

A

V

= 5V

DD

0.4

0.2

0

–0.2

DNL ERRO R (LSB)

–0.4

–0.6

0 200 400 600 800 1000

00929-006

CODE

00929-009

Figure 9. AD5314 Typical DNL Plot

1.0 TA = 25°C

V

= 5V

DD

0.5

0

INL ERROR (LS B)

–4

–8

–12

0 500 1000 1500 2000 2500 3000 3500 4000

CODE

Figure 7. AD5324 Typical INL Plot

00929-007

Rev. H | Page 8 of 24

0

DNL ERRO R (LSB)

–0.5

–1.0

0 500 1000 1500 2000 2500 3000 3500 4000

CODE

Figure 10. AD5324 Typical DNL Plot

00929-010

ANALOG DEVICES AD5304, AD5314, AD5324 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

FUNCTIONAL BLOCK DIAGRAM

GENERAL DESCRIPTION

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

AC CHARACTERISTICS

TIMING CHARACTERISTICS

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS