Analog Devices AD5303 13 23 a Datasheet

2.5 V to 5.5 V, 230 ␮A, Dual Rail-to-Rail
Voltage Output 8-/10-/12-Bit DACs

FEATURES
AD5303: 2 Buffered 8-Bit DACs in 1 Package

A Version: ⴞ1 LSB INL, B Version: ⴞ0.5 LSB INL

AD5313: 2 Buffered 10-Bit DACs in 1 Package

A Version: ⴞ4 LSB INL, B Version: ⴞ2 LSB INL

AD5323: 2 Buffered 12-Bit DACs in 1 Package

A Version: ⴞ16 LSB INL, B Version: ⴞ8 LSB INL
16-Lead TSSOP Package
Micropower Operation: 300 ␮A @ 5 V (Including

Reference Current)
Power-Down to 200 nA @ 5 V, 50 nA @ 3 V

2.5 V to 5.5 V Power Supply
Double-Buffered Input Logic
Guaranteed Monotonic by Design over All Codes
Buffered/Unbuffered Reference Input Options
Output Range: 0 V to V

or 0 V to 2 V

REF

REF

Power-On-Reset to 0 V
SDO Daisy-Chaining Option
Simultaneous Update of DAC Outputs via LDAC Pin
Asynchronous CLR Facility
Low Power Serial Interface with Schmitt-Triggered

Inputs
On-Chip Rail-to-Rail Output Buffer Amplifiers

APPLICATIONS
Portable Battery-Powered Instruments
Digital Gain and Offset Adjustment
Programmable Voltage and Current Sources
Programmable Attenuators

AD5303/AD5313/AD5323

*

GENERAL DESCRIPTION

The AD5303/AD5313/AD5323 are dual 8-, 10-, and 12-bit
buffered voltage output DACs in a 16-lead TSSOP package that
operate from a single 2.5 V to 5.5 V supply consuming 230 µA at
3V. Their on-chip output amplifiers allow the outputs to swing
rail-to-rail with a slew rate of 0.7 V/µs. The AD5303/AD5313/
AD5323 utilize a versatile 3-wire serial interface that operates at
clock rates up to 30 MHz and is compatible with standard SPI

®

,

QSPI™, MICROWIRE™, and DSP interface standards.

The references for the two DACs are derived from two reference
pins (one per DAC). These reference inputs may be configured as
buffered or unbuffered inputs. The parts incorporate a power-on
reset circuit, which ensures that the DAC outputs power-up to
0V and remain there until a valid write to the device takes place.
There is also an asynchronous active low CLR pin that clears
both DACs to 0 V. The outputs of both DACs may be updated
simultaneously using the asynchronous LDAC input. The parts
contain a power-down feature that reduces the current consump­tion of the devices to 200 nA at 5 V (50 nA at 3 V) and provides
software-selectable output loads while in power-down mode. The
parts may also be used in daisy-chaining applications using the
SDO pin.

The low power consumption of these parts in normal operation
makes them ideally suited to portable battery-operated equipment.
The power consumption is 1.5 mW at 5 V, 0.7 mW at 3 V,
reducing to 1 µW in power-down mode.

FUNCTIONAL BLOCK DIAGRAM

V

DD

BUF A

POWER-ON

RESET

INPUT

REGISTER

SYNC

SCLK

DIN

SDO

*Protected by U.S. Patent No. 5684481; other patents pending.

DCEN

INTERFACE

LOGIC

>

LDAC

CLR

INPUT

REGISTER

PD

DAC

REGISTER

DAC

REGISTER

BUF B

REV. A

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.

V

A

REF

AD5303/AD5313/AD5323

STRING

DAC

POWER-DOWN

LOGIC

STRING

DAC

B

V

REF

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2003 Analog Devices, Inc. All rights reserved.

BUFFER

BUFFER

GAIN-SELECT

LOGIC

GND

RESISTOR
NETWORK

RESISTOR
NETWORK

V

A

OUT

V

B

OUT

AD5303/AD5313/AD5323–SPECIFICATIONS

= 200 pF to GND; all specifications T

C

L

Parameter

1

DC PERFORMANCE

3, 4

A Version
Min Typ Max Min Typ Max Unit Conditions/Comments

MIN

to T

, unless otherwise noted.)

MAX

2

B Version

2

(VDD = 2.5 V to 5.5 V; V

= 2 V; RL = 2 k⍀ to GND;

REF

AD5303

Resolution 8 8 Bits
Relative Accuracy ± 0.15 ± 1 ± 0.15 ± 0.5 LSB
Differential Nonlinearity ± 0.02 ± 0.25 ± 0.02 ± 0.25 LSB Guaranteed Monotonic by Design over All Codes

AD5313

Resolution 10 10 Bits
Relative Accuracy ± 0.5 ± 4 ±0.5 ± 2 LSB
Differential Nonlinearity ± 0.05 ± 0.5 ± 0.05 ± 0.5 LSB Guaranteed Monotonic by Design over All Codes

AD5323

Resolution 12 12 Bits
Relative Accuracy ± 2 ± 16 ±2 ± 8 LSB

Differential Nonlinearity ± 0.2 ± 1 ±0.2 ± 1 LSB Guaranteed Monotonic by Design over All Codes
Offset Error ± 0.4 ± 3 ±0.4 ± 3% of FSR See Figures 3 and 4
Gain Error ± 0.15 ± 1 ±0.15 ± 1% of FSR See Figures 3 and 4
Lower Deadband 10 60 10 60 mV See Figures 3 and 4
Offset Error Drift
Gain Error Drift
Power Supply Rejection Ratio
DC Crosstalk

DAC REFERENCE INPUTS

V

Input Range 1 VDD1V

REF

V

Input Impedance >10 >10 MΩ Buffered Reference Mode

REF

Reference Feedthrough –90 –90 dB Frequency = 10 kHz

5

5

5

5

5

–12 –12 ppm of FSR/°C
–5 –5 ppm of FSR/°C
–60 –60 dB VDD = ± 10%

30 30 µV

V Buffered Reference Mode

0V

0V

DD

DD

V Unbuffered Reference Mode

DD

180 180 kΩ Unbuffered Reference Mode

90 90 kΩ Unbuffered Reference Mode

0 V to V

0 V to 2 V

Output Range, Input Impedance = R

REF

Output Range, Input Impedance = R

REF

Channel-to-Channel Isolation –80 –80 dB Frequency = 10 kHz

OUTPUT CHARACTERISTICS

Minimum Output Voltage
Maximum Output Voltage

5

6

6

0.001 0.001 V min This is a measure of the minimum and maximum

VDD – 0.001 VDD – 0.001 V max drive capability of the output amplifier.
DC Output Impedance 0.5 0.5 Ω
Short Circuit Current 50 50 mA VDD = 5 V

20 20 mA VDD = 3 V
Power-Up Time 2.5 2.5 µs Coming out of Power-Down Mode. VDD = 5 V

55µs Coming out of Power-Down Mode. VDD = 3 V

LOGIC INPUTS

5

Input Current ± 1 ± 1 µA
VIL, Input Low Voltage 0.8 0.8 V VDD = 5 V ± 10%

0.6 0.6 V VDD = 3 V ± 10%

0.5 0.5 V VDD = 2.5 V

VIH, Input High Voltage 2.4 2.4 V VDD = 5 V ± 10%

2.1 2.1 V VDD = 3 V ± 10%

2.0 2.0 V VDD = 2.5 V

Pin Capacitance 2 3.5 2 3.5 pF

LOGIC OUTPUT (SDO)

5

VDD = 5 V ± 10%

Output Low Voltage 0.4 0.4 V I
Output High Voltage 4.0 4.0 V I

VDD = 3 V ± 10%

Output Low Voltage 0.4 0.4 V I
Output High Voltage 2.4 2.4 V I

Floating-State Leakage Current 1 1 µA DCEN = GND

= 2 mA

SINK

SOURCE

= 2 mA

SINK

SOURCE

= 2 mA

= 2 mA

Floating State O/P Capacitance 3 3 pF DCEN = GND

POWER REQUIREMENTS

V

DD

IDD (Normal Mode) Both DACs Active and Excluding Load Currents

2.5 5.5 2.5 5.5 V IDD specification is valid for all DAC codes.

VDD = 4.5 V to 5.5 V 300 450 300 450 µA Both DACs in Unbuffered mode. VIH = VDD and
VDD = 2.5 V to 3.6 V 230 350 230 350 µAV

IDD (Full Power-Down)

= GND. In Buffered mode, extra current is

IL

typically x µA per DAC where x = 5 µA + V

REF/RDAC

VDD = 4.5 V to 5.5 V 0.2 1 0.2 1 µA
VDD = 2.5 V to 3.6 V 0.05 1 0.05 1 µA

DAC

DAC

.

REV. A–2–

AD5303/AD5313/AD5323

NOTES

1

See Terminology section.

2

Temperature range: A, B Version: –40°C to +105°C.

3

DC specifications tested with the outputs unloaded.

4

Linearity is tested using a reduced code range: AD5303 (Code 8 to 248); AD5313 (Code 28 to 995); AD5323 (Code 115 to 3981).

5

Guaranteed by design and characterization, not production tested.

6

In order for the amplifier output to reach its minimum voltage, offset error must be negative. In order for the amplifier output to reach its maximum voltage, V
and offset plus gain error must be positive.

Specifications subject to change without notice.

REF

= V

DD

(VDD = 2.5 V to 5.5 V; RL = 2 k⍀ to GND; CL = 200 pF to GND; all specifications T

1

AC CHARACTERISTICS

Parameter

2

otherwise noted.)

A, B Version

3

Min Typ Max Unit Conditions/Comments

Output Voltage Settling Time V

= VDD = 5 V

REF

MIN

to T

, unless

MAX

AD5303 6 8 µs 1/4 Scale to 3/4 Scale Change (0x40 to 0xC0)
AD5313 7 9 µs 1/4 Scale to 3/4 Scale Change (0x100 to 0x300)

AD5323 8 10 µs 1/4 Scale to 3/4 Scale Change (0x400 to 0xC00)
Slew Rate 0.7 V/µs
Major-Code Transition Glitch Energy 12 nV-s 1 LSB Change around Major Carry

(011 . . . 11 to 100 . . . 00)
Digital Feedthrough 0.10 nV-s
Analog Crosstalk 0.01 nV-s
DAC-to-DAC Crosstalk 0.01 nV-s
Multiplying Bandwidth 200 kHz V
Total Harmonic Distortion –70 dB V

NOTES

1

Guaranteed by design and characterization, not production tested.

2

See Terminology section.

3

Temperature range: A, B Version: –40°C to +105°C.

Specifications subject to change without notice.

TIMING CHARACTERISTICS

Limit at T

MIN

, T

1, 2, 3

MAX

(VDD = 2.5 V to 5.5 V; all specifications T

= 2 V ± 0.1 V p-p, Unbuffered Mode

REF

= 2.5 V ± 0.1 V p-p, Frequency = 10 kHz

REF

to T

MIN

, unless otherwise noted.)

MAX

Parameter (A, B Version) Unit Conditions/Comments

t

1

t

2

t

3

t

4

t

5

t

6

t

7

t

8

t

9

t

10

t

11

4, 5

t

12

4, 5

t

13

5

t

14

5

t

15

NOTES

1

Guaranteed by design and characterization, not production tested.

2

All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.

3

See Figures 1 and 2.

4

These are measured with the load circuit of Figure 1.

5

Daisy-chain mode only. (See Figure 23.)

Specifications subject to change without notice.

33 ns min SCLK Cycle Time
13 ns min SCLK High Time
13 ns min SCLK Low Time
0 ns min SYNC to SCLK Rising Edge Setup Time
5 ns min Data Setup Time

4.5 ns min Data Hold Time
0 ns min SCLK Falling Edge to SYNC Rising Edge
100 ns min Minimum SYNC High Time
20 ns min LDAC Pulsewidth
20 ns min SCLK Falling Edge to LDAC Rising Edge
20 ns min CLR Pulsewidth
5 ns min SCLK Falling Edge to SDO Invalid
20 ns max SCLK Falling Edge to SDO Valid
0 ns min SCLK Falling Edge to SYNC Rising Edge
10 ns min SYNC Rising Edge to SCLK Rising Edge

REV. A

–3–

AD5303/AD5313/AD5323

Figure 1. Load Circuit for Digital Output (SDO) Timing Specifications

SCLK

t

8

SYNC

*

DIN

LDAC

LDAC

DB15

I

2mA

TO

OUTPUT

PIN

C

L

50pF

2mA

t

1

t

t

t

4

t

6

t

5

3

2

DB0

OL

1.6V

I

OH

t

7

t

9

t

10

CLR

*

SEE INPUT SHIFT REGISTER SECTION

Figure 2. Serial Interface Timing Diagram

t

11

REV. A–4–

AD5303/AD5313/AD5323

ABSOLUTE MAXIMUM RATINGS

(TA = 25°C, unless otherwise noted.)

1, 2

VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

Digital Input Voltage to GND . . . . . . . . –0.3 V to V

Digital Output Voltage to GND . . . . . . –0.3 V to V

Reference Input Voltage to GND . . . . . –0.3 V to V

V

OUT

A, V

B to GND . . . . . . . . . . . . –0.3 V to VDD + 0.3 V

OUT

+ 0.3 V

DD

+ 0.3 V

DD

+ 0.3 V

DD

Operating Temperature Range

Industrial (A, B Version) . . . . . . . . . . . . . .–40°C to +105°C

Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C

Junction Temperature (T

Max) . . . . . . . . . . . . . . . . . . 150°C

J

16-Lead TSSOP Package

Power Dissipation . . . . . . . . . . . . . . . . . . . (T

Max – TA)/␪

J

JA

␪JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 160°C/W

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause perma­nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating condi­tions for extended periods may affect device reliability.

2

Transient currents of up to 100 mA will not cause SCR latch-up.

ORDERING GUIDE

PIN CONFIGURATION

CLR

LDAC

V

V

REF

V

REF

V

OUT

BUF A

BUF B

DD

B

A

A

1

2

AD5303/

3

AD5313/

AD5323

4

TOP VIEW

5

(Not to Scale)

6

7

8

16

SDO

GND

15

14

DIN

13

SCLK

12

SYNC

11

V

B

OUT

10

PD

9

DCEN

Model Temperature Range Package Description Package Option

AD5303ARU –40°C to +105°CThin Shrink Small Outline Package (TSSOP) RU-16
AD5303ARU-REEL7 –40°C to +105°CThin Shrink Small Outline Package (TSSOP) RU-16
AD5313ARU –40°C to +105°CThin Shrink Small Outline Package (TSSOP) RU-16
AD5313ARU-REEL7 –40°C to +105°CThin Shrink Small Outline Package (TSSOP) RU-16
AD5323ARU –40°C to +105°CThin Shrink Small Outline Package (TSSOP) RU-16
AD5323ARU-REEL7 –40°C to +105°CThin Shrink Small Outline Package (TSSOP) RU-16
AD5303BRU –40°C to +105°CThin Shrink Small Outline Package (TSSOP) RU-16
AD5303BRU-REEL –40°C to +105°CThin Shrink Small Outline Package (TSSOP) RU-16
AD5303BRU-REEL7 –40°C to +105°CThin Shrink Small Outline Package (TSSOP) RU-16
AD5313BRU –40°C to +105°CThin Shrink Small Outline Package (TSSOP) RU-16
AD5313BRU-REEL –40°C to +105°CThin Shrink Small Outline Package (TSSOP) RU-16
AD5313BRU-REEL7 –40°C to +105°CThin Shrink Small Outline Package (TSSOP) RU-16
AD5323BRU –40°C to +105°CThin Shrink Small Outline Package (TSSOP) RU-16
AD5323BRU-REEL –40°C to +105°CThin Shrink Small Outline Package (TSSOP) RU-16
AD5323BRU-REEL7 –40°C to +105°CThin Shrink Small Outline Package (TSSOP) RU-16

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD5303/AD5313/AD5323 feature proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions
are recommended to avoid performance degradation or loss of functionality.

REV. A

–5–

AD5303/AD5313/AD5323

PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic Function

1 CLR Active Low Control Input that Loads All Zeros to Both Input and DAC Registers.
2 LDAC Active Low Control Input that Transfers the Contents of the Input Registers to their Respective DAC Registers.

Pulsing this pin low allows either or both DAC registers to be updated if the input registers have new data.
This allows simultaneous update of both DAC outputs

3V

4V

5V

6V

DD

BReference Input Pin for DAC B. This is the reference for DAC B. It may be configured as a buffered or an

REF

AReference Input Pin for DAC A. This is the reference for DAC A. It may be configured as a buffered or an

REF

ABuffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.

OUT

7 BUF A Control Pin that Controls whether the Reference Input for DAC A is Unbuffered or Buffered. If this pin is

8 BUF B Control Pin that Controls whether the Reference Input for DAC B is Unbuffered or Buffered. If this pin is

9 DCEN This pin is used to enable the daisy-chaining option. This should be tied high if the part is being used in a

10 PD Active Low Control Input that Acts as a Hardware Power-Down Option. This pin overrides any software

11 V

BBuffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.

OUT

12 SYNC Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes

13 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input.

14 DIN Serial Data Input. This device has a 16-bit shift register. Data is clocked into the register on the falling edge

15 GND Ground Reference Point for All Circuitry on the Part.

16 SDO Serial Data Output. Can be used for daisy-chaining a number of these devices together or for reading back the

Power Supply Input. These parts can be operated from 2.5 V to 5.5 V, and the supply should be decoupled
to GND.

unbuffered input, depending on the state of the BUF B pin. It has an input range from 0 V to V
unbuffered mode and from 1 V to V

in buffered mode.

DD

DD

in

unbuffered input depending on the state of the BUF A pin. It has an input range from 0 to VDD in unbuffered
mode and from 1 V to V

in buffered mode.

DD

tied low, the reference input is unbuffered. If it is tied high, the reference input is buffered.

tied low, the reference input is unbuffered. If it is tied high, the reference input is buffered.

daisy-chain. The pin should be tied low if it is being used in standalone mode.

power-down option. Both DACs go into power-down mode when this pin is tied low. The DAC outputs go
into a high impedance state and the current consumption of the part drops to 200 nA @ 5 V (50 nA @ 3 V).

low, it powers on the SCLK and DIN buffers and enables the input shift register. Data is transferred in on
the falling edges of the following 16 clocks. If SYNC is taken high before the 16th falling edge, the rising
edge of SYNC acts as an interrupt and the write sequence is ignored by the device.

Data can be transferred at rates up to 30 MHz. The SCLK input buffer is powered down after each write cycle.

of the serial clock input. The DIN input buffer is powered down after each write cycle.

data in the shift register for diagnostic purposes. The serial data output is valid on the falling edge of the clock.

TERMINOLOGY
Relative Accuracy

For the DAC, relative accuracy or integral nonlinearity (INL) is
a measure of the maximum deviation, in LSB, from a straight
line passing through the actual endpoints of the DAC transfer
function. A typical INL versus code plot can be seen in TPC 1.

Differential Nonlinearity

Differential nonlinearity (DNL) is the difference between the
measured change and the ideal 1 LSB change between any two
adjacent codes. A specified DNL of ±1 LSB maximum ensures
monotonicity. This DAC is guaranteed monotonic by design.
A typical DNL versus code plot can be seen in TPC 4.

Offset Error

This is a measure of the offset error of the DAC and the output
amplifier. It is expressed as a percentage of the full-scale range.

Gain Error

This is a measure of the span error of the DAC. It is the devia­tion in slope of the actual DAC transfer characteristic from the
ideal expressed as a percentage of the full-scale range.

Offset Error Drift

This is a measure of the change in offset error with changes in
temperature. It is expressed in (ppm of full-scale range)/°C.

Gain Error Drift

This is a measure of the change in gain error with changes in
temperature. It is expressed in (ppm of full-scale range)/°C.

REV. A–6–