Datasheet AD5303 Datasheet (Analog Devices)

2.5 V to 5.5 V, 230 ␮A, Dual Rail-to-Rail
Voltage Output 8-/10-/12-Bit DACs

FEATURES
AD5303: 2 Buffered 8-Bit DACs in 1 Package

A Version: ⴞ1 LSB INL, B Version: ⴞ0.5 LSB INL

AD5313: 2 Buffered 10-Bit DACs in 1 Package

A Version: ⴞ4 LSB INL, B Version: ⴞ2 LSB INL

AD5323: 2 Buffered 12-Bit DACs in 1 Package

A Version: ⴞ16 LSB INL, B Version: ⴞ8 LSB INL
16-Lead TSSOP Package
Micropower Operation: 300 ␮A @ 5 V (Including

Reference Current)
Power-Down to 200 nA @ 5 V, 50 nA @ 3 V

2.5 V to 5.5 V Power Supply
Double-Buffered Input Logic
Guaranteed Monotonic by Design over All Codes
Buffered/Unbuffered Reference Input Options
Output Range: 0 V to V

or 0 V to 2 V

REF

REF

Power-On-Reset to 0 V
SDO Daisy-Chaining Option
Simultaneous Update of DAC Outputs via LDAC Pin
Asynchronous CLR Facility
Low Power Serial Interface with Schmitt-Triggered

Inputs
On-Chip Rail-to-Rail Output Buffer Amplifiers

APPLICATIONS
Portable Battery-Powered Instruments
Digital Gain and Offset Adjustment
Programmable Voltage and Current Sources
Programmable Attenuators

AD5303/AD5313/AD5323

*

GENERAL DESCRIPTION

The AD5303/AD5313/AD5323 are dual 8-, 10-, and 12-bit
buffered voltage output DACs in a 16-lead TSSOP package that
operate from a single 2.5 V to 5.5 V supply consuming 230 µA at
3V. Their on-chip output amplifiers allow the outputs to swing
rail-to-rail with a slew rate of 0.7 V/µs. The AD5303/AD5313/
AD5323 utilize a versatile 3-wire serial interface that operates at
clock rates up to 30 MHz and is compatible with standard SPI

®

,

QSPI™, MICROWIRE™, and DSP interface standards.

The references for the two DACs are derived from two reference
pins (one per DAC). These reference inputs may be configured as
buffered or unbuffered inputs. The parts incorporate a power-on
reset circuit, which ensures that the DAC outputs power-up to
0V and remain there until a valid write to the device takes place.
There is also an asynchronous active low CLR pin that clears
both DACs to 0 V. The outputs of both DACs may be updated
simultaneously using the asynchronous LDAC input. The parts
contain a power-down feature that reduces the current consump­tion of the devices to 200 nA at 5 V (50 nA at 3 V) and provides
software-selectable output loads while in power-down mode. The
parts may also be used in daisy-chaining applications using the
SDO pin.

The low power consumption of these parts in normal operation
makes them ideally suited to portable battery-operated equipment.
The power consumption is 1.5 mW at 5 V, 0.7 mW at 3 V,
reducing to 1 µW in power-down mode.

FUNCTIONAL BLOCK DIAGRAM

V

DD

BUF A

POWER-ON

RESET

INPUT

REGISTER

SYNC

SCLK

DIN

SDO

*Protected by U.S. Patent No. 5684481; other patents pending.

DCEN

INTERFACE

LOGIC

>

LDAC

CLR

INPUT

REGISTER

PD

DAC

REGISTER

DAC

REGISTER

BUF B

REV. A

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.

V

A

REF

AD5303/AD5313/AD5323

STRING

DAC

POWER-DOWN

LOGIC

STRING

DAC

B

V

REF

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2003 Analog Devices, Inc. All rights reserved.

BUFFER

BUFFER

GAIN-SELECT

LOGIC

GND

RESISTOR
NETWORK

RESISTOR
NETWORK

V

A

OUT

V

B

OUT

AD5303/AD5313/AD5323–SPECIFICATIONS

= 200 pF to GND; all specifications T

C

L

Parameter

1

DC PERFORMANCE

3, 4

A Version
Min Typ Max Min Typ Max Unit Conditions/Comments

MIN

to T

, unless otherwise noted.)

MAX

2

B Version

2

(VDD = 2.5 V to 5.5 V; V

= 2 V; RL = 2 k⍀ to GND;

REF

AD5303

Resolution 8 8 Bits
Relative Accuracy ± 0.15 ± 1 ± 0.15 ± 0.5 LSB
Differential Nonlinearity ± 0.02 ± 0.25 ± 0.02 ± 0.25 LSB Guaranteed Monotonic by Design over All Codes

AD5313

Resolution 10 10 Bits
Relative Accuracy ± 0.5 ± 4 ±0.5 ± 2 LSB
Differential Nonlinearity ± 0.05 ± 0.5 ± 0.05 ± 0.5 LSB Guaranteed Monotonic by Design over All Codes

AD5323

Resolution 12 12 Bits
Relative Accuracy ± 2 ± 16 ±2 ± 8 LSB

Differential Nonlinearity ± 0.2 ± 1 ±0.2 ± 1 LSB Guaranteed Monotonic by Design over All Codes
Offset Error ± 0.4 ± 3 ±0.4 ± 3% of FSR See Figures 3 and 4
Gain Error ± 0.15 ± 1 ±0.15 ± 1% of FSR See Figures 3 and 4
Lower Deadband 10 60 10 60 mV See Figures 3 and 4
Offset Error Drift
Gain Error Drift
Power Supply Rejection Ratio
DC Crosstalk

DAC REFERENCE INPUTS

V

Input Range 1 VDD1V

REF

V

Input Impedance >10 >10 MΩ Buffered Reference Mode

REF

Reference Feedthrough –90 –90 dB Frequency = 10 kHz

5

5

5

5

5

–12 –12 ppm of FSR/°C
–5 –5 ppm of FSR/°C
–60 –60 dB VDD = ± 10%

30 30 µV

V Buffered Reference Mode

0V

0V

DD

DD

V Unbuffered Reference Mode

DD

180 180 kΩ Unbuffered Reference Mode

90 90 kΩ Unbuffered Reference Mode

0 V to V

0 V to 2 V

Output Range, Input Impedance = R

REF

Output Range, Input Impedance = R

REF

Channel-to-Channel Isolation –80 –80 dB Frequency = 10 kHz

OUTPUT CHARACTERISTICS

Minimum Output Voltage
Maximum Output Voltage

5

6

6

0.001 0.001 V min This is a measure of the minimum and maximum

VDD – 0.001 VDD – 0.001 V max drive capability of the output amplifier.
DC Output Impedance 0.5 0.5 Ω
Short Circuit Current 50 50 mA VDD = 5 V

20 20 mA VDD = 3 V
Power-Up Time 2.5 2.5 µs Coming out of Power-Down Mode. VDD = 5 V

55µs Coming out of Power-Down Mode. VDD = 3 V

LOGIC INPUTS

5

Input Current ± 1 ± 1 µA
VIL, Input Low Voltage 0.8 0.8 V VDD = 5 V ± 10%

0.6 0.6 V VDD = 3 V ± 10%

0.5 0.5 V VDD = 2.5 V

VIH, Input High Voltage 2.4 2.4 V VDD = 5 V ± 10%

2.1 2.1 V VDD = 3 V ± 10%

2.0 2.0 V VDD = 2.5 V

Pin Capacitance 2 3.5 2 3.5 pF

LOGIC OUTPUT (SDO)

5

VDD = 5 V ± 10%

Output Low Voltage 0.4 0.4 V I
Output High Voltage 4.0 4.0 V I

VDD = 3 V ± 10%

Output Low Voltage 0.4 0.4 V I
Output High Voltage 2.4 2.4 V I

Floating-State Leakage Current 1 1 µA DCEN = GND

= 2 mA

SINK

SOURCE

= 2 mA

SINK

SOURCE

= 2 mA

= 2 mA

Floating State O/P Capacitance 3 3 pF DCEN = GND

POWER REQUIREMENTS

V

DD

IDD (Normal Mode) Both DACs Active and Excluding Load Currents

2.5 5.5 2.5 5.5 V IDD specification is valid for all DAC codes.

VDD = 4.5 V to 5.5 V 300 450 300 450 µA Both DACs in Unbuffered mode. VIH = VDD and
VDD = 2.5 V to 3.6 V 230 350 230 350 µAV

IDD (Full Power-Down)

= GND. In Buffered mode, extra current is

IL

typically x µA per DAC where x = 5 µA + V

REF/RDAC

VDD = 4.5 V to 5.5 V 0.2 1 0.2 1 µA
VDD = 2.5 V to 3.6 V 0.05 1 0.05 1 µA

DAC

DAC

.

REV. A–2–

AD5303/AD5313/AD5323

NOTES

1

See Terminology section.

2

Temperature range: A, B Version: –40°C to +105°C.

3

DC specifications tested with the outputs unloaded.

4

Linearity is tested using a reduced code range: AD5303 (Code 8 to 248); AD5313 (Code 28 to 995); AD5323 (Code 115 to 3981).

5

Guaranteed by design and characterization, not production tested.

6

In order for the amplifier output to reach its minimum voltage, offset error must be negative. In order for the amplifier output to reach its maximum voltage, V
and offset plus gain error must be positive.

Specifications subject to change without notice.

REF

= V

DD

(VDD = 2.5 V to 5.5 V; RL = 2 k⍀ to GND; CL = 200 pF to GND; all specifications T

1

AC CHARACTERISTICS

Parameter

2

otherwise noted.)

A, B Version

3

Min Typ Max Unit Conditions/Comments

Output Voltage Settling Time V

= VDD = 5 V

REF

MIN

to T

, unless

MAX

AD5303 6 8 µs 1/4 Scale to 3/4 Scale Change (0x40 to 0xC0)
AD5313 7 9 µs 1/4 Scale to 3/4 Scale Change (0x100 to 0x300)

AD5323 8 10 µs 1/4 Scale to 3/4 Scale Change (0x400 to 0xC00)
Slew Rate 0.7 V/µs
Major-Code Transition Glitch Energy 12 nV-s 1 LSB Change around Major Carry

(011 . . . 11 to 100 . . . 00)
Digital Feedthrough 0.10 nV-s
Analog Crosstalk 0.01 nV-s
DAC-to-DAC Crosstalk 0.01 nV-s
Multiplying Bandwidth 200 kHz V
Total Harmonic Distortion –70 dB V

NOTES

1

Guaranteed by design and characterization, not production tested.

2

See Terminology section.

3

Temperature range: A, B Version: –40°C to +105°C.

Specifications subject to change without notice.

TIMING CHARACTERISTICS

Limit at T

MIN

, T

1, 2, 3

MAX

(VDD = 2.5 V to 5.5 V; all specifications T

= 2 V ± 0.1 V p-p, Unbuffered Mode

REF

= 2.5 V ± 0.1 V p-p, Frequency = 10 kHz

REF

to T

MIN

, unless otherwise noted.)

MAX

Parameter (A, B Version) Unit Conditions/Comments

t

1

t

2

t

3

t

4

t

5

t

6

t

7

t

8

t

9

t

10

t

11

4, 5

t

12

4, 5

t

13

5

t

14

5

t

15

NOTES

1

Guaranteed by design and characterization, not production tested.

2

All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.

3

See Figures 1 and 2.

4

These are measured with the load circuit of Figure 1.

5

Daisy-chain mode only. (See Figure 23.)

Specifications subject to change without notice.

33 ns min SCLK Cycle Time
13 ns min SCLK High Time
13 ns min SCLK Low Time
0 ns min SYNC to SCLK Rising Edge Setup Time
5 ns min Data Setup Time

4.5 ns min Data Hold Time
0 ns min SCLK Falling Edge to SYNC Rising Edge
100 ns min Minimum SYNC High Time
20 ns min LDAC Pulsewidth
20 ns min SCLK Falling Edge to LDAC Rising Edge
20 ns min CLR Pulsewidth
5 ns min SCLK Falling Edge to SDO Invalid
20 ns max SCLK Falling Edge to SDO Valid
0 ns min SCLK Falling Edge to SYNC Rising Edge
10 ns min SYNC Rising Edge to SCLK Rising Edge

REV. A

–3–

AD5303/AD5313/AD5323

Figure 1. Load Circuit for Digital Output (SDO) Timing Specifications

SCLK

t

8

SYNC

*

DIN

LDAC

LDAC

DB15

I

2mA

TO

OUTPUT

PIN

C

L

50pF

2mA

t

1

t

t

t

4

t

6

t

5

3

2

DB0

OL

1.6V

I

OH

t

7

t

9

t

10

CLR

*

SEE INPUT SHIFT REGISTER SECTION

Figure 2. Serial Interface Timing Diagram

t

11

REV. A–4–

AD5303/AD5313/AD5323

ABSOLUTE MAXIMUM RATINGS

(TA = 25°C, unless otherwise noted.)

1, 2

VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

Digital Input Voltage to GND . . . . . . . . –0.3 V to V

Digital Output Voltage to GND . . . . . . –0.3 V to V

Reference Input Voltage to GND . . . . . –0.3 V to V

V

OUT

A, V

B to GND . . . . . . . . . . . . –0.3 V to VDD + 0.3 V

OUT

+ 0.3 V

DD

+ 0.3 V

DD

+ 0.3 V

DD

Operating Temperature Range

Industrial (A, B Version) . . . . . . . . . . . . . .–40°C to +105°C

Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C

Junction Temperature (T

Max) . . . . . . . . . . . . . . . . . . 150°C

J

16-Lead TSSOP Package

Power Dissipation . . . . . . . . . . . . . . . . . . . (T

Max – TA)/␪

J

JA

␪JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 160°C/W

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause perma­nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating condi­tions for extended periods may affect device reliability.

2

Transient currents of up to 100 mA will not cause SCR latch-up.

ORDERING GUIDE

PIN CONFIGURATION

CLR

LDAC

V

V

REF

V

REF

V

OUT

BUF A

BUF B

DD

B

A

A

1

2

AD5303/

3

AD5313/

AD5323

4

TOP VIEW

5

(Not to Scale)

6

7

8

16

SDO

GND

15

14

DIN

13

SCLK

12

SYNC

11

V

B

OUT

10

PD

9

DCEN

Model Temperature Range Package Description Package Option

AD5303ARU –40°C to +105°CThin Shrink Small Outline Package (TSSOP) RU-16
AD5303ARU-REEL7 –40°C to +105°CThin Shrink Small Outline Package (TSSOP) RU-16
AD5313ARU –40°C to +105°CThin Shrink Small Outline Package (TSSOP) RU-16
AD5313ARU-REEL7 –40°C to +105°CThin Shrink Small Outline Package (TSSOP) RU-16
AD5323ARU –40°C to +105°CThin Shrink Small Outline Package (TSSOP) RU-16
AD5323ARU-REEL7 –40°C to +105°CThin Shrink Small Outline Package (TSSOP) RU-16
AD5303BRU –40°C to +105°CThin Shrink Small Outline Package (TSSOP) RU-16
AD5303BRU-REEL –40°C to +105°CThin Shrink Small Outline Package (TSSOP) RU-16
AD5303BRU-REEL7 –40°C to +105°CThin Shrink Small Outline Package (TSSOP) RU-16
AD5313BRU –40°C to +105°CThin Shrink Small Outline Package (TSSOP) RU-16
AD5313BRU-REEL –40°C to +105°CThin Shrink Small Outline Package (TSSOP) RU-16
AD5313BRU-REEL7 –40°C to +105°CThin Shrink Small Outline Package (TSSOP) RU-16
AD5323BRU –40°C to +105°CThin Shrink Small Outline Package (TSSOP) RU-16
AD5323BRU-REEL –40°C to +105°CThin Shrink Small Outline Package (TSSOP) RU-16
AD5323BRU-REEL7 –40°C to +105°CThin Shrink Small Outline Package (TSSOP) RU-16

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD5303/AD5313/AD5323 feature proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions
are recommended to avoid performance degradation or loss of functionality.

REV. A

–5–

AD5303/AD5313/AD5323

PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic Function

1 CLR Active Low Control Input that Loads All Zeros to Both Input and DAC Registers.
2 LDAC Active Low Control Input that Transfers the Contents of the Input Registers to their Respective DAC Registers.

Pulsing this pin low allows either or both DAC registers to be updated if the input registers have new data.
This allows simultaneous update of both DAC outputs

3V

4V

5V

6V

DD

BReference Input Pin for DAC B. This is the reference for DAC B. It may be configured as a buffered or an

REF

AReference Input Pin for DAC A. This is the reference for DAC A. It may be configured as a buffered or an

REF

ABuffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.

OUT

7 BUF A Control Pin that Controls whether the Reference Input for DAC A is Unbuffered or Buffered. If this pin is

8 BUF B Control Pin that Controls whether the Reference Input for DAC B is Unbuffered or Buffered. If this pin is

9 DCEN This pin is used to enable the daisy-chaining option. This should be tied high if the part is being used in a

10 PD Active Low Control Input that Acts as a Hardware Power-Down Option. This pin overrides any software

11 V

BBuffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.

OUT

12 SYNC Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes

13 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input.

14 DIN Serial Data Input. This device has a 16-bit shift register. Data is clocked into the register on the falling edge

15 GND Ground Reference Point for All Circuitry on the Part.

16 SDO Serial Data Output. Can be used for daisy-chaining a number of these devices together or for reading back the

Power Supply Input. These parts can be operated from 2.5 V to 5.5 V, and the supply should be decoupled
to GND.

unbuffered input, depending on the state of the BUF B pin. It has an input range from 0 V to V
unbuffered mode and from 1 V to V

in buffered mode.

DD

DD

in

unbuffered input depending on the state of the BUF A pin. It has an input range from 0 to VDD in unbuffered
mode and from 1 V to V

in buffered mode.

DD

tied low, the reference input is unbuffered. If it is tied high, the reference input is buffered.

tied low, the reference input is unbuffered. If it is tied high, the reference input is buffered.

daisy-chain. The pin should be tied low if it is being used in standalone mode.

power-down option. Both DACs go into power-down mode when this pin is tied low. The DAC outputs go
into a high impedance state and the current consumption of the part drops to 200 nA @ 5 V (50 nA @ 3 V).

low, it powers on the SCLK and DIN buffers and enables the input shift register. Data is transferred in on
the falling edges of the following 16 clocks. If SYNC is taken high before the 16th falling edge, the rising
edge of SYNC acts as an interrupt and the write sequence is ignored by the device.

Data can be transferred at rates up to 30 MHz. The SCLK input buffer is powered down after each write cycle.

of the serial clock input. The DIN input buffer is powered down after each write cycle.

data in the shift register for diagnostic purposes. The serial data output is valid on the falling edge of the clock.

TERMINOLOGY
Relative Accuracy

For the DAC, relative accuracy or integral nonlinearity (INL) is
a measure of the maximum deviation, in LSB, from a straight
line passing through the actual endpoints of the DAC transfer
function. A typical INL versus code plot can be seen in TPC 1.

Differential Nonlinearity

Differential nonlinearity (DNL) is the difference between the
measured change and the ideal 1 LSB change between any two
adjacent codes. A specified DNL of ±1 LSB maximum ensures
monotonicity. This DAC is guaranteed monotonic by design.
A typical DNL versus code plot can be seen in TPC 4.

Offset Error

This is a measure of the offset error of the DAC and the output
amplifier. It is expressed as a percentage of the full-scale range.

Gain Error

This is a measure of the span error of the DAC. It is the devia­tion in slope of the actual DAC transfer characteristic from the
ideal expressed as a percentage of the full-scale range.

Offset Error Drift

This is a measure of the change in offset error with changes in
temperature. It is expressed in (ppm of full-scale range)/°C.

Gain Error Drift

This is a measure of the change in gain error with changes in
temperature. It is expressed in (ppm of full-scale range)/°C.

REV. A–6–

AD5303/AD5313/AD5323

GAIN ERROR

PLUS

OFFSET ERROR

OUTPUT

VOLTAGE

NEGATIVE

OFFSET

ERROR

DAC CODE

NEGATIVE

OFFSET

ERROR

AMPLIFIER

FOOTROOM

(1mV)

DEADBAND

IDEAL

ACTUAL

Major-Code Transition Glitch Energy

Major-code transition glitch energy is the energy of the impulse
injected into the analog output when the code in the DAC regis­ter changes state. It is normally specified as the area of the glitch
in nV-secs and is measured when the digital code is changed by
1 LSB at the major carry transition (011 . . . 11 to 100 . . . 00 or
100 . . . 00 to 011 . . . 11).

Digital Feedthrough

Digital feedthrough is a measure of the impulse injected into the
analog output of the DAC from the digital input pins of the
device, but is measured when the DAC is not being written to
(SYNC held high). It is specified in nV-secs and is measured
with a full-scale change on the digital input pins, i.e., from all 0s
to all 1s and vice versa.

Analog Crosstalk

This is the glitch impulse transferred to the output of one DAC
due to a change in the output of the other DAC. It is measured
by loading one of the input registers with a full-scale code change
(all 0s to all 1s and vice versa) while keeping LDAC high. Then
pulse LDAC low and monitor the output of the DAC whose
digital code was not changed. The area of the glitch is expressed
in nV-secs.

DAC-to-DAC Crosstalk

This is the glitch impulse transferred to the output of one DAC
due to a digital code change and subsequent output change of
the other DAC. This includes both digital and analog crosstalk.
It is measured by loading one of the DACs with a full-scale code
change (all 0s to all 1s and vice versa) while keeping LDAC low
and monitoring the output of the other DAC. The area of the
glitch is expressed in nV-secs.

DC Crosstalk

This is the dc change in the output level of one DAC in response
to a change in the output of the other DAC. It is measured with
a full-scale output change on one DAC while monitoring the
other DAC. It is expressed in µV.

Power Supply Rejection Ratio (PSRR)

This indicates how the output of the DAC is affected by changes
in the supply voltage. PSRR is the ratio of the change in V
to a change in VDD for full-scale output of the DAC. It is mea­sured in dB. V

is held at 2 V and VDD is varied ± 10%.

REF

OUT

Reference Feedthrough

This is the ratio of the amplitude of the signal at the DAC out­put to the reference input when the DAC output is not being
updated (i.e., LDAC is high). It is expressed in dB.

Total Harmonic Distortion

This is the difference between an ideal sine wave and its attenuated
version using the DAC. The sine wave is used as the reference
for the DAC and the THD is a measure of the harmonics present
on the DAC output. It is measured in dB.

Multiplying Bandwidth

The amplifiers within the DAC have a finite bandwidth. The
multiplying bandwidth is a measure of this. A sine wave on the
reference (with full-scale code loaded to the DAC) appears on
the output. The multiplying bandwidth is the frequency at which
the output amplitude falls to 3 dB below the input.

Channel-To-Channel Isolation

This is a ratio of the amplitude of the signal at the output of one
DAC to a sine wave on the reference input of the other DAC. It
is measured in dB.

Figure 3. Transfer Function with Negative Offset

GAIN ERROR

PLUS

OFFSET ERROR

OUTPUT

VOLTAGE

POSITIVE

OFFSET

ERROR

ACTUAL

IDEAL

DAC CODE

REV. A

Figure 4. Transfer Function with Positive Offset

–7–

AD5303/AD5313/AD5323–Typical Performance Characteristics

1.0

TA = 25ⴗC
V

= 5V

DD

0.5

0

INL ERROR (LSB)

–0.5

–1.0

050 250100 150 200

CODE

TPC 1. AD5303 Typical INL Plot

0.3

TA = 25ⴗC
V

= 5V

DD

0.2

0.1

0

–0.1

DNL ERROR (LSB)

–0.2

3

TA = 25ⴗC

= 5V

V

DD

2

1

0

–1

INL ERROR (LSB)

–2

–3

0 200 1000

400 600 800

CODE

TPC 2. AD5313 Typical INL Plot

0.6
TA = 25ⴗC

= 5V

V

DD

0.4

0.2

0

–0.2

DNL ERROR (LSB)

–0.4

12

TA = 25ⴗC

= 5V

V

DD

8

4

0

–4

INL ERROR (LSB)

–8

–12

1000

0

2000 3000

CODE

TPC 3. AD5323 Typical INL Plot

1.0

TA = 25ⴗC

= 5V

V

DD

0.5

0

DNL ERROR (LSB)

–0.5

4000

–0.3

050 250

100 150 200

CODE

TPC 4. AD5303 Typical DNL Plot

1.00

0.75

0.50

0.25

0

–0.25

ERROR (LSB)

–0.50

–0.75

–1.00

2345

MAX INL
MAX DNL

MIN DNL

MIN INL

V

REF

(V)

VDD = 5V

= 25ⴗC

T

A

TPC 7. AD5303 INL and DNL
Error vs. V

REF

–0.6

0

400 600 800

200 1000

CODE

TPC 5. AD5313 Typical DNL Plot

1.00
VDD = 5V

0.75

0.50

0.25

–0.25

ERROR (LSB)

–0.50

–0.75

–1.00

= 3V

V

REF

MAX INLMAX DNL

0

MIN DNLMIN INL

–40 0 120

40 80

TEMPERATURE (ⴗC)

TPC 8. AD5303 INL Error and
DNL Error vs. Temperature

–1.0

0 1000 40002000 3000

CODE

TPC 6. AD5323 Typical DNL Plot

1.0

VDD = 5V

= 2V

V

REF

0.5

GAIN ERROR

0.0

ERROR (%)

–0.5

–1.0

–40 0 12040 80

OFFSET ERROR

TEMPERATURE (ⴗC)

TPC 9. Offset Error and Gain
Error vs. Temperature

REV. A–8–

AD5303/AD5313/AD5323

VDD = 5V

VDD = 3V

FREQUENCY

0

100 150 400200 250 350300

IDD (␮A)

TPC 10. IDD Histogram with
VDD = 3 V and VDD = 5 V

600

BOTH DACS IN GAIN-OF-TWO MODE
REFERENCE INPUTS BUFFERED

500

400

300

(␮A)

DD

I

200

100

0

2.5 3.0 5.5

–40ⴗC

3.5 4.0
VDD (V)

+25ⴗC

+105ⴗC

4.5 5.0

5

5V SOURCE

4

3

(V)

OUT

V

2

1

0

01

SINK/SOURCE CURRENT (mA)

3V SOURCE

5V SINK

23

TPC 11. Source and Sink
Current Capability

1.0

BOTH DACS IN

0.9
THREE-STATE CONDITION

0.8

0.7

0.6

0.5

(␮A)

DD

I

0.4

0.3

–40ⴗC

0.2

0.1

0

2.7 3.2 5.23.7 4.2 4.7

+25ⴗC

VDD (V)

3V SINK

45 6

+105ⴗC

600

500

400

(␮A)

300

DD

I

200

100

0

ZERO SCALE FULL SCALE

VDD = 5V
T

= 25ⴗC

A

TPC 12. Supply Current vs. Code

700

TA = 25ⴗC

600

500

400

(␮A)

DD

I

300

200

100

0 0.5 4.5

VDD = 3V

1.5 2.5 3.5

1.0 2.0 3.0 4.0 5.0
V

LOGIC

VDD = 5V

(V)

TPC 13. Supply Current vs.
Supply Voltage

VDD = 5V
T

= 25ⴗC

A

CLK

CH2

CH1

V

OUT

CH1 1V, CH2 5V, TIME BASE = 5␮s/DIV

TPC 16. Half-Scale Settling (1/4 to
3/4 Scale Code Change)

TPC 14. Power-Down Current
vs. Supply Voltage

TA = 25ⴗC

V

DD

CH1

CH2

CH1 1V, CH2 1V, TIME BASE = 20␮s/DIV

V

A

OUT

TPC 17. Power-On Reset to 0 V

TPC 15. Supply Current vs.
Logic Input Voltage

TA = 25ⴗC

CH1

CH3

CLK

CH1 1V, CH3 5V, TIME BASE = 1␮s/DIV

TPC 18. Exiting Power-Down
to Midscale

REV. A

–9–

AD5303/AD5313/AD5323

2.50

2.49

(V)

OUT

V

2.48

2.47
1␮s/DIV

TPC 19. AD5323 Major-Code
Transition

0.10

VDD = 5V

= 25ⴗC

T

A

0.05

0.00

10

0

–10

–20

dB

–30

–40

–50

–60

10 100 100k10k

1k 1M 10M

FREQUENCY (Hz)

TPC 20. Multiplying Bandwidth
(Small-Signal Frequency Response)

2mV/DIV

500ns/DIV

TPC 21. DAC-DAC Crosstalk

–0.05

FULL-SCALE ERROR (V)

–0.10

12345

0

V

(V)

REF

TPC 22. Full-Scale Error vs.
V

(Buffered)

REF

REV. A–10–

AD5303/AD5313/AD5323

FUNCTIONAL DESCRIPTION

The AD5303/AD5313/AD5323 are dual resistor-string DACs
fabricated on a CMOS process with resolutions of 8, 10 and 12
bits respectively. They contain reference buffers and output
buffer amplifiers, and are written to via a 3-wire serial interface.
They operate from single supplies of 2.5 V to 5.5 V and the
output buffer amplifiers provide rail-to-rail output swing with a
slew rate of 0.7 V/µs. Each DAC is provided with a separate
reference input, which may be buffered to draw virtually no
current from the reference source, or unbuffered to give a refer­ence input range from GND to V

. The devices have three

DD

programmable power-down modes, in which one or both DACs
may be turned off completely with a high impedance output, or
the output may be pulled low by an on-chip resistor.

Digital-to-Analog Section

The architecture of one DAC channel consists of a reference
buffer and a resistor-string DAC followed by an output buffer
amplifier. The voltage at the V

pin provides the reference

REF

voltage for the DAC. Figure 5 shows a block diagram of the
DAC architecture. Since the input coding to the DAC is straight
binary, the ideal output voltage is given by

VD

×

V

OUT

REF

=

N

2

where

D = decimal equivalent of the binary code, which is loaded to
the DAC register:

0–255 for AD5303 (8 bits)
0–1023 for AD5313 (10 bits)
0–4095 for AD5323 (12 bits)

N = DAC resolution

V

A

REF

INPUT

REGISTER

REFERENCE

DAC

REGISTER

BUFFER

RESISTOR

STRING

BUF A

OUTPUT BUFFER

AMPLIFIER

V

A

OUT

Figure 5. Single DAC Channel Architecture

Resistor String

The resistor string section is shown in Figure 6. It is simply a
string of resistors, each of value R. The digital code loaded to
the DAC register determines at what node on the string the
voltage is tapped off to be fed into the output amplifier. The
voltage is tapped off by closing one of the switches connecting
the string to the amplifier. Because it is a string of resistors, it is
guaranteed monotonic.

R

R

R

R

R

TO OUTPUT
AMPLIFIER

Figure 6. Resistor String

DAC Reference Inputs

There is a reference input pin for each of the two DACs. The
reference inputs are buffered but can also be configured as
unbuffered. The advantage with the buffered input is the high
impedance it presents to the voltage source driving it. However,
if the unbuffered mode is used, the user can have a reference
voltage as low as GND and as high as V

since there is no

DD

restriction due to headroom and footroom of the reference
amplifier.

If there is a buffered reference in the circuit (e.g., REF192),
there is no need to use the on-chip buffers of the AD5303/
AD5313/AD5323. In unbuffered mode, the input impedance is
still large at typically 180 kΩ per reference input for 0 V to
V

mode and 90 kΩ for 0 V to 2 V

REF

REF

mode.

The buffered/unbuffered option is controlled by the BUF A and
BUF B pins. If the BUF pin is tied high, the reference input is
buffered, if tied low, it is unbuffered.

Output Amplifier

The output buffer amplifier is capable of generating output
voltages to within 1 mV of either rail, which gives an output
range of 0.001 V to V

– 0.001 V when the reference is VDD.

DD

It is capable of driving a load of 2 kΩ in parallel with 500 pF to
GND and V

. The source and sink capabilities of the output

DD

amplifier can be seen in TPC 11.

The slew rate is 0.7 V/µs with a half-scale settling time to ±0.5 LSB
(at eight bits) of 6 µs.

POWER-ON RESET

The AD5303/AD5313/AD5323 are provided with a power-on
reset function, so that they power up in a defined state. The
power-on state is

•

Normal operation

•

0 V to V

•

Output voltage set to 0 V

output range

REF

Both input and DAC registers are filled with zeros and remain
so until a valid write sequence is made to the device. This is
particularly useful in applications where it is important to know
the state of the DAC outputs while the device is powering up.

Clear Function (CLR)

The CLR pin is an active low input that, when pulled low, loads
all zeros to both input registers and both DAC registers. This
enables both analog outputs to be cleared to 0 V.

REV. A

–11–

AD5303/AD5313/AD5323

SERIAL INTERFACE

The AD5303/AD5313/AD5323 are controlled over a versatile,
3-wire serial interface, which operates at clock rates up to 30 MHz
and is compatible with SPI, QSPI, MICROWIRE, and DSP
interface standards.

Input Shift Register

The input shift register is 16 bits wide. Data is loaded into the
device as a 16-bit word under the control of a serial clock input,
SCLK. The timing diagram for this operation is shown in
Figure 2. The 16-bit word consists of four control bits followed
by 8, 10, or 12 bits of DAC data, depending on the device type.
The first bit loaded is the MSB (Bit 15), which determines
whether the data is for DAC A or DAC B. Bit 14 determines
the output range (0 V to V

or 0 V to 2 V

REF

). Bits 13 and 12

REF

control the operating mode of the DAC.

Table I. Control Bits

Power-On

Bit Name Function Default

15 A/B 0: Data Written to DAC A N/A

1: Data Written to DAC B

14 GAIN 0: Output Range of 0 V to V

1: Output Range of 0 V to 2 V

REF

0

REF

13 PD1 Mode Bit 0
12 PD0 Mode Bit 0

The remaining bits are DAC data bits, starting with the MSB and
ending with the LSB. The AD5323 uses all 12 bits of DAC data,
the AD5313 uses 10 bits and ignores the 2 LSB. The AD5303
uses eight bits and ignores the last four bits. The data format is
straight binary, with all 0s corresponding to 0 V output, and all
1s corresponding to full-scale output (V

– 1 LSB).

REF

The SYNC input is a level-triggered input that acts as a frame
synchronization signal and chip enable. Data can be transferred
into the device only while SYNC is low. To start the serial
data transfer, SYNC should be taken low observing the mini­mum SYNC to SCLK active edge setup time, t

. After SYNC

4

goes low, serial data will be shifted into the device’s input shift
register on the falling edges of SCLK for 16 clock pulses. Any
data and clock pulses after the 16th will be ignored, and no
further serial data transfer will occur until SYNC is taken high
and low again.

SYNC may be taken high after the falling edge of the 16th SCLK
pulse, observing the minimum SCLK falling edge to SYNC
rising edge time, t

.

7

After the end of serial data transfer, data will automatically be
transferred from the input shift register to the input register of
the selected DAC. If SYNC is taken high before the 16th falling
edge of SCLK, the data transfer will be aborted and the input
registers will not be updated.

When data has been transferred into both input registers, the
DAC registers of both DACs may be simultaneously updated,
by taking LDAC low. CLR is an active-low, asynchronous clear
that clears the input and DAC registers of both DACs to all 0s.

Low Power Serial Interface

To reduce the power consumption of the device even further,
the interface only powers up fully when the device is being writ­ten to. As soon as the 16-bit control word has been written to
the part, the SCLK and DIN input buffers are powered down.
They only power up again following a falling edge of SYNC.

Double-Buffered Interface

The AD5303/AD5313/AD5323 DACs all have double-buff­ered interfaces consisting of two banks of registers—input
registers and DAC registers. The input register is connected
directly to the input shift register and the digital code is trans­ferred to the relevant input register on completion of a valid
write sequence. The DAC register contains the digital code
used by the resistor string.

Access to the DAC register is controlled by the LDAC function.
When LDAC is high, the DAC register is latched and the input
register may change state without affecting the contents of the
DAC register. However, when LDAC is brought low, the DAC
register becomes transparent and the contents of the input regis­ter are transferred to it.

This is useful if the user requires simultaneous updating of both
DAC outputs. The user may write to both input registers indi­vidually and then, by pulsing the LDAC input low, both outputs
will update simultaneously.

These parts contain an extra feature whereby the DAC register
is not updated unless its input register has been updated since
the last time that LDAC was brought low. Normally, when
LDAC is brought low, the DAC registers are filled with the

A/B

A/B

A/B

PD1 PD0 D7 D6 D5 D4 D3 D2 D1 D0 X X X X

GAIN

DATA BITS

Figure 7. AD5303 Input Shift Register Contents

PD1 PD0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X

GAIN

DATA BITS

Figure 8. AD5313 Input Shift Register Contents

PD1 PD0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

GAIN

DATA BITS

Figure 9. AD5323 Input Shift Register Contents

DB0 (LSB)DB15 (MSB)

DB0 (LSB)DB15 (MSB)

DB0 (LSB)DB15 (MSB)

REV. A–12–

AD5303/AD5313/AD5323

contents of the input registers. In the case of the AD5303/AD5313/
AD5323, the part will only update the DAC register if the input
register has been changed since the last time the DAC register
was updated, thereby removing unnecessary digital crosstalk.

POWER-DOWN MODES

The AD5303/AD5313/AD5323 have very low power consump­tion, dissipating only 0.7 mW with a 3 V supply and 1.5 mW
with a 5 V supply. Power consumption can be further reduced
when the DACs are not in use by putting them into one of
three power-down modes, which are selected by Bits 13 and
12 (PD1 and PD0) of the control word. Table II shows how
the state of the bits corresponds to the mode of operation of
that particular DAC.

Table II. PD1/PD0 Operating Modes

PD1 PD0 Operating Mode

00 Normal Operation
01 Power-Down (1 kΩ Load to GND)
10 Power-Down (100 kΩ Load to GND)
11 Power-Down (High Impedance Output)

When both bits are set to 0, the DACs work normally with their
normal power consumption of 300 µA at 5 V. However, for the
three power-down modes, the supply current falls to 200 nA at
5 V (50 nA at 3 V) when both DACs are powered down. Not
only does the supply current drop but the output stage is also
internally switched from the output of the amplifier to a resistor
network of known values. This has the advantage that the output
impedance of the part is known while the part is in power-down
mode and provides a defined input condition for whatever is
connected to the output of the DAC amplifier. There are three
different options. The output is connected internally to GND
through either a 1 kΩ resistor or a 100 kΩ resistor, or it is left in
a high impedance state (three-state). The output stage is illus­trated in Figure 10.

The bias generator, the output amplifier, the resistor string, and
all other associated linear circuitry are shut down when the
power-down mode is activated. However, the contents of the
registers are unaffected when in power-down. The time to exit
power-down is typically 2.5 µs for V

= 3 V. See TPC 18 for a plot.

V

DD

= 5 V and 5 µs when

DD

The software power-down modes programmed by PD0 and
PD1 are overridden by the PD pin. Taking this pin low puts
both DACs into power-down mode simultaneously and both
outputs are put into a high impedance state. If PD is not used,
it should be tied high.

MICROPROCESSOR INTERFACING
AD5303/AD5313/AD5323 to ADSP-2101/ADSP-2103 Interface

Figure 11 shows a serial interface between the AD5303/AD5313/
AD5323 and the ADSP-2101/ADSP-2103. The ADSP-2101/
ADSP-2103 should be set up to operate in the SPORT Trans­mit Alternate Framing mode. The ADSP-2101/ADSP-2103
sport is programmed through the SPORT control register and
should be configured as follows: internal clock operation,
active-low framing, 16-bit word length. Transmission is initi­ated by writing a word to the Tx register after the SPORT has
been enabled.

ADSP-2101/
ADSP-2103

*

ADDITIONAL PINS OMITTED FOR CLARITY.

*

TFS

DT

SCLK

SYNC

DIN

SCLK

AD5303/
AD5313/

AD5323

*

Figure 11. AD5303/AD5313/AD5323 to ADSP-2101/
ADSP-2103 Interface

AD5303/AD5313/AD5323 to 68HC11/68L11 Interface

Figure 12 shows a serial interface between the AD5303/AD5313/
AD5323 and the 68HC11/68L11 microcontroller. SCK of the
68HC11/68L11 drives the SCLK of the AD5303/AD5313/
AD5323, while the MOSI output drives the serial data line
(DIN) of the DAC. The SYNC signal is derived from a port
line (PC7). The setup conditions for correct operation of this
interface are as follows: the 68HC11/68L11 should be config­ured so that its CPOL bit is a 0 and its CPHA bit is a 1. When
data is being transmitted to the DAC, the SYNC line is taken
low (PC7). When the 68HC11/68L11 is configured as above,
data appearing on the MOSI output is valid on the falling edge
of SCK. Serial data from the 68HC11/68L11 is transmitted in
8-bit bytes with only eight falling clock edges occurring in the
transmit cycle. Data is transmitted MSB first. In order to load
data to the AD5303/AD5313/AD5323, PC7 is left low after the
first eight bits are transferred and a second serial write operation
is performed to the DAC; PC7 is taken high at the end of this
procedure.

PC7

SCK

MOSI

*

SYNC

SCLK

DIN

AD5303/
AD5313/

AD5323

*

68HC11/68L11

RESISTOR

STRING DAC

AMPLIFIER

POWER-DOWN

CIRCUITRY

RESISTOR
NETWORK

Figure 10. Output Stage During Power-Down

REV. A

*

ADDITIONAL PINS OMITTED FOR CLARITY.

V

OUT

Figure 12. AD5303/AD5313/AD5323 to 68HC11/
68L11 Interface

–13–

AD5303/AD5313/AD5323

AD5303/AD5313/AD5323 to 80C51/80L51 Interface

Figure 13 shows a serial interface between the AD5303/AD5313/
AD5323 and the 80C51/80L51 microcontroller. The setup for
the interface is as follows: TXD of the 80C51/80L51 drives SCLK
of the AD5303/AD5313/AD5323, while RXD drives the serial
data line of the part. The SYNC signal is again derived from a
bit programmable pin on the port. In this case, port line P3.3 is
used. When data is to be transmitted to the AD5303/AD5313/
AD5323, P3.3 is taken low. The 80C51/80L51 transmits data
only in 8-bit bytes; thus only eight falling clock edges occur in the
transmit cycle. To load data to the DAC, P3.3 is left low after
the first eight bits are transmitted and a second write cycle is initiated
to transmit the second byte of data. P3.3 is taken high following
the completion of this cycle. The 80C51/80L51 outputs the serial
data in a format that has the LSB first. The AD5303/AD5313/
AD5323 requires its data with the MSB as the first bit received.
The 80C51/80L51 transmit routine should take this into account.

80C51/80L51

*

ADDITIONAL PINS OMITTED FOR CLARITY.

*

P3.3

TXD

RXD

SYNC

SCLK

DIN

AD5303/
AD5313/
AD5323

*

Figure 13. AD5303/AD5313/AD5323 to 80C51/
80L51 Interface

AD5303/AD5313/AD5323 to MICROWIRE Interface

Figure 14 shows an interface between the AD5303/AD5313/
AD5323 and any MICROWIRE compatible device. Serial data
is shifted out on the falling edge of the serial clock and is clocked
into the AD5303/AD5313/AD5323 on the rising edge of the SK.

MICROWIRE

*

CS

SK

SO

SYNC

SCLK

DIN

AD5303/
AD5313/
AD5323

*

input range is from 0 V to V

, but if the on-chip reference

DD

buffers are used, the reference range is reduced. Suitable references
for 5 V operation are the AD780 and REF192 (2.5 V references).
For 2.5 V operation, a suitable external reference would be the
REF191, a 2.048 V reference.

VDD = 2.5V TO 5.5V

V

EXT

V

OUT

REF

AD780/REF192
WITH V
OR REF191 WITH
V

DD

DD

= 2.5V

= 5V

1␮F

SERIAL

INTERFACE

V
V

SCLK

DIN

SYNC

REF

REF

GND

A
B

DD

V

OUT

AD5303/
AD5313/

AD5323

V

OUT

BUF A BUF B

A

B

Figure 15. AD5303/AD5313/AD5323 Using External
Reference

If an output range of 0 V to VDD is required when the reference
inputs are configured as unbuffered (for example 0 V to 5 V), the
simplest solution is to connect the reference inputs to V

DD

. As
this supply may not be very accurate and may be noisy, the
AD5303/AD5313/AD5323 may be powered from the reference
voltage, for example using a 5 V reference such as the REF195,
as shown in Figure 16. The REF195 will output a steady supply
voltage for the AD5303/AD5313/AD5323. The current required
from the REF195 is 300 µA supply current and approximately
30 µA or 60 µA into each of the reference inputs (if unbuffered).
This is with no load on the DAC outputs. When the DAC outputs
are loaded, the REF195 also needs to supply the current to the
loads. The total current required (with a 10 kΩ load on each
output) is:

360 2 5 10 1 36AVk mA+

()

=/.

The load regulation of the REF195 is typically 2 ppm/mA,
which results in an error of 2.7 ppm (13.5 µV) for the 1.36 mA
current drawn from it. This corresponds to a 0.0007 LSB error
at eight bits and 0.011 LSB error at 12 bits.

*

ADDITIONAL PINS OMITTED FOR CLARITY.

Figure 14. AD5303/AD5313/AD5323 to MICROWIRE
Interface

APPLICATIONS INFORMATION
Typical Application Circuit

The AD5303/AD5313/AD5323 can be used with a wide range
of reference voltages, especially if the reference inputs are con­figured to be unbuffered, in which case the devices offer full,
one-quadrant multiplying capability over a reference range of
0 V to V

DD

.

More typically, the AD5303/AD5313/AD5323 may be used with
a fixed precision reference voltage. Figure 15 shows a typical
setup for the AD5303/AD5313/AD5323 when using an external
reference. If the reference inputs are unbuffered, the reference

15V

V

IN

REF195

V

GND

OUT

0.1␮F 10␮F

1␮F

SERIAL

INTERFACE

V

DD

V

REF

V

REF

SCLK

DIN

SYNC

GND

A
B

AD5303/
AD5313/

AD5323

BUF A BUF B

A

V

OUT

V

B

OUT

Figure 16. Using an REF195 as Power and Reference
to the AD5303/AD5313/AD5323

REV. A–14–

Bipolar Operation Using the AD5303/AD5313/AD5323

V

DD

SCLK

10k⍀

V

REF

A

DIN

SYNC

V

DD

GND

V

OUT

A

0.1␮F

10␮F

BUF A BUF B

V

REF

B

V

OUT

B

SCLK

5V

REGULATOR

POWER

V

DD

SYNC

10k⍀

V

DD

DIN

10k⍀

AD5303/
AD5313/

AD5323

74HC139

V

CC

V

DD

ENABLE

CODED

ADDRESS

1G

1A

1B

DGND

SYNC

DIN

SCLK

1Y0

1Y1

1Y2

1Y3

SYNC

DIN

SCLK

SYNC

DIN

SCLK

SYNC

DIN

SCLK

SCLK

DIN

AD5303/
AD5313/

AD5323

AD5303/
AD5313/

AD5323

AD5303/
AD5313/

AD5323

AD5303/
AD5313/

AD5323

The AD5303/AD5313/AD5323 has been designed for single­supply operation, but bipolar operation is also achievable using the
circuit shown in Figure 17. The circuit shown has been config­ured to achieve an output voltage range of –5V < V

OUT

< +5 V.
Rail-to-rail operation at the amplifier output is achievable using
an AD820 or OP295 as the output amplifier.

AD5303/AD5313/AD5323

10␮F

V

REF

SCLK

DIN

SYNC

GND

VDD = +5V

V

DD

A/B

AD5303/
AD5313/

AD5323

V

BUF A BUF B

OUT

R1

10k⍀

A/B

R2

10k⍀

+5V

–5V

AD820/
OP295

ⴞ5V

+6V TO +16V

V

IN

REF195

V

OUT

GND

0.1␮F

1␮F

SERIAL

INTERFACE

Figure 17. Bipolar Operation Using the AD5303/
AD5313/AD5323

The output voltage for any input code can be calculated as follows:

VVD RRRVRR

=

()

OUT REF

[]

N

×

()

×+

//– /2121 21

()×()

REF

where

D is the decimal equivalent of the code loaded to the DAC and
N is the DAC resolution.

V

is the reference voltage input, and gain bit = 0.

REF

with

V

= 5 V

REF

R1 = R2 = 10 kΩ and V

VDV

= 5 V:

DD

=×

10 2 5/ –

()

OUT

N

Opto-Isolated Interface for Process Control Applications

The AD5303/AD5313/AD5323 has a versatile 3-wire serial
interface making it ideal for generating accurate voltages in
process control and industrial applications. Due to noise, safety
requirements, or distance, it may be necessary to isolate the
AD5303/AD5313/AD5323 from the controller. This can easily
be achieved by using opto-isolators, which will provide isolation
in excess of 3 kV. The serial loading structure of the AD5303/
AD5313/AD5323 makes it ideally suited for use in opto-isolated
applications. Figure 18 shows an opto-isolated interface to the
AD5303/AD5313/AD5323 where DIN, SCLK, and SYNC are
driven from opto-couplers. The power supply to the part also
needs to be isolated. This is done by using a transformer. On
the DAC side of the transformer, a 5 V regulator provides the
5 V supply required for the AD5303/AD5313/AD5323.

REV. A

–15–

Figure 18. AD5303/AD5313/AD5323 in an Opto­Isolated Interface

Decoding Multiple AD5303/AD5313/AD5323s

The SYNC pin on the AD5303/AD5313/AD5323 can be used in
applications to decode a number of DACs. In this application, all
the DACs in the system receive the same serial clock and serial
data, but only the SYNC to one of the devices will be active at
any one time, allowing access to two channels in this 8-channel
system. The 74HC139 is used as a 2-to-4 line decoder to address
any of the DACs in the system. To prevent timing errors from
occurring, the enable input should be brought to its inactive state
while the coded address inputs are changing state. Figure 19
shows a diagram of a typical setup for decoding multiple
AD5303/AD5313/AD5323 devices in a system.

Figure 19. Decoding Multiple AD5303/AD5313/
AD5323 Devices in a System

AD5303/AD5313/AD5323

AD5303/AD5313/AD5323 as a Digitally Programmable
Window Detector

A digitally programmable upper/lower limit detector using
the two DACs in the AD5303/AD5313/AD5323 is shown in
Figure 20. The upper and lower limits for the test are loaded to
DACs A and B, which, in turn, set the limits on the CMP04. If
the signal at the V

input is not within the programmed window,

IN

an LED will indicate the fail condition.

5V

V

REF

SYNC

DIN

SCLK

0.1␮F 10␮F

V

A

REF

V

B

REF

AD5303/
AD5313/

AD5323

SYNC

DIN

SCLK

GND

V

IN

V

DD

V

A

OUT

1/2

CMP04

B

V

OUT

1k⍀

FAIL

PASS/FAIL

1/6 74HC05

1k⍀

PASS

Figure 20. Window Detector Using AD5303/
AD5313/AD5323

Coarse and Fine Adjustment Using the AD5303/AD5313/AD5323

The DACs in the AD5303/AD5313/AD5323 can be paired
together to form a coarse and fine adjustment function, as shown
in Figure 21. DAC A is used to provide the coarse adjustment
while DAC B provides the fine adjustment. Varying the ratio of
R1 and R2 will change the relative effect of the coarse and fine
adjustments. With the resistor values and external reference shown,
the output amplifier has unity gain for the DAC A output, so the
output range is 0 V to 2.5 V – 1 LSB. For DAC B, the amplifier
has a gain of 7.6 × 10

–3

, giving DAC B a range equal to 19 mV.

The circuit is shown with a 2.5 V reference, but reference voltages
up to V

may be used. The op amps indicated will allow a

DD

rail-to-rail output swing.

V

IN

EXT

V

OUT

REF

GND

AD780/REF192
WITH VDD = 5V

0.1␮F

1␮F

10␮F

V

V

REF

REF

VDD = 5V

V

DD

A

AD5303/
AD5313/
AD5323

B

GND

R3

51.2k⍀R4390⍀

V

A

OUT

R1

390⍀

V

B

OUT

R2

51.2k⍀

+5V

AD820/
OP295

V

OUT

Figure 21. Coarse/Fine Adjustment

Daisy-Chain Mode

This mode is used for updating serially connected or standalone
devices on the rising edge of SYNC. For systems that contain
several DACs, or where the user wishes to read back the DAC

contents for diagnostic purposes, the SDO pin may be used to
daisy-chain several devices together and provide serial readback.

By connecting the DCEN (Daisy-Chain Enable) pin high, the
Daisy-Chain mode is enabled. It is tied low in the case of Standa­lone mode. In Daisy-Chain mode the internal gating on SCLK is
disabled. The SCLK is continuously applied to the input shift
register when SYNC is low. If more than 16 clock pulses are
applied, the data ripples out of the shift register and appears on
the SDO line. This data is clocked out after the falling edge of
SCLK and is valid on the subsequent rising and falling edges.
By connecting this line to the DIN input on the next DAC in
the chain, a multiDAC interface is constructed. Sixteen clock
pulses are required for each DAC in the system. Therefore, the
total number of clock cycles must equal 16N, where N is the
total number of devices in the chain. When the serial transfer to
all devices is complete, SYNC should be taken high. This prevents
any further data being clocked into the input shift register.

A continuous SCLK source may be used if it can be arranged
that SYNC is held low for the correct number of clock cycles.
Alternatively, a burst clock containing the exact number of clock
cycles may be used and SYNC may be taken high some time later.

When the transfer to all input registers is complete, a common
LDAC signal updates all DAC registers and all analog outputs
are updated simultaneously.

*

68HC11

MOSI

SCK

PC7

PC6

MISO

*

ADDITIONAL PINS OMITTED FOR CLARITY

DIN

SCLK

SYNC

LDAC

SCLK

SYNC

LDAC

SCLK

SYNC

LDAC

AD5303/
AD5313/

AD5323

(DAC 1)

SDO

DIN

AD5303/
AD5313/

AD5323

(DAC 2)

SDO

DIN

AD5303/
AD5313/
AD5323

(DAC N)

SDO

*

*

*

Figure 22. Daisy-Chain Mode

REV. A–16–

SCLK

SYNC

DIN

t

1

t

t

t

8

t

4

t

6

t

5

DB15 DB0 DB15 DB0

INPUT WORD FOR DAC N INPUT WORD FOR DAC (N+1)

3

2

AD5303/AD5313/AD5323

t

14

t

15

SDO

UNDEFINED INPUT WORD FOR DAC N

SCLK

SDO

Figure 23. Daisy-Chaining Timing Diagram

Power Supply Bypassing and Grounding

In any circuit where accuracy is important, careful consideration
of the power supply and ground return layout helps to ensure
the rated performance. The printed circuit board on which the
AD5303/AD5313/AD5323 is mounted should be designed so
that the analog and digital sections are separated and confined to
certain areas of the board. If the AD5303/AD5313/AD5323 is
in a system where multiple devices require an AGND to DGND
connection, the connection should be made at one point only. The
star ground point should be established as close as possible to
the AD5303/AD5313/AD5323. The AD5303/AD5313/AD5323
should have ample supply bypassing of 10 µF in parallel with

0.1 µF on the supply located as close to the package as possible,
ideally right up against the device. The 10 µF capacitors are the
tantalum bead type. The 0.1 µF capacitor should have low effective
series resistance (ESR) and effective series inductance (ESI),

DB15

t

13

V

V

t

12

IH

IL

DB0

like the common ceramic types that provide a low impedance
path to ground at high frequencies to handle transient currents
due to internal logic switching.

The power supply lines of the AD5303/AD5313/AD5323 should
use as large a trace as possible to provide low impedance paths
and reduce the effects of glitches on the power supply line. Fast
switching signals such as clocks should be shielded with digital
ground to avoid radiating noise to other parts of the board, and
should never be run near the reference inputs. Avoid crossover of
digital and analog signals. Traces on opposite sides of the board
should run at right angles to each other. This reduces the effects
of feedthrough through the board. A microstrip technique is by
far the best, but is not always possible with a double-sided board.
In this technique, the component side of the board is dedicated
to ground plane while signal traces are placed on the solder side.

REV. A

–17–

AD5303/AD5313/AD5323

OUTLINE DIMENSIONS

16-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-16)

Dimensions shown in millimeters

5.10

5.00

4.90

0.15

0.05

4.50

4.40

4.30

PIN 1

16

0.65
BSC

COPLANARITY

COMPLIANT TO JEDEC STANDARDS MO-153AB

0.10

0.30

0.19

9

81

1.20
MAX

6.40

BSC

SEATING

PLANE

0.20

0.09

0.75

8ⴗ
0ⴗ

0.60

0.45

REV. A–18–

AD5303/AD5313/AD5323

Revision History

Location Page

8/03—Data Sheet changed from REV. 0 to REV. A.

Added A Version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal

Changes to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Changes to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

REV. A

–19–

C00472–0–8/03(A)

–20–