Datasheet AD5302, AD5312, AD5322 Datasheet (ANALOG DEVICES)

2.5 V to 5.5 V, 230 μA, Dual Rail-to-Rail,

V

FEATURES

AD5302: Two 8-bit buffered DACs in 1 package

A version: ±1 LSB INL, B version: ±0.5 LSB INL

AD5312: Two 10-bit buffered DACs in 1 package

A version: ±4 LSB INL, B version: ±2 LSB INL

AD5322: Two 12-bit buffered DACs in 1 package

A version: ±16 LSB INL, B version: ±8 LSB INL
10-lead MSOP
Micropower operation: 300 μA @ 5 V (including

reference current)

Power-down to 200 nA @ 5 V, 50 nA @ 3 V

2.5 V to 5.5 V power supply
Double-buffered input logic
Guaranteed monotonic by design over all codes
Buffered/Unbuffered reference input options
0 V to V
Power-on-reset to 0 V
Simultaneous update of DAC outputs via

Low power serial interface with Schmitt-triggered inputs
On-chip rail-to-rail output buffer amplifiers
Qualified for automotive applications

APPLICATIONS

Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators

output voltage

REF

LDAC

FUNCTIONAL BLOCK DIAGRAM

DD

Voltage Output 8-/10-/12-Bit DACs

AD5302/AD5312/AD5322

GENERAL DESCRIPTION

The AD5302/AD5312/AD5322 are dual 8-, 10-, and 12-bit
buffered voltage output DACs in a 10-lead MSOP that operate
from a single 2.5 V to 5.5 V supply, consuming 230 A at 3 V.
Their on-chip output amplifiers allow the outputs to swing rail­to-rail with a slew rate of 0.7 V/s. The AD5302/AD5312/AD5322
utilize a versatile 3-wire serial interface that operates at clock
rates up to 30 MHz and is compatible with standard SPI®,
QSPI™, MICROWIRE™, and DSP interface standards.

The references for the two DACs are derived from two reference
pins (one per DAC). The reference inputs can be configured as
buffered or unbuffered inputs. The outputs of both DACs can be
updated simultaneously using the asynchronous
The parts incorporate a power-on reset circuit, which ensures
that the DAC outputs power-up to 0 V and remain there until a
valid write takes place to the device. The parts contain a power­down feature that reduces the current consumption of the
devices to 200 nA at 5 V (50 nA at 3 V) and provides software­selectable output loads while in power-down mode.

The low power consumption of these parts in normal operation
makes them ideally suited for portable battery-operated
equipment. The power consumption is 1.5 mW at 5 V, 0.7 mW
at 3 V, reducing to 1 W in power-down mode.

V

A

REF

LDAC

input.

POWER-ON

RESET

INPUT

REGISTER

SYNC

SCLK

DIN

Rev. D

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

INTERFACE

LOGIC

LDAC

INPUT

REGISTER

DAC

REGISTER

DAC

REGISTER

STRING

DAC

POWER-DOW N

STRING

DAC

REF

Figure 1.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2006-2011 Analog Devices, Inc. All rights reserved.

AD5302/AD5312/AD5322

BUFFER

LOGIC

BUFFER

B

A

V

OUTAVOUT

RESISTOR
NETWORK

B

V

OUTBVOUT

RESISTOR
NETWORK

GNDV

00928-001

AD5302/AD5312/AD5322

TABLE OF CONTENTS

Features.............................................................................................. 1

Low Power Serial Interface ....................................................... 15

Applications....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

AC Specifications.......................................................................... 4

Timing Characteristics ................................................................ 5

Absolute Maximum Ratings............................................................ 7

ESD Caution.................................................................................. 7

Pin Configuration and Function Descriptions............................. 8

Terminology ...................................................................................... 9

Typical Performance Characteristics ........................................... 10

Functional Description.................................................................. 14

Digital-to-Analog Section .........................................................14

Resistor String............................................................................. 14

DAC Reference Inputs............................................................... 14

Output Amplifier........................................................................ 14

Power-On Reset .......................................................................... 14

Serial Interface ................................................................................15

Input Shift Register..................................................................... 15

Double-Buffered Interface ........................................................ 15

Power-Down Modes ...................................................................... 16

Microprocessor Interfacing........................................................... 17

AD5302/AD5312/AD5322 to ADSP-2101/ADSP-2103

Interface....................................................................................... 17

AD5302/AD5312/AD5322 to 68HC11/68L11 Interface ...... 17

AD5302/AD5312/AD5322 to 80C51/80L51 Interface.......... 17

AD5302/AD5312/AD5322 to MICROWIRE Interface ........ 17

Applications Information.............................................................. 18

Typical Application Circuit....................................................... 18

Bipolar Operation Using the AD5302/AD5312/AD5322..... 18

Opto-Isolated Interface for Process Control Applications ... 19

Decoding Multiple AD5302/AD5312/AD5322s.................... 19

AD5302/AD5312/AD5322 as a Digitally Programmable

Window Detector....................................................................... 19

Coarse and Fine Adjustment Using the

AD5302/AD5312/AD5322 ....................................................... 20

Power Supply Bypassing and Grounding................................ 20

Outline Dimensions....................................................................... 21

Ordering Guide .......................................................................... 22







REVISION HISTORY

5/11—Rev. C to Rev. D

Added Automotive Products Information................. Throughout

Updated Outline Dimensions....................................................... 21

Changes to Ordering Guide.......................................................... 22

4/06—Rev. B to Rev. C

Updated Format..................................................................Universal

Updated Outline Dimensions....................................................... 21

Changes to Ordering Guide.......................................................... 21

12/05—Rev. A to Rev. B

Updated Format..................................................................Universal

Rev. D | Page 2 of 24

Updated Outline Dimensions....................................................... 21

Changes to Ordering Guide.......................................................... 21

8/03—Rev. 0 to Rev. A

Changes to Features ..........................................................................1

Changes to Specifications.................................................................2

Changes to Absolute Maximum Ratings........................................4

Changes to Ordering Guide.............................................................4

Updated Outline Dimensions....................................................... 16

AD5302/AD5312/AD5322

SPECIFICATIONS

VDD = 2.5 V to 5.5 V, V

Table 1.

Parameter2 Min Typ Max Min Typ Max Unit Test Conditions/Comments

DC PERFORMANCE

AD5302

Resolution 8 8 Bits
Relative Accuracy ±0.15 ±1 ±0.15 ±0.5 LSB
Differential Nonlinearity ±0.02 ±0.25 ±0.02 ±0.25 LSB Guaranteed monotonic by design over all codes

AD5312

Resolution 10 10 Bits
Relative Accuracy ±0.5 ±4 ±0.5 ±2 LSB
Differential Nonlinearity ±0.05 ±0.5 ±0.05 ±0.5 LSB Guaranteed monotonic by design over all codes

AD5322

Resolution 12 12 Bits
Relative Accuracy ±2 ±16 ±2 ±8 LSB

Differential Nonlinearity ±0.2 ±1 ±0.2 ±1 LSB Guaranteed monotonic by design over all codes
Offset Error ±0.4 ±3 ±0.4 ±3 % of FSR
Gain Error ±0.15 ±1 ±0.15 ±1 % of FSR
Lower Deadband 10 60 10 60 mV
Offset Error Drift5 −12 −12 ppm of

Gain Error Drift5 −5 −5 ppm of

Power Supply Rejection

5

Ratio
DC Crosstalk5 30 30 µV

DAC REFERENCE INPUTS5

V

Input Range 1 VDD 1 VDD V Buffered reference mode

REF

0 VDD 0 VDD V Unbuffered reference mode
V

Input Impedance >10 >10 MΩ Buffered reference mode

REF

180 180 kΩ Unbuffered reference mode, input impedance = R
Reference Feedthrough −90 −90 dB Frequency = 10 kHz
Channel-to-Channel

Isolation

OUTPUT CHARACTERISTICS5

Minimum Output Voltage6 0.001 0.001 V min A measure of the minimum drive capability of

Maximum Output Voltage6 VDD −

DC Output Impedance 0.5 0.5 Ω
Short-Circuit Current 50 50 mA VDD = 5 V
20 20 mA VDD = 3 V
Power-Up Time 2.5 2.5 µs Coming out of power-down mode, VDD = 5 V

5 5 µs Coming out of power-down mode, VDD = 3 V
LOGIC INPUTS5

Input Current ±1 ±1 µA
VIL, Input Low Voltage 0.8 0.8 V VDD = 5 V ± 10%

0.6 0.6 V VDD = 3 V ± 10%

0.5 0.5 V VDD = 2.5 V
VIH, Input High Voltage 2.4 2.4 V VDD = 5 V ± 10%

2.1 2.1 V VDD = 3 V ± 10%

2.0 2.0 V VDD = 2.5 V
Pin Capacitance 2 3.5 2 3.5 pF

= 2 V, RL = 2 kΩ to GND, CL = 200 pF to GND, all specifications T

REF

A Version

3, 4

1

B Version

1

MIN

See
See
See

FSR/°C

FSR/°C

−60 −60 dB V

−80 −80 dB Frequency = 10 kHz

the output amplifier

0.001

V

−

DD

0.001

V max A measure of the maximum drive capability of

the output amplifier

Rev. D | Page 3 of 24

to T

, unless otherwise noted.

MAX

Figure 3 and Figure 4
Figure 3 and Figure 4
Figure 3 and Figure 4

= ±10%

DD

DAC

AD5302/AD5312/AD5322

A Version

1

B Version

1

Parameter2 Min Typ Max Min Typ Max Unit Test Conditions/Comments

POWER REQUIREMENTS

VDD 2.5 5.5 2.5 5.5 V IDD specification is valid for all DAC codes
IDD (Normal Mode) Both DACs active and excluding load currents

VDD = 4.5 V to 5.5 V 300 450 300 450 µA Both DACs in unbuffered mode, VIH = VDD and
VDD = 2.5 V to 3.6 V 230 350 230 350 µA VIL = GND; in buffered mode, extra current is

typically × A per DAC where x = 5 A + V

IDD (Full Power-Down)

VDD = 4.5 V to 5.5 V 0.2 1 0.2 1 µA
VDD = 2.5 V to 3.6 V 0.05 1 0.05 1 µA

1

Temperature range: A, B version: –40°C to +105°C.

2

See Terminology section.

3

DC specifications tested with the outputs unloaded.

4

Linearity is tested using a reduced code range: AD5302 (Code 8 to 248); AD5312 (Code 28 to 995); AD5322 (Code 115 to 3981).

5

Guaranteed by design and characterization, not production tested.

6

In order for the amplifier output to reach its minimum voltage, offset error must be negative. In order for the amplifier output to reach its maximum voltage,

= VDD and offset plus gain error must be positive.

V

REF

AC SPECIFICATIONS

VDD = 2.5 V to 5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, all specifications T

Table 2.

A, B Version2
Parameter3 Min Typ Max Unit Test Conditions/Comments

Output Voltage Settling Time V

AD5302 6 8 µs ¼ Scale to ¾ Scale Change (0 × 40 to 0 × C0)
AD5312 7 9 µs ¼ Scale to ¾ Scale Change (0 × 100 to 0 × C300)

AD5322 8 10 µs ¼ Scale to ¾ Scale Change (0 × 400 to 0 × C00)
Slew Rate 0.7 V/µs
Major-Code Transition Glitch Energy 12 nV-s 1 LSB Change Around Major Carry (011…11 to 100…00)
Digital Feedthrough 0.10 nV-s
Analog Crosstalk 0.01 nV-s
DAC-to-DAC Crosstalk 0.01 nV-s
Multiplying Bandwidth 200 kHz V
Total Harmonic Distortion −70 dB V

1

Guaranteed by design and characterization, not production tested.

2

Temperature range: A, B version: −40°C to +105°C.

3

See Terminology section.

to T

MIN

= VDD = 5 V

REF

= 2 V ± 0.1 V p-p, Unbuffered Mode

REF

= 2.5 V ± 0.1 V p-p, Frequency = 10 kHz

REF

, unless otherwise noted.1

MAX

REF/RDAC

Rev. D | Page 4 of 24

AD5302/AD5312/AD5322

C

C

SYNC

TIMING CHARACTERISTICS

VDD = 2.5 V to 5.5 V, all specifications T

MIN

to T

, unless otherwise noted.

MAX

Table 3.

Parameter Limit at T

MIN

, T

(A, B Version) Unit Conditions/Comments

MAX

t1 33 ns min SCLK Cycle Time
t2 13 ns min SCLK High Time
t3 13 ns min SCLK Low Time
t4

0 ns min
t5 5 ns min Data Setup Time
t6 4.5 ns min Data Hold Time
t7
t8
t9

t10

1

Guaranteed by design and characterization, not production tested.

2

All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.

3

See Figure 2.

0 ns min

100 ns min

20 ns min

20

t

1

1, 2, 3

ns min

to SCLK Active Edge Setup Time

SYNC

SCLK Falling Edge to SYNC
Minimum SYNC

Pulse Width

LDAC
SCLK Falling Edge to LDAC

Rising Edge

High Time

Rising Edge

SCLK

t

8

1

DIN

LDA

LDA

1

SEE INPUT SHIFT REGISTER SECTION.

DB15

t

4

t

6

t

t

t

3

5

2

DB0

t

7

Figure 2. Serial Interface Timing Diagram

t

9

t

10

00928-002

Rev. D | Page 5 of 24

AD5302/AD5312/AD5322

R

V

GAIN ERROR

PLUS

OFFSET ERRO

OUTPUT

VO LTAGE

POSITIVE

OFFSET

ERROR

AMPLIFIER

FOOTROOM

(1mV)

NEGATIVE

OFFSET

ERROR

DEA

IDEAL

DBAND

DAC CODE

ACTUAL

02928-004

Figure 3. Transfer Function with Negative Offset

GAIN ERROR

PLUS

OFFSET ERROR

OUTPUT
OLTAGE

POSITIVE

OFFSET

ERROR

ACTUAL

IDEAL

DAC CODE

00928-005

Figure 4. Transfer Function with Positive Offset

Rev. D | Page 6 of 24

AD5302/AD5312/AD5322

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.1

Table 4.

Parameter Rating

VDD to GND –0.3 V to +7 V
Digital Input Voltage to GND –0.3 V to VDD + 0.3 V
Reference Input Voltage to

GND
V

A, V

OUT

Operating Temperature Range

Industrial (A, B Version) –40°C to +105°C
Storage Temperature Range –65°C to +150°C
Junction Temperature (TJ max) +150°C
10-Lead MSOP

Power Dissipation (TJ max – TA)/θJA
θJA Thermal Impedance 206°C/W
θJC Thermal Impedance 44°C/W
Lead Temperature, Soldering

Vapor Phase (60 sec) 215°C

Infrared (15 sec) 220°C

1

Transient currents of up to 100 mA do not cause SCR latch-up.

B to GND –0.3 V to VDD + 0.3 V

OUT

–0.3 V to V

+ 0.3 V

DD

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. D | Page 7 of 24

AD5302/AD5312/AD5322

V

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

LDAC

V

REF

V

REF

OUT

V

DD

2

B

3

A

4

5

A

AD5302/
AD5312/

AD5322

TOP VIEW

(Not to Scal e)

Figure 5. Pin Configuration

Table 5. Pin Function Descriptions

Pin No. Mnemonic Description

1

Active Low Control Input. This pin transfers the contents of the input registers to their respective DAC registers.

LDAC

Pulsing LDAC

low allows either or both DAC registers to be updated if the input registers have new data. This

allows simultaneous updating of both DAC outputs.
2 VDD Power Supply Input. The parts can be operated from 2.5 V to 5.5 V, and the supply should be decoupled to GND.
3 V

REF

B

Reference Input Pin for DAC B. This is the reference for DAC B. It can be configured as a buffered or an

unbuffered input, depending on the BUF bit in the control word of DAC B. It has an input range of 0 V to V

4 V

REF

A

unbuffered mode and 1 V to V

Reference Input Pin for DAC A. This is the reference for DAC A. It can be configured as a buffered or an

in buffered mode.

DD

unbuffered input depending on the BUF bit in the control word of DAC A. It has an input range of 0 V to VDD in

in buffered mode.

DD

5 V
6 V
7

unbuffered mode and 1 V to V

A Buffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.

OUT

B Buffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.

OUT

Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it

SYNC

powers on the SCLK and DIN buffers and enables the input shift register. Data is transferred in on the falling

edges of the following 16 clocks. If SYNC

as an interrupt and the write sequence is ignored by the device.
8 SCLK

Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data

can be transferred at rates up to 30 MHz. The SCLK input buffer is powered down after each write cycle.
9 DIN

Serial Data Input. This device has a 16-bit input shift register. Data is clocked into the register on the falling

edge of the serial clock input. The DIN input buffer is powered down after each write cycle.
10 GND Ground Reference Point for All Circuitry on the Part.

10

GND

DIN

9

SCLK

8

SYNC

7

6

V

B

OUT

00928-003

in

DD

is taken high before the 16th falling edge, the rising edge of SYNC acts

Rev. D | Page 8 of 24

AD5302/AD5312/AD5322

TERMINOLOGY

Relative Accuracy

For the DAC, relative accuracy or integral nonlinearity (INL) is
a measure of the maximum deviation, in LSB, from a straight
line passing through the actual endpoints of the DAC transfer
function. A typical INL vs. code plot can be seen in Figure 6.

Differential Nonlinearity

Differential nonlinearity (DNL) is the difference between the
measured change and the ideal 1 LSB change between any two
adjacent codes. A specified differential nonlinearity of ±1 LSB
maximum ensures monotonicity. This DAC is guaranteed
monotonic by design. A typical DNL vs. code plot can be seen
in Figure 9.

change (all 0s to all 1s and vice versa) while keeping
high, then pulsing

LDAC

low, and monitoring the output of the
DAC whose digital code is not changed. The area of the glitch is
expressed in nV-sec.

DAC-to-DAC C rosst a l k

This is the glitch impulse transferred to the output of one DAC
due to a digital code change and subsequent output change of
the other DAC. This includes both digital and analog crosstalk.
It is measured by loading one of the DACs with a full-scale code
change (all 0s to all 1s and vice versa) while keeping
and monitoring the output of the other DAC. The area of the
glitch is expressed in nV-sec.

LDAC

LDAC

low

Offset Error

This is a measure of the offset error of the DAC and the output
amplifier. It is expressed as a percentage of the full-scale range.

Gain Error

This is a measure of the span error of the DAC. It is the
deviation in slope of the actual DAC transfer characteristic from
the ideal expressed as a percentage of the full-scale range.

Offset Error Drift

This is a measure of the change in offset error with changes in
temperature. It is expressed in (ppm of full-scale range)/°C.

Gain Error Drift

This is a measure of the change in gain error with changes in
temperature. It is expressed in (ppm of full-scale range)/°C.

Major-Code Transition Glitch Energy

Major-code transition glitch energy is the energy of the impulse
injected into the analog output when the code in the DAC
register changes state. It is normally specified as the area of the
glitch in nV-sec and is measured when the digital code is
changed by 1 LSB at the major carry transition (011 . . . 11 to
100 . . . 00 or 100 . . . 00 to 011 . . . 11).

Digital Feedthrough

Digital feedthrough is a measure of the impulse injected into
the analog output of the DAC from the digital input pins of the
device, but is measured when the DAC is not being written to

SYNC

(

held high). It is specified in nV-sec and is measured
with a full-scale change on the digital input pins, that is, from
all 0s to all 1s and vice versa.

Analog Crosstalk

This is the glitch impulse transferred to the output of one DAC
due to a change in the output of the other DAC. It is measured
by loading one of the input registers with a full-scale code

DC Crosstalk

This is the dc change in the output level of one DAC in response
to a change in the output of the other DAC. It is measured with
a full-scale output change on one DAC while monitoring the
other DAC. It is expressed in V.

Power Supply Rejection Ratio (PSRR)

This indicates how the output of the DAC is affected by changes
in the supply voltage. PSRR is the ratio of the change in V
a change in V
in dB. V

for full-scale output of the DAC. It is measured

DD

is held at 2 V and VDD is varied ±10%.

REF

OUT

to

Reference Feedthrough

This is the ratio of the amplitude of the signal at the DAC
output to the reference input when the DAC output is not being
updated (that is,

LDAC

is high). It is expressed in dB.

Total Harmonic Distortion (THD)

This is the difference between an ideal sine wave and its
attenuated version using the DAC. The sine wave is used as the
reference for the DAC and the THD is a measure of the
harmonics present on the DAC output. It is measured in dB.

Multiplying Bandwidth

The amplifiers within the DAC have a finite bandwidth. The
multiplying bandwidth is a measure of this. A sine wave on the
reference (with full-scale code loaded to the DAC) appears on
the output. The multiplying bandwidth is the frequency at
which the output amplitude falls to 3 dB below the input.

Channel-to-Channel Isolation Definition

This is a ratio of the amplitude of the signal at the output of one
DAC to a sine wave on the reference input of the other DAC. It
is measured in dB.

Rev. D | Page 9 of 24

AD5302/AD5312/AD5322

TYPICAL PERFORMANCE CHARACTERISTICS

1.0

TA = 25°C

= 5V

V

DD

0.5

0.3

0.2

0.1

TA = 25°C

= 5V

V

DD

0

INL ERROR (L SB)

–0.5

–1.0

0 50 100 150 200 250

CODE

Figure 6. AD5302 Typical INL Plot

3

TA = 25°C

= 5V

V

DD

2

1

0

INL ERROR (LSB)

–1

–2

–3

0 200 400 600 800 1000

CODE

Figure 7. AD5312 Typical INL Plot

3

TA = 25°C

= 5V

V

DD

2

1

0

–0.1

DNL ERROR (LSB)

–0.2

00928-006

–0.3

0 50 100 150 250

CODE

200

00928-009

Figure 9. AD5302 Typical DNL Plot

0.6

TA = 25°C

V

= 5V

DD

0.4

0.2

0

–0.2

DNL ERROR (LSB)

–0.4

00928-007

–0.6

0 200 400 600 800 1000

CODE

00928-010

Figure 10. AD5312 Typical DNL Plot

1.0

TA = 25°C

= 5V

V

DD

0.5

0

INL ERROR (LSB)

–4

–8

–12

0 1000 2000 3000 4000

CODE

Figure 8. AD5322 Typical INL Plot

00928-008

Rev. D | Page 10 of 24

0

DNL ERROR (LSB)

–0.5

–1.0

0 1000 2000 3000 4000

CODE

Figure 11. AD5322 Typical DNL Plot

00928-011

AD5302/AD5312/AD5322

1.00

0.75

0.50

0.25

0

ERROR (LSB)

–0.25

–0.50

–0.75

–1.00

2345

MAX INL

MAX DNL

MIN DNL

MIN INL

V

(V)

REF

Figure 12. AD5302 INL and DNL Error vs. V

1.00
VDD = 5V

= 3V

V

REF

0.75

0.50

0.25

ERROR (LSB)

–0.25

–0.50

–0.75

–1.00

0

–40

MAX DNL

MIN INL

0 40 80 120

TEMPERATURE(° C)

MAX INL

MIN DNL

Figure 13. AD5302 INL Error and DNL Error vs. Temperature

1.0
VDD = 5V

=2V

V

REF

0.5

TA = 25°C

V

DD

REF

= 5V

VDD = 5V

VDD = 3V

FREQUENCY

00928-012

0
100 150 200 250 300 350 400

Figure 15. I

Histogram with VDD = 3 V and VDD = 5 V

DD

IDD(µA)

00928-015

5

5V SOURCE

4

3

(V)

OUT

V

2

1

00928-013

–0

012345

SINK/SOURCE CURRENT(mA)

5V SINK

3V SOURCE

3V SINK

00928-016

6

Figure 16. Source and Sink Current Capability

600

TA = 25°C

V

= 5V

DD

500

400

0

ERROR (%)

–0.5

–1.0

–40

0 40 80 120

TEMPERATURE(° C)

GAIN ERROR

OFFSET ERROR

Figure 14. Offset Error and Gain Error vs. Temperature

00928-014

Rev. D | Page 11 of 24

(µA)

300

DD

I

200

100

0

ZERO SCALE FULL SCALE

Figure 17. Supply Current vs. Code

00928-017

AD5302/AD5312/AD5322

C

C

600

BOTH DACS IN GAI N-OF-TWO MODE
REFERENCE INPUTS BUFFERED

500

400

(µA)

300

DD

I

200

100

–40°C

+105°C

+25°C

CH2

CH1

CLK

VDD = 5V
T

= 25°C

A

V

OUT

0

2.5 3.0 3.5 4. 0 4.5 5.0 5.5

(V)

V

DD

Figure 18. Supply Current vs. Supply Voltage

1.0

BOTH DACS IN
THREE-STATE CONDITION

0.8

0.6

(µA)

DD

I

0.4

+25°C

0.2

0

2.7 3.2 3. 7 4.2 4. 7 5.2

V

DD

–40°C

+105°C

(V)

Figure 19. Power-Down Current vs. Supply Voltage

700

TA = 25°C

600

00928-018

CH1 1V, CH2 5V, TIME BASE = 5µ s/DIV

00928-021

Figure 21. Half-Scale Setting (¼ to ¾ Scale Code Change)

TA = 25°C

V

DD

CH1

CH2

00928-019

CH1 1V, CH2 1V, T IME BASE = 20µs/DIV

V

A

OUT

00928-022

Figure 22. Power-On Reset to 0 V

TA = 25°C

500

400

(µA)

DD

I

300

200

100

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

VDD = 3V

V

LOGIC

VDD = 5V

(V)

Figure 20. Supply vs. Logic Input Voltage

H1

H3

00928-020

Figure 23. Existing Power-Down to Midscale

V

OUT

CLK

CH1 1V, CH3 5V, T IME BASE = 1µ s/DIV

00928-023

Rev. D | Page 12 of 24

AD5302/AD5312/AD5322

V

2.50

2.49

(V)

OUT

V

2.48

2mV/DI

2.47

1µs/DIV

Figure 24. AD5322 Major-Code Transition

10

0

–10

–20

dB

–30

–40

–50

–60

10 100 1k 10k 100k 1M 10M

FREQUENCY(Hz)

00928-024

500ns/DIV

Figure 26. DAC-to-DAC Crosstalk

1.0

TA = 25°C
V

= 5V

DD

0.5

0

FULL SCALE ERROR (V)

–0.5

00928-025

–1.0

012345

V

(V)

REF

Figure 27. Full-Scale Error vs. V

(Buffered) Figure 25. Multiplying Bandwidth (Small-Signal Frequency Response)

REF

00928-026

00928-027

Rev. D | Page 13 of 24

AD5302/AD5312/AD5322

V

A

A

FUNCTIONAL DESCRIPTION

The AD5302/AD5312/AD5322 are dual resistor-string DACs
fabricated on a CMOS process with resolutions of 8, 10, and 12
bits, respectively. They contain reference buffers and output
buffer amplifiers, and are written to via a 3-wire serial interface.
They operate from single supplies of 2.5 V to 5.5 V, and the
output buffer amplifiers provide rail-to-rail output swing with a
slew rate of 0.7 V/s. Each DAC is provided with a separate
reference input, which can be buffered to draw virtually no
current from the reference source, or unbuffered to give a
reference input range from GND to V
programmable power-down modes, in which one or both DACs
can be turned off completely with a high impedance output, or
the output can be pulled low by an on-chip resistor.

DIGITAL-TO-ANALOG SECTION

The architecture of one DAC channel consists of a reference
buffer and a resistor-string DAC followed by an output buffer
amplifier. The voltage at the V
voltage for the DAC. Figure 28 shows a block diagram of the
DAC architecture. Because the input coding to the DAC is
straight binary, the ideal output voltage is given by

DV

×

V

OUT

REF

=

N

2

where:

D = decimal equivalent of the binary code that is loaded to the
DAC register:

0 to 255 for AD5302 (8 bits)
0 to 1023 for AD5312 (10 bits)
0 to 4095 for AD5322 (12 bits)

N = DAC resolution.

REFERENCE

REF

BUFFER

. The devices have three

DD

pin provides the reference

REF

SWITCH
CONTROL LED
BY CONTROL
LOGIC

R

R

R

R

R

Figure 29. Resistor String

TO OUTPUT
AMPLIFIER

00928-029

DAC REFERENCE INPUTS

There is a reference input pin for each of the two DACs. The
reference inputs are buffered but can also be configured as
unbuffered. The advantage of the buffered input is the high
impedance it presents to the voltage source driving it.

However, if the unbuffered mode is used, the user can have a
reference voltage as low as GND and as high as V

because

DD

there is no restriction due to headroom and footroom of the
reference amplifier. If there is a buffered reference in the circuit
(for example, REF192), there is no need to use the on-chip
buffers of the AD5302/AD5312/AD5322. In unbuffered mode,
the impedance is still large (180 k per reference input).

The buffered/unbuffered option is controlled by the BUF bit in
the control word (see the Serial Interface section for a
description of the register contents).

OUTPUT AMPLIFIER

The output buffer amplifier is capable of generating output
voltages to within 1 mV of either rail, which gives an output
range of 0.001 V to V
It is capable of driving a load of 2 k in parallel with 500 pF to
GND and V

. The source and sink capabilities of the output

DD

amplifier can be seen in Figure 16.

– 0.001 V when the reference is VDD.

DD

INPUT

REGISTER

DAC

REGISTER

Figure 28. Single DAC Channel Architecture

RESISTOR

STRING

OUTPUT BUFFER

AMPLIFIER

V

OUT

RESISTOR STRING

The resistor-string section is shown in Figure 29. It is simply a
string of resistors, each of value R. The digital code loaded to
the DAC register determines at what node on the string the
voltage is tapped off to be fed into the output amplifier. The
voltage is tapped off by closing one of the switches connecting
the string to the amplifier. Because it is a string of resistors, it is
guaranteed monotonic.

00928-028

The slew rate is 0.7 V/s with a half-scale settling time to
±0.5 LSB (at eight bits) of 6 s. See Figure 21.

POWER-ON RESET

The AD5302/AD5312/AD5322 are provided with a power-on
reset function to power them up in a defined state. The power­on state is

• Normal operation

• Reference inputs unbuffered

• Output voltage set to 0 V

Both input and DAC registers are filled with zeros and remain
so until a valid write sequence is made to the device. This is
particularly useful in applications where it is important to know
the state of the DAC outputs while the device is powering up.

Rev. D | Page 14 of 24

AD5302/AD5312/AD5322

SERIAL INTERFACE

The AD5302/AD5312/AD5322 are controlled over a versatile,
3-wire serial interface, which operates at clock rates up to 30 MHz
and is compatible with SPI, QSPI, MICROWIRE, and DSP
interface standards.

INPUT SHIFT REGISTER

The input shift register is 16 bits wide (see Figure 30 to Figure 32).
Data is loaded into the device as a 16-bit word under the control
of a serial clock input, SCLK. The timing diagram for this
operation is shown in Figure 2. The 16-bit word consists of four
control bits followed by 8, 10, or 12 bits of DAC data, depending
on the device type. The first bit loaded is the MSB (Bit 15),
which determines whether the data is for DAC A or DAC B.
Bit 14 determines if the reference input is buffered or unbuffered.
Bit 13 and Bit 12 control the operating mode of the DAC.

Table 6. Control Bits

Bit Name Function Power-On Default

15

A
1: Data Written to DAC B
14 BUF 0: Reference Is Unbuffered 0
1: Reference Is Buffered
13 PD1 Mode Bit 0
12 PD0 Mode Bit 0

BIT 15
(MSB)

A/B

BIT 15
(MSB)

A/B

BIT 15
(MSB)

A/B

The remaining bits are DAC data bits, starting with the MSB and
ending with the LSB. The AD5322 uses all 12 bits of DAC data,
the AD5312 uses 10 bits and ignores the 2 LSB. The AD5302 uses
eight bits and ignores the last four bits. The data format is straight
binary, with all 0s corresponding to 0 V output, and all 1s
corresponding to full-scale output (VREF – 1 LSB).

SYNC

The
synchronization signal and chip enable. Data can only be
transferred into the device while
data transfer,
SYNC

to SCLK active edge setup time, t4. After

serial data is shifted into the device’s input shift register on the

0: Data Written to DAC A N/A

/B

PD0D7D6D5D4D3D2D1D0PD1BUF XXXX

DATA BITS

Figure 30. AD5302 Input Shift Register Contents

PD0 D7D6D5D4D3D2D1D0PD1BUF XX

D9 D8

DATA BITS

Figure 31. AD5312 Input Shift Register Contents

PD0 D7D6D5D4D3D2D1D0PD1BUF

Figure 32. AD5322 Input Shift Register Contents

D9 D8D11 D10

DATA BITS

input is a level-triggered input that acts as a frame

SYNC

is low. To start the serial

SYNC

should be taken low observing the minimum

SYNC

BIT 0
(LSB)

BIT 0
(LSB)

BIT 0
(LSB)

goes low,

Rev. D | Page 15 of 24

00928-030

00928-031

00928-032

falling edges of SCLK for 16 clock pulses. Any data and clock
pulses after the 16
transfers occur until

SYNC

can be taken high after the falling edge of the 16th SCLK
pulse, observing the minimum SCLK falling edge to
rising edge time, t

th

are ignored, and no further serial data

SYNC

is taken high and low again.

SYNC

.

7

After the end of serial data transfer, data is automatically
transferred from the input shift register to the input register of

SYNC

the selected DAC. If

is taken high before the 16th falling
edge of SCLK, the data transfer is aborted and the input
registers are not updated.

When data has been transferred into both input registers, the
DAC registers of both DACs can be simultaneously updated by

LDAC

taking

low.

LOW POWER SERIAL INTERFACE

To reduce the power consumption of the device even further,
the interface only powers up fully when the device is being
written to. As soon as the 16-bit control word has been written
to the part, the SCLK and DIN input buffers are powered down.
They only power up again following a falling edge of

SYNC

.

DOUBLE-BUFFERED INTERFACE

The AD5302/AD5312/AD5322 DACs all have double-buffered
interfaces consisting of two banks of registers—input registers and
DAC registers. The input register is connected directly to the input
shift register and the digital code is transferred to the relevant input
register on completion of a valid write sequence. The DAC
register contains the digital code used by the resistor string.

Access to the DAC register is controlled by the

LDAC

When

is high, the DAC register is latched and the input
register can change state without affecting the contents of the
DAC register. However, when

LDAC

is brought low, the DAC
register becomes transparent and the contents of the input
register are transferred to it.

This is useful if the user requires simultaneous updating of both
DAC outputs. The user can write to both input registers
individually and then, by pulsing the

LDAC

outputs update simultaneously.

These parts contain an extra feature whereby the DAC register
is not updated unless its input register has been updated since

LDAC

the last time that
LDAC

is brought low, the DAC registers are filled with the

was brought low. Normally, when

contents of the input registers. In the case of the AD5302/
AD5312/AD5322, the part only updates the DAC register if
the input register has been changed since the last time the
DAC register was updated, thereby removing unnecessary
digital crosstalk.

LDAC

function.

input low, both

AD5302/AD5312/AD5322

A

R

POWER-DOWN MODES

The AD5302/AD5312/AD5322 have very low power consump­tion, dissipating only 0.7 mW with a 3 V supply and 1.5 mW
with a 5 V supply. Power consumption can be further reduced
when the DACs are not in use by putting them into one of three
power-down modes, which are selected by Bit 13 and Bit 12
(PD1 and PD0) of the control word. Tab l e 7 shows how the
state of the bits corresponds to the mode of operation of that
particular DAC.

Table 7. PD1/PD0 Operating Modes

PD1 PDO Operating Mode

0 0 Normal Operation
0 1 Power-Down (1 kΩ Load to GND)
1 0 Power-Down (100 kΩ Load to GND)
1 1 Power-Down (High Impedance Output)

When both bits are set to 0, the DACs work normally with
their normal power consumption of 300 A at 5 V. However,
for the three power-down modes, the supply current falls to
200 nA at 5 V (50 nA at 3 V). Not only does the supply current
drop, but the output stage is also internally switched from the
output of the amplifier to a resistor network of known values.
This has the advantage that the output impedance of the part is
known while the part is in power-down mode and provides a
defined input condition for whatever is connected to the output
of the DAC amplifier. There are three different options.

• The output is connected internally to GND through a

1 k resistor,

• The output is connected internally to GND through a

100 k resistor, or

• The output is left open-circuited (three-state).

The output stage is illustrated in Figure 33.

The bias generator, the output amplifier, the resistor string,
and all other associated linear circuitry are shut down when
the power-down mode is activated. However, the contents of
the registers are unaffected when in power-down. The time to
exit power-down is typically 2.5 s for V
V

= 3 V. See Figure 23 for a plot.

DD

MPLIFIE

RESISTOR-

STRING DAC

POWER-DOWN

CIRCUIT RY

Figure 33. Output Stage During Power-Down

= 5 V and 5 s when

DD

V

OUT

RESISTOR
NETWORK

00928-033

Rev. D | Page 16 of 24

AD5302/AD5312/AD5322

MICROPROCESSOR INTERFACING

AD5302/AD5312/AD5322 TO ADSP-2101/ADSP­2103 INTERFACE

Figure 34 shows a serial interface between the AD5302/AD5312/
AD5322 and the ADSP-2101/ADSP-2103. The ADSP-2101/ADSP-

2103 should be set up to operate in the SPORT transmit alternate

framing mode. The ADSP-2101/ADSP-2103 sport is programmed
through the SPORT control register and should be configured
as follows: internal clock operation, active low framing, 16-bit
word length. Transmission is initiated by writing a word to the
Tx register after the SPORT has been enabled. The data is clocked
out on each falling edge of the DSP’s serial clock and clocked into
the AD5302/AD5312/AD5322 on the rising edge of the DSP’s serial
clock. This corresponds to the falling edge of the DAC’s SCLK.

SYNC

DIN

SCLK

AD5302/
AD5312/

AD5322

1

00928-034

ADSP-2101/
ADSP-2103

1

TFS

DT

SCLK

1

ADDITIONAL PINS OMI TTED FO R CLARITY

Figure 34. AD5302/AD5312/AD5322 to ADSP-2101/ADSP-2103 Interface

AD5302/AD5312/AD5322 TO 68HC11/68L11 INTERFACE

Figure 35 shows a serial interface between the AD5302/AD5312/
AD5322 and the 68HC11/68L11 microcontroller. SCK of the
68HC11/68L11 drives the SCLK of the AD5302/AD5312/AD5322,
while the MOSI output drives the serial data line of the DAC.

SYNC

The
conditions for correct operation of this interface are as follows:
the 68HC11/68L11 should be configured so that its CPOL bit = 0
and its CPHA bit = 1. When data is being transmitted to the
DAC, the
68L11 are configured as above, data appearing on the MOSI
output is valid on the falling edge of SCK. Serial data from the
68HC11/ 68L11 is transmitted in 8-bit bytes with only eight
falling clock edges occurring in the transmit cycle. Data is
transmitted MSB first. In order to load data to the
AD5302/AD5312/AD5322, PC7 is left low after the first eight
bits are transferred and a second serial write operation is
performed to the DAC; PC7 is taken high at the end of this
procedure.

signal is derived from a port line (PC7). The setup

SYNC

line is taken low (PC7). When the 68HC11/

68HC11/68L11

1

PC7

SCK

MOSI

1

ADDITIONAL PINS OMIT TED FOR CLARITY

Figure 35. AD5302/AD5312/AD5322 to 68HC11/68L11 Interface

AD5302/
AD5312/
AD5322

SYNC

SCLK

DIN

1

5
3
0

­8
2
9
0
0

Rev. D | Page 17 of 24

AD5302/AD5312/AD5322 TO 80C51/80L51 INTERFACE

Figure 36 shows a serial interface between the AD5302/AD5312/
AD5322 and the 80C51/80L51 microcontroller. The setup for
the interface is as follows: TXD of the 80C51/80L51 drives
SCLK of the AD5302/AD5312/AD5322, while RXD drives the
serial data line of the part. The

SYNC

signal is again derived
from a bit programmable pin on the port. In this case, port line
P3.3 is used. When data is to be transmitted to the AD5302/
AD5312/AD5322, P3.3 is taken low. The 80C51/80L51 transmit
data in 8-bit bytes only; thus only eight falling clock edges occur
in the transmit cycle. To load data to the DAC, P3.3 is left low
after the first eight bits are transmitted, and a second write cycle
is initiated to transmit the second byte of data. P3.3 is taken
high following the completion of this cycle. The 80C51/80L51
output the serial data in a format that has the LSB first. The
AD5302/AD5312/AD5322 require their data with the MSB as
the first bit received. The 80C51/80L51 transmit routine should
take this into account.

80C51/80L51

Figure 36. AD5302/AD5312/AD5322 to 80C51/80L51 Interface

1

P3.3

TXD

RXD

1

ADDITIONAL PI NS OMIT TED FOR CL ARITY

AD5302/
AD5312/
AD5322

SYNC

SCLK

DIN

1

00928-036

AD5302/AD5312/AD5322 TO MICROWIRE INTERFACE

Figure 37 shows an interface between the AD5302/AD5312/
AD5322 and any MICROWIRE-compatible device. Serial data is
shifted out on the falling edge of the serial clock and is clocked
into the AD5302/AD5312/AD5322 on the rising edge of the SK.

MICROWIRE

1

CS SYNC

SO

1

ADDITIONAL PINS OMI TTED FO R CLARITY

Figure 37. AD5302/AD5312/AD5322 to MICROWIRE Interface

AD5302/
AD5312/
AD5322

SCLKSK

DIN

1

00928-037

AD5302/AD5312/AD5322

V

V

V

V

V

(

(

APPLICATIONS INFORMATION

TYPICAL APPLICATION CIRCUIT

The AD5302/AD5312/AD5322 can be used with a wide range
of reference voltages, especially if the reference inputs are
configured to be unbuffered, in which case the devices offer full,
one-quadrant multiplying capability over a reference range of
0 V to V
be used with a fixed, precision reference voltage. Figure 38
shows a typical setup for the AD5302/AD5312/AD5322
when using an external reference. If the reference inputs are
unbuffered, the reference input range is from 0 V to V
the on-chip reference buffers are used, the reference range is
reduced. Suitable references for 5 V operation are the AD780
and REF192 (2.5 V references). For 2.5 V operation, a suitable
external reference would be the REF191, a 2.048 V reference.

If an output range of 0 V to VDD is required when the reference
inputs are configured as unbuffered (for example, 0 V to 5 V),
the simplest solution is to connect the reference inputs to V
As this supply cannot be very accurate and can be noisy, the
AD5302/AD5312/AD5322 can be powered from the reference
voltage, for example, a 5 V reference such as the REF195, as
shown in Figure 39. The REF195 outputs a steady supply
voltage for the AD5302/AD5312/AD5322. The current required
from the REF195 is 300 A supply current and approximately
30 A into each reference input. This is with no load on the
DAC outputs. When the DAC outputs are loaded, the REF195
also needs to supply the current to the loads. The total current
required (with a 10 k load on each output) is

The load regulation of the REF195 is typically 2 ppm/mA,
which results in an error of 2.7 ppm (13.5 V) for the 1.36 mA
current drawn from it. This corresponds to a 0.0007 LSB error
at eight bits and a 0.011 LSB error at 12 bits.

. More typically, the AD5302/AD5312/AD5322 can

DD

DD

= 2.5V to 5. 5

DD

V

EXT

V

OUT

REF

AD780/REF192
WITH V

= 5V

DD

OR REF191 WI TH
V

= 2.5V

DD

1µF

SERIAL

INTERFACE

DD

V

A

REF

V

REF

V

B

OUT

AD5302/AD5312/

AD5322

SCLK

DIN

SYNC

GND

V

OUT

A

B

Figure 38. AD5302/AD5312/AD5322 Using External Reference

⎛
⎜

2A360 =

+

⎜
⎝

⎞

V5

⎟
⎟

k10

Ω

⎠

mA36.1

, but if

00928-038

DD

.

6V to 16

V

IN

REF195

V

GND

OUT

0.1µF 10µF

1µF

V

DD

V

A

REF

V

B

REF

A

V

OUT

AD5302/AD5312/

AD5322

SCLK

SERIAL

INTERFACE

DIN

SYNC

GND

V

B

OUT

00928-039

Figure 39. Using a REF195 as Power and Reference to the

AD5302/AD5312/AD5322

BIPOLAR OPERATION USING THE AD5302/AD5312/AD5322

The AD5302/AD5312/AD5322 are designed for single-supply
operation, but bipolar operation is also achievable using the
circuit shown in Figure 40. This circuit is configured to achieve
an output voltage range of –5 V < V
operation at the amplifier output is achievable using an AD820
or OP295 as the output amplifier.

6V to 16V

0.1µF 10µF

V

IN

REF195

V

OUT

GND

1µF

SERIAL

INTERFACE

Figure 40. Bipolar Operation Using the AD5302/AD5312/AD5322

DD

V

A/B

REF

AD5302/AD5312/

AD5322

SCLK

DIN

SYNC

The output voltage for any input code can be calculated as
follows:

⎡

V

OUT

REF

=

⎢
⎣

N

)

()

1

R

where:

D is the decimal equivalent of the code loaded to the DAC.
N is the DAC resolution.
V

is the reference voltage input.

REF

If V

= 5 V, R1 = R2 = 1 k, and VDD = 5 V:

REF

N

)

OUT

DV

V52/10 −×=

< +5 V. Rail-to-rail

OUT

= 5

R1

10kΩ

V

DD

V

A/B

OUT

GND

⎤

+××

212/

RRDV

⎥
⎦

R2

10kΩ

+5V

AD820/
OP295

–5V

()

×−

REF

±5V

1/2

RRV

00928-040

Rev. D | Page 18 of 24

AD5302/AD5312/AD5322

A

V

V

OPTO-ISOLATED INTERFACE FOR PROCESS CONTROL APPLICATIONS

Each AD5302/AD5312/AD5322 has a versatile 3-wire serial
interface, making them ideal for generating accurate voltages in
process control and industrial applications. Due to noise, safety
requirements, or distance, it can be necessary to isolate the
AD5302/AD5312/AD5322 from the controller. This can easily
be achieved by using opto-isolators, which provide isolation in
excess of 3 kV. The serial loading structure of the AD5302/
AD5312/AD5322 makes them ideally suited for use in opto­isolated applications. Figure 41 shows an opto-isolated interface
to the AD5302/AD5312/AD5322 where DIN, SCLK, and

SYNC

are driven from opto-couplers. The power supply to the part
also needs to be isolated by using a transformer. On the DAC
side of the transformer, a 5 V regulator provides the 5 V supply
required for the AD5302/AD5312/AD5322.

5V

POWER

SCLK

SYNC

DIN

REGULATOR

V

DD

10kΩ

V

DD

10kΩ

V

DD

10kΩ

SCLK

AD5302/AD5312/

AD5322

SYNC

DIN

GND

Figure 41. AD5302/AD5312/AD5322 in an Opto-Isolated Interface

V

DD

10µF 0.1µF

A

V

REF

V

B

REF

V

A

OUT

V

B

OUT

DECODING MULTIPLE AD5302/AD5312/AD5322s

SYNC

The
applications to decode a number of DACs. In this application,
all the DACs in the system receive the same serial clock and serial
data, but only the
time, allowing access to two channels in this eight-channel system.

pin on the AD5302/AD5312/AD5322 can be used in

SYNC

to one of the devices is active at any one

00928-041

The 74HC139 is used as a 2-to-4 line decoder to address any of
the DACs in the system. To prevent timing errors from occurring,
the enable input should be brought to its inactive state while the
coded address inputs are changing state. Figure 42 shows a
diagram of a typical setup for decoding multiple AD5302/
AD5312/AD5322 devices in a system.

SCLK

DIN

ENABLE

CODED

DDRESS

1G

1A

1B

V

DD

V

CC

74HC139

DGND

1Y0

1Y1

1Y2
1Y3

Figure 42. Decoding Multiple AD5302/AD5312/AD5322 Devices in a System

AD5302/AD5312/AD5322

SYNC
DIN
SCLK

AD5302/AD5312/AD5322

SYNC
DIN
SCLK

AD5302/AD5312/AD5322

SYNC
DIN
SCLK

AD5302/AD5312/AD5322

SYNC
DIN
SCLK

AD5302/AD5312/AD5322 AS A DIGITALLY PROGRAMMABLE WINDOW DETECTOR

Figure 43 shows a digitally programmable upper-/lower-limit
detector using the two DACs in the AD5302/AD5312/AD5322.
The upper and lower limits for the test are loaded to DAC A
and DAC B, which, in turn, set the limits on the CMP04. If the
signal at the V
an LED indicates the fail condition.

5

REF

SYNC

DIN

SCLK

Figure 43. Window Detector Using AD5302/AD5312/AD5322

input is not within the programmed window,

IN

0.1µF 10µF

V

A

REF

V

B

REF

AD5302/AD5312/

AD5322

SYNC

DIN

SCLK

GND

V

IN

V

DD

A

V

OUT

1/2

CMP04

V

B

OUT

1kΩ 1kΩ

PAS S/F AIL

1/6 74HC05

FAIL P ASS

00928-042

00928-043

Rev. D | Page 19 of 24

AD5302/AD5312/AD5322

V

V

COARSE AND FINE ADJUSTMENT USING THE AD5302/AD5312/AD5322

The DACs in the AD5302/AD5312/AD5322 can be paired
together to form a coarse and fine adjustment function, as
shown in Figure 44. DAC A is used to provide the coarse
adjustment while DAC B provides the fine adjustment. Varying
the ratio of R1 and R2 changes the relative effect of the coarse
and fine adjustments. With the resistor values and external
reference shown, the output amplifier has unity gain for the
DAC A output, so the output range is 0 V to 2.5 V − 1 LSB. For
DAC B, the amplifier has a gain of 7.6 × 10
range equal to 19 mV.

The circuit is shown with a 2.5 V reference, but reference
voltages up to V

can be used. The op amps indicated allow a

DD

rail-to-rail output swing.

= 5

DD

0.1µF

1µF

10µF

V

DD

A

V

REF

AD5302/AD5312/

AD5322

V

B

REF

GND

EXT
REF

V

GND

IN

V

OUT

Figure 44. Coarse/Fine Adjustment

V

V

OUT

OUT

R3

51.2kΩ

A

B

–3

R1

390Ω

R2

R2

51.2kΩ

51.2kΩ

, giving DAC B a

R4

900Ω

+5V

AD820/
OP295

V

OUT

POWER SUPPLY BYPASSING AND GROUNDING

In any circuit where accuracy is important, careful considera­tion of the power supply and ground return layout helps to
ensure the rated performance. The printed circuit board on
which the AD5302/AD5312/AD5322 is mounted should be
designed so that the analog and digital sections are separated
and confined to certain areas of the board. If the AD5302/
AD5312/AD5322 are in a system where multiple devices require
an AGND-to-DGND connection, the connection should be
made at one point only. The star ground point should be
established as close as possible to the AD5302/AD5312/
AD5322. The part should have ample supply bypassing of 10 F
in parallel with 0.1 F on the supply located as close as possible
to the package, ideally right up against the device. The 10 F
capacitors are the tantalum bead type. The 0.1 F capacitor
should have low effective series resistance (ESR) and effective
series inductance (ESI), similar to the common ceramic types
that provide a low impedance path to ground at high frequencies
that handle transient currents due to internal logic switching.

The power supply lines of the AD5302/AD5312/AD5322
should use as large a trace as possible to provide low impedance
paths and reduce the effects of glitches on the power supply line.
Fast switching signals such as clocks should be shielded with
digital ground to avoid radiating noise to other parts of the board,
and should never be run near the reference inputs. Avoid crossover
of digital and analog signals. Traces on opposite sides of the

0928-044

board should run at right angles to each other. This reduces the
effects of feedthrough through the board. A microstrip technique
is by far the best, but is not always possible with a double-sided
board. In this technique, the component side of the board is dedi­cated to ground while signal traces are placed on the solder side.

Rev. D | Page 20 of 24

AD5302/AD5312/AD5322

OUTLINE DIMENSIONS

3.10

3.00

2.90

10

6

3.10

3.00

2.90

PIN 1

IDENTIFIER

0.95

0.85

0.75

0.15

0.05

COPLANARITY

0.10

1

0.50 BSC

COMPLIANT TO JEDEC STANDARDS MO-187-BA

Figure 45. 10-Lead Mini Small Outline Package [MSOP]

5.15

4.90

4.65

5

15° MAX

6°
0°

0.23

0.13

0.30

0.15

1.10 MAX

(RM-10)

Dimensions shown in millimeters

0.70

0.55

0.40

091709-A

Rev. D | Page 21 of 24

AD5302/AD5312/AD5322

ORDERING GUIDE

Model1, 2 Temperature Range Package Description Package Option Branding

AD5302ARM −40°C to +105°C 10-Lead MSOP RM-10 D5A
AD5302ARM-REEL7 −40°C to +105°C 10-Lead MSOP RM-10 D5A
AD5302ARMZ −40°C to +105°C 10-Lead MSOP RM-10 D5A#
AD5302ARMZ-REEL −40°C to +105°C 10-Lead MSOP RM-10 D5A#
AD5302ARMZ-REEL7 −40°C to +105°C 10-Lead MSOP RM-10 D5A#
AD5302BRM −40°C to +105°C 10-Lead MSOP RM-10 D5B
AD5302BRM-REEL −40°C to +105°C 10-Lead MSOP RM-10 D5B
AD5302BRM-REEL7 −40°C to +105°C 10-Lead MSOP RM-10 D5B
AD5302BRMZ −40°C to +105°C 10-Lead MSOP RM-10 D5B#
AD5302BRMZ-REEL −40°C to +105°C 10-Lead MSOP RM-10 D5B#
AD5302BRMZ-REEL7 −40°C to +105°C 10-Lead MSOP RM-10 D5B#
AD5312ARM −40°C to +105°C 10-Lead MSOP RM-10 D6A
AD5312ARMZ −40°C to +105°C 10-Lead MSOP RM-10 D6A#
AD5312ARMZ-REEL7 −40°C to +105°C 10-Lead MSOP RM-10 D6A#
AD5312BRM −40°C to +105°C 10-Lead MSOP RM-10 D6B
AD5312BRM-REEL −40°C to +105°C 10-Lead MSOP RM-10 D6B
AD5312BRM-REEL7 −40°C to +105°C 10-Lead MSOP RM-10 D6B
AD5312BRMZ −40°C to +105°C 10-Lead MSOP RM-10 D6B#
AD5312BRMZ-REEL −40°C to +105°C 10-Lead MSOP RM-10 D6B#
AD5312BRMZ-REEL7 −40°C to +105°C 10-Lead MSOP RM-10 D6B#
AD5322ARM −40°C to +105°C 10-Lead MSOP RM-10 D7A
AD5322ARM-REEL7 −40°C to +105°C 10-Lead MSOP RM-10 D7A
AD5322ARMZ −40°C to +105°C 10-Lead MSOP RM-10 D6T
AD5322ARMZ-REEL7 −40°C to +105°C 10-Lead MSOP RM-10 D6T
AD5322BRM −40°C to +105°C 10-Lead MSOP RM-10 D7B
AD5322BRM-REEL −40°C to +105°C 10-Lead MSOP RM-10 D7B
AD5322BRM-REEL7 −40°C to +105°C 10-Lead MSOP RM-10 D7B
AD5322BRMZ −40°C to +105°C 10-Lead MSOP RM-10 D7B#
AD5322BRMZ-REEL −40°C to +105°C 10-Lead MSOP RM-10 D7B#
AD5322BRMZ-REEL7 −40°C to +105°C 10-Lead MSOP RM-10 D7B#
AD5312WARMZ-REEL7 −40°C to +105°C 10-Lead MSOP RM-10 D6A#

1

Z = RoHS Compliant Part.

2

W = Qualified for Automotive Applications.

AUTOMOTIVE PRODUCTS

The AD5312WARMZ-REEL7 model is available with controlled manufacturing to support the quality and reliability requirements of
automotive applications. Note that this automotive model may have specifications that differ from the commercial models; therefore,
designers should review the Specifications section of this data sheet carefully. Only the automotive grade product shown is available for
use in automotive applications. Contact your local Analog Devices, Inc., account representative for specific product ordering information
and to obtain the specific Automotive Reliability report for this model.

Rev. D | Page 22 of 24

AD5302/AD5312/AD5322

NOTES

Rev. D | Page 23 of 24

AD5302/AD5312/AD5322

NOTES

©2006-2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00928-0-5/11(D)

Rev. D | Page 24 of 24