ANALOG DEVICES AD5292-EP Service Manual

1024-Position, Digital Potentiometer with

V

Maximum ±1% R-Tolerance Error and 20-TP Memory

Data Sheet

FEATURES

Single-channel, 1024-position resolution
20 kΩ nominal resistance
Maximum ±1% nominal resistor tolerance error (resistor

performance mode)
20-times programmable wiper memory
Rheostat mode temperature coefficient: 35 ppm/°C
Voltage divider temperature coefficient: 5 ppm/°C
+9 V to +33 V single-supply operation
±9 V to ±16.5 V dual-supply operation
SPI-compatible serial interface
Wiper setting readback
Power-on refreshed from 20-TP memory

ENHANCED PRODUCT FEATURES

Supports defense and aerospace applications (AQEC)
Temperature range: −55°C to +125°C
Controlled manufacturing baseline
1 assembly/test site
1 fabrication site
Enhanced product change notification
Qualification data available on request

V

LOGIC

SCLK

SYNC

DIN

SDO

RDY

AD5292-EP

FUNCTIONAL BLOCK DIAGRAM

REGISTER

OTP

MEMORY

BLOCK

EXT_CAP

RESET

AD5292-EP

RDAC

GND

DD

POWER-ON

RESET

SERIAL

INTERFACE

V

SS

DATA

Figure 1.

A

W

B

10095-001

APPLICATIONS

Mechanical potentiometer replacement
Instrumentation: gain and offset adjustment
Programmable voltage-to-current conversion
Programmable filters, delays, and time constants
Programmable power supply
Low resolution DAC replacement
Sensor calibration

GENERAL DESCRIPTION

The AD5292-EP is a single-channel, 1024-position digital
potentiometer
performance with nonvolatile memory (NVM) in a compact
package. This device is capable of operating across a wide voltage
range, supporting both dual supply operation at ±10.5 V to ±16.5
V and single-supply operation at +21 V to +33 V, while ensuring
less than 1% end-to-end resistor tolerance error and offering 20­time programmable (20-TP) memory.

The guaranteed industry leading low resistor tolerance error
feature simplifies open-loop applications as well as precision
calibration and tolerance matching applications.

1

The terms digital potentiometer and RDAC are used interchangeably.

1

that combines industry leading variable resistor

The AD5292-EP device wiper settings are controllable through
the SPI digital interface. Unlimited adjustments are allowed
before programming the resistance value into the 20-TP memory.
The AD5292-EP does not require any external voltage supply
to facilitate fuse blow, and there are 20 opportunities for perma­nent programming. During 20-TP activation, a permanent blow
fuse command freezes the wiper position (analogous to placing
epoxy on a mechanical trimmer).

The AD5292-EP is available in a compact 14-lead TSSOP
package. The part is guaranteed to operate over the extended
industrial temperature range of −55°C to +125°C.

Additional application and technical information can be found
in the AD5292 data sheet.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2011 Analog Devices, Inc. All rights reserved.

AD5292-EP Data Sheet

TABLE OF CONTENTS

Features.............................................................................................. 1

Enhanced Product Features ............................................................ 1

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Electrical Characteristics—AD5292-EP.................................... 3

Resistor Performance Mode Code Range ................................. 4

REVISION HISTORY

9/11—Revision 0: Initial Version

Interface Timing Specifications...................................................5

Absolute Maximum Ratings ............................................................7

Thermal Resistance.......................................................................7

ESD Caution...................................................................................7

Pin Configuration and Function Descriptions..............................8

Typical Performance Characteristics..............................................9

Test Circuits..................................................................................... 14

Outline Dimensions....................................................................... 15

Ordering Guide .......................................................................... 15

Rev. 0 | Page 2 of 16

Data Sheet AD5292-EP

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS—AD5292-EP

VDD = 21 V to 33 V, VSS = 0 V; VDD = 10.5 V to 16.5 V, VSS = −10.5 V to −16.5 V; V

−55°C < T

< +125°C, unless otherwise noted.

A

Table 1.

Parameter Symbol Conditions Min Typ1 Max Unit

DC CHARACTERISTICS—RHEOSTAT MODE

Resolution N 10 Bits

Resistor Differential Nonlinearity2 R-DNL RWB, VA = NC −1 +1 LSB

Resistor Integral Nonlinearity2 R-INL R

R-INL R

Nominal Resistor Tolerance (R-Perf Mode)3 ∆RAB/RAB See Table 2 −1 ±0.5 +1 %

Nominal Resistor Tolerance (Normal

Mode)

4

±7 %

∆R

AB/RAB

Resistance Temperature Coefficient (∆RAB/RAB)/∆T × 106 Code = full scale; see Figure 14 35 ppm/°C

Wiper Resistance RW Code= zero scale 60 100 Ω

DC CHARACTERISTICS—POTENTIOMETER

DIVIDER MODE

Resolution N 10 Bits

Differential Nonlinearity5 DNL −1 +1 LSB

Integral Nonlinearity5 INL −2.5 +2.5 LSB

Voltage Divider Temperature Coefficient4 (∆VW/VW)/∆T × 106 Code = half scale; see Figure 17 5 ppm/°C

Full-Scale Error V

Zero-Scale Error V

Code = full scale −8 +1 LSB

WFSE

Code = zero scale 0 10 LSB

WZSE

RESISTOR TERMINALS

Terminal Voltage Range6 V

Capacitance A, Capacitance B4 C

Capacitance W4 C

Common-Mode Leakage Current4 I

, VB, VW V

A

, CB f = 1 MHz, measured to GND,

A

f = 1 MHz, measured to GND,

W

V

CM

DIGITAL INPUTS JEDEC compliant

Input Logic High

Input Logic Low4 V

4

VIH V

V

IL

Input Current IIL V

Input Capacitance4 C

5 pF

IL

DIGITAL OUTPUTS (SDO and RDY)

Output High Voltage4 V

Output Low Voltage4 V

R

OH

R

OL

Three-State Leakage Current −1 +1 μA

Output Capacitance4 C

5 pF

OL

POWER SUPPLIES

Single-Supply Power Range VDD V

Dual-Supply Power Range VDD/VSS ±9 ±16.5 V

Positive Supply Current IDD V

Negative Supply Current ISS V

Logic Supply Range V

Logic Supply Current I

OTP Store Current

OTP Read Current

4, 7

4, 8

Power Dissipation9 P

2.7 5.5 V

LOGIC

V

LOGIC

I

VIH = 5 V or VIL = GND 25 mA

LOGIC_PROG

I

LOGIC_FUSE_READ

DISS

VIH = 5 V or VIL = GND 25 mA

V

Power Supply Rejection Ratio PSRR ∆VDD/∆VSS = ±15 V ± 10% 0.103 %/%

=20 kΩ, |VDD − VSS| = 26 V to 33 V −2 +2 LSB

AB

=20 kΩ, |VDD − VSS| = 21 V to 26 V −3 +3 LSB

AB

code = half scale

code = half scale

= VB = VW −120 ±1 120 nA

A

= 2.7 V to 5.5 V 2.0 V

LOGIC

= 2.7 V to 5.5 V 0.8 V

LOGIC

= 0 V or V

IN

= 2.2 kΩ to V

PULL_UP

= 2.2 kΩ to V

PULL_UP

= 0 V 9 33 V

SS

= ±16.5 V 0.1 2 μA

DD/VSS

= ±16.5 V −2 −0.1 μA

DD/VSS

= 5 V, VIH = 5 V or VIL = GND 1 10 μA

LOGIC

= 5 V or VIL = GND 8 110 μW

IH

±1 μA

LOGIC

= 2.7 V to 5.5 V, VA = VDD, VB = VSS,

LOGIC

V

SS

V

DD

85 pF

65 pF

V

LOGIC

GND + 0.4 V

LOGIC

− 0.4 V

LOGIC

Rev. 0 | Page 3 of 16

AD5292-EP Data Sheet

Parameter Symbol Conditions Min Typ1 Max Unit

DYNAMIC CHARACTERISTICS

Bandwidth BW −3 dB 520 kHz
Total Harmonic Distortion THDW V
VW Settling Time tS V

Code = full-scale, normal mode 750 ns
Code = full-scale, R-Perf mode 2.5 μs
Code = half-scale, normal mode 2.5 μs
Code = half-scale, R-Perf mode 5 μs
Resistor Noise Density e

1

Typical values represent average readings at 25°C, VDD = 15 V, VSS = −15 V, and V

2

Resistor position nonlinearity error. R-INL is the deviation from an ideal value measured between RWB at Code 0x00B and Code 0x3FF or between RWA at Code 0x3F3

and Code 0x000. R-DNL measures the relative step change from ideal between successive tap positions. The specification is guaranteed in resistor performance mode,
with a wiper current of 1 mA for VA < 12 V and 1.2 mA for VA ≥ 12 V.

3

Resistor performance mode. The terms resistor performance mode and R-Perf mode are used interchangeably.

4

Guaranteed by design and characterization, not subject to production test.

5

INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits

of ±1 LSB maximum are guaranteed monotonic operating conditions.

6

Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other. Dual-supply operation enables ground-

referenced bipolar signal adjustment.

7

Different from operating current; supply current for fuse program lasts approximately 550 μs.

8

Different from operating current; supply current for fuse read lasts approximately 550 μs.

9

P

is calculated from (IDD × VDD) + (ISS × VSS) + (I

DISS

10

All dynamic characteristics use VDD = 15 V, VSS = −15 V, and V

5, 10

= 1 V rms, VB = 0 V, f = 1 kHz −93 dB

A

= 30 V, VB = 0 V, ±0.5 LSB error

A

band, initial code = zero scale, board
capacitance = 170 pF

Code = half-scale, TA = 25°C, 0 kHz to

N_WB

10 nV/√Hz

200 kHz

= 5 V.

LOGIC

× V

LOGIC

).

= 5 V.

LOGIC

LOGIC

RESISTOR PERFORMANCE MODE CODE RANGE

Table 2.

Resistor
Tolerance per
Code

1% R-Tolerance

2% R-Tolerance

3% R-Tolerance

|VDD − VSS| = 30 V to 33 V |VDD − VSS| = 26 V to 30 V |VDD − VSS| = 22 V to 26 V |VDD − VSS| = 21 V to 22 V

R

R

WB

From 0x1EF
to 0x3FF

From 0x0C3
to 0x3FF

From 0x073
to 0x3FF

R

WA

From 0x000
to 0x210

From 0x000
to 0x33C

From 0x000
to 0x38C

WB

From 0x1F4
to 0x3FF

From 0x0E6
to 0x3FF

From 0x087
to 0x3FF

R

−55°C < TA < +125°C

R

WA

From 0x000
to 0x20B

From 0x000
to 0x319

From 0x000
to 0x378

WB

From 0x1F4
to 0x3FF

From 0x131
to 0x3FF

From 0x0AF
to 0x3FF

R

R

WA

From 0x000
to 0x20B

From 0x000
to 0x2CE

From 0x000
to 0x350

R

WB

WA

N/A N/A

From 0x131
to 0x3FF

From 0x0AF
to 0x3FF

From 0x000
to 0x2CE

From 0x000
to 0x350

Rev. 0 | Page 4 of 16

Data Sheet AD5292-EP

INTERFACE TIMING SPECIFICATIONS

VDD/VSS = ±15 V, V

Table 3.

Parameter Limit1 Unit Description

2

t

20 ns min SCLK cycle time

1

t2 10 ns min SCLK high time
t3 10 ns min SCLK low time
t4 10 ns min

t5 5 ns min Data setup time
t6 5 ns min Data hold time
t7 1 ns min

t8 4003 ns min
t9 14 ns min

4

t

1 ns min

10

4

t

40 ns max

11

4

t

2.4 μs max RDY low time, RDAC register write command execute time (R-Perf mode)

12

4

t

410 ns max RDY low time, RDAC register write command execute time (normal mode)

12

4

t

8 ms max RDY low time, memory program execute time

12

4

t

1.5 ms min Software/hardware reset

12

4

t

450 ns max RDY low time, RDAC register readback execute time

13

4

t

1.3 ms max RDY low time, memory readback execute time

13

4

t

450 ns max SCLK rising edge to SDO valid

14

t

20 ns min

RESET

5

t

POWER-UP

1

All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.

2

Maximum SCLK frequency is 50 MHz.

3

Refer to t12 and t13 for RDAC register and memory commands operations.

4

R

= 2.2 kΩ to V

PULL_UP

5

Maximum time after V

= 2.7 V to 5.5 V, −55°C < TA < +125°C. All specifications T

LOGIC

to SCLK falling edge setup time

SYNC

SCLK falling edge to SYNC
Minimum SYNC

rising edge to next SCLK fall ignore

SYNC

high time

RDY rising edge to SYNC

rising edge to RDY fall time

SYNC

Minimum RESET

pulse width (asynchronous)

2 ms max Power-on OTP restore time

, with a capacitance load of 168 pF.

LOGIC

is equal to 2.5 V.

LOGIC

DB9 (MSB) DB0 (LSB)

MIN

rising edge

falling edge

to T

, unless otherwise noted.

MAX

C0C1

C3

00

C2

CONTROL BI TS

D9

D7 D6 D5 D4 D3

D8

DATA BITS

D2 D1

D0

10095-003

Figure 2. Shift Register Content

Rev. 0 | Page 5 of 16