Datasheet AD5292-EP Datasheet (ANALOG DEVICES)

1024-Position, Digital Potentiometer with

V

Maximum ±1% R-Tolerance Error and 20-TP Memory

Data Sheet

FEATURES

Single-channel, 1024-position resolution
20 kΩ nominal resistance
Maximum ±1% nominal resistor tolerance error (resistor

performance mode)
20-times programmable wiper memory
Rheostat mode temperature coefficient: 35 ppm/°C
Voltage divider temperature coefficient: 5 ppm/°C
+9 V to +33 V single-supply operation
±9 V to ±16.5 V dual-supply operation
SPI-compatible serial interface
Wiper setting readback
Power-on refreshed from 20-TP memory

ENHANCED PRODUCT FEATURES

Supports defense and aerospace applications (AQEC)
Temperature range: −55°C to +125°C
Controlled manufacturing baseline
1 assembly/test site
1 fabrication site
Enhanced product change notification
Qualification data available on request

V

LOGIC

SCLK

SYNC

DIN

SDO

RDY

AD5292-EP

FUNCTIONAL BLOCK DIAGRAM

REGISTER

OTP

MEMORY

BLOCK

EXT_CAP

RESET

AD5292-EP

RDAC

GND

DD

POWER-ON

RESET

SERIAL

INTERFACE

V

SS

DATA

Figure 1.

A

W

B

10095-001

APPLICATIONS

Mechanical potentiometer replacement
Instrumentation: gain and offset adjustment
Programmable voltage-to-current conversion
Programmable filters, delays, and time constants
Programmable power supply
Low resolution DAC replacement
Sensor calibration

GENERAL DESCRIPTION

The AD5292-EP is a single-channel, 1024-position digital
potentiometer
performance with nonvolatile memory (NVM) in a compact
package. This device is capable of operating across a wide voltage
range, supporting both dual supply operation at ±10.5 V to ±16.5
V and single-supply operation at +21 V to +33 V, while ensuring
less than 1% end-to-end resistor tolerance error and offering 20­time programmable (20-TP) memory.

The guaranteed industry leading low resistor tolerance error
feature simplifies open-loop applications as well as precision
calibration and tolerance matching applications.

1

The terms digital potentiometer and RDAC are used interchangeably.

1

that combines industry leading variable resistor

The AD5292-EP device wiper settings are controllable through
the SPI digital interface. Unlimited adjustments are allowed
before programming the resistance value into the 20-TP memory.
The AD5292-EP does not require any external voltage supply
to facilitate fuse blow, and there are 20 opportunities for perma­nent programming. During 20-TP activation, a permanent blow
fuse command freezes the wiper position (analogous to placing
epoxy on a mechanical trimmer).

The AD5292-EP is available in a compact 14-lead TSSOP
package. The part is guaranteed to operate over the extended
industrial temperature range of −55°C to +125°C.

Additional application and technical information can be found
in the AD5292 data sheet.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2011 Analog Devices, Inc. All rights reserved.

AD5292-EP Data Sheet

TABLE OF CONTENTS

Features.............................................................................................. 1

Enhanced Product Features ............................................................ 1

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Electrical Characteristics—AD5292-EP.................................... 3

Resistor Performance Mode Code Range ................................. 4

REVISION HISTORY

9/11—Revision 0: Initial Version

Interface Timing Specifications...................................................5

Absolute Maximum Ratings ............................................................7

Thermal Resistance.......................................................................7

ESD Caution...................................................................................7

Pin Configuration and Function Descriptions..............................8

Typical Performance Characteristics..............................................9

Test Circuits..................................................................................... 14

Outline Dimensions....................................................................... 15

Ordering Guide .......................................................................... 15

Rev. 0 | Page 2 of 16

Data Sheet AD5292-EP

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS—AD5292-EP

VDD = 21 V to 33 V, VSS = 0 V; VDD = 10.5 V to 16.5 V, VSS = −10.5 V to −16.5 V; V

−55°C < T

< +125°C, unless otherwise noted.

A

Table 1.

Parameter Symbol Conditions Min Typ1 Max Unit

DC CHARACTERISTICS—RHEOSTAT MODE

Resolution N 10 Bits

Resistor Differential Nonlinearity2 R-DNL RWB, VA = NC −1 +1 LSB

Resistor Integral Nonlinearity2 R-INL R

R-INL R

Nominal Resistor Tolerance (R-Perf Mode)3 ∆RAB/RAB See Table 2 −1 ±0.5 +1 %

Nominal Resistor Tolerance (Normal

Mode)

4

±7 %

∆R

AB/RAB

Resistance Temperature Coefficient (∆RAB/RAB)/∆T × 106 Code = full scale; see Figure 14 35 ppm/°C

Wiper Resistance RW Code= zero scale 60 100 Ω

DC CHARACTERISTICS—POTENTIOMETER

DIVIDER MODE

Resolution N 10 Bits

Differential Nonlinearity5 DNL −1 +1 LSB

Integral Nonlinearity5 INL −2.5 +2.5 LSB

Voltage Divider Temperature Coefficient4 (∆VW/VW)/∆T × 106 Code = half scale; see Figure 17 5 ppm/°C

Full-Scale Error V

Zero-Scale Error V

Code = full scale −8 +1 LSB

WFSE

Code = zero scale 0 10 LSB

WZSE

RESISTOR TERMINALS

Terminal Voltage Range6 V

Capacitance A, Capacitance B4 C

Capacitance W4 C

Common-Mode Leakage Current4 I

, VB, VW V

A

, CB f = 1 MHz, measured to GND,

A

f = 1 MHz, measured to GND,

W

V

CM

DIGITAL INPUTS JEDEC compliant

Input Logic High

Input Logic Low4 V

4

VIH V

V

IL

Input Current IIL V

Input Capacitance4 C

5 pF

IL

DIGITAL OUTPUTS (SDO and RDY)

Output High Voltage4 V

Output Low Voltage4 V

R

OH

R

OL

Three-State Leakage Current −1 +1 μA

Output Capacitance4 C

5 pF

OL

POWER SUPPLIES

Single-Supply Power Range VDD V

Dual-Supply Power Range VDD/VSS ±9 ±16.5 V

Positive Supply Current IDD V

Negative Supply Current ISS V

Logic Supply Range V

Logic Supply Current I

OTP Store Current

OTP Read Current

4, 7

4, 8

Power Dissipation9 P

2.7 5.5 V

LOGIC

V

LOGIC

I

VIH = 5 V or VIL = GND 25 mA

LOGIC_PROG

I

LOGIC_FUSE_READ

DISS

VIH = 5 V or VIL = GND 25 mA

V

Power Supply Rejection Ratio PSRR ∆VDD/∆VSS = ±15 V ± 10% 0.103 %/%

=20 kΩ, |VDD − VSS| = 26 V to 33 V −2 +2 LSB

AB

=20 kΩ, |VDD − VSS| = 21 V to 26 V −3 +3 LSB

AB

code = half scale

code = half scale

= VB = VW −120 ±1 120 nA

A

= 2.7 V to 5.5 V 2.0 V

LOGIC

= 2.7 V to 5.5 V 0.8 V

LOGIC

= 0 V or V

IN

= 2.2 kΩ to V

PULL_UP

= 2.2 kΩ to V

PULL_UP

= 0 V 9 33 V

SS

= ±16.5 V 0.1 2 μA

DD/VSS

= ±16.5 V −2 −0.1 μA

DD/VSS

= 5 V, VIH = 5 V or VIL = GND 1 10 μA

LOGIC

= 5 V or VIL = GND 8 110 μW

IH

±1 μA

LOGIC

= 2.7 V to 5.5 V, VA = VDD, VB = VSS,

LOGIC

V

SS

V

DD

85 pF

65 pF

V

LOGIC

GND + 0.4 V

LOGIC

− 0.4 V

LOGIC

Rev. 0 | Page 3 of 16

AD5292-EP Data Sheet

Parameter Symbol Conditions Min Typ1 Max Unit

DYNAMIC CHARACTERISTICS

Bandwidth BW −3 dB 520 kHz
Total Harmonic Distortion THDW V
VW Settling Time tS V

Code = full-scale, normal mode 750 ns
Code = full-scale, R-Perf mode 2.5 μs
Code = half-scale, normal mode 2.5 μs
Code = half-scale, R-Perf mode 5 μs
Resistor Noise Density e

1

Typical values represent average readings at 25°C, VDD = 15 V, VSS = −15 V, and V

2

Resistor position nonlinearity error. R-INL is the deviation from an ideal value measured between RWB at Code 0x00B and Code 0x3FF or between RWA at Code 0x3F3

and Code 0x000. R-DNL measures the relative step change from ideal between successive tap positions. The specification is guaranteed in resistor performance mode,
with a wiper current of 1 mA for VA < 12 V and 1.2 mA for VA ≥ 12 V.

3

Resistor performance mode. The terms resistor performance mode and R-Perf mode are used interchangeably.

4

Guaranteed by design and characterization, not subject to production test.

5

INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits

of ±1 LSB maximum are guaranteed monotonic operating conditions.

6

Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other. Dual-supply operation enables ground-

referenced bipolar signal adjustment.

7

Different from operating current; supply current for fuse program lasts approximately 550 μs.

8

Different from operating current; supply current for fuse read lasts approximately 550 μs.

9

P

is calculated from (IDD × VDD) + (ISS × VSS) + (I

DISS

10

All dynamic characteristics use VDD = 15 V, VSS = −15 V, and V

5, 10

= 1 V rms, VB = 0 V, f = 1 kHz −93 dB

A

= 30 V, VB = 0 V, ±0.5 LSB error

A

band, initial code = zero scale, board
capacitance = 170 pF

Code = half-scale, TA = 25°C, 0 kHz to

N_WB

10 nV/√Hz

200 kHz

= 5 V.

LOGIC

× V

LOGIC

).

= 5 V.

LOGIC

LOGIC

RESISTOR PERFORMANCE MODE CODE RANGE

Table 2.

Resistor
Tolerance per
Code

1% R-Tolerance

2% R-Tolerance

3% R-Tolerance

|VDD − VSS| = 30 V to 33 V |VDD − VSS| = 26 V to 30 V |VDD − VSS| = 22 V to 26 V |VDD − VSS| = 21 V to 22 V

R

R

WB

From 0x1EF
to 0x3FF

From 0x0C3
to 0x3FF

From 0x073
to 0x3FF

R

WA

From 0x000
to 0x210

From 0x000
to 0x33C

From 0x000
to 0x38C

WB

From 0x1F4
to 0x3FF

From 0x0E6
to 0x3FF

From 0x087
to 0x3FF

R

−55°C < TA < +125°C

R

WA

From 0x000
to 0x20B

From 0x000
to 0x319

From 0x000
to 0x378

WB

From 0x1F4
to 0x3FF

From 0x131
to 0x3FF

From 0x0AF
to 0x3FF

R

R

WA

From 0x000
to 0x20B

From 0x000
to 0x2CE

From 0x000
to 0x350

R

WB

WA

N/A N/A

From 0x131
to 0x3FF

From 0x0AF
to 0x3FF

From 0x000
to 0x2CE

From 0x000
to 0x350

Rev. 0 | Page 4 of 16

Data Sheet AD5292-EP

INTERFACE TIMING SPECIFICATIONS

VDD/VSS = ±15 V, V

Table 3.

Parameter Limit1 Unit Description

2

t

20 ns min SCLK cycle time

1

t2 10 ns min SCLK high time
t3 10 ns min SCLK low time
t4 10 ns min

t5 5 ns min Data setup time
t6 5 ns min Data hold time
t7 1 ns min

t8 4003 ns min
t9 14 ns min

4

t

1 ns min

10

4

t

40 ns max

11

4

t

2.4 μs max RDY low time, RDAC register write command execute time (R-Perf mode)

12

4

t

410 ns max RDY low time, RDAC register write command execute time (normal mode)

12

4

t

8 ms max RDY low time, memory program execute time

12

4

t

1.5 ms min Software/hardware reset

12

4

t

450 ns max RDY low time, RDAC register readback execute time

13

4

t

1.3 ms max RDY low time, memory readback execute time

13

4

t

450 ns max SCLK rising edge to SDO valid

14

t

20 ns min

RESET

5

t

POWER-UP

1

All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.

2

Maximum SCLK frequency is 50 MHz.

3

Refer to t12 and t13 for RDAC register and memory commands operations.

4

R

= 2.2 kΩ to V

PULL_UP

5

Maximum time after V

= 2.7 V to 5.5 V, −55°C < TA < +125°C. All specifications T

LOGIC

to SCLK falling edge setup time

SYNC

SCLK falling edge to SYNC
Minimum SYNC

rising edge to next SCLK fall ignore

SYNC

high time

RDY rising edge to SYNC

rising edge to RDY fall time

SYNC

Minimum RESET

pulse width (asynchronous)

2 ms max Power-on OTP restore time

, with a capacitance load of 168 pF.

LOGIC

is equal to 2.5 V.

LOGIC

DB9 (MSB) DB0 (LSB)

MIN

rising edge

falling edge

to T

, unless otherwise noted.

MAX

C0C1

C3

00

C2

CONTROL BI TS

D9

D7 D6 D5 D4 D3

D8

DATA BITS

D2 D1

D0

10095-003

Figure 2. Shift Register Content

Rev. 0 | Page 5 of 16

AD5292-EP Data Sheet

Timing Diagrams

t

SCLK

SYNC

DIN

4

t

8

X

t

2

t

3

XC3 C2

t

1

D7

D6

D2

t

7

t

9

t

5

t

6

D0D1

SDO

RDY

RESET

SCLK

SYNC

SDO

RDY

DIN

t

t

10

11

t

12

t

RESET

10095-004

Figure 3. Write Timing Diagram, CPOL = 0, CPHA = 1

t

9

X

XC3

D0

t

11

D0

t

13

X

X

X

C3

t

14

X

C3

D0D1

D0D1

10095-005

Figure 4. Read Timing Diagram, CPOL = 0, CPHA = 1

Rev. 0 | Page 6 of 16

Data Sheet AD5292-EP

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 4.

Parameter Rating

VDD to GND −0.3 V to +35 V
VSS to GND +0.3 V to −25 V
V

to GND −0.3 V to +7 V

LOGI C

VDD to VSS 35 V
VA, VB, VW to GND VSS − 0.3 V, VDD + 0.3 V
Digital Input and Output Voltage to GND −0.3 V to V

LOGI C

+ 0.3 V
EXT_CAP Voltage to GND −0.3 V to +7 V
IA, IB, IW

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

THERMAL RESISTANCE

θJA is defined by JEDEC specification JESD-51 and the value is
dependent on the test board and test environment.

Continuous ±3 mA
Pulsed1

Frequency > 10 kHz ±3/d2
Frequency ≤ 10 kHz ±3/√d

2

Operating Temperature Range3 −55°C to +125°C
Maximum Junction Temperature (TJ max) 150°C
Storage Temperature Range −65°C to +150°C
Reflow Soldering

Table 5. Thermal Resistance

Package Type θJA θ

14-Lead TSSOP 931 20 °C/W

1

JEDEC 2S2P test board, still air (0 m/sec to 1 m/sec air flow).

ESD CAUTION

Peak Temperature 260°C
Time at Peak Temperature 20 sec to 40 sec

Package Power Dissipation (TJ max − TA)/θJA

1

Maximum terminal current is bounded by the maximum current handling of

the switches, maximum power dissipation of the package, and maximum
applied voltage across any two of the A, B, and W terminals at a given
resistance.

2

Pulse duty factor.

3

Includes programming of OTP memory.

Unit

JC

Rev. 0 | Page 7 of 16

AD5292-EP Data Sheet

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

RESET

1

2

V

SS

3

A

AD5292-EP

W

4

TOP VIEW

(Not to Scale)

B

5

V

6

DD

EXT_CAP

7

Figure 5. Pin Configuration

Table 6. Pin Function Descriptions

Pin No. Mnemonic Description

1

Hardware Reset Pin. Refreshes the RDAC register with the contents of the 20-TP memory register. Factory

RESET

default loads midscale until the first 20-TP wiper memory location is programmed. RESET

2 VSS

logic high transition. Tie RESET
Negative Supply. Connect to 0 V for single-supply applications. This pin should be decoupled with 0.1 μF

to V

if not used.

LOGI C

ceramic capacitors and 10 μF capacitors.
3 A Terminal A of RDAC. VSS ≤ VA ≤ VDD.
4 W Wiper Terminal of RDAC. VSS ≤ VW ≤ VDD.
5 B Terminal B of RDAC. VSS ≤ VB ≤ VDD.
6 VDD Positive Power Supply. This pin should be decoupled with 0.1 μF ceramic capacitors and 10 μF capacitors.
7 EXT_CAP External Capacitor. Connect a 1 μF capacitor to EXT_CAP. This capacitor must have a voltage rating of ≥7 V.
8 V

LOGI C

Logic Power Supply; 2.7 V to 5.5 V. This pin should be decoupled with 0.1 μF ceramic capacitors and 10 μF

capacitors.
9 GND Ground Pin, Logic Ground Reference.
10 DIN

Serial Data Input. The AD5292-EP has a 16-bit shift register. Data is clocked into the register on the falling edge

of the serial clock input.
11 SCLK

Serial Clock Input. Data is clocked into the shift register on the falling edge of the serial clock input. Data can be

transferred at rates up to 50 MHz.
12

Falling Edge Synchronization Signal. This is the frame synchronization signal for the input data. When SYNC

SYNC

goes low, it enables the shift register and data is transferred in on the falling edges of the following clocks. The

selected register is updated on the rising edge of SYNC following the 16th clock cycle. If SYNC is taken high

before the 16th clock cycle, the rising edge of SYNC acts as an interrupt, and the write sequence is ignored by

the DAC.
13 SDO

Serial Data Output. This open-drain output requires an external pull-up resistor. SDO can be used to clock data

from the shift register in daisy-chain mode or in readback mode.
14 RDY

Ready Pin. This active-high open-drain output identifies the completion of a write or read operation to or from

the RDAC register or memory.

14

RDY

13

SDO

12

SYNC

SCLK

11

10

DIN

9

GND

8

V

LOGIC

10095-006

is activated at the

Rev. 0 | Page 8 of 16

Data Sheet AD5292-EP

TYPICAL PERFORMANCE CHARACTERISTICS

1.0

0.8

0.6

0.4

0.2

0

INL (LSB)

–0.2

–0.4

–0.6

–0.8

–1.0

0 128 256 384 512 640 768 896 1023

CODE (Decimal)

Figure 6. R-INL in R-Perf Mode vs. Code

–40°C

+25°C

+105°C

10095-106

0.6

0.5

0.4

0.3

0.2

0.1

DNL (LSB)

0

–0.1

–0.2

–0.3

0 128 256 384 512 640 768 896 1023

–40°C

+25°C

CODE (Decimal)

+105°C

Figure 9. R-DNL in R-Perf Mode vs. Code

10095-007

1.5

1.0

0.5

0

INL (LSB)

–0.5

–1.0

–1.5

0 128 256 384 512 640 768 896 1023

–40°C

+25°C

CODE (Decimal)

+105°C

Figure 7. INL in R-Perf Mode vs. Code

1.0

0.8

0.6

0.4

0.2

INL (LSB)

0

–0.2

–0.4

–0.6

0 128 256 384 512 640 768 896 1023

–40°C

+25°C

CODE (Decimal)

+105°C

Figure 8. R-INL in Normal Mode vs. Code

0.6

0.5

0.4

0.3

0.2

DNL (LSB)

0.1

0

–0.1

–0.2

0 128 256 384 512 640 768 896 1023

10095-014

–40°C

+25°C

CODE (Decimal)

+105°C

10095-015

Figure 10. DNL in R-Perf Mode vs. Code

0.15

0.10

0.05

0

–0.05

DNL (LSB)

–0.10

–0.15

–0.20

0 128 256 384 512 640 768 896 1023

10095-010

–40°C

+25°C

CODE (Decimal)

+105°C

10095-011

Figure 11. R-DNL in Normal Mode vs. Code

Rev. 0 | Page 9 of 16

AD5292-EP Data Sheet

A

0.8

0.6

0.4

0.2

–40°C

+25°C

+105°C

0.10

0.05

–40°C

+25°C

+105°C

0

0

INL (LSB)

–0.2

–0.4

–0.6

–0.8

0 128 256 384 512 640 768 896 1023

CODE (Decimal)

Figure 12. INL in Normal Mode vs. Code

450

400

350

300

250

200

150

100

SUPPLY CURRENT (nA)

50

0

–50

–40–30–20–100 102030405060708090100

Figure 13. Supply Current (I

TEMPERATURE (° C)

, ISS, I

DD

VDD/VSS = ±15V
V

I

LOGIC

) vs. Temperature

LOGIC

LOGIC

I

SS

= +5V

I

DD

–0.05

DNL (LSB)

–0.10

–0.15

–0.20

0 128 256 384 512 640 768 896 1023

10095-018

CODE (Decimal)

10095-019

Figure 15. DNL in Normal Mode vs. Code

0.20

0.18

0.16

(mA)

0.14

LOGIC

0.12

0.10

0.08

0.06

SUPPLY CURRENT I

0.04

0.02

0

10095-022

0 0.5 1.0 1.5 2. 0 2. 5 3.0 3.5 4.0 4.5 5. 0

Figure 16. Supply Current I

DIGITAL INPUT VOLTAGE (V)

vs. Digital Input Voltage

LOGIC

VDD = ±15V

10095-031

700

600

500

400

300

T MODE TEMPCO (ppm/°C)

200

100

RHEOST

0

0 256 512 768 1023

CODE (Decimal)

Figure 14. Rheostat Mode Tempco ΔR

VDD = 30V
V

/ΔT vs. Code

WB

700

= 0V

SS

10095-024

600

500

400

300

200

100

POTENTI OMETER MO DE TEMPCO (ppm/° C)

0

0 256 512 768 1023

CODE (Decimal)

Figure 17. Potentiometer Mode Tempco ΔR

VDD = 30V

= 0V

V

SS

/ΔT vs. Code

WB

10095-023

Rev. 0 | Page 10 of 16

Data Sheet AD5292-EP

0

0x200

–5

–10

0x100

–15

0x080

–20

0x040

–25

0x020

GAIN (dB)

–30

0x010

–35

0x008

–40

0x004

–45

0x002 0x001

–50

FREQUENC Y (Hz)

Figure 18. 20 kΩ Gain vs. Frequency vs. Code

0

VDD/VSS = ±15V
CODE = HALF SCALE

–15

= 1V rms

V

IN

NOISE BW = 22kHz

–30

–45

–60

THD + N (dB)

–75

–90

–105

–120

100 1k 10k 100k

FREQUENCY (Hz)

Figure 19. THD + Noise vs. Frequency

1M100k10k1k10010

10095-025

10095-027

0

–10

–20

–30

–40

PSRR (dB)

–50

–60

–70

100 1k 10k

FREQUENCY (Hz)

100k 1M

Figure 21. Power Supply Rejection Ratio vs. Frequency

0

–20

–40

–60

–80

THD + N (dB)

–100

–120

–140

0.001 0.01 0.1 1 10

AMPLIT UDE (V rms)

VDD/VSS = ±15V,
CODE = HALF SCALE

f

= 1kHz

IN

NOISE BW = 22kHz

Figure 22. THD + Noise vs. Amplitude

10095-026

10095-220

1,000,000

900,000

800,000

700,000

600,000

500,000

400,000

BANDWIDTH (Hz)

300,000

200,000

100,000

0

CODE (Decimal)

Figure 20. Bandwidth vs. Code vs. Net Capacitance

0pF
75pF
150pF
250pF

5120 128 2566432168

10095-222

Rev. 0 | Page 11 of 16

(mA)

DD

SUPPLY CURRENT I

35

30

25

20

15

10

5

0

–5

–0.4 1.21.00.80.60.40.20–0. 2

Figure 23. I

TIME (ms)

Waveform While Blowing/Reading Fuse

DD

10095-034

AD5292-EP Data Sheet

A

T

T

T

35

VWB, CODE: F ULL SCALE,
NORMAL MODE

30

25

20

15

VO LTAG E (V )

10

SYNC

5

0

–5

–2

–1

VWB, CODE: F ULL SCAL E,
R-PERF MODE

012345678

TIME (µs)

VDD/VSS = 30V/0V

= 5V

V

LOGIC

= V

V

A

DD

VB = V

SS

VWB, CODE: HALF-SCAL E,
NORMAL MODE

V

, CODE: HAL F-SCALE ,

WB

R-PERF MODE

9

1011121314

Figure 24. Large-Signal Settling Time from Code Zero Scale

15

10095-033

40

32

24

16

8

0

AGE (μV)

–8

VOL

–16

–24

–32

–40

–0.5 0 5 10 15 20 25 30 35 40 45

TIME (µs)

VDD/VSS = ±15V
V

= V

A

DD

VB= V

SS

CODE = HALF CO DE

Figure 27. Digital Feedthrough

10095-032

8

7

6

(mA)

5

WB_MAX

4

L I

3

2

THEORETIC

1

0

0 256 512 768 1023

CODE (Decimal)

VDD/VSS = 30V/0V
V

= V

A

DD

VB = V

SS

Figure 25. Theoretical Maximum Current vs. Code

1.2

1.0

0.8

0.6

0.4

0.2

0

VOLTAGE (V)

–0.2

–0.4

–0.6

–0.8

–2 0 2 4 6 8 10 12 14 16

TIME (µs)

VDD/VSS = ±15V
V

LOGIC

V

= V

A

VB = V

Figure 26. Maximum Transition Glitch

= +5V

DD
SS

6

5

4

3

AGE (V)

2

VOL

1

0

–1

10095-029

Figure 28. V

8

6

3

AGE (V)

2

VOL

0

–2

10095-035

–1.0

–0.4

EXT_CAP

–2.0

–0.8

Figure 29. V

0.2

0.8

1.4

2.0

2.6

3.2

3.8

4.4

TIME (ms)

Waveform While Reading Fuse Or Calibration

0.4

1.6

2.8

4.0

5.2

6.4

7.6

8.8

TIME (ms)

Waveform While Writing Fuse

EXT_CAP

5.0

10.0

11.2

VDD/VSS = ±15V
V

LOGIC

5.6

6.2

6.8

VDD/VSS = ±15V
V

LOGIC

12.4

13.6

= +5V

7.4

= +5V

14.8

8.0

8.6

10095-036

16.0

17.2

10095-037

Rev. 0 | Page 12 of 16

Data Sheet AD5292-EP

300

VDD/VSS= ±15V

250

200

80

70

60

50

VA = V

DD

VB = V

SS

TEMPERATURE = 25°C

150

100

NUMBER OF CO DES

50

0

–40–30–20–100 102030405060708090100

TEMPERATURE (° C)

Figure 30. Code Range > 1% R-Tolerance Error vs. Temperature

40

30

NUMBER OF CO DES

20

10

0

10095-056

21 26 30 33

VO LTAG E V

DD/VSS

10095-219

Figure 31. Code Range > 1% R-Tolerance Error vs. Voltage

Rev. 0 | Page 13 of 16

AD5292-EP Data Sheet

V

V

V

–

TEST CIRCUITS

Figure 32 to Figure 37 define the test conditions used in the Specifications section.

NC

DUT

A

W

B

NC = NO CONNE CT

Figure 32. Resistor Position Nonlinearity Error

(Rheostat Operation; R-INL, R-DNL)

DUT

A

V+

W

B

Figure 33. Potentiometer Divider Nonlinearity Error

(INL, DNL)

I

W

V

MS

+ = V

1LSB = V+/2

V

A

V

A

DD

V+

~

10095-041

W

B

V

MS

V+ = V

± 10%

DD

PSRR (dB) = 20 log

∆V

PSS (%/%) =

∆V

MS

DD

∆V

MS

∆V

DD

%
%

10095-044

Figure 35. Power Supply Sensitivity (PSS, PSRR)

+15

OP42

–15V

V

OUT

10095-047

DD

N

MS

10095-042

OFFSET

GND

V

IN

DUT

2.5V

A

W

B

Figure 36. Gain vs. Frequency

+15V

NC

15V

GND

DUT

A

B

A = NC

W

CODE = 0x00

I

WB

V

SS

TO V

Figure 34. Wiper Resistance

0.1V

RWB=

I

WB

R

WB

RW =

+

DD

2

0.1V

–

10095-043

V

DD

DUT

V

SS

NC

GND

+15V

A

B

W

–15V

GND

I

CM

GND

GND

NC = NO CONNECT

+15V

–15V

10095-048

Figure 37. Common-Mode Leakage Current

Rev. 0 | Page 14 of 16

AD5292-EP Data Sheet

OUTLINE DIMENSIONS

5.10

5.00

4.90

4.50

4.40

4.30

PIN 1

1.05

1.00

0.80

0.15

0.05

COPLANARITY

0.10

14

1

0.65 BSC

0.30

0.19

COMPLIANT TO JEDEC STANDARDS MO-153-AB-1

8

6.40
BSC

7

1.20

0.20

MAX

SEATING
PLANE

0.09

8°
0°

0.75

0.60

0.45

061908-A

Figure 38. 14-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-14)

Dimensions shown in millimeters

ORDERING GUIDE

Model RAB (kΩ) Resolution Memory Temperature Range Package Description Package Option

AD5292SRU-20-EP 20 1024 20-TP −55°C to +125°C 14-Lead TSSOP RU-14

Rev. 0 | Page 15 of 16

AD5292-EP Data Sheet

NOTES

©2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D10095-0-9/11(0)

Rev. 0 | Page 16 of 16