Analog Devices AD5290 pre Datasheet

Compact +30V/±15V 256-Position Digital

Preliminary Technical Data

FEATURES

256-position
+4.5V to +30V Single Supply Operation
±4.5V to ±15V Dual Supply Operation
End-to-end resistance 10 kΩ, 50 kΩ, 100 kΩ
Low temperature coefficient 35 ppm/°C
Power-on preset to midscale
SPI compatible interface
Automotive temperature range –40°C
Compact MSOP-10 (3 mm × 4.9 mm) package

iCMOS™ Process Technology

APPLICATIONS
Programmable Gain and Offset
Programmable Power Supply
Industrial Actuator Control
LED Array Driver
Audio Volume Control
General Purpose DAC Replacement
Mechanical Potentiometer Replacement

to +125°C

The AD5290 is available in 10k, 50k, and 100kΩ in compact
MSOP-10 package. AD5290 can be operated from a single
supply +30 V or dual supply ±15 V. All parts are guaranteed to
operate over the automotive temperature range of -40°C to
+125°C.

FUNCTIONAL BLOCK DIAGRAM

Q

SDO

SDO

SDI

SDI

CLK

CLK

CS

CS

Q

8-Bit

8-Bit

SERIAL

SERIAL

REG

REG

D

D

CK

CK

88

88

Potentiometer

AD5290

AD5290

AD5290

8-Bit

8-Bit

LATCH

LATCH

RS

RS

POR

POR

GENERAL OVERVIEW

DGND

The AD5290 is a low cost, compact 2.9 mm × 3 mm
+30V/±15V, 256-position digital potentiometer. This device
performs the same electronic adjustment function as
mechanical potentiometers or variable resistors, with enhanced
resolution, solid-state reliability, and superior low temperature
coefficient performance.

The wiper settings are controllable through an SPI compatible
digital interface. The resistance between the wiper and either
end point of the fixed resistor varies linearly with respect to the
digital code transferred into the RDAC latch.

iCMOS™ Process Technology
For analog systems designers within industrial/instrumentation equipment OEMs who need high performance ICs at higher-voltage levels, iCMOS is a
technology platform that enables the development of analog ICs capable of 30V and operating at +/-15V supplies while allowing dramatic reductions in
power consumption and package size, and increased AC and DC performance.

Note:
The terms digital potentiometer and RDAC are used interchangeably.

Figure 1.

DGND

V

V

DD

DD

A

A

W

W

B

B

V

V

SS

SS

Rev. PrE

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Preliminary Technical Data AD5290

ELECTRICAL CHARACTERISTICS—10 kΩ, 50 kΩ, 100 kΩ VERSIONS

(VDD/VSS = ±15V±10% or ±5V±10%, VA = +VDD, VB = VSS/0V, -40°C < TA < +125°C unless otherwise noted)

Table 1.

Parameter Symbol Conditions Min Typ1 Max Unit

DC CHARACTERISTICS—RHEOSTAT MODE
Resistor Differential Nonlinearity2 R-DNL RWB, V
Resistor Integral Nonlinearity2 R-INL RWB, V
Nominal Resistor Tolerance3 ∆RAB T
Resistance Temperature Coefficient (∆RAB/RAB)/∆T*106

Wiper Resistance RW V
V
DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE
Resolution N 8 Bits
Differential Nonlinearity4 DNL –1 ±0.1 +1 LSB
Integral Nonlinearity4 INL –1 ±0.3 +1 LSB
Voltage Divider Temperature Coefficient (∆VW/VW)/∆T*106 Code = 0x80 5 ppm/°C
Full-Scale Error V
Zero-Scale Error V

Code = 0xFF –3 –1 0 LSB

WFSE

Code = 0x00 0 1 3 LSB

WZSE

RESISTOR TERMINALS
Voltage Range5 V
Capacitance6 A, B C

V

A,B,W

A,B

Capacitance6 W CW

Common-Mode Leakage ICM V
DIGITAL INPUTS AND OUTPUTS
Input Logic High VIH

Input Logic Low VIL
Output Logic High VOH
Output Logic Low VOL

Input Current II V
Input Capacitance CI 5 pF
POWER SUPPLIES
Power Supply Range

V

/V

SS

DD

Power Supply Range VDD

Supply Current6 IDD

Supply Current IDD

Supply Current ISS

Power Dissipation7 P

DISS

Power Supply Sensitivity PSS

DYNAMIC CHARACTERISTICS

6, 8

Bandwidth –3dB BW

= no connect –1 ±0.1 +1 LSB

A

= no connect –2 ±0.25 +2 LSB

A

= 25°C –30 +30 %

A

V

= VDD,

AB

35 ppm/°C

Wiper = no connect

= ±15 V 60 150 Ω

DD

= ±4.5 V 240 450 Ω

DD

VDD V

SS

f = 1 MHz, measured to

45 pF

GND, Code = 0x80
f = 1 MHz, measured to

60 pF

GND, Code = 0x80

= VB = VW 1 nA

A

V

= +5V or +15V

DD

V

= +5V or +15V

DD

= 2.2 kΩ to +5 V

R

L

IOL = 1.6mA, V

LOGIC

= +5V,

2.4 V

0.8 V

4.9 V

0.4 V

VDD = +15V

= 0 V or +15 V ±1 µA

IN

Dual Supply Range ±4.5 ±16.5 V

+4.5 +30 V

Single Supply Range, V

=

SS

0 V
V

= 5 V or VIL = 0 V, VDD =

IH

0.1 10 µA
+5 V
V

= 5 V or VIL = 0 V, VDD =

IH

0.75 2 mA
+15 V
V

= 5 V or VIL = 0 V, VSS = -

IH

0.02 0.1 mA
5 V or –15 V

= 5 V or VIL = 0 V, VDD =

V

IH

+15 V, V

∆V
∆V

= -15 V

SS

= +15V ±10%, or

DD

= -15V ±10%, Code =

SS

11 30 mW

±0.01 ±0.02 %/%

Midscale

= 10 kΩ/50 kΩ/100 kΩ,

R

AB

525/125/60 kHz

Code = 0x80

Rev. Pr E | Page 2 of 11

Preliminary Technical Data AD5290

Total Harmonic Distortion THDW

VW Settling Time (10 kΩ/50 kΩ/100 kΩ) tS

Resistor Noise Voltage Density e

N_WB

=1 V rms, VB = 0 V,

V

A

f = 1 kHz, R

= 5 V, VB = 0 V,

V

A

= 10 kΩ

AB

±1 LSB error band

R

= 25 kΩ 14 nV/√Hz

WB

0.005 %

4 µs

Rev. Pr E | Page 3 of 11

Preliminary Technical Data AD5290

TIMING CHARACTERISTICS— 10 kΩ, 50 kΩ, 100 kΩ VERSIONS

(VDD/VSS = ±15V±10% or ±5V±10%, VA = +VDD, VB = 0V, -40°C < TA < +125°C unless otherwise noted.)

Table 2.

Parameter Symbol Conditions Min Typ1 Max Unit

SPI INTERFACE TIMING CHARACTERISTICS
Clock Frequency f
Input Clock Pulsewidth tCH, tCL Clock level high or low 120 ns
Data Setup Time tDS 30 ns
Data Hold Time tDH 20 ns
CLK to SDO Propagation Delay tPD

CS Setup Time
CS High Pulsewidth
CLK Fall to CS Fall Hold Time
CLK Fall to CS Rise Hold Time
CS Rise to Clock Rise Setup

NOTES

1. Typical specifications represent average readings at +25°C and V

2. Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper

positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.

3. V

= VDD, Wiper (VW) = no connect.

AB

4. INL and DNL are measured at V

5. Resistor terminals A, B, W have no limitations on polarity with respect to each other.

6. Guaranteed by design and not subject to production test.

7. P

8. All dynamic characteristics use V

9. See timing diagram for location of measured values. All input control voltages are specified with t

is calculated from (IDD × VDD+ ISS × VSS) CMOS logic level inputs result in minimum power dissipation.

DISS

of 1.5 V.

with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA=VDD and VB=0 V.

W

/ VSS = ±15 V.

DD

6, 8,9

(Specifications Apply to All Parts)

CLK

R

= 1KΩ, CL < 20pF

PU

t

120 ns

CSS

t

150 ns

CSW

t

TBD ns

CSH0

t

120 ns

CSH1

t

120 ns

CS1

= ±15 V.

DD/VSS

10 100 ns

= tF = 2 ns (10% to 90% of 3 V) and timed from a voltage level

R

4 MHz

Rev. Pr E | Page 4 of 11