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Compact +30 V / ±15 V 256-Position
FEATURES
256 position
10 kΩ, 50 kΩ, 100 kΩ
+4.5 V to +30 V single-supply operation
±4.5 V to ±15 V dual-supply operation
3-wire SPI®-compatible serial interface
Low temperature coefficient 35 ppm/
THD 0.006% typical
Midscale preset
Compact MSOP-10 package
Automotive temperature range: −40oC to +125oC
1
iCMOS™
process technology
APPLICATIONS
High voltage DAC
Programmable power supply
Programmable gain and offset adjustment
Programmable filters and delays
Actuator control
Audio volume control
Mechanical potentiometer replacement
GENERAL DESCRIPTION
o
C typical
Digital Potentiometer
AD5290
FUNCTIONAL BLOCK DIAGRAM
AD5290
SDO
SDI
CLK
CS
Q
8-BIT
SERIAL
REGISTER
D
CK
8 8
8-BIT
LATCH
RS
POR
Figure 1.
DGND
V
DD
A
W
B
V
SS
04716-001
The AD5290 is one of the few high voltage, high performance,
2, 3
and compact digital potentiometers
in the market at present.
This device can be used as a programmable resistor or resistor
divider. The AD5290 performs the same electronic adjustment
function as mechanical potentiometers, variable resistors, and
trimmers, with enhanced resolution, solid-state reliability, and
superior temperature stability.
With digital rather than manual control, the AD5290 provides
la
yout flexibility and allows closed-loop dynamic controllability.
The AD5290 is available in MSOP-10 package and has 10 kΩ,
50 kΩ, a
nd 100 kΩ options. All parts are guaranteed to operate
over the –40°C to +125°C extended automotive temperature range.
1
iCMOS™ Process Technology. For analog systems designers who need high performance ICs at higher voltage levels, iCMOS is a technology platform that enables the
development of analog ICs capable of 30 V and operating at ±15 V supplies while allowing dramatic reductions in power consumption and package size, and
increased ac and dc performance.
2
The terms digital potentiometer and RDAC are used interchangeably.
3
The RDAC segmentation is protected by U.S. Patent Number 5,495,245.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved.
AD5290
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TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Electrical Characteristics—10 kΩ Version................................ 3
Electrical Characteristics—50 kΩ, 100 kΩ Versions............... 5
Interface Timing Characteristics................................................ 7
3-Wire Digital Interface................................................................... 8
Absolute Maximum Ratings............................................................ 9
ESD Caution.................................................................................. 9
Pin Configuration and Descriptions............................................ 10
Typical Performance Characteristics ........................................... 11
Theory of Operation ...................................................................... 15
Programming the Variable Resistor......................................... 15
Programming the Potentiometer Divider............................... 16
3-Wire Serial Bus Digital Interface .......................................... 16
Daisy Chain Operation.............................................................. 16
ESD Protection ........................................................................... 17
Terminal Voltage Operating Range ......................................... 17
Power-Up and Power-Down Sequences.................................. 17
Layout and Power Supply Biasing ............................................ 17
Applications..................................................................................... 18
High Voltage DAC...................................................................... 18
Programmable Power Supply ................................................... 18
Audio Volume Control .............................................................. 18
Outline Dimensions ....................................................................... 20
Ordering Guide .......................................................................... 20
REVISION HISTORY
12/05—Revision 0: Initial Version
Rev. 0 | Page 2 of 20
AD5290
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SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—10 kΩ VERSION
VDD/VSS = ±15 V ± 10%, VA = VDD, VB = VB
Table 1.
Parameter Symbol Conditions Min Typ1Max Unit
DC CHARACTERISTICS RHEOSTAT MODE
Resistor Differential NL
Resistor Nonlinearity
2
2
Nominal Resistor Tolerance R
Resistance Temperature Coefficient
Wiper Resistance R
DC CHARACTERISTICS POTENTIOMETER
DIVIDER MODE
Integral Nonlinearity
Differential Nonlinearity
4
4
Voltage Divider Temperature Coefficient (VW/VW)/T*106Code = 0x80 5 ppm/°C
Full-Scale Error V
Zero-Scale Error V
RESISTOR TERMINALS
Voltage Range
5
Capacitance6 A, B C
Capacitance
6
Common-Mode Leakage I
DIGITAL INPUTS AND OUTPUTS
Input Logic High (CS, CLK, SDI)
Input Logic Low (CS, CLK, SDI)
Output Logic High (SDO) V
Output Logic Low (SDO) V
Input Current I
Input Capacitance
6
POWER SUPPLIES
Positive Supply Current I
Negative Supply Current I
Power Dissipation
7
Power Supply Rejection Ratio PSRR ∆VDD/∆VSS = ±15 V ± 10% −0.15 ±0.08 +0.15 %/%
or 0 V, −40°C < TA < +125°C, unless otherwise noted.
SS
R-DNL RWB, VA = NC −1 ±0.3 +1 LSB
R-INL RWB, VA = NC −1.5 ±0.7 +1.5 LSB
3
AB
(RAB/RAB)/T*106V
W
TA = +25°C −30 +30 %
= VDD, wiper = no connect 35 ppm/°C
AB
50 100 Ω
INL −1 ±0.3 +1 LSB
DNL −1 ±0.3 +1 LSB
Code = 0xFF −6 −4 0 LSB
Code = 0x00 0 +3 +5 LSB
V
f = 1 MHz, measured to GND,
V
WFSE
WZSE
A, B, W
A, B
code = 0x80
C
W
f = 1 MHz, measured to GND,
code = 0x80
CM
V
IH
V
IL
OH
OL
IL
C
IL
DD
SS
P
DISS
VA = VB = V
W
2.4 V
0.8 V
R
= 2.2 kΩ to 5 V 4.9 V
Pull-up
IOL = 1.6 mA 0.4 V
VIN = 0 V or 5 V ±1 µA
5 pF
VIH = +5 V or VIL = 0 V,
V
= ±15 V
DD/VSS
VIH = +5 V or VIL = 0 V,
= ±15 V
V
DD/VSS
VIH = +5 V or VIL = 0 V,
V
= ±15 V
DD/VSS
VDDV
SS
45 pF
60 pF
1 nA
15 50 A
−0.01 −1 A
765 W
Rev. 0 | Page 3 of 20
AD5290
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Parameter Symbol Conditions Min Typ1Max Unit
DYNAMIC CHARACTERISTICS
Bandwidth −3 dB BW Code = 0x80 470 kHz
Total Harmonic Distortion THD
VW Settling Time t
Resistor Noise Voltage e
1
Typical represents average reading at +25°C, VDD = +15 V, and VSS = −15 V.
2
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from an ideal value measured between successive tap positions. Parts are guaranteed monotonic.
3
All parts have a 35 ppm/°C temperature coefficient.
4
INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits
of ±1 LSB maximum are guaranteed monotonic operating conditions.
5
Resistor Terminal A, Terminal B, and Terminal W have no limitations on polarity with respect to each other.
6
Guaranteed by design and not subject to production test.
7
P
is calculated from (IDD × VDD) + abs (ISS × VSS). CMOS logic-level inputs result in minimum power dissipation.
DISS
8
Bandwidth, noise, and settling times are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest
bandwidth. The highest R value results in the minimum overall power consumption.
9
All dynamic characteristics use VDD = +15 V and VSS = −15 V.
6, , 8 9
W
S
VA = 1 V rms, VB = 0 V, f = 1 kHz 0.006 %
VA = 10 V, VB = 0 V, ±1 LSB error
B
4 µs
band
N_WB
RWB = 5 kΩ, f = 1 kHz 9 nV/√Hz
Rev. 0 | Page 4 of 20
AD5290
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ELECTRICAL CHARACTERISTICS—50 KΩ, 100 KΩ VERSIONS
VDD/VSS = ±15 V ± 10%, VA = +VDD, VB = VB
Table 2.
Parameter Symbol Conditions Min Typ1Max Unit
DC CHARACTERISTICS RHEOSTAT MODE
Resistor Differential NL
Resistor Nonlinearity
2
2
Nominal Resistor Tolerance R
Resistance Temperature Coefficient
Wiper Resistance R
DC CHARACTERISTICS POTENTIOMETER
DIVIDER MODE
Integral Nonlinearity
Differential Nonlinearity
4
4
Voltage Divider Temperature
Coefficient
Full-Scale Error V
Zero-Scale Error V
RESISTOR TERMINALS
Voltage Range
5
Capacitance6 A, B C
Capacitance
6
Common-Mode Leakage I
DIGITAL INPUTS AND OUTPUTS
Input Logic High (CS, CLK, SDI)
Input Logic Low (CS, CLK, SDI)
Output Logic High (SDO) V
Output Logic Low (SDO) V
Input Current I
Input Capacitance
6
POWER SUPPLIES
Positive Supply Current I
Negative Supply Current I
Power Dissipation
7
Power Supply Rejection Ratio PSRR ∆VDD/∆VSS = ±15 V ± 10% −0.05 ±0.01 +0.05 %/%
or 0 V, −40°C < TA < +125°C, unless otherwise noted.
SS
R-DNL RWB, VA = NC −0.5 ±0.1 +0.5 LSB
R-INL RWB, VA = NC −1 ±0.5 +1 LSB
3
AB
(RAB/RAB)/T*106VAB = VDD, wiper = no connect 35 ppm/°C
W
TA = +25°C −30 +30 %
50 100 Ω
INL −1 ±0.5 +1 LSB
DNL −1 ±0.5 +1 LSB
(V
V
)/T*106Code = 0x80 5 ppm/°C
W/VW
WFSE
WZSE
A, B, W
A, B
Code = 0xFF −2.5 −1.6 0 LSB
Code = 0x00 0 +0.6 +1.5 LSB
V
f = 1 MHz, measured to GND,
SS
45 pF
VDDV
code = 0x80
C
W
f = 1 MHz, measured to GND,
60 pF
code = 0x80
CM
V
IH
V
IL
OH
OL
IL
C
IL
DD
SS
P
DISS
VA = VB = V
W
2.4 V
0.8 V
R
= 2.2 kΩ to 5 V 4.9 V
Pull-up
IOL = 1.6 mA 0.4 V
VIN = 0 V or 5 V ±1 µA
5 pF
VIH = +5 V or VIL = 0 V,
= ±15 V
V
DD/VSS
VIH = +5 V or VIL = 0 V,
V
= ±15 V
DD/VSS
VIH = +5 V or VIL = 0 V,
= ±15 V
V
DD/VSS
1 nA
15 50 A
−0.01 −1 A
765 W
Rev. 0 | Page 5 of 20
AD5290
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Parameter Symbol Conditions Min Typ1Max Unit
DYNAMIC CHARACTERISTICS
Bandwidth −3 dB BW RAB = 50 kΩ, code = 0x80 90 kHz
R
Total Harmonic Distortion THD
VW Settling Time t
Resistor Noise Voltage e
1
Typical represents average reading at +25°C, VDD = +15 V, and VSS = −15 V.
2
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from an ideal value measured between successive tap positions. Parts are guaranteed monotonic.
3
All parts have a 35 ppm/°C temperature coefficient.
4
INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification
limits of ±1 LSB maximum are guaranteed monotonic operating conditions.
5
Resistor Terminal A, Terminal B, and Terminal W have no limitations on polarity with respect to each other.
6
Guaranteed by design and not subject to production test.
7
P
is calculated from (IDD × VDD) + abs (ISS × VSS). CMOS logic level inputs result in minimum power dissipation.
DISS
8
Bandwidth, noise, and settling times are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest
bandwidth. The highest R value results in the minimum overall power consumption.
9
All dynamic characteristics use VDD = +15 V and VSS = −15 V.
6, , 8 9
= 100 kΩ, code = 0x80 50 kHz
AB
W
S
VA = 1 V rms, VB = 0 V, f = 1 kHz 0.002 %
VA = 10 V, VB = 0 V,
B
4 µs
±1 LSB error band
N_WB
RWB = 25 kΩ, f = 1 kHz 20
nV√Hz
Rev. 0 | Page 6 of 20
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INTERFACE TIMING CHARACTERISTICS
Table 3.
Parameter
Clock Frequency f
Input Clock Pulse Width tCH, t
Data Setup Time t
Data Hold Time t
CLK to SDO Propagation Delay
CS Setup Time
CS High Pulse Width
CLK Fall to CS Fall Hold Time
CLK Rise to CS Rise Hold Time
CS Rise to Clock Rise Setup
1
See Figure 3 for the location of the measured values. All input control voltages are specified with tR = tF = 1 ns (10% to 90% of VDD) and timed from a voltage level of
1.6 V. Switching characteristics are measured using V
2
Guaranteed by design and not subject to production test.
3
Propagation delay depends on the value of VDD, R
, 1 2
Symbol Conditions Min Typ Max Unit
CLK
CL
DS
3
DH
t
PD
t
CSS
t
CSW
t
CSH0
t
CSH
t
CS1
= +15 V and VSS = −15 V.
DD
, and CL.
Pull-up
Clock level high or low 120 ns
30 ns
20 ns
R
= 2.2 kΩ, CL < 20 pF 10
Pull-up
120 ns
150 ns
10 ns
120 ns
120 ns
4 MHz
100 ns
Rev. 0 | Page 7 of 20
AD5290
)
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3-WIRE DIGITAL INTERFACE
Data is loaded MSB first.
Table 4. AD5290 Serial Data-Word Format
B7 B6 B5 B4 B3 B2 B1 B0
D7 D6 D5 D4 D3 D2 D1 D0
MSB LSB
7
2
2
1
V
SDI
CLK
CS
OUT
D7 D6 D5 D4 D3 D2 D1 D0
0
1
0
1
0
1
0
RDAC REGISTER LOAD
Figure 2. AD5290 3-Wire Digital Interface Timing Diagram
= VDD, VB = 0 V, V
B
(V
A
= V
W
OUT
)
0
04716-002
(DATA IN)
SDO
(DATA OUT
CLK
V
OUT
SDI
CS
t
CSH0
V
1
0
1
0
1
0
1
0
DD
0V
D
X
D'
X
t
CH
t
CSS
D
X
t
DS
t
DH
D'
X
t
PD_MAX
t
CS1
t
CL
t
CSH
t
CSW
t
S
±1 LSB ERROR BAND
±1 LSB
04716-003
Figure 3. Detail Timing Diagram
Rev. 0 | Page 8 of 20
AD5290
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ABSOLUTE MAXIMUM RATINGS
TA = +25°C, unless otherwise noted.
Table 5.
Parameter Rating
VDD to GND −0.3 V, +35 V
VSS to GND +0.3 V, −16.5 V
VDD to V
SS
VA, VB, VW to GND VSS, V
Maximum Current
IWB, IWA Pulsed ±20 mA
IWB Continuous (RWB ≤ 6 kΩ, A Open, ±5 mA
VDD/VSS = 30 V/0 V)
IWA Continuous (RWA ≤ 6 kΩ, B Open, ±5 mA
VDD/VSS = 30 V/0 V)1
Digital Input and Output Voltages to GND 0 V, +7 V
Operating Temperature Range −40°C to +125°C
Maximum Junction Temperature (T
Storage Temperature −65°C to +150°C
Lead Temperature
(Soldering, 10 sec to 30 sec)
Thermal Resistance2 θJA: MSOP-10 230°C/W
1
The maximum terminal current is bound by the maximum current handling
of the switches, maximum power dissipation of the package, and the
maximum applied voltage across any two of the following at a given
resistance: A terminal, B terminal, and W terminal.
2
Package power dissipation = (T – T )/θ
1
JMAX A JA
JMAX
2
)
.
−0.3 V, +35 V
DD
+150°C
245°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page 9 of 20
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PIN CONFIGURATION AND DESCRIPTIONS
A
1
B
2
SS
CS
AD5290
3
TOP VIEW
(Not to Scale)
4
5
Table 6. AD5290 Pin Function Descriptions
Pin No. Mnemonic Description
1 A A Terminal. V ≤ V
2 B B Terminal. V ≤ V ≤ V .
3 V
SS
4 GND
5
CS
6 CLK
7 SDI
8 SDO
Negative Supply. Connect to 0 V for single-supply applications.
Digital Ground.
Chip Select Input; Active Low. When
Serial Clock Input. Positive edge triggered.
Serial Data Input Pin. Shifts in one bit at a time on positive clock CLK edges. MSB loaded first.
Serial Data Output Pin. Internal N-Ch FET with open-drain output that requires external pull-up resistor.
≤ V .
SS A
SS B DD
DD
It shifts out the previous eight SDI bits that allow daisy-chain operation of multiple packages.
9 V
DD
10 W W Terminal. V ≤ V ≤ V .
Positive Power Supply.
SS W DD
V
GND
Figure 4. AD5290 Pin Configuration
W
10
V
9
DD
SDO
8
7
SDI
6
CLK
04716-004
CS
returns high, data is loaded into the wiper register.
Rev. 0 | Page 10 of 20
AD5290
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TYPICAL PERFORMANCE CHARACTERISTICS
1.0
VDD = 16.5V
0.8
0.6
0.4
0.2
0
–0.2
–0.4
RHEOSTAT MODE INL (LSB)
–0.6
–0.8
–1.0
0
32 64 96 128 160 192 224
–40°C
+25°C
+125°C
CODE (Decimal)
04716-029
256
Figure 5. Resistance Step Position Nonlinearity Error vs. Code Figure 8. Potentiometer Divider Differential Nonlinearity Error vs. Code
1.0
VDD = 16.5V
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
POTENTIOMETER MODE DNL (LSB)
–0.8
–1.0
0
32 64 96 128 160 192 224
–40°C
+25°C
+125°C
CODE (Decimal)
256
04716-032
1.0
VDD = 16.5V
0.8
0.6
0.4
0.2
0
–0.2
–0.4
RHEOSTAT MODE DNL (LSB)
–0.6
–0.8
–1.0
0
32 64 96 128 160 192 224
–40°C
+25°C
+125°C
CODE (Decimal)
04716-030
256
Figure 6. Resistance Step Change Differential Nonlinearity Error vs. Code Figure 9. Supply Current I vs. Temperature
1.0
VDD = 16.5V
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
POTENTIOMETER MODE INL (LSB)
–0.8
–1.0
0
32 64 96 128 160 192 224
–40°C
+25°C
+125°C
CODE (Decimal)
256
04716-031
Figure 7. Potentiometer Divider Nonlinearity Error vs. Code
20
16
12
8
4
SUPPLY CURRENT (μA)
0
–4
–40
120
100
(kΩ)
AB
80
60
40
TOTAL RESISTANCE, R
20
0
–40
IDD @ VDD/VSS = 30V/0V
IDD @ VDD/VSS = ±15V
ISS @ VDD/VSS = 30V/0V
ISS @ VDD/VSS = ±15V
–20 0 20 40 60 80 100 120
–20 0 20 40 60 80 100 120
TEMPERATURE (°C)
DD
100kΩ
50kΩ
10kΩ
TEMPERATURE (°C)
VDD/VSS = ±15V
Figure 10. Total Resistance vs. Temperature
04716-005
04716-007
Rev. 0 | Page 11 of 20
AD5290
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100
80
C)
°
60
40
20
0
–20
–40
–60
RHEOSTAT MODE TEMPCO (ppm/
–80
–100
10k
50k
100k
0
32 64 96 128 160 192 224
Figure 11. (ΔR
CODE (Decimal)
)/ΔT Rheostat Mode Tempco
WB/RWB
256
04716-033
(dB)
0
0x80
–6
0x40
–12
0x20
–18
0x10
–24
0x08
–30
0x04
–36
0x02
–42
0x01
–48
–54
–60
1k
(Hz)
Figure 14. 50 kΩ Gain vs. Frequency vs. Code
04716-023
1M10k 100k
100
C)
80
°
60
40
20
0
–20
–40
–60
–80
POTENTIOMETER MODE TEMPCO (ppm/
–100
0
Figure 12. (ΔV
0
0x80
–6
0x40
–12
0x20
–18
0x10
–24
0x08
0x04
–30
(dB)
–36
0x02
–42
0x01
–48
–54
–60
1k
Figure 13. 10 kΩ Gain vs. Frequency vs. Code
10k
50k
100k
32 64 96 128 160 192 224
CODE (Decimal)
)/ΔT Potentiometer Mode Tempco
WB/VWB
(Hz)
256
1M10k 100k
04716-034
04716-022
(dB)
0
0x80
–6
0x40
–12
0x20
–18
0x10
–24
0x08
–30
0x04
–36
0x02
–42
0x01
–48
–54
–60
1k
(Hz)
Figure 15. 100 kΩ Gain vs. Frequency vs. Code
Figure 16. Midscale Transition Glitch
1M10k 100k
04716-024
04716-035
Rev. 0 | Page 12 of 20
AD5290
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–60
CODE = 80H, VDD/VSS =±15V, VA/VB =±10V
6
5
VDD/VSS = 30V/0V
V
= V
A
DD
VB = 0V
–40
+PSRR @ VDD/VSS =±15V DC± 10% p-p AC
–20
POWER SUPPLY REJECTION RATIO (dB)
–PSRR @ VDD/VSS =±15V DC± 10% p-p AC
0
100
Figure 17. Power Supply R
1
0.01
THD + N (%)
0.001
(mA)
4
WB_MAX
3
RAB = 50kΩ
RAB = 100kΩ
64 128 192
CODE (Decimal)
FREQUENCY (Hz)
2
THEORETICAL I
1
04716-036
1M1k 10k 100k
0
0
ejection vs. Frequency Figure 20. Theoretical Maximum Current vs. Code
A)
μ
(
DD
SUPPLY CURRENT I
140
120
100
80
60
40
20
VDD = +15V
= –15V
V
SS
V
= +5V
DIG
CODE = AA
100kΩ
VDD/VSS = ±15V
CODE = MIDSCALE
V
= 1V
IN
10kΩ
50kΩ
RMS
RAB = 10kΩ
CODE = FF
256
04716-027
0.0001
10
FREQUENCY (Hz)
Figure 18. Total Harmonic Distortion Plus Noise vs. Frequency
1
0.1
THD + N (%)
0.01
0.001
0.001
10kΩ
AMPLITUDE (V)
VDD/VSS = ±15V
CODE = MIDSCALE
f
= 1kHz
IN
Figure 19. Total Harmonic Distortion Plus Noise vs. Amplitude
50kΩ
100kΩ
04716-009
100k100 1k 10k
04716-010
100.01 0.1 1
(nA)
SS
SUPPLY CURRENT I
0
10k
Figure 21. Supply Current I
10
VDD = +15V
V
= –15V
SS
= +5V
V
DIG
8
6
4
2
0
10k
Figure 22. Supply Current I
FREQUENCY (Hz)
vs. Frequency
DD
FREQUENCY (Hz)
vs. Frequency
SS
CODE = AA
CODE = FF
04716-037
10M100k 1M
04716-038
10M100k 1M
Rev. 0 | Page 13 of 20
AD5290
www.BDTIC.com/ADI
1000
(μA)
DD
100
SUPPLY CURRENT I
10
0
Figure 23. Supply Current vs. Digital Input Voltage
Figure 24. Digital Feedthrough
VDD/VSS = ±16.5V
1234
DIGITAL INPUT VOLTAGE VIH (V)
5
04716-039
04716-040
04716-041
Figure 25. Large Signal Settling Time, Code = 0x00 to 0xFF
Rev. 0 | Page 14 of 20
AD5290
−
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THEORY OF OPERATION
PROGRAMMING THE VARIABLE RESISTOR
Rheostat Operation
The part operates in the rheostat mode when only two terminals are used as a variable resistor. The unused terminal can
be floating or tied to the W terminal as shown in
A
W
B
Figure 26. Rheostat Mode Configuration
A
W
B
The nom i na l res ist anc e be twe e n Te r mi n al A an d Ter m in a l B,
, is available in 10 kΩ, 50 kΩ, and 100 kΩ with ±30% toler-
R
AB
ance and has 256 tap points accessed by the wiper terminal.
The 8-bit data in the RDAC latch is decoded to select one of
the 256 possible settings.
st
ructure.
8-BIT ADDRESS
DECODER
Figure 27. AD5290 Simplified RDAC Circuit.
(R
S
Figure 27 shows a simplified RDAC
A
4R
S
4R
S
4R
S
4R
S
4R
S
B
= Step Resistor, Rw = Wiper Resistor)
2R
S
2R
S
R
W
2R
R
W
S
2R
S
In order to achieve optimum cost performance, Analog Devices
has patented the RDAC segmentation architecture for all the
digital potentiometers. In particular, the AD5290 employs a
3-stage segmentation approach as shown in
esult, the general equation determining the digitally
a r
programmed output resistance between the W terminal
and B terminal is
WB
256
D
DR ×+×= 3
)( (1)
RR
AB
W
Figure 26.
A
W
B
R
W
R
S
R
S
Figure 27. As
04716-011
W
04716-012
where:
D is the decimal equivalent of the binary code loaded in
the 8-bit RDAC register from 0 to 255.
R
is the end-to-end resistance.
AB
R
is one of the wiper resistances contributed by the on
W
resistance of an internal switch.
The AD5290 wiper switch is designed with the transmission
gate CMOS topology and with the gate voltage derived from
. The wiper resistance, RW, is a function of VDD and
V
DD
temperature. Contrary to the temperature coefficient of the R
AB
which is only 35 ppm/°C, the temperature coefficient of the wiper
resistance is significantly higher because the wiper resistance
doubles from 25°C to 125°C. As a result, the user must take into
consideration the contribution of RW on the desirable
resistance. On the other hand, the wiper resistance is insensitive
to the tap point potential. As a result, RW remains relatively flat
at a given V
and temperature at various codes.
DD
Assuming that an ideal 10 kΩ part is used, the wiper’s first
connection starts at the B terminal for the programming code
of 0x00 where SWB is closed. The minimum resistance between
Terminal W and Terminal B is, therefore, generally 150 Ω. The
second connection is the first tap point, which corresponds to
R
189 Ω (
= 1/256 × R
WB AB
+ 3RW = 39 Ω + 150 Ω) for code 0x01,
and so on. Each LSB data value increase moves the wiper up the
resistor ladder until the last tap point is reached at 10,110 Ω.
In the zero-scale condition, a finite total wiper resistance of
150 Ω is p
resent. Regardless of which setting the part is operating in, care should be taken to limit the current between
the A terminal to B terminal, W terminal to A terminal, and
W terminal to B terminal, to the maximum dc current of 5 mA
or pulse current of 20 mA. Otherwise, degradation, or possible
destruction of the internal switch contact, can occur.
Similar to the mechanical potentiometer, the resistance of
he RDAC between the W terminal and the A terminal also
t
produces a digitally controlled complementary resistance, R
R
starts at the maximum resistance value and decreases as
WA
.
WA
the data loaded into the latch increases. The general equation
for this operation is
D
256
DR ×+×
= 3
)(
256
RR
(2)
ABWA
W
,
Rev. 0 | Page 15 of 20
AD5290
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PROGRAMMING THE POTENTIOMETER DIVIDER 3-WIRE SERIAL BUS DIGITAL INTERFACE
Voltage Output Operation
The digital potentiometer easily generates a voltage divider
at wiper to B and wiper to A proportional to the input voltage
at A to B. Unlike the polarity of V
to GND, which must be
DD
positive, voltage across A to B, W to A, and W to B can be at
either polarity.
V
I
A
W
V
O
B
04716-013
Figure 28. Potentiometer Mode Configuration
The AD5290 contains a 3-wire digital interface (CS, CLK,
and SDI). The 8-bit serial word must be loaded MSB first.
The format of the word is shown in
Tabl e 4. The positive edge
sensitive CLK input requires clean transitions to avoid clocking
incorrect data into the serial input register. Standard logic fami-
CS
lies work well. When
is low, the clock loads data into the
serial register on each positive clock edge.
The data setup and data hold times in the Specifications section
ermine the valid timing requirements. The AD5290 uses an
det
8-bit serial input data register word that is transferred to the
CS
internal RDAC register when the
line returns to logic high.
Extra MSB bits are ignored.
If ignoring the effect of the wiper resistance for simplicity, connecting the A terminal to 30 V and the B terminal to ground
produces an output voltage at the Wiper W to Terminal B
ranging from 0 V to 1 LSB less than 30 V. Each LSB of voltage
is equal to the voltage applied across Terminal A and Terminal B,
divided by the 256 positions of the potentiometer divider. The
general equation defining the output voltage at V
with respect
W
to ground for any valid input voltage applied to Terminal A and
Terminal B is
D
256
V
A
DV ×
)( (3)
W
D
−
256
+×=
256
V
B
Operation of the digital potentiometer in the divider mode
sults in a more accurate operation over temperature. Unlike
re
the rheostat mode, the output voltage is dependent mainly on
the ratio of the internal resistors R
and R
WA WB
and not the
absolute values. Therefore, the temperature drift reduces to
5 ppm/°C.
DAISY CHAIN OPERATION
SDO shifts out the SDI content in the previous frame; thus it
can be used for daisy-chaining multiple devices. The SDO pin
contains an open drain N-Ch MOSFET and requires a pullup resistor if the SDO function is used. Users need to tie the
SDO pin of one package to the SDI pin of the next package.
Users may need to increase the clock period because the pull-up
resistor and the capacitive loading at the SDO to SDI interface
can induce time delay to the subsequent devices.
For example, in Figure 29, if two AD5290s are daisy-chained, a
t
otal of 16 bits of data are required for each operation. The first
set of eight bits goes to U2, and the second set of eight bits goes
CS
to U1. The
into their respective serial registers. The
to complete the operation.
μC
MOSI
should be kept low until all 16 bits are clocked
is then pulled high
CS
V
DD
AD5290
U1
SDOSDI
SSSCLK
CLKCS
R
PU
2.2kΩ
AD5290
SDI
CS
U2
SDO
CLK
Figure 29. Daisy Chain Configuration
Rev. 0 | Page 16 of 20
04716-014
AD5290
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ESD PROTECTION
All digital inputs are protected with a series input resistor and
ener ESD structure, as shown in Figure 30. These structures
a Z
GND
340Ω
CS
, Pin CLK, Pin SDI, and
LOGIC
04716-015
a
pply to digital input pins, Pin
DO.
Pin S
Figure 30. Equivalent ESD Protection Circuit
All analog terminals are also protected by Zener ESD protection
diodes, as shown in Figure 31.
V
DD
A
W
B
V
04716-016
SS
Figure 31. Equivalent ESD Protection Analog Pins
TERMINAL VOLTAGE OPERATING RANGE
The AD5290 VDD and VSS power supplies define the boundary
conditions for proper 3-terminal digital potentiometer operation. The AD5290 can operate in single supply from +4.5 V to
+33 V or dual supply from ±4.5 V to ±16.5 V. The AD5290 is
functional at low supply voltages such as 4.5 V, but the
performance parameters are not guaranteed.
The voltages present on Terminal A, Terminal B, and Terminal W
at are more positive than V
th
clamped by the internal forward-biased diodes (Figure 31).
or more negative than VSS are
DD
POWER-UP AND POWER-DOWN SEQUENCES
Because of the ESD protection diodes that limit the voltage
compliance at Terminal A, Terminal B, and Terminal W
Figure 31), it is important to power V
(
before applying
DD/VSS
any voltage to Terminal A, Terminal B, and Terminal W.
/V
Otherwise, the diodes are forward-biased such that V
DD SS
are powered unintentionally and affect the system. Similarly,
should be powered down last. The ideal power-up
V
DD/VSS
sequence is as follows: GND, V
/V
B
V /V
A
. The order of powering V , V
B
W
, VSS, digital inputs, and
DD
B, V
A B
, and the digital
W
inputs is not important, as long as they are powered after
.
V
DD/VSS
LAYOUT AND POWER SUPPLY BIASING
It is good practice to use a compact, minimum lead-length
layout design. The leads to the input should be as direct as
possible, with a minimum conductor length. Ground paths
should have low resistance and low inductance.
Similarly, it is also good practice to bypass the power supplies
th quality capacitors. Low equivalent series resistance (ESR),
wi
1 μF to 10 μF tantalum or electrolytic capacitors, should be
applied at the supplies to minimize any transient disturbance
and to filter low frequency ripple. Figure 32 illustrates the basic
upply-bypassing configuration for the AD5290.
s
The ground pin of the AD5290 is a digital ground reference.
o minimize the digital ground bounce, the AD5290 digital
T
ground terminal should be joined remotely to the analog
ground (Figure 32).
V
DD
+
C1
C3
10μF
0.1μF
+
C4
C2
10μF
V
SS
0.1μF
V
DD
AD5290
V
SS
GND
Figure 32. Power Supply Bypassing
Rev. 0 | Page 17 of 20
04716-017
AD5290
A
www.BDTIC.com/ADI
APPLICATIONS
HIGH VOLTAGE DAC AUDIO VOLUME CONTROL
AD5290 can be configured as a high voltage DAC, with output voltage as high as 30 V. The circuit is shown in Figure 33.
The o
utput is
RD
2
(4)
DV
O
where D is t
V
DD
R
BIAS
DR512
)(
256
he decimal code from 0 to 255.
V
DD
U1A
D1
V+
AD8512
V–
R2
R1
+××=
)]1(V2.1[
R
1
U2
AD5290
B
100kΩ
U1B
AD8512
V
OUT
Figure 33. High Voltage DAC
PROGRAMMABLE POWER SUPPLY
With a boost regulator, such as ADP1611, AD5290 can be used
as the variable resistor at the regulator’s FB pin to provide the
programmable power supply (Figure 34). The output is
D
)(
−
R
256
AB
(5)
1[V23.1
V
O
AD5290’s V
DD
a short, and V
+×=
is derived from the output. Initially, L1 acts as
is one diode voltage drop below +5 V. The
DD
output slowly establishes the final value.
]
R
2
04716-018
Because of its good THD performance and high voltage
ca
pability, AD5290 can be used as a digital volume control.
If AD5290 is used directly as an audio attenuator or gain
amplifier, a large step change in the volume level at any arbitrary time can lead to an abrupt discontinuity of the audio
signal causing an audible zipper noise. To prevent this, a zerocrossing window detector can be inserted to the
delay the device update until the audio signal crosses the
window. Since the input signal can operate on top of any
dc level rather than absolute zero volt level, zero-crossing in this
case means the signal is ac-coupled, and the dc offset level is the
signal zero reference point.
results of using this configuration are shown in Figure 36. The
i
nput is ac-coupled by C1 and attenuated down before feeding
into the window comparator formed by U
is used to establish the signal zero reference. The upper limit
U
6
of the comparator is set above its offset and, therefore, the
output pulses high whenever the input falls between 2.502 V
and 2.497 V (or 0.005 V window) in this example. This output
is AND’ed with the chip select signal such that the AD5290
updates whenever the signal crosses the window. To avoid a
constant update of the device, the chip select signal should be
programmed as two pulses, rather than as one shown in Figure 36.
In Figure 35, the lower trace shows that the volume level changes
f
rom a quarter-scale to full-scale when a signal change occurs
near the zero-crossing window.
line to
CS
Figure 35The configuration to reduce zipper noise ( ) and the
, U3, and U4B (Figure 35).
2
0.1μF
U1
AD5290
V
DD
C1
R1
100kΩ
R2
8.5kΩ
A
W
B
5V
C
10μF
1.23V
22nF
IN
C
SS
U2
ADP1611
RT
FB
SS
GND
IN
SW
COMP
L1
4.7μH
D1
R
C
220kΩ
C
C
150pF
C
OUT
10μF
V
OUT
04716-019
Figure 34. Programmable Power Supply
Rev. 0 | Page 18 of 20
AD5290
V
www.BDTIC.com/ADI
C1
IN
100kΩ
200Ω
5V
R1
R2
R3
100kΩ
+5V
U2
V+
ADCM371
V–
+5V
U3
V+
ADCM371
V–
U4B
4
7408
5
CS
+15V
0.1μF
0.1μF
–15V
U4A
16
7408
2
CLK
SDI
U1
V
DD
V
SS
CS
CLK
SDI
A
100kΩ
B
W
GND
AD5290
+15V
U5
V+
V–
–15V
V
OUT
04716-028
C3
C2
1μF
R4
90kΩ
R5
10kΩ
5V
U6
V+
AD8541
V–
Figure 35. Audio Volume Control with Zipper Noise Reduction
1
2
CHANNEL 1
FREQ = 20.25kHz
1.03V p-p
04716-021
Figure 36. Input (Trace 1) and Output (Trace 2) of the Circuit in Figure 35
(The Command of Volume Change May Occur at Any Time, but the Level Change Occurs Only Near the Zero-Crossing Window)
Rev. 0 | Page 19 of 20
AD5290
www.BDTIC.com/ADI
OUTLINE DIMENSIONS
3.10
3.00
2.90
6
0.95
0.85
0.75
3.10
3.00
2.90
0.15
0.05
PIN 1
10
1
0.50 BSC
0.33
0.17
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-BA
5.15
4.90
4.65
5
1.10 MAX
SEATING
PLANE
0.23
0.08
Figure 37. 10-Lead Mini Small Outline Package [MSOP]
M-10)
(R
Dimensions shown in millimeters
8°
0°
0.80
0.60
0.40
ORDERING GUIDE
Model RAB (kΩ) Temperature Range Package Description Package Option Branding
AD5290YRMZ10 10 –40°C to +125°C 10-Lead MSOP RM-10 D4U
AD5290YRMZ10-R7 10 –40°C to +125°C 10-Lead MSOP RM-10 D4U
AD5290YRMZ50 50 –40°C to +125°C 10-Lead MSOP RM-10 D4T
AD5290YRMZ50-R7 50 –40°C to +125°C 10-Lead MSOP RM-10 D4T
AD5290YRMZ100 100 –40°C to +125°C 10-Lead MSOP RM-10 D4V
AD5290YRMZ100-R7 100 –40°C to +125°C 10-Lead MSOP RM-10 D4V
AD5290EVAL 10 Evaluation Board
1
Z = Pb-free part.
1
1
1
1
1
1
©2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04716–0–12/05(0)
T
Rev. 0 | Page 20 of 20
TTT
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