Analog Devices AD5282BRU50, AD5282BRU200, AD5280BRU50, AD5280BRU200, AD5280BRU20 Datasheet

PRELIMINARY TECHNICAL DATA

+15V, I2C Compatible

a

Digital Potentiometers

Preliminary Technical Data AD5280/AD5282

FEATURES

256 Position
AD5280 – 1-Channel
AD5282 – 2-Channel (Independently Programmable)
Potentiometer Replacement
20K, 50K, 200K Ohm with TC < 50ppm/ºC
Internal Power ON Mid-Scale Preset
+5 to +15V Single-Supply; ±5.5V Dual-Supply Operation

2

I

C Compatible Interface

APPLICATIONS

Multi-Media, Video & Audio
Communications
Mechanical Potentiometer Replacement
Instrumentation: Gain, Offset Adjustment
Programmable Voltage to Current Conversion
Line Impedance Matching

GENERAL DESCRIPTION

The AD5280/AD5282 provides a single/dual channel, 256 position
digitally-controlled variable resistor (VR) device. These devices
perform the same electronic adjustment function as a
potentiometer, trimmer or variable resistor. Each VR offers a
completely programmable value of resistance, between t he A
terminal and the wiper, or the B terminal and the wiper. The fixed
A-to-B terminal resistance of 20, 50 or 200K ohms has a 1%
channel-to-channel matching tolerance with a nominal temperature
coefficient of 30 ppm/°C.

Wiper Position programming defaults to midscale at system power
ON. Once powered the VR wiper position is programmed by a I

2

C
compatible 2-wire serial data interface. Both parts have two
programmable logic outputs available to drive digital loads, gates,
LED drivers, analog switches, etc.

FUNCTIONAL BLOCK DIAGRAMS

SHDN

V

V

SCL
SDA
GND

A

W1B

1

DD

SS

V

L

RDAC1 REGISTER

ADDRESS

DECODE

1

RR

RDAC2 REGISTER

AD5280

SERIAL INPUT REGISTER

O

O

1

2

PWR ON

RESET

8

SHDN

V

DD

V

SS

V

L

SCL
SDA

GND

The AD5280/AD5282 are available in ultra compact surface mount
thin TSSOP-14/-16 packages. All parts are guarant eed to operate
over the extended industrial temperature range of -40°C to +85°C.
For 3-wire, SPI compatibl e i nterface applications, see
AD5203/AD5204/AD5206/AD7376/AD8400/AD8402/AD8403/
AD5260/AD5262/AD5200/AD5201 products.

Kilo Package Package
Model Ohms Temp Description Option

AD5280BRU20 20 -40/+85°C TSSOP-14 RU-14
AD5280BRU50 50 -40/+85°C TSSOP-14 RU-14
AD5280BRU200 200 -40/+85°C TSSOP-14 RU-14

AD5282BRU20 20 -40/+85°C TSSOP-16 RU-16
AD5282BRU50 50 -40/+85°C TSSOP-16 RU-16
AD5282BRU200 200 -40/+85°C TSSOP-16 RU-16

The AD5280/AD5282 die size is 75 mil X 120 mil, 9,000 sq. mil.
Contains xxx transistors. Patent Number xxx ap plies.

A

1

RDAC1 REGISTER

ADDRESS

DECODE

AD0 AD1

W

B

A

W

1

1

2

RR

AD5282

SERIAL INP UT REGISTER

RDAC2 REGISTER

8

2

PWR ON

RESET

B

2

ORDERING GUIDE

O

1

OUTPUT

REGISTER

R

AD0 AD1

REV PrE 12 MAR 02

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Tel: [phone] www.analog.com
Fax: [phone] ©Analog Devices, Inc., 2002

Norwood, MA 02062-9106 U.S.A.

PRELIMINARY TECHNICAL DATA

AD5280/AD5282

(V

ELECTRICAL CHARACTERISTICS 20K, 50K, 200K OHM VERSION

V

= +VDD, VB = 0V, -40°C < T

A

< +85°C unless otherwise noted.)

A

= +5V, VSS = -5V, V

DD

Parameter Symbol Conditions Min Typ1 Max Units

DC CHARACTERISTICS RHEOSTAT MODE Specifications apply to all VRs
Resistor Differential NL2 R-DNL RWB, VA=NC -1 ±0.4 +1 LSB

Resistor Nonlinearity2 R-INL RWB, VA=NC -1 ±0.5 +1 LSB
Nominal resistor tolerance3 ∆R TA = 25°C -30 30 %

Resistance Temperature Coefficient RAB/∆T V
Wiper Resistance RW I

= VDD, Wiper = No Connect 30 ppm/°C

AB

= VDD /R, VDD = +3V or +5V 40 100 Ω

W

DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE Specifications apply to all VRs
Resolution N 8 Bits

Integral Nonlinearity4 INL RAB=20KΩ, 50KΩ –1 ±0.5 +1 LSB
Integral Nonlinearity4 INL RAB=200KΩ –2 ±0.5 +2 LSB
Differential Nonlinearity4 DNL –1 ±0.4 +1 LSB
Voltage Divider Temperature Coefficient ∆VW/∆T Code = 80H 5 ppm/°C
Full-Scale Error V
Zero-Scale Error V

Code = FFH –1 -0.5 +0 LSB

WFSE

Code = 00H 0 +0.5 +1 LSB

WZSE

RESISTOR TERMINALS
Voltage Range5 V

Capacitance6 A, B C

VSS V

A,B,W

f = 1 MHz, measured to GND, Code = 80H 45 pF

A,B

V

DD

Capacitance6 W CW f = 1 MHz, measured to GND, Code = 80H 60 pF
Common Mode Leakage ICM V

= VB = VW 1 nA

A

DIGITAL INPUTS
Input Logic High VIH SDA & SCL 0.7V

Input Logic Low VIL SDA & SCL -0.5 0.3V
Input Logic High VIH AD0 & AD1 2.4 V

V

LOGIC

+0.5 V

LOGIC

V

LOGIC

V

LOGIC

Input Logic Low VIL AD0 & AD1 0 0.8 V
Input Logic High VIH V
Input Logic Low VIL V
Input Current IIL V
Input Capacitance6 C

3 pF

IL

= +3V, AD0 & AD1 2.1 V

LOGIC

= +3V, AD0 & AD1 0 0.6 V

LOGIC

= 0V or +5V ±1 µA

IN

V

LOGIC

DIGITAL Output
O1, O2 VOH I

O1, O2 VOL I
SDA VOL I

SDA VOL I
Three-State Leakage Current IOZ V
Output Capacitance6 C

3 8 pF

OZ

=0.4mA 2.4 5.5 V

OH

=-1.6mA 0 0.4 V

OL

= -6mA 0.6 V

OL

= -3mA 0.4 V

OL

= 0V or +5V ±1 µA

IN

POWER SUPPLIES

Logic Supply V
Power Single-Supply Range V
Power Dual-Supply Range V

Logic Supply Current I
Positive Supply Current IDD V

+2.7 +5.5 V

LOGIC

VSS = 0V +5 +15 V

DD RANGE
DD/SS RANGE

LOGIC

±4.5 ±5.5 V

V

= +5V 10 µA

LOGIC

= +5V or VIL = 0V 20 60 µA

IH

Negative Supply Current ISS 20 60 µA
Power Dissipation10 P

VIH = +5V or VIL = 0V, VDD = +5V, VSS = -5V 0.2 0.6 mW

DISS

Power Supply Sensitivity PSS 0.05 0.015 %/%

LOGIC

= +5V,

Information contained in this Product Concept Data Sheet describes a product in the early definition stage. There is no guarantee that the information contained here will become a final
product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa Clara, CA. TEL [phone]; FAX [phone]; email; [e-mail]

2 REV PrE 12 MAR 02

PRELIMINARY TECHNICAL DATA

AD5280/AD5282

(V

ELECTRICAL CHARACTERISTICS 20K, 50K, 200K OHM VERSION

V

= +VDD, VB = 0V, -40°C < T

A

< +85°C unless otherwise noted.)

A

= +5V, VSS = -5V, V

DD

Parameter Symbol Conditions Min Typ1 Max Units

6,9,11

DYNAMIC CHARACTERISTICS
Bandwidth –3dB BW_20K RAB = 20KΩ, Code = 80H 650 kHz

BW_50K RAB = 50KΩ, Code = 80H 142 kHz
BW_200K RAB = 200KΩ, Code = 80H 69 kHz
Total Harmonic Distortion THDW VA =1Vrms + 2V dc, VB = 2V DC, f=1KHz 0.005 %

VW Settling Time tS V
Resistor Noise Voltage e

RWB = 10KΩ, f = 1KHz 14 nV√Hz

N_WB

= VDD, VB=0V, ±1 LSB error band 2 µs

A

INTERFACE TIMING CHARACTERISTICS applies to all parts(Notes 6,12)
SCL Clock Frequency f

t

Bus free time between STOP & START t1 1.3 µs

BUF

t

Hold Time (repeated START) t2 After this period the first clock pulse is generated 0.6 µs

HD;STA

t

Low Period of SCL Clock t3 1.3 µs

LOW

t

High Period of SCL Clock t4 0.6 µs

HIGH

t

Setup Time For START Condition t5 0.6 µs

SU;STA

t

Data Hold Time t6 0 0.9 µs

HD;DAT

t

Data Setup Time t7 100 ns

SU;DAT

tF Fall Time of both SDA & SCL signals t8 300 ns
tR Rise Time of both SDA & SCL signals t9 300 ns
t

Setup time for STOP Condition t10 0.6 µs

SU;STO

NOTES:

1. Typicals represent average readings at +25°C, VDD = +5V, VSS = -5V.

2. Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the

relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.

3. V

= VDD, Wiper (VW) = No connect

AB

4. INL and DNL are measured at V
DNL specification limits of ±1LSB maximum are Guaranteed Monotonic operating conditions.

5. Resistor terminals A,B,W have no limitations on polarity with respect to each other.

6. Guaranteed by design and not subject to production test.

9. Bandwidth, noise and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest bandwidth. The highest R value

result in the minimum overall power consumption.

10. P

11. All dynamic characteristics use V

12. See timing diagram for location of measured values.

is calculated from (IDD x VDD). CMOS logic level inputs result in minimum power dissipation.

DISS

with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0V.

W

= +5V.

DD

0 400 KHz

SCL

LOGIC

= +5V,

REV PrE 12 MAR 02 3

Information contained in this Product Concept Data Sheet describes a product in the early definition stage. There is no guarantee that the information contained here will become a final
product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa Clara, CA. TEL [phone]; FAX [phone]; email; [e-mail]